AD8321

a FEATURES Linear in dB Gain Response Over >53 dB Range Drives Low Distortion >11 dBm Signal into 75 � Load: –53 dBc SFDR at 42 MHz Very Low Output Noise Level Maintains Constant 75 � Output Impedance Power-Up and Power-Down Condition No Line Transformer Required Upper Bandwidth: 235 MHz (Min Gain) 9 V Single Supply Operation Power-Down Functionality Supports SPI Interface Low Cost APPLICATIONS Gain Programmable Line Driver HFC High Speed Data Modems Interactive CATV Set-Top Boxes CATV Plant Test Equipment General Purpose IF Variable Gain Block VCC Gain Programmable CATV Line Driver AD8321 FUNCTIONAL BLOCK DIAGRAM GND AD8321 VIN+ INV VIN– ATTENUATOR CORE PWR AMP VOUT REVERSE AMP DATA LATCH DATA SHIFT REGISTER POWERDOWN/ SWITCH INTER PD DATA SHIFT REGISTER DATEN CLK SDATA DESCRIPTION The AD8321 is a low cost digitally controlled variable gain amplifier optimized for coaxial line driving applications such as cable modems that are designed to the DOCSIS* (upstream) standard. An 8-bit serial word determines the desired output gain over a 53.4 dB range, resulting in gain changes of 0.75 dB/LSB. The AD8321 comprises a digitally controlled variable attenuator of 0 dB to –53.4 dB, which is preceded by a low noise, fixed gain buffer and followed by a low distortion high power ampli­ fier. The AD8321 accepts a differential or single-ended input signal. The output is specified for driving a 75 W load, such as coaxial cable, although the AD8321 is capable of driving other loads. Performance of –53 dBc is achieved with an output level up to 11 dBm at 42 MHz bandwidth using a 9 V supply. A key performance and cost advantage of the AD8321 results from the ability to maintain a constant 75 W output impedance during power-up and power-down conditions. This eliminates the need for external 75 W termination, resulting in twice the effective output voltage when compared to a standard opera­ tional amplifier, thus eliminating the need for a transformer. *Data-Over-Cable Service Interface Specifications The AD8321 is packaged in a low cost 20-lead SOIC, operates from a single +9 V supply, and has an operational temperature range of –40∞C to +85∞C. –40 fO = 42MHz VIN = 137mV p-p (PIN = –15dBm) (POUT = 11dBm @ MAX GAIN) –50 DISTORTION – dBc –60 HD3 –70 HD2 –80 –90 0 8 16 24 32 40 48 GAIN CONTROL – Decimal 56 64 72 Figure 1. Harmonic Distortion vs. Gain Control R EV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/461-3113 © 2005 Analog Devices, Inc. All rights reserved. AD8321–SPECIFICATIONS 75 � unless otherwise noted) Parameter INPUT CHARACTERISTICS Specified AC Voltage Noise Figure Input Resistance Input Capacitance GAIN CONTROL INTERFACE Gain Range Maximum Gain Minimum Gain Gain Scaling Factor OUTPUT CHARACTERISTICS Bandwidth (–3 dB) Bandwidth Roll-Off Bandwidth Peaking Output Offset Voltage Output Noise Spectral Density Conditions Output = 11 dBm, Max Gain Max Gain, f = 10 MHz Single-Ended Input Differential Input (@ VCC = +9 V, TA = +25�C, VIN = 0.137 V p-p, single-ended input, RL = 75 �, RIN = Min Typ 0.137 15 820 900 2.0 52.4 25.25 –28.15 53.4 26 –27.4 0.7526 120 0.8 0 ± 30 60 20 0.02 1 19.5 75 –53 –51 0.03 ± 0.2 0.004 60 30 –80 54.4 26.75 –26.4 Max Unit V p-p dB W W pF dB dB dB dB/LSB MHz dB dB mV nV/÷Hz nV/÷Hz nV/÷Hz/∞C nV/÷Hz dBm W dBc dBc dBc/∞C dB dB/∞C ns ns dBc All Gain Codes f = 65 MHz f = 65 MHz All Gain Codes, Full Temperature Range Max Gain, f = 10 MHz Min Gain, f = 10 MHz Output Noise Temperature Sensitivity 0 £ TA £ +70∞C, Min Gain Power-Down Spectral Density 1 dB Compression Point Max Gain, f = 10 MHz Output Impedance Power-Up and Power-Down f = 42 MHz, POUT = 11 dBm, VCC = +9 V f = 65 MHz, POUT = 11 dBm, VCC = +9 V –40∞C £ TA £ +85∞C f = 10 MHz, All Gain Codes 0 £ TA £ +70∞C Min to Max Gain, VIN = 0 V Max Gain, VIN = 0.15 V Step Power Down, 65 MHz, Min Gain VIN = 0.137 V p-p Max Gain, VIN = 0 Max Gain, VIN = 0 Max Gain, VIN = 0 Max Gain, VIN = 0 Power-Up, VCC = +9 V Power-Down, VCC = +9 V 60 90 OVERALL PERFORMANCE Worst Harmonic Distortion Distortion Temperature Sensitivity Gain Accuracy Gain Temperature Sensitivity Output Settling to 1 mV Gain Change @ TDATEN = 1 Input Change Signal Feedthrough POWER CONTROL Power-Down Settling Time to 1 mV Power-Up Settling Time to 1 mV Power-Up/Down Pedestal Offset Power-Up/Down Glitch POWER SUPPLY Quiescent Current Specifications subject to change without notice. 40 300 ± 30 40 82 45 90 52 97 60 ns ns mV mV p-p mA mA –2– REV. A AD8321 LOGIC INPUTS (TTL/CMOS Logic) (DATEN, CLK, SDATA, V Parameter Logic “1” Voltage Logic “0” Voltage Logic “1” Current (VINH = 5 V) CLK, SDATA, DATEN Logic “0” Current (VINL = 0 V) CLK, SDATA, DATEN Logic “1” Current (VINH = 5 V) PD Logic “0” Current (VINL = 0 V) PD CC = +9 V; Full Temperature Range) Min 2.1 0 0 –600 50 –250 Typ Max 5.0 0.8 20 –100 190 –30 Unit V V nA nA mA mA TIMING REQUIREMENTS (Full Temperature Range, V Parameter Clock Pulsewidth (TWH) Clock Period (TC) Setup Time SDATA vs. Clock (TDS) Setup Time DATEN vs. Clock (TES) Hold Time SDATA vs. Clock (TDH) Hold Time DATEN vs. Clock (TEH) Input Rise and Fall Times, SDATA, DATEN, Clock (TR, TF) Specifications subject to change without notice. TDS SDATA VALID DATA WORD G1 MSB. . . .LSB CC = +9 V, TR = TF = 4 ns, fCLK = 8 MHz unless otherwise noted.) Min 16.0 32.0 5.0 15.0 5.0 3.0 10 Typ Max Unit ns ns ns ns ns ns ns VALID DATA WORD G2 TC TWH CLK TES DATEN TEH 8 CLOCK CYCLES GAIN TRANSFER (G1) TOFF PD TGS GAIN TRANSFER (G2) TON ANALOG OUTPUT SIGNAL AMPLITUDE (p-p) PEDESTAL Figure 2. Serial Interface Timing VALID DATA BIT SDATA MSB MSB-1 MSB-2 TDS TDH CLK Figure 3. SDATA Timing REV. A – 3– AD8321 ABSOLUTE MAXIMUM RATINGS * PIN CONFIGURATION SDATA 1 CLK 2 DATEN 3 GND 4 BYP1 5 PD 6 VCC VIN– VIN+ VCC GND Supply Voltage +VS Pins 7, 8, 9, 17, 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . +11 V Input Voltages Pins 18, 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 0.5 V Pins 1, 2, 3, 6 . . . . . . . . . . . . . . . . . . . . . . . –0.8 V to +5.5 V Internal Power Dissipation Small Outline (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.90 W Operating Temperature Range . . . . . . . . . . . –40∞C to +85∞C Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C Lead Temperature, Soldering 60 seconds . . . . . . . . . . +300∞C * Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 20 19 18 17 AD8321 16 TOP VIEW 1 5 GND (Not to Scale) 1 4 BYP2 VCC 7 VCC 8 VCC 9 VOUT 1 0 13 12 11 GND GND GND ORDERING GUIDE Model AD8321AR AD8321AR-REEL AD8321ARZ2 AD8321ARZ-REEL2 AD8321-EVAL 1 2 Temperature Range –40∞C to +85∞C –40∞C to +85∞C –40∞C to +85∞C –40∞C to +85∞C Package Description 20-Lead SOIC 20-Lead SOIC 20-Lead SOIC 20-Lead SOIC Evaluation Board �JA 58∞C/W 58∞C/W1 58∞C/W1 58∞C/W1 1 Package Option R-20 R-20 R-20 R-20 Thermal Resistance measured on SEMI standard 4-layer board. Z = Pb-free part. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8321 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. PIN FUNCTION DESCRIPTIONS WARNING! ESD SENSITIVE DEVICE Pin 1 2 Function SDATA CLK Description Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the internal register with the MSB (most significant bit) first. Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-slave register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to the slave. This requires the input serial data word to be valid at or before this clock transition. Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0-to­ 1 transition transfers the latched data to the attenuator core (updates the gain) and simultaneously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch (holds the previ­ ous gain state) and simultaneously enables the register for serial data load. Common External Ground Reference. VCC/2 Reference Pin. A dc output reference level that is equal to 1/2 of the supply voltage (VCC). This port should be externally ac-decoupled (0.1 mF capacitor). For external use of this reference voltage, buffering is required. Power-Down Low Logic Input. A Logic 0 powers down (shuts off) the power amplifier disabling the output signal and enabling the reverse amplifier. A Logic 1 enables the output power amplifier and disables the reverse amplifier. Common Positive External Supply Voltage. Output Signal Port. DC-biased to approximately VCC/2. Internal Bypass. This pin must be externally ac-decoupled (0.1 mF capacitor). Noninverting Input. DC-biased to approximately VCC/2. For single-ended inverting operation, use 0.1 mF decoupling capacitor between VIN+ and ground. Inverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 mF capacitor. – 4– REV. A 3 DATEN 4, 11, 12, 13, 15, 16 5 GND BYP1 6 PD 7, 8, 9, 17, 20 10 14 18 19 VCC VOUT BYP2 VIN+ VIN– Typical Performance Characteristics–AD8321 0.6 30 20 f = 10MHz GAIN ERROR – dB 10 0 GAIN – dB 70 71D OUTPUT NOISE – nV/ Hz f = 10MHz PD =1 60 0.3 50 0 –10 46D –0.3 f = 42MHz 40 –0.6 f = 65MHz –0.9 –1.2 23D –20 –30 –40 0.1 30 20 00D 0 8 16 24 32 40 48 56 GAIN CONTROL – Decimal 64 72 10 1 10 100 FREQUENCY – MHz 1000 0 8 16 24 32 40 48 56 GAIN CONTROL – Decimal 64 72 Figure 4. Gain Error vs. Gain Control Figure 5. AC Response Figure 6. Output Referred Noise vs. Gain Control 70 PD = 1 60 –30 fO = 65MHz VIN = 0.137V p-p (PIN = –15dBm) (POUT = 11dBm @ MAX GAIN) –47 OUTPUT NOISE – nV/ Hz DISTORTION – dBc DISTORTION – dBc MAX GAIN (71D) 50 –40 PIN = –14dBm (POUT = 12dBm @ MAX GAIN) PIN = –13dBm (POUT = 13dBm @ MAX GAIN) PIN = –15dBm (POUT = 11dBm @ MAX GAIN) –50 –50 HD3 40 –53 –60 HD2 30 MIN GAIN (00D) 20 10 1 10 FREQUENCY – MHz 100 –56 PIN = –17dBm (POUT = 9dBm @ MAX GAIN) –70 –80 0 8 16 24 32 40 48 56 GAIN CONTROL – Decimal 64 72 –59 5 15 25 35 45 55 FUNDAMENTAL FREQUENCY – MHz 65 Figure 7. Output Referred Noise vs. Frequency Figure 8. Harmonic Distortion vs. Gain Control Figure 9. Second Order Harmonic Distortion vs. Frequency for Various Input Levels –47 PIN = –13dBm (POUT = 13dBm @ MAX GAIN) –50 20 3RD ORDER INTERCEPT – dBm 30 POUT = 11dBm MAX GAIN 29 28 27 26 25 24 23 POUT = 11dBm MAX GAIN DISTORTION – dBc POUT – dBm PIN = –14dBm (POUT = 12dBm @ MAX GAIN) 0 –20 –53 PIN = –15dBm (POUT = 11dBm @ MAX GAIN) PIN = –17dBm (POUT = 9dBm @ MAX GAIN) –59 5 15 25 35 45 55 FUNDAMENTAL FREQUENCY – MHz 65 –40 –56 –60 –80 41.0 41.4 41.8 42.2 42.6 FREQUENCY – MHz 43.0 22 5 15 35 45 25 FREQUENCY – MHz 55 65 Figure 10. Third Order Harmonic Distortion vs. Frequency for Various Input Levels Figure 11. Two-Tone Intermodulation Distortion Figure 12. Third Order Intercept vs. Frequency REV. A –5– AD8321 34 MAX GAIN POUT = 11dBm 30 CL = 10pF CL = 0pF GAIN – dB 5mV MIN GAIN VIN = 0V p-p VOUT 15mV MAX GAIN VIN = 0V p-p VOUT 26 22 CL = 20pF CL = 50pF PD PD 18 5V 14 1 10 FREQUENCY – MHz 100 75ns 5V 75ns Figure 13. AC Response for Various Capacitor Loads Figure 14. Power Up/Power Down Glitch Figure 15. Power Up/Power Down Glitch 7.5mV 0 PD = 0 –20 0.75V MAX GAIN VIN = 0V p-p – 0.137V p-p VOUT VIN = 0V p-p MAX GAIN tr(CLK) = 3ns CLK FEEDTHROUGH – dB VOUT MAX GAIN –40 –60 –80 VIN MIN GAIN DATEN 5V 150ns –100 0.1 200mV 1 10 100 FREQUENCY – MHz 1000 30ns Figure 16. Clock Feedthrough Figure 17. Input Signal Feedthrough vs. Frequency 90 Figure 18. Output Settling Time Due to Input Change 100 PD =1 1.5V MAX GAIN 85 90 VOUT IMPEDANCE – � 80 +ICC – mA 80 PD = 0 75 PD = 1 70 70 60 PD = 0 50 VIN 65 0.5V 30ns 60 1 10 FREQUENCY – MHz 100 40 –50 –25 50 0 25 TEMPERATURE – �C 75 100 Figure 19. Overload Recovery Figure 20. Output Impedance vs. Frequency Figure 21. Supply Current vs. Temperature – 6– REV. A AD8321 OPERATIONAL DESCRIPTION The gain transfer function is as follows: AV = 26 dB – ((71 – CODE) ¥ 0.7526 dB) for CODE £ 71 AV = 26 dB for 71 £ CODE £ 127 AV = 26 dB + ((199 – CODE) ¥ 0.7526 dB) for 128 £ CODE £ 199 AV = 26 dB for 199 £ CODE £ 255 where CODE is the decimal equivalent of the 8-bit word loaded in the AD8321’s data latch (see Figure 23). 30 The AD8321 is a digitally controlled variable gain power ampli­ fier that is optimized for driving a 75 W cable. As a multifunc­ tional bipolar device on a single silicon die, it incorporates all the analog features necessary to accommodate reverse path (upstream) high speed (5 MHz to 65 MHz) cable data modem requirements. The AD8321 has an overall gain range of approximately 53 dB and is capable of greater than 100 MHz operation at output signal levels exceeding 12 dBm. Overall, when considering the device’s wide gain range, low distortion, wide bandwidth and variable load drive, the device can be used in many variable gain block applications. VCC GND 20 10 PWR AMP VOUT REVERSE AMP GAIN – dB AD8321 VIN+ INV VIN– ATTENUATOR CORE 0 –10 –20 DATA LATCH DATA SHIFT REGISTER POWERDOWN/ SWITCH INTER –30 PD 0 32 64 96 128 160 GAIN CODE – Decimal 192 224 256 DATA SHIFT REGISTER Figure 23. Linear-In dB Gain vs. Gain Control DATEN CLK SDATA Figure 22. Functional Block Diagram The digitally programmable gain is controlled by the three-wire “SPI” compatible inputs. These inputs are called SDATA (serial data input port), DATEN (data enable low input port) and CLK (clock input port). See Pin Function Descriptions and Functional Block diagram. The AD8321 is programmed by an 8-bit “attenuator” word. When a standard 8-bit word is used, the first data bit MSB will be shifted out of the 7-bit shift register during the eighth rising CLK edge. The lower seven bits will then be loaded into the AD8321’s digital decode sec­ tion when the DATEN input is taken high. The AD8321 is composed of four analog functions in the power-up or forward mode. The input amplifier (preamp) which can be used single-endedly or differentially and provides a maxi­ mum of 12 dB of attenuation. If the input is used in the differ­ ential configuration, it is imperative that the input signals are 180 degrees out of phase and of equal amplitudes. This will ensure the proper gain accuracy and harmonic performance. The preamp stage drives a vernier stage that provides the fine tune gain adjustment. The 0.7526 dB step resolution is imple­ mented in this stage. After the vernier stage, a DAC provides the bulk of the AD8321’s attenuation (six bits or 36 dB). The signals in the preamp and vernier gain blocks are differential to improve the PSRR and linearity. A single-ended current is fed from the DAC into the output stage, which amplifies this current to the appropriate level necessary to drive a 75 W load. The output stage utilizes negative feedback to implement a 75 W output impedance. This eliminates the need for an external 75 W match­ ing resistor needed in typical video (or video filter) termination requirements. The gain of the AD8321 is linear in steps of 0.7526 dB. The gain transfer function starts at –27.43 dB (at decimal code 0) and increases 0.7526 dB/LSB. The gain increases up to decimal code 71. At this point the gain is at its maximum level of 26 dB. If a decimal word between 71 and 127 is entered, the gain is no longer incremented and stays at 26 dB. Since the MSB of an 8-bit word is a “don’t care” bit, at decimal code 128, the AD8321’s gain returns to its minimum value. The gain vs. gain control relationship repeats itself as shown in Figure 23 for the upper 127 codes. REV. A – 7– AD8321 The attenuation setting in the AD8321 is determined by the 8-bit word in the data latch. The SDATA load sequence is initiated by a falling edge on DATEN. The gain control data (SDATA) is serially loaded (MSB first) into the 7-bit shift register at each rising edge of the clock. See Figure 24. While DATEN is low, the data latch holds the previous data word allowing the attenuation level to remain unchanged. After eight clock cycles the new data word is fully loaded and DATEN is switched high. This enables the data latch and the loaded register data is passed to the attenuator with the updated gain value. Also at this DATEN transition, the internal clock is disabled, thus inhibiting new serial input data. The power amplifier has two basic modes of operation. A for­ ward mode (or power-up mode) and a reverse mode (or powerdown) mode. In the power-up mode (PD = 1), the power amplifier stage is enabled and the AD8321 has a maximum gain of 20 V/V or 26 dB (into 75 W). With a total attenuation of 53.43 dB in the DAC, vernier and preamp, the AD8321’s total gain range is 26 dB to –27.43 dB. In both the forward or reverse mode the single-ended output signal maintains a dc level of VCC/2. This dc output level provides for optimum large signal linearity. In the power-down mode (PD = 0), the power amplifier is turned off and a “reverse” amplifier (the inner triangle in Figure 22) is enabled. During this 1-to-0 transition, the output power is disabled. This assures that S11 and S22 remain approximately equal to zero thus minimizing line reflections. In the time domain, as PD switches states, a transitional glitch and pedestal offset results (See Figures 14 and 15). These anomalies have been minimized by temperature compensated internal circuitry and laser trimming. The powered down supply current drops to 52 mA versus 90 mA in the power-up mode. APPLICATIONS General Application The AD8321 is primarily intended for use as the return path (also called upstream path) Power Amplifier (PA) or line driver in cable modem applications. Upstream data is modulated in either QPSK or QAM format. This is done either in DSP or by a dedicated QPSK/QAM modulator such as the AD9853 or other modem/modulator chip. The amplifier receives its input signal either from the dedicated QPSK/QAM modulator or from a DAC. In both cases, the signal must be low-pass filtered before being applied to the line driving amplifier. Because the distance to the central office varies from cable modem sub­ scriber to subscriber, resulting in various line losses, signals from various subscribers will require attenuation while others may require gain. As a result, the AD8321 line driver is required to vary its output applying attenuation or gain as needed so that all signals arriving at the central office are of the same amplitude. DOCSIS (Data Over Cable Service Interface Specifications) requires a cable modem output signal ranging in power from a minimum of 8 dBmV to a maximum of 58 dBmV. In cable modem applications where DOCSIS compliance is desired, the AD8321 amplifier must be used in conjunction with a 75 W matching attenuator connected between the AD8321 output and the low-pass input port of the diplexer. See the schematic in Figure 28. The matching attenuator is used to achieve DOCSIScompliant noise levels at the lower end of the AD8321 output power range. The insertion loss of a diplexer is typically less than 1 dB. As a result of these combined losses, the PA line driver must be capable of delivering sufficient power into a 75 W load while maintaining reasonable distortion performance at the output of the modem. (See sections containing “DOCSIS” for further information. All references to DOCSIS pertain to SP-RFI-I04-980724 entitled Radio Frequency Interface Specification.) TDS SDATA VALID DATA WORD G1 MSB. . . .LSB VALID DATA WORD G2 TC TWH CLK TES DATEN TEH 8 CLOCK CYCLES GAIN TRANSFER (G1) TOFF PD TGS GAIN TRANSFER (G2) TON ANALOG OUTPUT SIGNAL AMPLITUDE (p-p) PEDESTAL Figure 24. Serial Interface Timing – 8– REV. A AD8321 Basic Connection Input Bias, Impedance and Termination Figure 25 shows the basic schematic for operating the AD8321 in single-ended inverting mode. To operate in inverting mode, connect the input signal through an ac coupling capacitor to VIN–; VIN+ should be decoupled to ground with a 0.1 mF capacitor. Because the amplifier operates from a single supply, and the differential input pins are biased to approximately VCC/2, the differential inputs must be ac-coupled using 0.1 mF capacitors. For operation in the noninverting mode, the VIN– pin should be decoupled to ground via a 0.1 mF capacitor, with the input signal being fed to the AD8321 through the (ac-coupled) VIN+ pin. Inverting mode should be chosen if the AD8321 is being used as a drop-in replacement for the AD8320 (the AD8321 predecessor). Balanced differential inputs to the AD8321 may also be applied at an amplitude that is one-half the specified single-ended input amplitude. See the Differential Inputs section for more on this mode of operation. Power Supply and Decoupling On the input side, the VIN+ and VIN– have a dc bias level equal to (VCC/2) – 0.2 V. The input signal must therefore be ac-coupled before being applied to either input pin. The input impedance, when operated in single-ended mode is roughly 820 W (900 W in differential mode). An external shunt resis­ tance (R1) to ground of 82.5 W is required to create a singleended input impedance of close to 75 W. If single-ended 50 W termination is required, a 53.6 W shunt resistor may be used. Differential input operation may be achieved by using a shunt resistor of 41 W to ground on each of the inputs, or 82.6 W across the inputs resulting in a differential input impedance of approximately 75 W. Note: to avoid dc loading of either the VIN+ or VIN– pin, the ac-coupling capacitor must be placed between the input pin(s) and the shunt resistor(s). Refer to the Differential Inputs section for more details on this mode of operation. Output Bias, Impedance and Termination The AD8321 should be powered with a good quality (i.e., low noise) single supply of 9 V. Although the AD8321 circuit will function at voltages lower than 9 V, optimum performance will not be achieved at lower supply settings. Careful attention must be paid to decoupling the power supply pins. A 10 mF capacitor located in near proximity to the AD8321 is required to provide good decoupling for lower frequency signals. In addition, and more importantly, five 0.1 mF decoupling capacitors should be located close to each of the five power supply pins (7, 8, 9, 17, and 20). A 0.1 mF capacitor must also be connected to the pins labeled BYP1 and BYP2 (Pins 5 and 14) to provide decoupling to internal nodes of the device. All six ground pins should be connected to a common low impedance ground plane. On the output side, the VOUT pin is also dc-biased to VCC/2 or midway between the supply voltage and ground. The output signal must therefore be ac-coupled before being applied to the load. The dc-bias voltage is available on the BYP1 and BYP2 pins (Pins 5 and 14 respectively) and can be used in dc-biasing schemes. These nodes must be decoupled to ground using a 0.1 mF capacitor as shown in Figure 25. If the BYP1 and/or BYP2 voltages are used externally, they should be buffered. External back termination resistors are not required when using the AD8321. The output impedance of the AD8321 is 75 W and is maintained dynamically. This on chip back termination is maintained regardless of whether the amplifier is in forward transmit mode or reverse powered down mode. If the output signal is being evaluated on 50 W test equipment such as a spectrum analyzer, a 75 W to 50 W adapter (commonly called a minimum loss pad) should be used to maintain a properly matched circuit. C4 C5 0.1�F 0.1�F VCC +9V C6 10�F C7 0.1�F C8 0.1�F C9 0.1�F C10 0.1�F C11 0.1�F C2 0.1�F VCC VIN+ VCC VCC VCC VCC BYP1 BYP2 VOUT AD8321 ATTENUATOR CORE Ce 0.1�F C1 0.1�F INPUT R1 82.5� TO DIPLEXER RIN = 75� VIN– DATA LATCH POWER­ DOWN/ SWITCH INTER DATA SHIFT REGISTER CLK DATEN DATEN CLK SDATA PD SDATA GND GND GND GND GND Figure 25. Basic Connection for Single-Ended Inverting Operation REV. A – 9– AD8321 Varying the Gain and SPI Programming The gain of the AD8321 can be varied over a range of 53 dB from approximately –27 dB to +26 dB, in increments of approximately 0.7526 dB per LSB. Programming the gain of the AD8321 is accomplished using conventional Serial Peripheral Interface or SPI protocol. Three digital lines, DATEN, CLK and SDATA, are used to stream eight bits of data into the serial shift register of the AD8321. Changing the state of the DATEN port from Logic 1-to-0 starts the load sequence by activating the CLK line. No changes in output signal are realized during this transi­ tion. Subsequently, any data applied to SDATA is clocked into the serial shift register Most Significant Bit (MSB) first and on the rising edge of each CLK pulse. The AD8321 may be pro­ grammed to deliver maximum gain (+26 dB) at decimal code 71. As a result, only the last seven bits of a typical 8-bit SPI word effect the gain resulting in the gain response depicted in Figure 22. Since the SPI codes from 0 through 71 appear digi­ tally identical to codes 128 through 199 for all bits except the MSB, the AD8321 repeats the gain vs. decimal code response twice in the 256 available codes (see Operational Description for gain equations and Figure 23 for Gain Response). The MSB of a typical SPI word (i.e., the first data bit presented to the SDATA line after the DATEN transition from Logic 1 to 0 and prior to the rising edge of the first clock pulse) is disregarded or ignored. Data enters the serial shift register through the SDATA port on the rising edge of the next seven CLK pulses. Returning the DATEN line to Logic 1 latches the content of the shift register into the attenuator core resulting in a well controlled change in output signal level. The timing diagram for AD8321’s serial interface is shown in Figure 24. The AD8321 has a dynamic output impedance of 75 W. This dynamic output impedance is trimmed to provide a maximum gain of +26 dB when loaded with 75 W. Operating the AD8321 at load impedances other than 75 W will only change the gain of the AD8321 while the specified gain range of 53 dB is unchanged. Varying the load impedance will result in 6 dB of additional gain when RLOAD approaches infinity. The relationship between RLOAD and gain is depicted in Figure 26 and is described by the following equation: Gain (dB) = [20 log ((2 ¥ RLOAD)/(RLOAD +75))]+(26–(0.7526 ¥ (71-Code))) 35 30 25 GAIN – dB Between Burst On/Off Transients, Asynchronous PowerDown and DOCSIS A 42% reduction in consumed power may be achieved asynchro­ nously by applying Logic 0 to PD Pin 6 activating the on-chip “reverse amplifier.” The supply current is then reduced to approximately 52 mA and the modem can no longer transmit in the upstream direction. The on-chip reverse amplifier is designed to reduce “between burst noise” and maintain a 75 W source impedance to the low pass port of the modem’s diplexer while minimizing power consumption. Changing the logic level applied to the PD pin will result in a Burst On/Off Transient at the output of the AD8321. The transient results from switching between the forward transmit amplifier and the powered down (reverse) amplifier. Although the resulting transient meets the DOCSIS transient amplitude requirements at maximum gain, it is the lower gain range (i.e., 8 dBmV to 31 dBmV) where the AD8321 may exceed the 7 mV maximum. The diplexer may further reduce the glitch amplitude. An external RF switch, such as Alpha Industries AS128-73 GaAs 2 Watt High Linearity SPDT RF switch, may be used to further reduce the spurious emissions, improve the isolation between the cable plant and the upstream line driver and switch in a 75 W back termination required to maintain proper line termination to the LP port of the diplexer (see Figure 28). Noise and DOCSIS Gain Dependence on Load Impedance One of the most difficult issues facing designers of DOCSIS compliant modems is maintaining a quiet output from the PA during times when no information is being transmitted upstream. In addition, maintaining proper signal-to-noise ratios serves to ensure the quality of transmitted data. This is extremely critical when the output signal of the modem is set to the minimum DOCSIS specified output level or 8 dBmV. The AD8321 output noise spectral density at minimum gain (or 8 dBmV) is 20 nV/÷Hz measured at 10 MHz. Considering the “Spurious Emissions in 5 MHz to 42 MHz” of Table 4–8 in DOCSIS, the calculated noise power in dBmV for 160 KSYM/SEC is: Ê Ê ˆˆ 2 Á 20 log Á Ê 20 nV / Hz ˆ ¥ 160E + 3 ˜ ˜ + 60 or - 41.5 dBmV ¯ ÁË ˜˜ Á ¯¯ Ë Ë 20 Comparing the computed noise power to the signal at 8 dBmV yields –49.5 dBc or 3.5 dB higher than the required –53 dBc in DOCSIS Table 4–8. An attenuator designed to match the AD8321 75 W source to the 75 W load may be required. Refer­ ring to the schematic of Figure 28 and the evaluation board silkscreen of Figure 31, the matching attenuator is comprised of the three resistors referred to as Rc, Rd and Re. Select the at­ tenuation level from Table I such that noise floor is reduced to levels specified in DOCSIS. Table I. 15 10 5 0 Rc (�) 1304 654.3 432 331.5 Rd (�) 8.65 17.42 26.1 35.75 Re (�) 1304 654.3 432 331.5 Attenuation (dB) –1 –2 –3 –4 0 100 200 300 400 500 RLOAD – � Figure 26. Maximum Gain vs. RLOAD – 10– REV. A AD8321 Distortion and DOCSIS Overshoot on PC Printer Ports Care must be taken when selecting attenuation levels specified in Table I as the output signal from the AD8321 must compen­ sate for the losses resulting from any added attenuation as well as the insertion losses associated with the diplexer. An increase in input signal becomes apparent at the upper end of the gain range and will be needed to achieve the 58 dBmV at the modem output. The insertion losses of the diplexer may vary, depend­ ing on the quality of the diplexer and whether the frequency of operation is in near proximity to the cut-off frequency of the low-pass filter. Figures 9 and 10 show the expected second and third harmonic distortion performance vs. fundamental frequency at various input power levels. These graphs indicate the worst harmonic levels exhibited over the entire output range of the AD8321 (i.e., –27 dB to +26 dB). Figures 9 and 10 are useful when it is necessary to determine inband harmonic levels (5 MHz to 42 MHz or 5 MHz to 65 MHz). Harmonics that are higher in frequency, as compared to the cutoff frequency of the low-pass filter of the diplexer, will be further suppressed by the stop band attenuation level of the LP filter in the diplexer. Designers must balance the need to improve noise performance by adding attenuation with the resulting need for increased signal amplitude while maintaining DOCSIS specified dis­ tortion performance. Evaluation Board Features and Operation The data lines on some PC parallel printer ports have excessive overshoot. Overshoot presented to the CLK pin (TP7 on the evaluation board) may cause communications problems. The evaluation board layout was designed to accommodate a series resistor and shunt capacitor (R6 and C12) if required to filter or condition the CLK data. Between Burst Transient Reduction The AD8321 evaluation board (p/n AD8321-EVAL) and com­ panion software program written in Microsoft Visual Basic are available through Analog Devices, Inc. and can be used to control the AD8321 Variable Gain Upstream Power Amplifier via the parallel port of a PC. This evaluation package provides a convenient way to program the gain/attenuation of the AD8321 without the addition of any external glue logic. AD8321-EVAL has been developed to facilitate the use of the AD8321 in an application targeted at DOCSIS compliance. A low cost Alpha Industries AS128-73 GaAs 2 Watt High Linearity SPDT RF switch (referred to as SWb) is included on the evaluation board (see Figure 28) along with accommodations for a user specified 75 W matching attenuator (See Table I for a table of resistor values of attenuators ranging from –1 dB to –4 dB). The AD8321 DATEN, CLK and SDATA digital lines are pro­ grammed according to the gain setting and mode of operation selected using the Windows® interface of the control software (see Figure 30). The serial interface of the AD8321 is ad­ dressed through the parallel port of a PC using four or more bits (plus ground). Two additional bits from the parallel port are used to control the RF switch(s). This software programs the AD8321 gain or attenuation, incorporates asynchronous control of the power-down feature (PD Pin 6) as well as asyn­ chronous control of the Alpha Industries RF switch(es) AS128­ 73.* A standard printer cable is used to feed the necessary data to the AD8321-EVAL board. These features allow the designer to fully develop and evaluate the upstream signal path begin­ ning at the input to the PA. In order to reduce the amplitude of the “Burst On/Off Tran­ sient” glitch at the output of the AD8321, when switching from forward transmit mode to reverse powered down mode, position the SWb switch in Figure 28 to position “a” before changing the logic applied to PD Pin 6 of the AD8321 from Logic 1-to-0 (and also 0-to-1). Use the “Enable Output Switch” feature in the evaluation board control software (see Figure 31) to select the appropriate position of the AS128-73 switch. A check in this box enables the switch to pass upstream data to the output of the evaluation board. The AS128-73 produces a glitch of approxi­ mately 5 mV p-p regardless of the AD8321 gain setting. The AD8321-EVAL board comes with resistors and capacitors installed on the logic lines controlling the RF switch (R8, R9, C16, C17). These values were selected to reduce the glitch amplitude to DOCSIS acceptable levels and may be modified if required. The SPDT function of the AS128-73 RF switch accommodates the need to maintain proper termination when the diplexer is disconnected from the output of the AD8321. The AD8321-EVAL board accommodates the needed back termination (refer to the Cb and Rb of the evaluation circuit). Differential Inputs When evaluating the AD8321 in differential input mode, termi­ nation resistor(s) should be selected and applied such that the combined resistance of the termination resistor(s) and the input impedance of the AD8321 results in a match between the signal source impedance and the input impedance of the AD8321. The evaluation board is designed to accommodate Mini-Circuits T1­ 6T-KK81 1:1 transformer for the purposes of converting a single-ended (i.e., ground referenced) input signal to differen­ tial inputs. The following paragraphs identify three options for providing differential input signals to the AD8321 evaluation board. Option 1 uses a transformer to produce a truly differen­ tial input signal. The termination resistor(s) specified in Option 1 and 2 may also be used without the transformer if a differen­ tial signal source is available. Option 2 uses a transformer andproduces ground referenced input signals that are separated in phase by 180∞. Option 3 relies on differential signals provided by the user and does not employ a transformer for single-to­ differential conversion. Differential Input Option 1: Install the Mini-Circuits T1-6T­ KK81 1:1 transformer in the T1 location of the evaluation board. Jumpers J1, J2 and J3 should be applied pointing in the direction of the transformer. A differential input termination resistor of 82.5 W can be used in the R3 position. This value should be used when the single-ended input signal has a source impedance of 75 W. In this configuration, the input signal must be applied to the VIN+/DIFF IN port of the evaluation board. An open circuit is required in R1, R2 and J4 positions resulting in a 75 W differential input termination to the AD8321. If a 50 W single-ended input source is applied to the VIN+/DIFF IN port, the R3 value should be 53.6 W. Windows is a registered trademark of Microsoft Corporation. *Alpha Industries @ www.alphaind.com REV. A – 11– AD8321 Differential Input Option 2: Install the Mini-Circuits T1-6T­ KK81 1:1 transformer in the T1 location of the evaluation board. Jumpers J1, J2 and J3 should be applied pointing in the direction of the transformer. Apply an open circuit in the R3 position while J4 is applied connecting the center-tap of the secondary to ground. A 41 W resistor should be used between each input and ground at R1 and R2. This option will also result in a 75 W differential input termination to the AD8321. If a 50 W single-ended input source is applied to the VIN+/ DIFF IN port, the R1 and R2 values should be 26.7 W. Differential Input Option 3: A differential input may be applied to both VIN– and VIN+ inputs of the evaluation board. In this example, no transformer is employed. Jumpers J1, J2 and J3 are installed in line with the input signals. Select the differen­ tial input termination configuration of either Option 1 or Option 2. Apply Option 1 resistor value to R3 for a true differential input or apply Option 2 values to R1 and R2 to produce ground refer­ enced inputs that are separated in phase by 180∞. If the differen­ tial input signal source impedance is anything other than 75 W or 50 W, calculate the appropriate value according to the equa­ tions below: For Option 1 Configurations: Desired Input Impedance = R3�900 For Option 2 and 3 (R1 = R2 = R): Desired Input Impedance = 2 ¥ (R�450) DIFF IN T1 R3 Controlling the Evaluation Board from a PC The AD8321-EVAL package comes with the circuit described by Figure 28 and includes a –2 dB attenuator (reference Rc, Rd and Re) and the control software allowing the user to program the gain/attenuation of the AD8321 via a standard printer cable connected to the parallel port of a PC. Install Software To install the “CABDRIVE” software that controls the AD8321­ EVAL evaluation circuit, close all Windows applications and select the “SETUP” file located on Disk 1 of the AD8321­ EVAL software. Follow the on screen instructions (see Figure 29) and insert Disk 2 when prompted to do so. Enter the path of the directory into which the control software will be installed. Select the button in the upper left corner to begin the installa­ tion of “CABDRIVE” software into the specified directory. Running the Software To invoke the control software, select the “AD8321” icon from the directory containing the installed software. After invoking the control software, choose the appropriate printer port from the display portrayed in Figure 30. Controlling the Gain/Attenuation of AD8321 The AD8321 control panel has four different functions. The slide bar controls the gain/attenuation of the AD8321. Adjust the slider to the gain/attenuation displayed in units of dB. The additional displays show the selection in units of Volts (output)/ Volts (input), and the corresponding control codes in decimal, binary and hexadecimal. (See Figure 31.) “POWER UP” and “POWER DOWN” AD8321 OPTION 1 DIFFERENTIAL INPUT TERMINATION R2 DIFF IN T1 AD8321 R1 OPTION 2 DIFFERENTIAL INPUT TERMINATION R2 VIN+ The buttons marked “Power Up” and “Power Down” select the mode of operation of the AD8321. The “Power Up” button puts the AD8321 in forward transmit mode feeding the condi­ tioned signal to the VOUT port on the evaluation board. Con­ versely, the “Power Down” button selects the reverse mode where the forward signal transmission is disabled and the low noise reverse amplifier actively maintains a 75 W back termina­ tion. These features may be selected asynchronously (at any time). (See the section on Between Burst Transient Reduction for more specific details.) Enable Output Switch AD8321 VIN– R1 OPTION 3 DIFFERENTIAL INPUT TERMINATION Figure 27. Differential Input Termination Options An Alpha Industries AS128-73 GaAs 2W Hi Linearity switch is installed on a standard AD8321-EVAL circuit and is controlled by the check box on the control panel portrayed in Figure 31. This feature is intended to remove the output of the AD8321 from the VOUT port prior to using the “Power Up” and “Power Down” feature described above. This application circuit may be used to reduce any transients created between bursts to DOCSIS compliant levels. (See the section on Between Burst Transient Reduction for more specific details.) – 12– REV. A AD8321 TP1 J3 VIN– R1 82.5� TP4 VCC P1–5 P1–6 P1–2 SDATA CLK TP6 TP7 1 20 19 18 C1 0.1�F C10 R6 C12 1000pF 2 3 4 DATEN TP8 C11 C4 P1–3 PD TP9 C7 C8 VCT C15 0.1�F C14 10�F Jb TP5 GND VCC C10 0.1�F R8 1k� C16 1000pF C6 10�F TPc TPa C9 AD8321 17 16 15 14 13 12 11 C2 0.1�F 5 6 7 8 9 10 C5 NOTE: BYPASS CAPACITORS C4, C5, C7, C8, C9, C10 AND C11 ARE 0.1�F. TPd Cc 0.1�F Cd 0.1�F Re Cb 0.1�F Rb 75� AS128-73 SWb V1 b TP12 Vct Rf 10k� TO DIPLEXER Rd Rc TPe TP13 V2 Ce 0.1�F P1–8 V1 P1–7 V2 R9 1k� C17 1000pF Figure 28. AD8321-EVAL Schematic of Single-Ended Inverting Input, Upstream PA Driver Solution Using AD8321, Matching Attenuator and Alpha Industries AS128-73 RF Switch REV. A – 13– AD8321 EVALUATION BOARD FEATURES AND OPERATION Figure 29. Evaluation Board Software Installation Figure 30. Evaluation Board Control Software – 14– REV. A AD8321 Figure 31. Screen Display of Windows-Based Control Software REV. A – 15– AD8321 Figure 32. Evaluation Board Silkscreen (Component Side) – 16– REV. A AD8321 Figure 33. Evaluation Board Layout (Component Side) Figure 34. Evaluation Board Layout (Solder Side) REV. A – 17– AD8321 EVALUATION BOARD BILL OF MATERIALS AD8321 Evaluation Board Rev. B SINGLE- ENDED INVERTING INPUT March 17, 1999 Qty. 2 14 3 1 3 2 1 2 1 1 1 2 1 6 2 3 1 2 2 5 2 1 4 1 1 4 4 2 2 2 2 Description 10 mF 16 V. 1350 size tantalum chip capacitor 0.1 mF 50 V. 1206 size ceramic chip capacitor 1,000 pF 50 V. 1206 size ceramic chip capacitor 82.5 W 1% 1/8 W. 1206 size chip resistor 0 W 5% 1/8 W. 1206 size chip resistor 1.00 kW 1% 1/8 W. 1206 size chip resistor 75.0 W 1% 1/8 W. 1206 size chip resistor 649 W 1% 1/8 W. 1206 size chip resistor 10.0 kW 1% 1/8 W. 1206 size chip resistor 17.4 W 1% 1/8 W. 1206 size chip resistor Alpha # AS 128-73 GaAs Hi Linearity switch Pink Test Point Blue Test Point [Vct] Grey Test Point [Bus lines] Yellow Test Point [INPUTS] Orange Test Point [OUTPUTS] Red Test Point [DUT VCC] Black Test Point [GND] 2 pin .1 inch ctr. shunt Berg # 65474 - 001 2 pin .1 inch ctr. male Header Berg # 69157 - 102 75 W right-angle BNC Telegartner # J01003A1949 Conn. 36 pin Centronics Right Angle 5-way Metal Binding Post AD8321 AR AD8321 REV. B Evaluation PC board #4 - 40 ¥ 1/4 inch ss panhead machine screw #4 - 40 ¥ 3/4 inch long aluminum round stand-off # 2 - 56 ¥ 3/8 inch ss panhead machine screw # 2 steel flat washer # 2 steel internal tooth lockwasher # 2 ss hex. machine nut Vendor ADS# 4-7-6 ADS# 4-5-18 ADS# 4-5-20 D -K # P 82.5 FCT-ND ADS# 3-18- 88 ADS# 3-18-11 ADS# 3-18-145 D -K # P 649 FCT-ND ADS# 3-18-119 D -K # P17.4 FCT-ND Alpha # AS 128-73 ADS# 12-18-63 ADS# 12-18-62 ADS# 12-18-64 ADS# 12-18-32 ADS# 12-18-60 ADS# 12-18-43 ADS# 12-18-44 ADS# 11-2-38 ADS# 11-2-37 Comp. Mktg. Services ADS# 12-3-50 ADS# 12-7-7 ADS# AD8321AR E.M.C. ADS# 30-1-1 ADS# 30-16-3 ADS# 30-1-17 ADS# 30-6-6 ADS# 30-5-2 ADS# 30-7-6 Ref Desc. C6 & C14 C1–C5, C7–C11, Cb–e C12, C16 & C17 R1 R2 & R6, Ca R8 & 9 Rb Rc & Re Rf Rd SWb TPc & TPd TP14 TP6–TP9, TP12 & TP13 TP1 & TP2 TPa, TPb & TPe TP4 TP5 & TP15 J3 & Jb J3, Ja, Jb, Jc, Jd INPUTS, OUTPUT P1 DUT VCC, GND, Vct D.U.T. Evaluation PC board (p1 hardware) (p1 hardware) (p1 hardware) (p1 hardware) Optional Components J1, J2, J4, R3, Ra, SWa, T1, +VIN+ – 18– REV. A AD8321 OUTLINE DIMENSIONS 20-Lead Standard Small Outline Package [SOIC_W] Wide Body (R-20) Dimensions shown in millimeters and (inches) Revision History Location 6/05—Data Sheet Changed from REV. 0 to REV. A. Page Changes to ORDERING GUIDE .................................................................................................................................................... 4 Updated OUTLINE DIMENSIONS ............................................................................................................................................. 19 REV. A – 19– –20– C01013–0–6/05(A)