a
5 V CATV Line Driver
Coarse Step Output Power Control
AD8322
FEATURES
Supports DOCSIS Standard for Reverse Path
Transmission
Gain Programmable in 6 dB Steps Over a 42 dB
Range
Low Distortion at 60 dBmV Output
–58 dBc SFDR at 21 MHz
–56 dBc SFDR at 42 MHz
Output Noise Level
–46 dBmV in 160 kHz Bandwidth
Maintains 75 ⍀ Output Impedance
Power-Up and Power-Down Condition
180 MHz Bandwidth
5 V Supply Operation
Supports SPI Interfaces
FUNCTIONAL BLOCK DIAGRAM
VCC (7 PINS)
R1
VIN+
AD8322
VOUT+
DIFF
OR SINGLE
INPUT
AMP
VIN–
BUFFER
ATTENUATION
CORE
POWER
AMP
8
DECODE
TE
R2
ZIN (SINGLE) = 210⍀
ZIN (DIFF) = 235⍀
VOUT–
ZOUT DIFF =
75⍀
8
POWER-DOWN
LOGIC
DATA LATCH
8
SHIFT
REGISTER
DATEN
DATA CLK
GND (12 PINS)
PD
B
SO
LE
APPLICATIONS
Gain Programmable Line Driver
DOCSIS-Compliant Data Modems
Interactive Set-Top Boxes
PC Plug-in Modems
General-Purpose Digitally Controlled Variable Gain Block
–55
GENERAL DESCRIPTION
O
The AD8322 comprises a digitally controlled variable attenuator
of 0 dB to –42.14 dB, which is preceded by a low-noise, fixed-gain
buffer and is followed by a low-distortion, high-power amplifier. The AD8322 accepts a differential or single-ended input
signal. The output is specified for driving a 75 Ω load, such as
coaxial cable.
Distortion performance of –58 dBc is achieved with an output level
up to 60 dBmV at 21 MHz bandwidth. A key performance and
cost advantage of the AD8322 results from the ability to maintain
a constant 75 Ω output impedance during power-up and powerdown conditions. This eliminates the need for external 75 Ω
termination resulting in twice the effective output voltage when
compared to a standard operational amplifier.
fO = 42MHz
VO = 60dBmV
@ MAX GAIN
–60
DISTORTION – dBc
The AD8322 is a low-cost, digitally controlled variable gain amplifier optimized for coaxial line driving applications such as cable
modems that are designed to the MCNS-DOCSIS upstream
standard. An 8-bit serial word determines the desired output
gain over a 42.14 dB range, with gain steps of 6.02 dB/major
carry.
HD3
–65
HD2
–70
–75
1
2
4
8
16
32
GAIN CODE – Decimal
64
128
Figure 1. Harmonic Distortion vs. Gain Control
The AD8322 is packaged in a low-cost 28-lead TSSOP, operates
from a single 5 V supply, and has an operational temperature
range of –40°C to +85°C.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
(TA = 25ⴗC, VS = 5 V, RL = RIN = 75 ⍀, VIN = 92 mV p-p differential, VOUT measured through
AD8322–SPECIFICATIONS a 1:1 transformer with insertion loss of 0.5 dB @ 10 MHz unless otherwise noted)
1
Parameter
Conditions
INPUT CHARACTERISTICS
Specified AC Voltage
Noise Figure
Input Resistance
Min
POUT = 60 dBmV, Max Gain
Max Gain, f = 10 MHz
Single-Ended Input
Differential Input
OVERALL PERFORMANCE
Second Order Harmonic Distortion2
180
0.25
0.05
–32
–46
–68
19
75 ± 20%
Gain Linearity Error
Output Settling to 1 mV
Due to Gain Change
Due to Input Change
Signal Feedthrough
O
POWER CONTROL
Power-Up Settling Time to 1 mV
Power-Down Settling Time to 1 mV
Between Burst Transients3
POWER SUPPLY
Operating Range
Quiescent Current
dB
dB
dB
dB/Major Carry
MHz
dB
dB
dBmV in 160 kHz BW
dBmV in 160 kHz BW
dBmV in 160 kHz BW
dBm
Ω
f = 5 MHz, POUT = 60 dBmV @ Max Gain
f = 14 MHz, POUT = 60 dBmV @ Max Gain
f = 21 MHz, POUT = 60 dBmV @ Max Gain
f = 32 MHz, POUT = 60 dBmV @ Max Gain
f = 42 MHz, POUT = 60 dBmV @ Max Gain
f = 65 MHz, POUT = 60 dBmV @ Max Gain
f = 5 MHz, POUT = 60 dBmV @ Max Gain
f = 14 MHz, POUT = 60 dBmV @ Max Gain
f = 21 MHz, POUT = 60 dBmV @ Max Gain
f = 32 MHz, POUT = 60 dBmV @ Max Gain
f = 42 MHz, POUT = 60 dBmV @ Max Gain
f = 65 MHz, POUT = 60 dBmV @ Max Gain
f = 10 MHz, Code to Code
–64
–60
–58
–57
–56
–52
–67
–64
–61
–58
–56
–53
± 0.2
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dB
Min to Max Gain
Max Gain, VIN = 0 V to 0.09 V p-p
Max Gain, Power-Down, f = 42 MHz,
VIN = 0.09 V p-p
60
30
–24
ns
ns
dBc
Max Gain, VIN = 0
Max Gain, VIN = 0
Equivalent POUT = 17.6 to 35.67 dBmV
Equivalent POUT = 60 dBmV
300
40
3
16
ns
ns
mV p-p
mV p-p
B
SO
Third Order Harmonic Distortion
All Gain Codes
f = 65 MHz
f = 65 MHz
Max Gain, f = 10 MHz
Min Gain, f = 10 MHz
Power-Down Mode, f = 10 MHz
Max Gain, f = 10 MHz
Power-Up and Power-Down
43.2
31.5
–10.64
TE
1 dB Compression Point
Differential Output Impedance
41.0
42.14
27.5
29.5
–14.64 –12.64
6.02
Gain Code = 1xxxxxxx
Gain Code = 00000001
Unit
mV p-p
dB
Ω
Ω
pF
LE
OUTPUT CHARACTERISTICS
Bandwidth (–3 dB)
Bandwidth Roll-Off
Bandwidth Peaking
Output Noise
Max
92
11.8
210
235
2
Input Capacitance
GAIN CONTROL INTERFACE
Gain Range
Maximum Gain
Minimum Gain
Gain Scaling Factor
Typ
4.75
100
44
Power-Up Mode
Power-Down Mode
OPERATING TEMPERATURE
RANGE
5
113
54
–40
5.25
126
60
V
mA
mA
+85
°C
NOTES
1
TOKO # 617 DB-A0070 used for above specifications. MACOM ETC-1-IT-15 can be substituted.
2
All distortion measurements taken with differential input signal and represent worst distortion across all gain codes.
3
Between burst transients measured at the output of PULSE B5008 42 MHz diplexer.
Specifications subject to change without notice.
–2–
REV. 0
AD8322
LOGIC INPUTS (TTL/CMOS Compatible Logic)
(DATEN, CLK, SDATA, PD, VCC = 5 V: Full Temperature Range)
Parameter
Min
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current (VINH = 5 V) CLK, SDATA, DATEN
Logic “0” Current (VINL = 0 V) CLK, SDATA, DATEN
Logic “1” Current (VINH = 5 V) PD
Logic “0” Current (VINL = 0 V) PD
2.1
0
0
–600
50
–250
TIMING REQUIREMENTS (Full Temperature Range, V
CC
Clock Pulsewidth (TWH)
Clock Period (TC)
Setup Time SDATA vs. Clock (TDS)
Setup Time DATEN vs. Clock (TES)
Hold Time SDATA vs. Clock (TDH)
Hold Time DATEN vs. Clock (TEH)
Input Rise and Fall Times, SDATA, DATEN, Clock (TR, TF)
16.0
32.0
5.0
15.0
5.0
3.0
VALID DATA WORD G2
TC
TWH
CLK
V
V
nA
nA
µA
µA
Max
10
Unit
ns
ns
ns
ns
ns
ns
ns
TEH
Decimal
Gain Code
8-Bit SPI Data Word
MSB
LSB
Nominal Gain (dB)
1
2
4
8
16
32
64
128
00000001
00000010
00000100
00001000
00010000
00100000
01000000
1xxxxxxx
–12.64
–6.62
–0.60
5.42
11.44
17.46
23.48
29.50
B
SO
TES
8 CLOCK CYCLES
GAIN TRANSFER (G1)
GAIN TRANSFER (G2)
TOFF
TGS
0 = low, 1 = high, x = don’t care.
TON
PEDESTAL
SIGNAL AMPLITUDE (p-p)
O
Figure 2. Serial Interface Timing
VALID DATA BIT
SDATA MSB
MSB-1
TDS
MSB-2
TDH
CLK
Figure 3. SDATA Timing
REV. 0
Typ
LE
VALID DATA WORD G1
MSB. . . .LSB
ANALOG
OUTPUT
5.0
0.8
20
–100
190
–30
Table I. Gain vs. Gain Code
TDS
PD
Unit
TE
Min
DATEN
Max
= 5 V, TR = TF = 4 ns, fCLK = 8 MHz unless otherwise noted.)
Parameter
SDATA
Typ
–3–
AD8322
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
Supply Voltage +VS
Pins 6, 8, 9, 20, 21, 23, 27 . . . . . . . . . . . . . . . . . . . . . . . 6 V
Input Voltages
Pins 25, 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 0.5 V
Pins 1, 2, 3, 7 . . . . . . . . . . . . . . . . . . . . . . . –0.8 V to +5.5 V
Internal Power Dissipation
TSSOP (RU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.90 W
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature, Soldering 60 seconds . . . . . . . . . . . 300°C
1
28
GND
CLK
2
27
VCC
DATEN
3
26
VIN–
GND
4
25
VIN+
BYP
5
24
GND
VCC
6
23
VCC
PD
7
VCC
8
VCC
AD8322
GND
TOP VIEW
(Not to Scale) 21 VCC
22
9
20
VCC
OUT– 10
19
OUT+
GND 11
18
GND
GND 12
17
GND
GND 13
16
GND
GND 14
15
GND
TE
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
SDATA
ORDERING GUIDE
Temperature Range
Package Description
JA
Package Option
AD8322ARU
AD8322ARU-REEL
AD8322-EVAL
–40°C to +85°C
–40°C to +85°C
28-Lead TSSOP
28-Lead TSSOP
Evaluation Board
67.7°C/W*
67.7°C/W*
RU-28
RU-28
LE
Model
*Thermal Resistance measured on SEMI standard 4-layer board.
B
SO
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8322 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN FUNCTION DESCRIPTIONS
Pin No.
1
3
SDATA
GND
Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the internal
register with the MSB (Most Significant Bit) first.
Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-slave
register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to the slave.
This requires the input serial data word to be valid at or before this clock transition.
Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0-to-1
transition transfers the latched data to the attenuator core (updates the gain) and simultaneously inhibits
serial data transfer into the register. A 1-to-0 transition inhibits the data latch (holds the previous gain
state) and simultaneously enables the register for serial data load.
Common External Ground Reference.
BYP
VCC
Internal Bypass. This pin must be externally ac-decoupled (0.1 µF capacitor).
Common Positive External Supply Voltage. A 0.1 µF capacitor must decouple each pin.
PD
OUT–
OUT+
VIN+
Logic “0” powers down the part. Logic “1” powers up the part.
Negative Output Signal.
Positive Output Signal.
Noninverting Input. DC-biased to approximately V CC/2. Refer to Applications section for proper
termination.
Inverting Input. DC-biased to approximately VCC/2. Refer to Applications section for proper termination.
CLK
4, 11, 12, 13,
14, 15, 16, 17,
18, 22, 24, 28
5
6, 8, 9, 20,
21, 23, 27
7
10
19
25
26
Description
DATEN
O
2
Mnemonic
VIN–
–4–
REV. 0
Typical Performance Characteristics– AD8322
5V
10F
0.1F
0.1F
75⍀
VCC
0.1F
VIN+
+1/2 VIN
OUT+
AD8322
432⍀
75⍀
OUT–
VIN–
0.1F
–1/2 VIN
BYP
+
75⍀ VO
–
CL
0.1F
GND
1:1
TOKO
617DB-A0070
TE
0.1F
DEVICE UNDER TEST
TPC 1. Test Circuit
32
0.15
PO = 60dBmV
@ MAX GAIN
0.10
CL = 0pF
f = 5MHz
–0.05
f = 42MHz
–0.10
f = 65MHz
–0.15
–0.25
–0.30
–0.35
1
B
SO
–0.20
GAIN – dB
30
0.00
2
4
8
16
32
GAIN CONTROL – Decimal
64
36
GC64
O
GC32
GAIN – dB
18
GC16
12
GC8
6
GC4
0
GC2
–6
GC1
–12
–18
CL = 20pF
1
10
FREQUENCY – MHz
100
TPC 4. AC Response for Various Capacitor Loads
f = 10MHz
PD = 1
–32
–36
–40
–44
–48
1
10
100
FREQUENCY – MHz
1k
1
2
4
8
16
32
64
GAIN CODE – Decimal
TPC 3. AC Response vs. Gain Control
REV. 0
24
GC128
24
CL = 10pF
CL = 50pF
128
TPC 2. Gain Error vs. Gain Control
30
28
26
OUTPUT NOISE – dBmV in 160 kHz BW
GAIN ERROR – dB
0.05
LE
f = 10MHz
TPC 5. Output Noise vs. Gain Code
–5–
128
AD8322
170
0
PD = 0
170
–10
PD = 1
FEEDTHROUGH – dBc
–20
150
MAX GAIN
PD = 0
IMPEDANCE – ⍀
–30
–40
–50
MIN GAIN
–60
130
110
90
–70
70
–80
GAIN CODE 0
50
–90
10
100
FREQUENCY – MHz
1
30
1k
TPC 6. Input Signal Feedthrough vs. Frequency
150
PO = 60dBmV
at MAX GAIN
–55
–60
125
IMPEDANCE – ⍀
DISTORTION – dBc
–50
LE
PO = 62dBmV
at MAX GAIN
B
SO
PO = 58dBmV
at MAX GAIN
15
25
35
45
55
FUNDAMENTAL FREQUENCY – MHz
65
TPC 7. Second Order Harmonic Distortion vs.
Frequency for Various Output Levels
–45
1k
TPC 9. Input Impedance vs. Frequency (Inputs Shunted
with 432 Ω)
–45
–65
5
10
100
FREQUENCY – MHz
1
TE
–100
100
75
PD = 0
PD = 1
50
25
0.1
1
10
FREQUENCY – MHz
100
1k
TPC 10. Output Impedance vs. Frequency
PO = 62dBmV
at MAX GAIN
DISTORTION – dBc
O
–50
–55
PO = 60dBmV
at MAX GAIN
–60
–65
PO = 58dBmV
at MAX GAIN
–70
–75
5
15
25
35
45
55
FUNDAMENTAL FREQUENCY – MHz
65
TPC 8. Third Order Harmonic Distortion vs. Frequency
for Various Output Levels
–6–
REV. 0
AD8322
The AD8322 is primarily intended for use as the upstream power
amplifier (PA) in DOCSIS (Data Over Cable Service Interface
Specifications) certified cable modems and CATV set-top boxes.
Upstream data is modulated in QPSK or QAM format. This is
done with DSP or a dedicated QPSK/QAM modulator. The
amplifier receives its input signal from the QPSK/QAM modulator or from a DAC. In either case the signal must be low-pass
filtered before being applied to the amplifier. Because the distance
from the cable modem to the central office will vary with each
subscriber, the AD8322 must be capable of varying its output
power by applying gain or attenuation to ensure that all signals
arriving at the central office are of the same amplitude. The
upstream signal path contains components such as a transformer
and diplexer that will result in some amount of power loss. Therefore, the amplifier must be capable of providing enough power
into a 75 Ω load to overcome these losses without sacrificing the
integrity of the output signal.
from decimal 1–128 (decimal values 1, 2, 4, 8, 16, 32, 64, 128).
The resulting gain for each code can be seen in Table I. Although
the AD8322 is designed for use with the previous eight codes,
the intermediate codes can be used.
The gain transfer function is as follows:
AV = 20 × LOG (0.2332 × CODE) for 1 ≤ CODE ≤ 128
AV = 29.5 dB for CODE ≥ 128
where AV is the gain in dB and CODE is the decimal equivalent
of the 8-bit word.
Figure 4 shows the gain characteristic for all possible values
(except 0) in an 8-bit word. Code 0 may be used if more
feedthrough isolation is required. It typically provides –85 dB of
isolation across the 5 MHz to 65 MHz upstream band.
TE
APPLICATIONS
General Application
35
30
25
20
Operational Description
GAIN – dB
15
10
LE
The AD8322 is composed of three analog functions in the powerup or forward mode. The input amplifier (preamp) can be used
single-ended or differentially. If the input is used in the differential configuration, it is imperative that the input signals be 180
degrees out of phase and of equal amplitudes. This will ensure
the proper gain accuracy and harmonic performance. The preamp
stage drives a DAC, which provides the bulk of the AD8322’s
attenuation (7 bits or 42.14 dB). The signals in the preamp and
DAC gain blocks are differential to improve the PSRR and linearity. A differential current is fed from the DAC into the output
stage, which amplifies these currents to the appropriate levels
necessary to drive a 75 Ω load. The output stage utilizes negative
feedback to implement a differential 75 Ω output impedance.
This eliminates the need for external matching resistors.
0
–5
–10
–15
–20
B
SO
SPI Programming and Gain Adjustment
REV. 0
0
32
64
96
128
160
GAIN CODE – Decimal
192
224
256
Figure 4. Gain vs. Gain Code
Input Bias, Impedance, and Termination
The VIN+ and VIN– inputs have a dc bias level of approximately
VCC/2, therefore the input signal should be ac-coupled. The
differential input impedance is approximately 235 Ω while the
single-ended input impedance is 210 Ω. If the AD8322 is being
operated in a single-ended input configuration with a desired
input impedance of 75 Ω, the VIN+ and VIN– inputs should be
terminated as shown in Figure 5. For input impedances other
than 75 Ω, the value of R1 in Figure 5 can be calculated using
the following equation:
O
Gain programming of the AD8322 is accomplished using a serial
peripheral interface (SPI) and three digital control lines, DATEN,
SDATA, and CLK. To change the gain, eight bits of data are
streamed into the serial shift register through the SDATA port.
The SDATA load sequence begins with a falling edge on the
DATEN pin, thus activating the CLK line. Although the CLK
line is now activated, no change in gain is observed. With the
CLK line activated, data on the SDATA line is clocked into the
serial shift register, Most Significant Bit (MSB) first, on the
rising edge of each CLK pulse. A rising edge on the DATEN line
latches the contents of the shift register into the attenuator core
resulting in a well-controlled change in the output signal level.
The serial interface timing for the AD8322 is shown in Figures 2 and 3. The programmable gain range of the AD8322 is
–12.64 dB to +29.5 dB and scales 6.02 dB for each major carry.
Because the AD8322 was characterized with a TOKO transformer,
the stated gain values already take into account the losses associated with the transformer. Valid gain codes are the major carries
5
Z IN = R1 210
ZIN = 75⍀
R1 = 118⍀
AD8322
Figure 5. Single-Ended Input Termination
–7–
AD8322
5V
10F
25V
2
3
DATEN
0.1F
0.1F
PD
0.1F
0.1F
4
5
6
7
8
9
10
11
12
13
14
0.1F
AD8322TSSOP
SDATA
CLK
28
PD
VCC1
VCC2
OUT–
GND2
GND3
GND4
GND5
GND12
VCC6
VIN–
VIN+
GND11
VCC5
GND10
VCC4
VCC3
OUT+
GND9
GND8
GND7
GND6
0.1F
0.1F
DATEN
GND1
BYP
VCC
VIN–
0.1F
27
26
25
ZIN = 150⍀
432⍀
24
23
0.1F
0.1F
VIN+
22
21
20
0.1F
19
0.1F
18
17
16
15
TE
1
SDATA
CLK
TOKO 617DB-A0070
TO DIPLEXER
ZIN = 75⍀
Output Bias, Impedance, and Termination
LE
Figure 6. Typical Applications Circuit
minimize coupling (crosstalk) through the board. Following these
guidelines will improve the overall performance of the AD8322
in all applications.
The differential output pins VOUT+ and VOUT– are also biased to
a dc level of approximately VCC/2. Therefore, the outputs should
be ac-coupled before being applied to the load. This may be
accomplished by connecting 0.1 µF capacitors in series with the
outputs as shown in the typical applications circuit of Figure 6.
The differential output impedance of the AD8322 is internally
maintained at 75 Ω, regardless of whether the amplifier is in
forward transmit mode or reverse power-down mode, eliminating the need for external back termination resistors. A 1:1
transformer (TOKO #617DB-A0070) is used to couple the
amplifier’s differential output to the coaxial cable while maintaining a proper impedance match. If the output signal is being
evaluated on standard 50 Ω test equipment, a 75 Ω to 50 Ω
pad must be used to provide the test circuit with the correct
impedance match.
Initial Power-Up
B
SO
When the 5 V supply is first applied to the VCC pins of the
AD8322, the gain setting of the amplifier is indeterminate.
Therefore, as power is first applied to the amplifier, the PD pin
should be held low (Logic 0) thus preventing forward signal
transmission. After power has been applied to the amplifier, the
gain can be set to the desired level by following the procedure in
the SPI Programming and Gain Adjustment section. The PD pin
can then be brought from Logic 0 to 1, enabling forward signal
transmission at the desired gain level.
Asynchronous Power-Down
The asynchronous PD pin is used to place the AD8322 into
“Between Burst” mode while maintaining a differential output
impedance of 75 Ω. Applying a Logic 0 to the PD pin activates
the on-chip reverse amplifier, providing a 52% reduction in consumed power. The supply current is reduced from approximately
113 mA to approximately 54 mA. In this mode of operation,
between burst noise is minimized and the amplifier can no longer
transmit in the upstream direction.
Power Supply Decoupling, Grounding, and Layout
Considerations
O
Careful attention to printed circuit board layout details will
prevent problems due to associated board parasitics. Proper RF
design technique is mandatory. The 5 V supply power should be
delivered to each of the VCC pins via a low impedance power bus
to ensure that each pin is at the same potential. The power bus
should be decoupled to ground with a 10 µF tantalum capacitor
located in close proximity to the AD8322. In addition to the
10 µF capacitor, each VCC pin should be individually decoupled
to ground with a 0.1 µF ceramic chip capacitor located as close
to the pin as possible. The pin labeled BYP (Pin 5) should also
be decoupled with a 0.1 µF capacitor. The PCB should have a
low impedance ground plane covering all unused portions of the
component side of the board, except in the area of the input and
output traces (see Figure 11). It is important to connect all of
the AD8322 ground pins to ensure proper grounding of all
internal nodes. The differential input and output traces should
be kept as short and as symmetrical as possible. In addition, the
input and output traces should be kept far apart in order to
Distortion, Adjacent Channel Power, and DOCSIS
In order to deliver 58 dBmV of high-fidelity output power
required by DOCSIS, the PA should be able to deliver about
60 to 61 dBmV in order to make up for losses associated with the
transformer and diplexer. It should be noted that the AD8322
was characterized with the TOKO 617DB-A0070 transformer.
TPC 7 and TPC 8 show the AD8322 second and third harmonic
distortion performance versus fundamental frequency for various output power levels. These figures are useful for determining
the in-band harmonic levels from 5 MHz to 65 MHz. Harmonics
higher in frequency will be sharply attenuated by the low-pass
filter function of the diplexer. Another measure of signal integrity is adjacent channel power or ACP. DOCSIS section 4.2.9.1.1
states, “Spurious emissions from a transmitted carrier may occur
–8–
REV. 0
AD8322
in an adjacent channel which could be occupied by a carrier of
the same or different symbol rates.” Figure 7 shows the measured
ACP, for a 16 QAM, 60 dBmV signal, taken at the output of the
AD8322 evaluation board (see Figure 13 for evaluation board
schematic). The transmit channel width and adjacent channel
width in Figure 7 correspond to symbol rates of 160 KSYM/SEC.
Table II shows the ACP results for the AD8322 for all conditions
in DOCSIS Table 4-7 “Adjacent Channel Spurious Emissions.”
RBW 500Hz RF ATT 40dB
VBW 5kHz
SWT 12s UNIT dBm
–10
CH PWR 5.39dBm
ACP UP –54.22dB
ACP LOW –56.84dB
–20
–30
The AD8322 evaluation board (Part # AD8322-EVAL) and
control software can be used to control the AD8322 upstream
cable driver via the parallel port of a PC. A standard printer cable
connected between the parallel port and the evaluation board is
used to feed all the necessary data to the AD8322 by means of the
Windows® based, Microsoft Visual Basic control software. This
package provides a means of evaluating the amplifier by providing a convenient way to program the gain/attenuation as well
as offering easy control of the amplifiers asynchronous PD pin.
With this evaluation kit the AD8322 can be evaluated with either
a single-ended or differential input configuration. The amplifier
can also be evaluated with or without the PULSE diplexer in the
output signal path. To remove the diplexer from the signal path,
move the two 0 Ω chip resistors R18 and R10 to locations R11 and
R20. A schematic of the evaluation board is provided in Figure 13.
TE
–40
Evaluation Board Features and Operation
Overshoot on PC Printer Ports
–50
The data lines on some PC parallel printer ports have excessive
overshoot that may cause communications problems when presented to the CLK pin of the AD8322 (TP5 on the evaluation
board). The evaluation board was designed to accommodate
a series resistor and shunt capacitor (R1 and C15) to filter the
CLK signal if required.
–60
C0
–70
C0
CU1
CL1
CU1
CL1
–80
F1
60kHz
SPAN 600kHz
LE
CENTER 10MHz
Transformer and Diplexer
Figure 7. Adjacent Channel Power
Table II. ACP Performance for All DOCSIS Conditions
(All Values in dBc)
160 KSYM/SEC
320 KSYM/SEC
640 KSYM/SEC
1280 KSYM/SEC
2560 KSYM/SEC
B
SO
ADJACENT CHANNEL SYMBOL RATE
TRANSMIT
CHANNEL
SYMBOL RATE 160 KSYM/SEC 320 KSYM/SEC 640 KSYM/SEC 1280 KSYM/SEC 2560 KSYM/SEC
A 1:1 transformer is needed to couple the differential outputs of
the AD8322 to the cable while maintaining a proper impedance
match. The specified transformer is available from TOKO (Part
# 617DB-A0070), however, MA/COM part # ETC-1-1T-15
can also be used. The evaluation board is equipped with the
TOKO transformer, but is also designed to accept the MA/COM
transformer. The PULSE diplexer included on the evaluation
board provides a high-order low-pass filter function, typically
used in the upstream path. The ability of the PULSE diplexer to
achieve DOCSIS compliance is neither expressed nor implied by
Analog Devices Inc. Data on the diplexer should be obtained
from PULSE.
–54.2
–54.7
–55.4
–56.6
–55.9
–53.8
–54.6
–54.6
–55.1
–54.8
–54.0
–54.1
–54.5
–54.4
–54.1
–53.9
–54.1
–53.9
–54.3
–53.7
–54.2
–54.2
–54.2
–53.8
–53.5
Differential Inputs
At minimum gain, the AD8322’s output noise spectral density is
12 nV/√Hz measured at 10 MHz. DOCSIS Table 4-8, “Spurious
Emissions in 5 MHz to 42 MHz” specifies the output noise for
various symbol rates. The calculated noise power in dBmV for
160 KSYM/SEC is:
The AD8322-EVAL evaluation board is designed to accommodate a Mini-Circuits T1-6T-KK81 1:1 transformer for the purpose
of converting a single-ended (ground referenced) input signal to
differential inputs. Figure 8 and the following paragraphs identify three options for providing differential input signals to the
AD8322 evaluation board.
O
Noise and DOCSIS
2
20 log 12 nV × 160 kHz + 60 = –46.4 dBmV
Hz
Comparing the computed noise power of –46.4 dBmV to the
8 dBmV signal yields –54.4 dBc, which meets the required level
of –53 dBc set forth in DOCSIS Table 4-8. As the AD8322’s
gain is increased from this minimum value, the output signal
increases at a faster rate than the noise, resulting in a signal-tonoise ratio that improves with gain. In transmit disable mode
the output noise spectral density computed over 160 KSYM/SEC is
1.0 nV/√Hz or –68 dBmV.
Windows is a registered trademark of Microsoft Corporation.
REV. 0
–9–
AD8322
Single-Ended-to-Differential Input (Figure 8 Option 1)
Installing the Visual Basic Control Software
Install the Mini-Circuits T1-6T-KK81 1:1 transformer in the T1
location of the evaluation board. Install 0 Ω chip resistors in R12,
R13, and R17, and leave R14, R16, and R19 open. For 75 Ω
input impedance, install a 110 Ω resistor in R7 located on the back
side of the evaluation board and leave R5 and R6 open. In this
configuration the input signal must be applied to the VIN+ port of
the evaluation board from a single-ended 75 Ω signal source. For
input impedances other than 75 Ω, use the following equation
to compute the correct value for R7.
To install the “CABDRIVE_22” evaluation board control software, first close all Windows applications and run “SETUP.EXE”
located on Disk 1 of the AD8322 Evaluation Software. Follow
the on-screen instructions and insert Disk 2 when prompted to
do so. Enter the path of the directory into which the software
will be installed and select the button in the upper left corner to
complete the installation.
Single-Ended-to-Differential Input (Figure 8 Option 2)
Install the Mini-Circuits T1-6T-KK81 1:1 transformer in the T1
location of the evaluation board. Install 0 Ω chip resistors in R12,
R13, R17, and R19, and leave R14 and R16 open. For 75 Ω input
impedance, install 55 Ω resistors in R5 and R6 located on the back
side of the evaluation board and leave R7 open. In this configuration the input signal must be applied to the VIN+ port of the
evaluation board from a single-ended 75 Ω signal source. For
input impedances other than 75 Ω, use the following equation
to compute the correct values for R5 and R6.
Differential Input (Figure 8 Option 3)
The slide bar controls the AD8322’s gain/attenuation, which is
displayed in dB and in V/V. Although the AD8322 is designed
for use at the eight gain codes described in the SPI Programming
and Gain Adjustment section, all of the intermediate codes are
included in the software. Code 0 is also included because of the
high isolation it provides. The gain code (i.e., position of the slide
bar) is displayed in decimal, binary, and hexadecimal (see
Figure 9).
POWER-UP AND POWER-DOWN
The “Power-Up” and “Power-Down” buttons select the mode of
operation of the AD8322 by controlling the logic level on the
asynchronous PD pin. The “Power-Up” button applies a Logic
1 to the PD pin putting the AD8322 in forward transmit mode.
The “Power-Down” button applies a Logic 0 to the PD pin selecting reverse mode, where the forward signal transmission is disabled
while a back termination of 75 Ω is maintained.
B
SO
If a differential signal source is available, it may be applied directly
to both the VIN+ and VIN– input ports of the evaluation board. In
this case, install 0 Ω chip resistors in R8, R14, R15, and R16, and
leave R12, R13, and R19 open. Referring to Figure 8 Option 3 and
the AD8322 evaluation board, a differential input impedance
of 150 Ω can be achieved by installing a 432 Ω resistor in R7,
leaving R5 and R6 open. If another input impedance is desired,
the following equation can be used to compute the correct
value for R7.
Desired Input Impedance = R7储235
DIFF IN
Controlling the Gain/Attenuation of the AD8322
LE
R5 = R6 = R, Desired Input Impedance = 2 × (R储117.5)
To invoke the control software, go to START -> PROGRAMS
-> CABDRIVE_22, or select the AD8322.EXE icon from the
directory containing the software.
TE
Desired Input Impedance = R7储235
Running the Software
R7
T1
AD8322
Memory Section
The “MEMORY” section of the software provides a convenient
way to alternate between two gain settings. The “X->M1” button stores the current value of the gain slide bar into memory
while the “RM1” button recalls the stored value, returning the
gain slide bar to that level. The “X->M2” and “RM2” buttons
work in the same manner.
OPTION 1 DIFFERENTIAL INPUT TERMINATION
O
R6
DIFF IN
T1
AD8322
R5
OPTION 2 DIFFERENTIAL INPUT TERMINATION
VIN+
R7
AD8322
VIN–
OPTION 3 DIFFERENTIAL INPUT TERMINATION
Figure 8. Differential Input Termination Options
–10–
REV. 0
B
SO
LE
TE
AD8322
O
Figure 9. Screen Display of Windows-Based Control Software
REV. 0
–11–
LE
TE
AD8322
O
B
SO
Figure 10. Evaluation Board—Assembly (Component Side)
Figure 11. Evaluation Board Layout (Component Side)
–12–
REV. 0
LE
TE
AD8322
O
B
SO
Figure 12. Evaluation Board—Solder Side
REV. 0
–13–
AD8322
RED
C2
0.1F
C6
0.1F
C5
0.1F
DATEN
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
TP4
R2
WHT 0⍀
TP6
TP1
WHT
SDATA
TP2
R1
WHT 0⍀
TP12
DNI C11
0.1F
TP5
TP17
C10
0.1F
WHT
6
T1
R17
DNI
S3
R16
0⍀
U2
C16
DNI
3
2
1
TP22
DNI
TOKO-B4F
4
5
5
1
1:1
NC = 2
4
1:1
T2A
DNI
VIN+
TP13
YEL
ETCC1-1T
3
R18
0⍀
TP21
HPP
DNI
S4
R10
0⍀
R11
DNI
R20
DNI
T2B
TP10
DNI
TP19
WHT
1:1
1
TP9
DNI
TP11
DNI
WHT
CLK
C15
DNI
R9
DNI
4
R15
0⍀
R6
0⍀
WHT
PD
C14
DNI
NC = 5
2
R7
118⍀ R12
DNI
C12
0.1F
S2
1
WHT
AMP-552742
3
R19
DNI
AD8322TSSOP
TP3
R13
DNI
R5
DNI
9 PULSEB5008
0.1F
0.1F
VIN–
B
C4
C7
R8
0⍀
A–B
0.1F
O
–14–
Figure 13. Evaluation Board Schematic
C3
R14
0⍀
5
PD
TP14
YEL
C13
0.1F
3
AGND
0.1F
18
17
16
15
14
13
12
11
10
1
0.1F
C8
SO
J2
C1
28
GND12
SDATA
27
VCC6
CLK
26
VIN–
DATEN
25
GND1
VIN+
24
BYP
GND11
23
VCC5
VCC
22
GND10
PD
U1
21
VCC4
VCC1
20
VCC3
VCC2
19
OUT–
OUT+
18
GND2
GND9
17
GND8
GND3
16
GND4
GND7
15
GND5
GND6
G1
G2
G3
G4
G5
G6
G7
G8
G9
BLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SDATA
CLK
DATEN
A
+ C18
10F
25V
LE
TE
TP20
TP15
B
J1
VCC
1
TP7
DNI
TP8
DNI
C9
DNI
R3
0⍀
CABLE
S1
R4
DNI
REV. 0
AD8322
EVALUATION BOARD BILL OF MATERIALS
AD8322 Evaluation Board Rev. DC SINGLE-ENDED INVERTING INPUT – Revised – June 22, 2000
Description
Vendor
Ref Desc.
1
12
10
1
8
1
1
2
4
1
2
1
1
1
1
4
4
2
2
2
2
10 µF 16 V. ‘C’ size tantalum chip capacitor
0.1 µF 50 V. 1206 size ceramic chip capacitor
0 1/8 W. 1206 size chip resistor
118 1% 1/8 W. 1206 size chip resistor
White Test Point (CLK, PD, CP, SDATA, DATEN)
Black Test Point (GND)
Red Test Point (VCC)
Yellow Test Point (+/- INPUT)
75 right-angle BNC Telegartner # J01003A1949
Centronics type 36-pin Right-Angle female connector
5-way Metal Binding Post
TOKO # 617 DB-A0070 transformer
Diplexer PULSE*
AD8322 (TSSOP)
AD8322 REV. E Evaluation PC board
#4 – 40 × 1/4 inch ss panhead machine screw
#4 – 40 × 3/4 inch long aluminum round stand-off
# 2 – 56 × 3/8 inch ss panhead machine screw
# 2 steel flat washer
# 2 steel internal tooth lockwasher
# 2 ss hex. machine nut
ADS# 4-7-6
ADS# 4-5-18
ADS# 3-18-88
ADS# 3-18-106
ADS# 12-18-42
ADS# 12-18-44
ADS# 12-18-43
ADS# 12-18-32
ADS# 12-6-28
ADS# 12-3-50
ADS# 12-7-7
Toko # 617DB-A0070
PULSE
ADS# AD8322
D.S.C.
ADS# 30-1-1
ADS# 30-16-3
ADS# 30-1-17
ADS# 30-6-6
ADS# 30-5-2
ADS# 30-7-6
C18
C1–8, 10–13
R1, 2, 3, 6, 8, 10, 14–16, 18
R7
TP1–6, 17, 19
TP20
TP15
TP13 & TP14
S1–4 (INPUT, OUTPUT)
P1
J1, 2 (VCC, GND)
T2B
U2
D.U.T. (U1)
Evaluation PC board
LE
TE
Qty.
O
B
SO
DO NOT INSTALL C9, C14–C16, TP7–TP12, TP21, TP22, R4, R5, R9, R11–R13, R17, R19, R20, T1, T2A.
*PULSE Diplexer Part #’s B5008 (42 MHz), CX6002 (42 MHz), B5009 (65 MHz).
REV. 0
–15–
(p1 hardware)
(p1 hardware)
(p1 hardware)
(p1 hardware)
AD8322
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C02049–2.5–7/00 (rev. 0)
28-Lead TSSOP
(RU-28)
0.386 (9.80)
0.378 (9.60)
28
15
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
14
0.006 (0.15)
0.002 (0.05)
0.0256 (0.65) 0.0118 (0.30)
BSC
0.0075 (0.19)
0.0079 (0.20)
0.0035 (0.090)
8ⴗ
0ⴗ
0.028 (0.70)
0.020 (0.50)
PRINTED IN U.S.A.
O
B
SO
LE
SEATING
PLANE
0.0433 (1.10)
MAX
TE
1
PIN 1
–16–
REV. 0
