AD8323ARU-REEL

a 5 V CATV Line Driver Fine Step Output Power Control AD8323 FEATURES Supports DOCSIS Standard for Reverse Path Transmission Gain Programmable in 0.75 dB Steps Over a 53.5 dB Range Low Distortion at 60 dBmV Output –56 dBc SFDR at 21 MHz –55 dBc SFDR at 42 MHz Output Noise Level –48 dBmV in 160 kHz Maintains 75 ⍀ Output Impedance Power-Up and Power-Down Condition Upper Bandwidth: 100 MHz (Full Gain Range) 5 V Supply Operation Supports SPI Interfaces FUNCTIONAL BLOCK DIAGRAM VCC (7 PINS) R1 VIN+ VOUT+ VOUT– TE 8 DATA LATCH 8 LE O Distortion performance of –56 dBc is achieved with an output level up to 60 dBmV at 21 MHz bandwidth. A key performance and cost advantage of the AD8323 results from the ability to maintain a constant 75 Ω output impedance during power-up and power-down conditions. This eliminates the need for external 75 Ω termination, resulting in twice the effective output voltage when compared to a standard operational amplifier. In addition, this device has a sleep mode function that reduces the quiescent current to 4 mA. POWER-DOWN LOGIC SHIFT REGISTER DATEN DATA CLK GND (11 PINS) PD SLEEP –50 FO = 42MHz PO = 60dBmV @ MAX GAIN –55 DISTORTION – dBc The AD8323 comprises a digitally controlled variable attenuator of 0 dB to –53.5 dB, which is preceded by a low noise, fixed gain buffer and is followed by a low distortion high power amplifier. The AD8323 accepts a differential or single-ended input signal. The output is specified for driving a 75 Ω load, such as coaxial cable. ZOUT DIFF = 75⍀ DECODE R2 ZIN (SINGLE) = 800⍀ ZIN (DIFF) = 1.6k⍀ B SO The AD8323 is a low-cost, digitally controlled, variable gain amplifier optimized for coaxial line driving applications such as cable modems that are designed to the MCNS-DOCSIS upstream standard. An 8-bit serial word determines the desired output gain over a 53.5 dB range resulting in gain changes of 0.7526 dB/LSB. POWER AMP ATTENUATION CORE BUFFER 8 APPLICATIONS Gain-Programmable Line Driver HFC High-Speed Data Modems Interactive Set-Top Boxes PC Plug-in Modems General-Purpose Digitally Controlled Variable Gain Block GENERAL DESCRIPTION AD8323 DIFF OR SINGLE INPUT AMP VIN– BYP HD3 –60 –65 HD2 –70 –75 0 8 16 24 32 40 48 56 GAIN CONTROL – DEC Code 64 72 Figure 1. Harmonic Distortion vs. Gain Control The AD8323 is packaged in a low-cost 28-lead TSSOP, operates from a single 5 V supply, and has an operational temperature range of –40°C to +85°C. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 (TA = 25ⴗC, VS = 5 V, RL = RIN = 75 ⍀, VIN = 116 mV p-p, VOUT measured through a 1:1 AD8323–SPECIFICATIONS transformer with an insertion loss of 0.5 dB @ 10 MHz unless otherwise noted.) 1 Parameter Conditions INPUT CHARACTERISTICS Specified AC Voltage Noise Figure Input Resistance Min Output = 60 dBmV, Max Gain Max Gain, f = 10 MHz Single-Ended Input Differential Input 52.5 26.5 –27 Gain Code = 71 Dec Gain Code = 0 Dec All Gain Codes f = 65 MHz f = 65 MHz Max Gain, f = 10 MHz Gain Linearity Error Output Settling to 1 mV Due to Gain Change Due to Input Step Change Signal Feedthrough O POWER CONTROL Power-Up Settling Time to 1 mV Power-Down Settling Time to 1 mV Between Burst Transients2 POWER SUPPLY Operating Range Quiescent Current dB dB dB dB/LSB Max Gain, f = 10 MHz Power-Up and Power-Down 18.5 75 ± 20% f = 21 MHz, POUT = 60 dBmV @ Max Gain f = 42 MHz, POUT = 60 dBmV @ Max Gain f = 65 MHz, POUT = 60 dBmV @ Max Gain f = 21 MHz, POUT = 60 dBmV @ Max Gain f = 42 MHz, POUT = 60 dBmV @ Max Gain f = 65 MHz, POUT = 60 dBmV @ Max Gain f = 10 MHz, Code to Code –77 –71 –64 –56 –55 –53 ± 0.3 dBc dBc dBc dBc dBc dBc dB Min to Max Gain Max Gain, VIN = 0 V to 116 mV p-p Max Gain, PD = 0, f = 42 MHz 60 30 –30 ns ns dBc Max Gain, VIN = 0 Max Gain, VIN = 0 Equivalent Output = 31 dBmV Equivalent Output = 60 dBmV 300 40 3 30 ns ns mV p-p mV p-p LE –68 B SO Third Order Harmonic Distortion 100 1.3 0 –34 –48 Power-Down Mode, f = 10 MHz OVERALL PERFORMANCE Second Order Harmonic Distortion 54.5 28.5 –25 MHz dB dB dBmV in 160 kHz dBmV in 160 kHz dBmV in 160 kHz dBm Ω Min Gain, f = 10 MHz 1 dB Compression Point Differential Output Impedance 53.5 27.5 –26 0.7526 Unit mV p-p dB Ω Ω pF TE OUTPUT CHARACTERISTICS Bandwidth (–3 dB) Bandwidth Roll-Off Bandwidth Peaking Output Noise Spectral Density Max 116 13.8 800 1600 2 Input Capacitance GAIN CONTROL INTERFACE Gain Range Maximum Gain Minimum Gain Gain Scaling Factor Typ 4.75 123 30 2 Power-Up Mode Power-Down Mode Sleep Mode OPERATING TEMPERATURE RANGE –40 5 133 35 4 5.25 140 40 7 V mA mA mA +85 °C NOTES 1 TOKO 617DB-A0070 used for above specifications. MACOM ETC-1-IT-15 can be substituted. 2 Between Burst Transients measured at the output of a 42 MHz diplexer. Specifications subject to change without notice. –2– REV. 0 AD8323 LOGIC INPUTS (TTL/CMOS Compatible Logic) (DATEN, CLK, SDATA, PD, SLEEP, V Parameter Min Logic “1” Voltage Logic “0” Voltage Logic “1” Current (VINH = 5 V) CLK, SDATA, DATEN Logic “0” Current (VINL = 0 V) CLK, SDATA, DATEN Logic “1” Current (VINH = 5 V) PD Logic “0” Current (VINL = 0 V) PD Logic “1” Current (VINH = 5 V) SLEEP Logic “0” Current (VINL = 0 V) SLEEP 2.1 0 0 –600 50 –250 50 –250 TIMING REQUIREMENTS CC = 5 V: Full Temperature Range) Typ 5.0 0.8 20 –100 190 –30 190 –30 V V nA nA µA µA µA µA Typ TDS VALID DATA WORD G1 MSB. . . .LSB VALID DATA WORD G2 TC B SO TWH CLK TES TEH 8 CLOCK CYCLES DATEN GAIN TRANSFER (G1) GAIN TRANSFER (G2) TOFF PD TGS TON ANALOG OUTPUT PEDESTAL SIGNAL AMPLITUDE (p-p) Figure 2. Serial Interface Timing VALID DATA BIT SDATA MSB Unit 10 ns ns ns ns ns ns ns 16.0 32.0 5.0 15.0 5.0 3.0 LE Clock Pulsewidth (TWH) Clock Period (TC) Setup Time SDATA vs. Clock (TDS) Setup Time DATEN vs. Clock (TES) Hold Time SDATA vs. Clock (TDH) Hold Time DATEN vs. Clock (TEH) Input Rise and Fall Times, SDATA, DATEN, Clock (TR, TF) SDATA Max TE Min O Unit (Full Temperature Range, VCC = 5 V, TR = TF = 4 ns, fCLK = 8 MHz unless otherwise noted.) Parameter MSB-1 TDS MSB-2 TDH CLK Figure 3. SDATA Timing REV. 0 Max –3– AD8323 PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS* Supply Voltage +VS Pins 5, 9, 10, 19, 20, 23, 27 . . . . . . . . . . . . . . . . . . . . . . 6 V Input Voltages Pins 25, 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 0.5 V Pins 1, 2, 3, 6, 7 . . . . . . . . . . . . . . . . . . . . . –0.8 V to +5.5 V Internal Power Dissipation TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9 W Operating Temperature Range . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature, Soldering 60 seconds . . . . . . . . . . . 300°C 1 28 GND SDATA 2 27 VCC CLK 3 26 VIN– GND 4 25 VIN+ VCC 5 24 GND PD 6 23 VCC SLEEP 7 22 GND GND 8 VCC VCC AD8323 TOP VIEW (Not to Scale) 21 BYP 9 20 VCC 10 19 VCC GND 11 18 GND GND 12 17 GND GND 13 16 GND OUT– 14 15 OUT+ TE *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DATEN ORDERING GUIDE Temperature Range Package Description ␪JA Package Option AD8323ARU AD8323ARU-REEL AD8323-EVAL –40°C to +85°C –40°C to +85°C 28-Lead TSSOP 28-Lead TSSOP Evaluation Board 67.7°C/W* 67.7°C/W* RU-28 RU-28 LE Model *Thermal Resistance measured on SEMI standard 4-layer board. B SO CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8323 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE PIN FUNCTION DESCRIPTIONS Pin No. 1 Mnemonic Description DATEN 4, 8, 11,12, 13, 16, 17, 18, 22, 24, 28 5, 9, 10, 19, 20, 23, 27 6 7 GND Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simultaneously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch (holds the previous gain state) and simultaneously enables the register for serial data load. Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the internal register with the MSB (Most Significant Bit) first. Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit masterslave register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to the slave. This requires the input serial data word to be valid at or before this clock transition. Common External Ground Reference. VCC Common Positive External Supply Voltage. A 0.1 µF capacitor must decouple each pin. PD SLEEP 14 15 21 25 OUT– OUT+ BYP VIN+ 26 VIN– Logic “0” powers down the part. Logic “1” powers up the part. Low Power Sleep Mode. In the Sleep mode, the AD8323’s supply current is reduced to 4 mA. A Logic “0” powers down the part (High ZOUT State) and a Logic “1” powers up the part. Negative Output Signal. Positive Output Signal. Internal Bypass. This pin must be externally ac-coupled (0.1 µF cap). Noninverting Input. DC-biased to approximately VCC/2. For single-ended inverting operation, use a 0.1 µF decoupling capacitor and a 39.2 Ω resistor between VIN+ and ground. Inverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 µF capacitor. 3 SDATA CLK O 2 –4– REV. 0 Typical Performance Characteristics– AD8323 34 1:1 IN VIN– VIN+ 31 VCC RL 75⍀ OUT– 82.5⍀ OUT+ VIN+ 0.1␮F RL 75⍀ 28 25 CL = 50pF CL = 20pF CL = 10pF GND 0.1␮F 39.2⍀ CL CL = 0pF OUT 0.1␮F VIN– GAIN – dB 0.1␮F VIN RTI TOKO 617DB–A0070 1:1 POUT = 60dBmV @ MAX GAIN OUT 22 19 100 TPC 4. AC Response for Various Cap Loads TPC 1. Basic Test Circuit 0.5 f = 10MHz 0.0 f = 5MHz f = 42MHz B SO –0.5 –1.0 f = 10MHz PD = 1 –34 LE 1.0 OUTPUT NOISE – dBmV in 160kHz –30 1.5 GAIN ERROR – dB 10 FREQUENCY – MHz TE 1 –38 –42 –46 f = 65MHz 0 8 16 24 32 40 48 GAIN CONTROL – Decimal 56 64 TPC 2. Gain Error vs. Gain Control 40 30 20 GAIN – dB 0 8 16 24 32 40 48 GAIN CONTROL – Decimal 46D 0 23D –10 –20 00D 56 64 72 TPC 5. Output Referred Noise vs. Gain Control 0 PD = 0 VIN = 116mV p-p 71D O 10 –50 72 –20 FEEDTHROUGH – dB –1.5 MAX GAIN –40 –60 MIN GAIN –80 –30 –40 0.1 –100 1 10 FREQUENCY – MHz 100 1k 0.1 10 FREQUENCY – MHz 100 1k TPC 6. Input Signal Feedthrough vs. Frequency TPC 3. AC Response REV. 0 1 –5– AD8323 85 –60 RTI = 82.5⍀ 80 POUT = 62dBmV @ MAX GAIN PD = 0 IMPEDANCE – ⍀ DISTORTION – dBc –65 POUT = 61dBmV @ MAX GAIN –70 POUT = 60dBmV @ MAX GAIN –75 –80 75 PD = 1 70 65 60 POUT = 58dBmV @ MAX GAIN –85 15 25 35 45 55 FUNDAMENTAL FREQUENCY – MHz 55 65 TPC 7. Second Order Harmonic Distortion vs. Frequency for Various Output Levels 10 FREQUENCY – MHz 100 TPC 10. Input Impedance vs. Frequency –45 80 75 LE POUT = 61dBmV @ MAX GAIN IMPEDANCE – ⍀ POUT = 62dBmV @ MAX GAIN –50 –55 POUT = 60dBmV @ MAX GAIN –60 B SO DISTORTION – dBc 1 TE 5 PD = 1 70 PD = 0 65 60 55 POUT = 58dBmV @ MAX GAIN –65 5 15 25 35 45 55 FUNDAMENTAL FREQUENCY – MHz 50 65 TPC 8. Third Order Harmonic Distortion vs. Frequency for Various Output Levels 60 50 100 140 130 PD = 1 120 110 30 100 20 +ICC – mA POUT – dBmV 10 FREQUENCY – MHz TPC 11. Output Impedance vs. Frequency POUT = 60dBmV @ MAX GAIN O 40 1 10 0 90 80 70 60 –10 50 –20 –40 41.0 41.2 PD = 0 40 –30 30 41.4 41.6 41.8 42.0 42.2 42.4 FREQUENCY – MHz 42.6 42.8 20 –50 43.0 TPC 9. Two-Tone Intermodulation Distortion –25 0 25 50 TEMPERATURE – ⴗC 75 100 TPC 12. Supply Current vs. Temperature –6– REV. 0 AD8323 The gain transfer function is as follows: The AD8323 is primarily intended for use as the upstream power amplifier (PA) in DOCSIS (Data Over Cable Service Interface Specifications) certified cable modems and CATV settop boxes. Upstream data is modulated in QPSK or QAM format, and done with DSP or a dedicated QPSK/QAM modulator. The amplifier receives its input signal from the QPSK/QAM modulator or from a DAC. In either case the signal must be low-pass filtered before being applied to the amplifier. Because the distance from the cable modem to the central office will vary with each subscriber, the AD8323 must be capable of varying its output power by applying gain or attenuation to ensure that all signals arriving at the central office are of the same amplitude. The upstream signal path contains components such as a transformer and diplexer that will result in some amount of power loss. Therefore, the amplifier must be capable of providing enough power into a 75 Ω load to overcome these losses without sacrificing the integrity of the output signal. AV = 27.5 dB – (0.7526 dB × (71 – CODE)) for 0 ≤ CODE ≤ 71 where AV is the gain in dB and CODE is the decimal equivalent of the 8-bit word. Valid gain codes are from 0 to 71. Figure 4 shows the gain characteristics of the AD8323 for all possible values in an 8-bit word. Note that maximum gain is achieved at Code 71. From Code 72 through 127 the 5.25 dB of attenuation from the vernier stage is being applied over every eight codes, resulting in the sawtooth characteristic at the top of the gain range. Because the eighth bit is a “don’t care” bit, the characteristic for codes 0 through 127 repeats from Codes 128 through 255. 28 TE APPLICATIONS General Application 21 14 7 0 –7 LE The AD8323 is composed of four analog functions in the power-up or forward mode. The input amplifier (preamp) can be used single-ended or differentially. If the input is used in the differential configuration, it is imperative that the input signals are 180 degrees out of phase and of equal amplitudes. This will ensure the proper gain accuracy and harmonic performance. The preamp stage drives a vernier stage that provides the fine tune gain adjustment. The 0.7526 dB step resolution is implemented in this stage and provides a total of approximately 5.25 dB of attenuation. After the vernier stage, a DAC provides the bulk of the AD8323’s attenuation (8 bits or 48 dB). The signals in the preamp and vernier gain blocks are differential to improve the PSRR and linearity. A differential current is fed from the DAC into the output stage, which amplifies these currents to the appropriate levels necessary to drive a 75 Ω load. The output stage utilizes negative feedback to implement a differential 75 Ω output impedance. This eliminates the need for external matching resistors needed in typical video (or video filter) termination requirements. GAIN – dB Operational Description –14 –21 –28 B SO 0 SPI Programming and Gain Adjustment REV. 0 64 96 128 160 GAIN CODE – Decimal 192 224 256 Figure 4. Gain vs. Gain Code Input Bias, Impedance, and Termination The VIN+ and VIN– inputs have a dc bias level of approximately VCC/2, therefore the input signal should be ac-coupled. The differential input impedance is approximately 1600 Ω while the single-ended input impedance is 800 Ω. If the AD8323 is being operated in a single-ended input configuration with a desired input impedance of 75 Ω, the VIN+ and VIN– inputs should be terminated as shown in Figure 5. If an input impedance other than 75 Ω is desired, the values of R1 and R2 in Figure 5 can be calculated using the following equations: O Gain programming of the AD8323 is accomplished using a serial peripheral interface (SPI) and three digital control lines, DATEN, SDATA, and CLK. To change the gain, eight bits of data are streamed into the serial shift register through the SDATA port. The SDATA load sequence begins with a falling edge on the DATEN pin, thus activating the CLK line. Although the CLK line is now activated, no change in gain is yet observed at the output of the amplifier. With the CLK line activated, data on the SDATA line is clocked into the serial shift register Most Significant Bit (MSB) first, on the rising edge of each CLK pulse. Because only a 7-bit shift register is used, the MSB of the 8-bit word is a “don’t care” bit and is shifted out of the register on the eighth clock pulse. A rising edge on the DATEN line latches the contents of the shift register into the attenuator core resulting in a well controlled change in the output signal level. The serial interface timing for the AD8323 is shown in Figures 2 and 3. The programmable gain range of the AD8323 is –26 dB to +27.5 dB and scales 0.7526 dB per least significant bit (LSB). Because the AD8323 was characterized with a TOKO transformer, the stated gain values already take into account the losses associated with the transformer. 32 ZIN = R1 800 R2 = ZIN R1 ZIN = 75⍀ – R1 = 82.5⍀ AD8323 + R2 = 39.2⍀ Figure 5. Single-Ended Input Termination –7– AD8323 input and output traces should be kept as short and symmetrical as possible. In addition, the input and output traces should be kept far apart in order to minimize coupling (crosstalk) through the board. Following these guidelines will improve the overall performance of the AD8323 in all applications. Output Bias, Impedance, and Termination The differential output pins VOUT+ and VOUT– are also biased to a dc level of approximately VCC/2. Therefore, the outputs should be ac-coupled before being applied to the load. This may be accomplished by connecting 0.1 µF capacitors in series with the outputs as shown in the typical applications circuit of Figure 6. The differential output impedance of the AD8323 is internally maintained at 75 Ω, regardless of whether the amplifier is in forward transmit mode or reverse power-down mode, eliminating the need for external back termination resistors. A 1:1 transformer (TOKO #617DB-A0070) is used to couple the amplifier’s differential output to the coaxial cable while maintaining a proper impedance match. If the output signal is being evaluated on standard 50 Ω test equipment, a 75 Ω to 50 Ω pad must be used to provide the test circuit with the correct impedance match. Initial Power-Up TE When the 5 V supply is first applied to the VCC pins of the AD8323, the gain setting of the amplifier is indeterminate. Therefore, as power is first applied to the amplifier, the PD pin should be held low (Logic 0) thus preventing forward signal transmission. After power has been applied to the amplifier, the gain can be set to the desired level by following the procedure in the SPI Programming and Gain Adjustment section. The PD pin can then be brought from Logic 0 to 1, enabling forward signal transmission at the desired gain level. Asynchronous Power-Down Power Supply Decoupling, Grounding, and Layout Considerations The asynchronous PD pin is used to place the AD8323 into “Between Burst” mode while maintaining a differential output impedance of 75 Ω. Applying a Logic 0 to the PD pin activates the on-chip reverse amplifier, providing a 74% reduction in consumed power. The supply current is reduced from approximately 133 mA to approximately 35 mA. In this mode of operation, between burst noise is minimized and the amplifier can no longer transmit in the upstream direction. In addition to the PD pin, the AD8323 also incorporates an asynchronous SLEEP pin, which may be used to place the amplifier in a high output impedance state and further reduce the supply current to approximately 4 mA. Applying a Logic 0 to the SLEEP pin places the amplifier into SLEEP mode. Transitioning into or out of SLEEP mode will result in a transient voltage at the output of the amplifier. Therefore, use only the PD pin for DOCSIS compliant “Between Burst” operation. 5V B SO LE Careful attention to printed circuit board layout details will prevent problems due to associated board parasitics. Proper RF design technique is mandatory. The 5 V supply power should be delivered to each of the VCC pins via a low impedance power bus to ensure that each pin is at the same potential. The power bus should be decoupled to ground with a 10 µF tantalum capacitor located in close proximity to the AD8323. In addition to the 10 µF capacitor, each VCC pin should be individually decoupled to ground with a 0.1 µF ceramic chip capacitor located as close to the pin as possible. The pin labeled BYP (Pin 21) should also be decoupled with a 0.1 µF capacitor. The PCB should have a lowimpedance ground plane covering all unused portions of the component side of the board, except in the area of the input and output traces (see Figure 11). It is important that all of the AD8323’s ground pins are connected to the ground plane to ensure proper grounding of all internal nodes. The differential 10␮F 25V 0.1␮F AD8323TSSOP O DATEN SDATA CLK 0.1␮F PD 0.1␮F SLEEP 0.1␮F DATEN SDATA CLK GND1 VCC PD SLEEP GND2 VCC1 VCC2 GND3 GND4 GND5 OUT– 0.1␮F ZIN = 150⍀ VIN– VIN+ GND10 VCC5 GND9 BYP VCC4 VCC3 GND8 GND7 GND6 OUT+ VIN– 0.1␮F GND11 VCC6 165⍀ 0.1␮F VIN+ 0.1␮F 0.1␮F 0.1␮F 0.1␮F 0.1␮F TOKO 617DB-A0070 TO DIPLEXER ZIN = 75⍀ Figure 6. Typical Applications Circuit –8– REV. 0 AD8323 RBW 500 Hz RF ATT 40dB –10 VBW 5 kHz SWT 12s UNIT dBm –20 CH PWR ACP UP ACP LOW –70 5.44 dBm –52.99 dB –54.36 dB C0 C0 CU1 The data lines on some PC parallel printer ports have excessive overshoot that may cause communications problems when presented to the CLK pin of the AD8323 (TP5 on the evaluation board). The evaluation board was designed to accommodate a series resistor and shunt capacitor (R1 and C15) to filter the CLK signal if required. Transformer and Diplexer CL1 –80 The AD8323 evaluation board (Part # AD8323-EVAL) and control software can be used to control the AD8323 upstream cable driver via the parallel port of a PC. A standard printer cable connected between the parallel port and the evaluation board is used to feed all the necessary data to the AD8323 by means of the Windows-based, Microsoft Visual Basic control software. This package provides a means of evaluating the amplifier by providing a convenient way to program the gain/ attenuation as well as offering easy control of the amplifiers’ asynchronous PD and SLEEP pins. With this evaluation kit the AD8323 can be evaluated with either a single-ended or differential input configuration. The amplifier can also be evaluated with or without the PULSE diplexer in the output signal path. To remove the diplexer from the signal path, move the 0 Ω chip resistor at JP5 so the output signal is directed away from the diplexer and toward the CABLE port of the evaluation board. Also, remove the 0 Ω resistor at JP4. A schematic of the evaluation board is provided in Figure 13. B SO –40 –60 Evaluation Board Features and Operation Overshoot on PC Printer Ports –30 –50 Comparing the computed noise power of –48 dBmV to the 8 dBmV signal yields –56 dBc, which meets the required level of –53 dBc set forth in DOCSIS Table 4-8. As the AD8323’s gain is increased from this minimum value, the output signal increases at a faster rate than the noise, resulting in a signal to noise ratio that improves with gain. In transmit disable mode, the output noise spectral density computed over 160 KSYM/SECOND is 1.0 nV/√Hz or –68 dBmV. LE In order to deliver 58 dBmV of high fidelity output power required by DOCSIS, the PA should be able to deliver about 60 dBmV to 61 dBmV in order to make up for losses associated with the transformer and diplexer. It should be noted that the AD8323 was characterized with the TOKO 617DB-A0070 transformer. TPC 7 and TPC 8 show the AD8323 second and third harmonic distortion performance versus fundamental frequency for various output power levels. These figures are useful for determining the inband harmonic levels from 5 MHz to 65 MHz. Harmonics higher in frequency will be sharply attenuated by the low-pass filter function of the diplexer. Another measure of signal integrity is adjacent channel power or ACP. DOCSIS section 4.2.9.1.1 states, “Spurious emissions from a transmitted carrier may occur in an adjacent channel that could be occupied by a carrier of the same or different symbol rates.” Figure 7 shows the measured ACP for a 16 QAM, 60 dBmV signal, taken at the output of the AD8323 evaluation board (see Figure 13 for evaluation board schematic). The transmit channel width and adjacent channel width in Figure 7 correspond to symbol rates of 160 KSYM/SEC. Table I shows the ACP results for the AD8323 for all conditions in DOCSIS Table 4-7 “Adjacent Channel Spurious Emissions.” TE Distortion, Adjacent Channel Power, and DOCSIS CL1 CU1 F1 CENTER 10 MHz 60 kHz SPAN 600 kHz Figure 7. Adjacent Channel Power O Table I. ACP Performance for All DOCSIS Conditions (All Values in dBc) TRANSMIT ADJACENT CHANNEL SYMBOL RATE CHANNEL SYMBOL RATE 160 KSYM/SEC 320 KSYM/SEC 640 KSYM/SEC 1280 KSYM/SEC 2560 KSYM/SEC 160 KSYM/SEC –53.0 –53.8 –55.0 –56.6 –56.3 320 KSYM/SEC –52.7 –53.4 –53.8 –54.8 –55.4 640 KSYM/SEC –53.8 –52.9 –53.3 –53.6 –54.2 1280 KSYM/SEC –53.7 –53.4 –53.0 –53.3 –53.5 2560 KSYM/SEC –55.4 –54.0 –53.6 –53.1 –53.3 Noise and DOCSIS At minimum gain, the AD8323’s output noise spectral density is 10 nV/√Hz measured at 10 MHz. DOCSIS Table 4-8, “Spurious Emissions in 5 MHz to 42 MHz,” specifies the output noise for various symbol rates. The calculated noise power in dBmV for 160 KSYM/SECOND is: A 1:1 transformer is needed to couple the differential outputs of the AD8323 to the cable while maintaining a proper impedance match. The specified transformer is available from TOKO (Part # 617DB-A0070); however, MA/COM part # ETC-1-1T-15 can also be used. The evaluation board is equipped with the TOKO transformer, but is also designed to accept the MA/ COM transformer. The PULSE diplexer included on the evaluation board provides a high-order low-pass filter function, typically used in the upstream path. The ability of the PULSE diplexer to achieve DOCSIS compliance is neither expressed nor implied by Analog Devices Inc. Data on the diplexer should be obtained from PULSE. Differential Inputs The AD8323-EVAL evaluation board is designed to accommodate a Mini-Circuits T1-6T-KK81 1:1 transformer for the purpose of converting a single-ended (ground-referenced) input signal to differential inputs. Figure 8 and the following paragraphs identify two options for providing differential input signals to the AD8323 evaluation board.    2  10 nV      × 160 kHz   + 60 = –48 dBmV  20 log     Hz       REV. 0 –9– AD8323 Single-Ended-to-Differential Input (Figure 8, Option 1) Installing the Visual Basic Control Software Install the Mini-Circuits T1-6T-KK81 1:1 transformer in the T1 location of the evaluation board. Place 0 Ω chip resistors at locations JP1, JP2, and JP3 such that the signal coming in VIN+ is directed toward the transformer and the differential signal coming out of the transformer is directed toward TP13 and TP14. For 75 Ω input impedance, install 39.2 Ω resistors in R5 and R6 located on the back side of the evaluation board. In this configuration the input signal must be applied to the VIN+ port of the evaluation board from a single-ended 75 Ω signal source. For input impedances other than 75 Ω, the correct value for R5 and R6 can be computed using the following equation: To install the “CABDRIVE_23” evaluation board control software, close all Windows applications and then run “SETUP.EXE” located on Disk 1 of the AD8323 Evaluation Software. Follow the on-screen instructions and insert Disk 2 when prompted to do so. Enter the path of the directory into which the software will be installed and select the button in the upper left corner to complete the installation. (R5 = R6 = R), Desired Impedance = 2 × (R 800) ) AD8323 T1 R5 OPTION 1 DIFFERENTIAL INPUT TERMINATION VIN+ R7 VIN– TE POWER-UP, POWER-DOWN AND SLEEP The “Power-Up” and “Power-Down” buttons select the mode of operation of the AD8323 by controlling the logic level on the asynchronous PD pin. The “Power-Up” button applies a Logic 1 to the PD pin putting the AD8323 in forward transmit mode. The “Power-Down” button applies a Logic 0 to the PD pin selecting reverse mode, where the forward signal transmission is disabled while a back termination of 75 Ω is maintained. Checking the “Enable SLEEP Mode” box applies a Logic 0 to the asynchronous SLEEP pin, putting the AD8323 into SLEEP mode. B SO R6 DIFF IN The slide bar controls the AD8323’s gain/attenuation, which is displayed in dB and in V/V. The gain scales at 0.7526 dB per LSB with the valid codes being from decimal 0 to 71. The gain code (i.e., position of the slide bar) is displayed in decimal, binary, and hexadecimal (see Figure 9). LE If a differential signal source is available, it may be applied directly to both the VIN+ and VIN– input ports of the evaluation board. In this case, 0 Ω chip resistors should be placed at locations R8, JP1, JP2, and JP3 such that the VIN+ and VIN– signals are directed toward TP13 and TP14. Referring to Figure 8, Option 2, a differential input impedance of 150 Ω can be achieved by using a 165 Ω resistor for R7. For input impedances other than 150 Ω, the correct value for R7 can be computed using the following equation: ( To invoke the control software, go to START -> PROGRAMS -> CABDRIVE_23, or select the AD8323.EXE icon from the directory containing the software. Controlling the Gain/Attenuation of the AD8323 Differential Input (Figure 8, Option 2) Desired Impedance = R7 1600 Running the Software Memory Section The “MEMORY” section of the software provides a convenient way to alternate between two gain settings. The “X->M1” button stores the current value of the gain slide bar into memory while the “RM1” button recalls the stored value, returning the gain slide bar to that level. The “X->M2” and “RM2” buttons work in the same manner. AD8323 O OPTION 2 DIFFERENTIAL INPUT TERMINATION Figure 8. Differential Input Termination Options –10– REV. 0 AD8323 B SO LE TE EVALUATION BOARD FEATURES AND OPERATION O Figure 9. Screen Display of Windows-Based Control Software REV. 0 –11– LE TE AD8323 O B SO Figure 10. Evaluation Board—Assembly (Component Side) Figure 11. Evaluation Board Layout (Component Side) –12– REV. 0 LE TE AD8323 O B SO Figure 12. Evaluation Board—Solder Side REV. 0 –13– 1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 AGND J2 BLK TP20 J1 1 –14– 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 AMP-552742 + C18 10␮F 25V RED TP15 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 PD SLEEP DATEN SDATA CLK DATEN SDATA WHT TP1 WHT TP3 C17 DNI R12 WHT 0⍀ TP19 C16 DNI R11 WHT 0⍀ C15 DNI R1 WHT 0⍀ TP17 TP2 C14 DNI R2 WHT 0⍀ TP4 C4 0.1␮F C3 0.1␮F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 WHT CLK WHT PD TP18 WHT SPARE TP16 WHT SLEEP TP5 TP6 AD8323TSSOP 28 GND11 DATEN 27 VCC6 SDATA 26 VIN– CLK 25 VIN+ GND1 24 GND10 VCC 23 VCC5 PD U1 22 GND9 SLEEP 21 GND2 BYP 20 VCC4 VCC1 19 VCC2 VCC3 18 GND3 GND8 17 GND4 GND7 16 GND5 GND6 15 OUT– OUT+ C2 0.1␮F C7 0.1␮F C6 0.1␮F C5 0.1␮F C8 0.1␮F C12 0.1␮F R5 82.5⍀ C13 0.1␮F TP7 DNI C10 0.1␮F TP12 DNI C11 0.1␮F TP8 DNI 1 2 3 TP11 DNI 4 TP9 DNI 5 TP13 YEL R7 DNI TP14 YEL TOKO-B4F 1 JP3 B 3 A 2 1 2 3 A B JP1 1 3 2 T2A DNI 1:1 5 1 T2B 1:1 NC = 2 TE ETCC1-1T R6 39.2⍀ LE B SO C1 0.1␮F O 3 4 T1 DNI 1:1 NC = 5 6 4 R9 DNI 2 3 A R3 0⍀ B 1 JP5 U2 JP2 1 B A 3 2 R8 0⍀ AGND;3,4,5 TP10 DNI JP4 R4 DNI AGND;3,4,5 S1 CABLE TP21 DNI HPP S4 AGND;3,4,5 TP22 DNI S3 VIN+ S2 VIN– AGND;3,4,5 18 1 G1 A 17 G2 16 3 G3 A–B 15 G4 5 14 B G5 13 G6 12 G7 11 9 PULSEB5008 G8 OUT = 2,4,6,7,8 G9 10 VCC AD8323 Figure 13. Evaluation Board Schematic REV. 0 AD8323 EVALUATION BOARD BILL OF MATERIALS AD8323 Evaluation Board Rev. C SINGLE-ENDED INVERTING INPUT – Revised – June 22, 2000 Description Vendor Ref Desc. 1 12 6 1 1 2 10 1 1 3 4 1 2 1 1 1 1 4 4 2 2 2 3 10 µF 16 V. ‘C’ size tantalum chip capacitor 0.1 µF 50 V. 1206 size ceramic chip capacitor 0 Ω 1/8 W. 1206 size chip resistor 39.2 Ω 1% 1/8 W. 1206 size chip resistor 82.5 Ω 1% 1/8 W. 1206 size chip resistor Yellow Test Point [INPUTS] (Bisco TP104-01-04) White Test Point [DATA] (Bisco TP104-01-09) Red Test Point [VCC] (Bisco TP104-01-02) Black Test Point [A.GND] (Bisco TP104-01-00) 0 Ω 0805 size chip resistors 75 Ω right-angle BNC Telegartner # J01003A1949 Centronics type 36 pin Right-Angle Connector 5-way Metal Binding Post (E F Johnson # 111-2223-001) 1:1 Transformer TOKO # 617DB - A0070 Diplexer PULSE* AD8323 (TSSOP) UPSTREAM Cable Driver AD8323 REV. C Evaluation PC board #4 - 40 × 1/4 inch STAINLESS panhead machine screw #4 - 40 × 3/4 inch long aluminum round stand-off # 2 - 56 × 3/8 inch STAINLESS panhead machine screw # 2 steel flat washer # 2 steel internal tooth lockwasher # 2 STAINLESS STEEL hex. machine nut ADS# 4-7-6 ADS# 4-5-18 ADS# 3-18- 88 ADS# 3-18-113 ADS# 3-18-189 ADS# 12-18-32 ADS# 12-18-42 ADS# 12-18-43 ADS# 12-18-44 ADS# 3-27-22 ADS# 12-6-28 ADS# 12-3-50 ADS# 12-7-7 TOKO PULSE ADI# AD8323XRU DCS ADS# 30-1-1 ADS# 30-16-3 ADS# 30-1-17 ADS# 30-6-6 ADS# 30-5-2 ADS# 30-7-6 C18 C1–8, 10–13 R1–3, 8, 11, 12 R6 R5 TP13, 14 TP1–6, 16–19 TP15 TP20 JP1–3 VIN+, VIN–, HPP, CABLE P1 VCC, GND T2 B U2 U1 Evaluation PC Board LE O B SO DO NOT INSTALL C14–C17, R4, R7, R9, T1, T2A, TP7–TP12, TP21, TP22. *PULSE Diplexer part #’s B5008 (42 MHz), CX6002 (42 MHz), B5009 (65 MHz). REV. 0 TE Qty. –15– (p1 hardware) (p1 hardware) (p1 hardware) (p1 hardware) AD8323 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C02045–2.5–7/00 (Rev. 0) 28-Lead TSSOP (RU-28) 0.386 (9.80) 0.378 (9.60) 28 15 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 14 0.006 (0.15) 0.002 (0.05) 0.0256 (0.65) 0.0118 (0.30) BSC 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) 8ⴗ 0ⴗ 0.028 (0.70) 0.020 (0.50) PRINTED IN U.S.A. O B SO LE SEATING PLANE 0.0433 (1.10) MAX TE 1 PIN 1 –16– REV. 0