AD8328ACPZ-REEL

5 V Upstream Cable Line Driver AD8328 FUNCTIONAL BLOCK DIAGRAM FEATURES VIN– VOUT+ The AD8328 is a low cost amplifier designed for coaxial line driving. The features and specifications make the AD8328 ideally suited for MCNS-DOCSIS and EuroDOCSIS applications. The gain of the AD8328 is digitally controlled. An 8-bit serial word determines the desired output gain over a 59 dB range, resulting in gain changes of 1 dB/LSB. The AD8328 accepts a differential or single-ended input signal. The output is specified for driving a 75 Ω load through a 2:1 transformer. O Distortion performance of −53 dBc is achieved with an output level up to 60 dBmV at 65 MHz bandwidth over a wide temperature range. This device has a sleep mode function that reduces the quiescent current to 2.6 mA and a full power-down function that reduces power-down current to 20 μA. ATTENUATION CORE VERNIER POWER AMP ZOUT DIFF = 300Ω 8 ZIN (SINGLE) = 800Ω ZIN (DIFF) = 1.6kΩ VOUT– DECODE 8 DATA LATCH POWER-DOWN LOGIC RAMP GND DATEN SDATA CLK TXEN 03158-001 8 SHIFT REGISTER SLEEP Figure 1. –50 –52 VOUT = 60dBmV @ MAX GAIN, THIRD HARMONIC –54 –56 –58 –60 –62 VOUT = 60dBmV @ MAX GAIN, SECOND HARMONIC –64 –66 03158-002 B SO GENERAL DESCRIPTION DIFF OR SINGLE INPUT AMP VIN+ DISTORTION (dBc) DOCSIS and EuroDOCSIS cable modems CATV set-top boxes CATV telephony modems Coaxial and twisted pair line drivers AD8328 LE APPLICATIONS BYP TE Supports DOCSIS and EuroDOCSIS standards for reverse path transmission systems Gain programmable in 1 dB steps over a 59 dB range Low distortion at 60 dBmV output −57.5 dBc SFDR at 21 MHz −54 dBc SFDR at 65 MHz Output noise level @ minimum gain 1.2 nV/√Hz Maintains 300 Ω output impedance Tx-enable and Tx-disable condition Upper bandwidth: 107 MHz (full gain range) 5 V supply operation Supports SPI interfaces –68 –70 5 15 25 35 45 FREQUENCY (MHz) 55 65 Figure 2. Worst Harmonic Distortion vs. Frequency The AD8328 is packaged in a low cost 20-lead LFCSP and a 20-lead QSOP. The AD8328 operates from a single 5 V supply and has an operational temperature range of −40°C to +85°C. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. AD8328 TABLE OF CONTENTS Signal Integrity Layout Considerations................................... 11 Applications....................................................................................... 1 Initial Power-Up ......................................................................... 12 Functional Block Diagram .............................................................. 1 RAMP Pin and BYP Pin Features ............................................ 12 General Description ......................................................................... 1 Transmit Enable (TXEN) and SLEEP ...................................... 12 Revision History ............................................................................... 2 Distortion, Adjacent Channel Power, and DOCSIS .............. 12 Specifications..................................................................................... 3 Noise and DOCSIS..................................................................... 12 Logic Inputs (TTL-/CMOS-Compatible Logic)....................... 4 Evaluation Board Features and Operation.............................. 12 Timing Requirements .................................................................. 4 Differential Signal Source ......................................................... 13 Absolute Maximum Ratings............................................................ 6 Differential Signal from Single-Ended Source ....................... 13 ESD Caution.................................................................................. 6 Single-Ended Source.................................................................. 13 Pin Configurations and Function Descriptions ........................... 7 Overshoot on PC Printer Ports ................................................ 13 LE TE Features .............................................................................................. 1 Installing Visual Basic Control Software................................. 13 Applications..................................................................................... 10 Running AD8328 Software ....................................................... 14 General Applications.................................................................. 10 Controlling Gain/Attenuation of the AD8328 ....................... 14 Circuit Description..................................................................... 10 Transmit Enable and Sleep Mode............................................. 14 B SO Typical Performance Characteristics ............................................. 8 SPI Programming and Gain Adjustment ................................ 10 Memory Functions..................................................................... 14 Input Bias, Impedance, and Termination................................ 10 Outline Dimensions ....................................................................... 17 Output Bias, Impedance, and Termination............................. 10 Ordering Guide............................................................................... 18 Power Supply............................................................................... 11 REVISION HISTORY O 10/05—Rev. 0 to Rev. A Updated Format..................................................................Universal Changes to Table 4............................................................................ 6 Updated Outline Dimensions ....................................................... 17 Changes to Ordering Guide .......................................................... 18 11/02—Revision 0: Initial Version Rev. A | Page 2 of 20 AD8328 SPECIFICATIONS TA = 25°C, VS = 5 V, RL = RIN = 75 Ω, VIN (differential) = 29 dBmV. The AD8328 is characterized using a 2:1 transformer 1 at the device output. Table 1. Output = 60 dBmV, max gain Single-ended input Differential input Gain code = 60 decimal codes Gain code = 1 decimal code TA = −40°C to +85°C Third-Order Harmonic Distortion4, 5 O ACPR2, 6 Isolation (Tx Disable)2 POWER CONTROL Tx Enable Settling Time Tx Disable Settling Time Output Switching Transients2 Output Settling Due to Gain Change Due to Input Step Change POWER SUPPLY Operating Range Quiescent Current Typ All gain codes (1 to 60 decimal codes) f = 65 MHz Maximum gain, f = 10 MHz, output referred Minimum gain, f = 10 MHz, input referred Max 29 800 1600 2 58 30.5 −28.5 0.6 17.9 2.2 59.0 31.5 −27.5 1.0 ±0.0005 Unit dBmV Ω Ω pF 60 32.5 −26.5 1.4 107 1.2 18.4 3.3 dB dB dB dB/LSB dB/°C MHz dB dBm dBm f = 10 MHz f = 10 MHz f = 10 MHz 135 1.2 1.1 151 1.3 1.2 nV/√Hz nV/√Hz nV/√Hz f = 10 MHz Tx enable and Tx disable 16.7 75 ± 30% 3 17.7 dB Ω f = 33 MHz, VOUT = 60 dBmV @ maximum gain f = 65 MHz, VOUT = 60 dBmV @ maximum gain f = 21 MHz, VOUT = 60 dBmV @ maximum gain f = 65 MHz, VOUT = 60 dBmV @ maximum gain Maximum gain, f = 65 MHz −67 −61 −57.5 −54 −58 −85 −56 −55 −56 −52.5 −56 −81 dBc dBc dBc dBc dBc dB Maximum gain, VIN = 0 Maximum gain, VIN = 0 Equivalent output = 31 dBmV Equivalent output = 61 dBmV 2.5 3.8 2.5 16 6 54 μs μs mV p-p mV p-p Minimum to maximum gain Maximum gain, VIN = 29 dBmV 60 30 B SO Output Noise2 Maximum Gain Minimum Gain Tx Disable Noise Figure2 Maximum Gain Differential Output Impedance OVERALL PERFORMANCE Second-Order Harmonic Distortion 4, 5 Min TE Input Capacitance GAIN CONTROL INTERFACE Voltage Gain Range Maximum Gain Minimum Gain Output Step Size Output Step Size Temperature Coefficient OUTPUT CHARACTERISTICS Bandwidth (−3 dB) Bandwidth Roll-Off 1 dB Compression Point 2 Conditions LE Parameter INPUT CHARACTERISTICS Specified AC Voltage Input Resistance Maximum gain Minimum gain Tx disable (TXEN = 0) SLEEP mode (power-down) OPERATING TEMPERATURE RANGE 4.75 98 18 1 1 −40 Rev. A | Page 3 of 20 5 120 26 2.6 20 ns ns 5.25 140 34 3.5 100 V mA mA mA μA +85 °C AD8328 1 TOKO 458 PT-1087 used for above specifications. Typical insertion loss of 0.3 dB @ 10 MHz. Guaranteed by design and characterization to ±4 sigma for TA = 25°C. 3 Measured through a 2:1 transformer. 4 Specification is worst case over all gain codes. 5 Guaranteed by design and characterization to ±3 sigma for TA = 25°C. 6 VIN = 29 dBmV, QPSK modulation, 160 kSPS symbol rate. 2 LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC) DATEN, CLK, SDATA, TXEN, SLEEP, VCC = 5 V; full temperature range. Table 2. Typ LE TIMING REQUIREMENTS Min 2.1 0 0 –600 50 −250 50 −250 Max 5.0 0.8 20 –100 190 −30 190 −30 TE Parameter Logic 1 Voltage Logic 0 Voltage Logic 1 Current (VINH = 5 V) CLK, SDATA, DATEN Logic 0 Current (VINL = 0 V) CLK, SDATA, DATEN Logic 1 Current (VINH = 5 V) TXEN Logic 0 Current (VINL = 0 V) TXEN Logic 1 Current (VINH = 5 V) SLEEP Logic 0 Current (VINL = 0 V) SLEEP Unit V V nA nA μA μA μA μA Full temperature range, VCC = 5 V, tR = tF = 4 ns, fCLK = 8 MHz, unless otherwise noted. Table 3. O B SO Parameter Clock Pulse Width (tWH) Clock Period (tC) Setup Time SDATA vs. Clock (tDS) Setup Time DATEN vs. Clock (tES) Hold Time SDATA vs. Clock (tDH) Hold Time DATEN vs. Clock (tEH) Input Rise and Fall Times, SDATA, DATEN, Clock (tR, tF) Rev. A | Page 4 of 20 Min 16.0 32.0 5.0 15.0 5.0 3.0 Typ Max 10 Unit ns ns ns ns ns ns ns AD8328 t DS VALID DATA-WORD G1 MSB. . . .LSB SDATA VALID DATA-WORD G2 tC t WH CLK t EH t ES 8 CLOCK CYCLES DATEN GAIN TRANSFER (G1) GAIN TRANSFER (G2) t GS TE t OFF TXEN t ON 03158-003 ANALOG OUTPUT SIGNAL AMPLITUDE (p-p) LE Figure 3. Serial Interface Timing VALID DATA BIT MSB-1 t DS MSB-2 t DH CLK O Figure 4. SDATA Timing Rev. A | Page 5 of 20 03158-004 MSB B SO SDATA AD8328 ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage VCC Input Voltage VIN+, VIN− DATEN, SDATA, CLK, SLEEP, TXEN Internal Power Dissipation QSOP (θJA = 83.2°C/W) 1 LFCSP (θJA = 30.4°C/W) 2 Operating Temperature Range Storage Temperature Range Lead Temperature, Soldering 60 sec 2 1.5 V p-p −0.8 V to +5.5 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 700 mW 700 mW −40°C to +85°C −65°C to +150°C 300°C Thermal resistance measured on SEMI standard 4-layer board. Thermal resistance measured on SEMI standard 4-layer board, paddle soldered to board. LE 1 Rating 6V TE Table 4. ESD CAUTION O B SO ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 6 of 20 AD8328 TXEN GND 20 GND VCC 2 19 VCC 20 19 18 17 16 GND 3 18 TXEN 17 RAMP NC SDATA 9 12 SLEEP CLK 10 11 GND 12 BYP 6 7 8 9 10 Figure 5. 20-Lead QSOP Pin Configuration 03158-006 13 03158-005 8 13 VOUT– 11 NC GND 5 DATEN NC = NO CONNECT VIN– 4 SLEEP BYP TOP VIEW (Not to Scale) GND 14 AD8328 VIN+ 3 CLK GND 7 14 VOUT+ GND 2 SDATA VIN– 16 VOUT+ TOP VIEW 6 (Not to Scale) 15 V OUT– 5 15 RAMP GND 1 TE VIN+ AD8328 DATEN GND 4 VCC GND 1 VCC GND PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 6. 20-Lead LFCSP Pin Configuration Table 5. 20-Lead QSOP and 20-Lead LFCSP Pin Function Descriptions Pin No. 20-Lead LFCSP 1, 2, 5, 9, 18, 19 17, 20 3 4 6 Mnemonic GND Description Common External Ground Reference. VCC VIN+ VIN− DATEN 9 7 SDATA 10 8 12 10 Common Positive External Supply Voltage. A 0.1 μF capacitor must decouple each pin. Noninverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 μF capacitor. Inverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 μF capacitor. Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic 0-to-Logic 1 transition transfers the latched data to the attenuator core (updates the gain) and simultaneously inhibits serial data transfer into the register. A Logic 1-to-Logic 0 transition inhibits the data latch (holds the previous gain state) and simultaneously enables the register for serial data load. Serial Data Input. This digital input allows an 8-bit serial (gain) word to be loaded into the internal register with the most significant bit (MSB) first. Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-slave register. A Logic 0-to-Logic 1 transition latches the data bit, and a Logic 1-to-Logic 0 transfers the data bit to the slave. This requires the input serial data-word to be valid at or before this clock transition. Low Power Sleep Mode. In the sleep mode, the AD8328’s supply current is reduced to 20 μA. A Logic 0 powers down the part (high ZOUT state), and a Logic 1 powers up the part. No Connect. Internal Bypass. This pin must be externally ac-coupled (0.1 μF capacitor). Negative Output Signal Positive Output Signal External RAMP Capacitor (Optional) Logic 0 Disables Forward Transmission. Logic 1 enables forward transmission. B SO CLK SLEEP O 13 14 15 16 17 18 LE Pin No. 20-Lead QSOP 1, 3, 4, 7, 11, 20 2, 19 5 6 8 11 12 13 14 15 16 NC BYP VOUT− VOUT+ RAMP TXEN Rev. A | Page 7 of 20 AD8328 TYPICAL PERFORMANCE CHARACTERISTICS –55 –50 VOUT = 61dBmV @ MAX GAIN –55 VOUT = 60dBmV @ MAX GAIN –65 –60 –70 03158-007 –75 15 25 35 45 FREQUENCY (MHz) TE –65 VOUT = 59dBmV @ MAX GAIN 5 55 –70 65 Figure 7. Second-Order Harmonic Distortion vs. Frequency for Various Output Powers TA = –40°C –60 TA = +25°C B SO –65 VOUT = 60dBmV @ MAX GAIN TA = +85°C TA = +25°C TA = –40°C 15 25 35 45 55 –65 65 03158-011 03158-008 5 Figure 8. Second-Order Harmonic Distortion vs. Frequency vs. Temperature 10 CH PWR ACP 0 5 15 25 35 45 FREQUENCY (MHz) 55 65 Figure 11. Third-Order Harmonic Distortion vs. Frequency vs. Temperature 60 60dBmV –58.2dB O –10 50 30 VOUT (dBmV) –30 –40 –50 VOUT = 57dBmV/TONE @ MAX GAIN 40 –20 20 10 0 –10 –60 –20 –70 C0 C0 c11 cu1 75kHz/DIV cu1 03158-012 c11 –30 03158-009 POUT (dBm) 65 –60 FREQUENCY (MHz) –90 55 TA = +85°C –70 –80 25 35 45 FREQUENCY (MHz) –55 DISTORTION (dBc) –55 15 LE –50 VOUT = 60dBmV @ MAX GAIN DISTORTION (dBc) 5 Figure 10. Third-Order Harmonic Distortion vs. Frequency for Various Output Powers –50 –75 VOUT = 59dBmV @ MAX GAIN 03158-010 VOUT = 61dBmV @ MAX GAIN DISTORTION (dBc) DISTORTION (dBc) –60 VOUT = 60dBmV @ MAX GAIN –40 41.6 SPAN 750kHz Figure 9. Adjacent Channel Power 41.7 41.8 41.9 42.0 42.1 42.2 FREQUENCY (MHz) 42.3 42.4 Figure 12. Two-Tone Intermodulation Distortion Rev. A | Page 8 of 20 42.5 AD8328 0 40 –20 DEC60 –30 DEC48 DEC42 0 DEC36 –10 DEC30 DEC24 –20 –60 –80 03158-013 DEC12 DEC 1 TO DEC 6 1 10 100 FREQUENCY (MHz) MAX GAIN –90 –100 1000 MIN GAIN 1 100 1000 FREQUENCY (MHz) Figure 13. AC Response Figure 16. Isolation in Transmit Disable Mode vs. Frequency 1.4 1.6 f = 10MHz 1.2 1.2 0.4 f = 10MHz 0 f = 5MHz LE GAIN ERROR (dB) 0.8 1.0 0.8 –0.4 f = 42MHz –0.8 0 B SO 03158-014 –1.2 6 12 18 24 30 36 42 48 54 –1.6 60 GAIN CONTROL (Decimal Code) 0 100 80 f = 10MHz 130 TXEN = 1 120 O 60 40 03158-015 20 0 0 6 12 18 24 30 36 42 48 GAIN CONTROL (Decimal Code) 54 18 24 30 36 42 48 54 60 110 100 90 80 70 60 50 40 03158-018 120 12 Figure 17. Gain Error vs. Gain Control QUIESCENT SUPPLY CURRENT (mA) 140 6 f = 65MHz GAIN CONTROL (Decimal Code) Figure 14. Output Step Size vs. Gain Control OUTPUT REFERRED VOLTAGE NOISE (nV/√Hz) 10 TE –40 0.1 OUTPUT STEP SIZE (dB) –50 –70 DEC18 –30 –40 03158-017 GAIN (dB) ISOLATION (dB) DEC54 10 03158-016 20 0.6 TXEN = 0 VIN = 29dBmV –10 30 30 20 60 0 Figure 15. Output Referred Voltage Noise vs. Gain Control 10 20 30 40 GAIN CONTROL (Decimal Code) 50 Figure 18. Supply Current vs. Gain Control Rev. A | Page 9 of 20 60 AD8328 APPLICATIONS SPI PROGRAMMING AND GAIN ADJUSTMENT The AD8328 is primarily intended for use as the power amplifier (PA) in Data Over Cable Service Interface Specification (DOCSIS)-certified cable modems and CATV set-top boxes. The upstream signal is either a QPSK or QAM signal generated by a DSP, a dedicated QPSK/QAM modulator, or a DAC. In all cases, the signal must be low-pass filtered before being applied to the PA to filter out-of-band noise and higher order harmonics from the amplified signal. The AD8328 is controlled through a serial peripheral interface (SPI) of three digital data lines: CLK, DATEN, and SDATA. Changing the gain requires eight bits of data to be streamed into the SDATA port. The sequence of loading the SDATA register begins on the falling edge of the DATEN pin, which activates the CLK line. With the CLK line activated, data on the SDATA line is clocked into the serial shift register on the rising edge of the CLK pulses, MSB first. The 8-bit data-word is latched into the attenuator core on the rising edge of the DATEN line. This provides control over the changes in the output signal level. The serial interface timing for the AD8328 is shown in Figure 3 and Figure 4. The programmable gain range of the AD8328 is −28 dB to +31 dB with steps of 1 dB per least significant bit (LSB). This provides a total gain range of 59 dB. The AD8328 was characterized with a differential signal on the input and a TOKO 458PT-1087 2:1 transformer on the output. The AD8328 incorporates supply current scaling with gain code, as shown in Figure 18. This allows reduced power consumption when operating in lower gain codes. LE Due to the varying distances between the cable modem and the head-end, the upstream PA must be capable of varying the output power by applying gain or attenuation. The ability to vary the output power of the AD8328 ensures that the signal from the cable modem has the proper level once it arrives at the head-end. The upstream signal path commonly includes a diplexer and cable splitters. The AD8328 has been designed to overcome losses associated with these passive components in the upstream cable path. TE GENERAL APPLICATIONS CIRCUIT DESCRIPTION INPUT BIAS, IMPEDANCE, AND TERMINATION The VIN+ and VIN− inputs have a dc bias level of VCC/2; therefore, the input signal should be ac-coupled as shown in Figure 20. The differential input impedance of the AD8328 is approximately 1.6 kΩ, while the single-ended input is 800 Ω. The high input impedance of the AD8328 allows flexibility in termination and properly matching filter networks. The AD8328 exhibits optimum performance when driven with a pure differential signal. B SO The AD8328 is composed of three analog functions in the power-up or forward mode. The input amplifier (preamp) can be used single-ended or differentially. If the input is used in the differential configuration, it is imperative that the input signals be 180° out of phase and of equal amplitude. A vernier is used in the input stage for controlling the fine 1 dB gain steps. This stage then drives a DAC, which provides the bulk of the AD8328’s attenuation. The signals in the preamp and DAC gain blocks are differential to improve the PSRR and linearity. A differential current is fed from the DAC into the output stage. The output stage maintains 300 Ω differential output impedance, which maintains proper match to 75 Ω when used with a 2:1 balun transformer. O 5V OUTPUT BIAS, IMPEDANCE, AND TERMINATION The output stage of the AD8328 requires a bias of 5 V. The 5 V power supply should be connected to the center tap of the output transformer. In addition, the VCC applied to the center tap of the transformer should be decoupled as seen in Figure 20. VCC VIN+ VOUT+ AD8328 1V 2 IN VIN– BYP GND 03158-019 1V 2 IN RL VOUT– Figure 19. Characterization Circuit Rev. A | Page 10 of 20 AD8328 VCC 10µF 1 0.1µF VIN+ 165Ω 0.1µF VIN– SDATA CLK TXEN SLEEP 1kΩ 20 GND 19 VCC 18 TXEN 17 RAMP 16 VOUT+ 15 VOUT– 14 BYP 13 NC 0.1μF 12 SLEEP 11 GND 0.1μF TO DIPLEXER ZIN = 75Ω TOKO 458PT-1087 0.1μF 1kΩ 1kΩ 1kΩ 1kΩ 03158-020 DATEN QSOP TE ZIN = 150Ω AD8328 GND 2 VCC 3 GND 4 GND 5 VIN+ 6 VIN– 7 GND 8 DATEN 9 SDATA 10 CLK Figure 20. Typical Application Circuit Table 6. Adjacent Channel Power LE Adjacent Channel Symbol Rate (kSym/s) 160 320 640 1280 −58 −60 −63 −66 −58 −59 −60 −64 −60 −58 −59 −61 −62 −60 −59 −60 −64 −62 −60 −59 −66 −65 −62 −61 B SO Channel Symbol Rate (kSym/s) 160 320 640 1280 2560 5120 O The output impedance of the AD8328 is 300 Ω, regardless of whether the amplifier is in transmit enable or transmit disable mode. This, when combined with a 2:1 voltage ratio (4:1 impedance ratio) transformer, eliminates the need for external back termination resistors. If the output signal is being evaluated using standard 50 Ω test equipment, a minimum loss 75 Ω to 50 Ω pad must be used to provide the test circuit with the proper impedance match. The AD8328 evaluation board provides a convenient means to implement a matching attenuator. Soldering a 43.3 Ω resistor in the R15 placeholder and an 86.6 Ω resistor in the R16 placeholder allows testing on a 50 Ω system. When using a matching attenuator, it should be noted that there is a 5.7 dB of power loss (7.5 dB voltage) through the network. POWER SUPPLY The 5 V supply should be delivered to each of the VCC pins via a low impedance power bus to ensure that each pin is at the same potential. The power bus should be decoupled to ground using a 10 μF tantalum capacitor located close to the AD8328. In addition to the 10 μF capacitor, each VCC pin should be individually decoupled to ground with ceramic chip capacitors located close to the pins. The bypass pin, BYP, should also be decoupled. The PCB should have a low impedance ground plane covering all unused portions of the board, except in areas of the board where input and output traces are in close proximity to the 2560 −66 −66 −64 −61 −60 −59 5120 −64 −65 −65 −63 −61 −60 AD8328 and the output transformer. All AD8328 ground pins must be connected to the ground plane to ensure proper grounding of all internal nodes. SIGNAL INTEGRITY LAYOUT CONSIDERATIONS Careful attention to printed circuit board layout details will prevent problems due to board parasitics. Proper RF design techniques are mandatory. The differential input and output traces should be kept as short as possible. Keeping the traces short minimizes parasitic capacitance and inductance. This is most critical between the outputs of the AD8328 and the 2:1 output transformer. It is also critical that all differential signal paths be symmetrical in length and width. In addition, the input and output traces should be adequately spaced to minimize coupling (crosstalk) through the board. Following these guidelines optimizes the overall performance of the AD8328 in all applications. Rev. A | Page 11 of 20 AD8328 When the supply voltage is first applied to the AD8328, the gain of the amplifier is initially set to Gain Code 1. Since power is first applied to the amplifier, the TXEN pin should be held low (Logic 0) to prevent forward signal transmission. After power is applied to the amplifier, the gain can be set to the desired level by following the procedure provided in the SPI Programming and Gain Adjustment section. The TXEN pin can then be brought from Logic 0 to Logic 1, enabling forward signal transmission at the desired gain level. RAMP PIN AND BYP PIN FEATURES Another measure of signal integrity is adjacent channel power, commonly referred to as ACP. DOCSIS 2.0, Section 6.2.21.1.1 states, “Spurious emissions from a transmitted carrier may occur in an adjacent channel that could be occupied by a carrier of the same or different symbol rates.” Figure 9 shows the measured ACP for a 60 dBmV QPSK signal taken at the output of the AD8328 evaluation board. The transmit channel width and adjacent channel width in Figure 9 correspond to the symbol rates of 160 kSym/s. Table 6 shows the ACP results for the AD8328 driving a QPSK 60 dBmV signal for all conditions in DOCSIS Table 6-9, Adjacent Channel Spurious Emissions. NOISE AND DOCSIS At minimum gain, the AD8328 output noise spectral density is 1.2 nV/√Hz measured at 10 MHz. DOCSIS Table 6-10, Spurious Emissions in 5 MHz to 42 MHz, specifies the output noise for various symbol rates. The calculated noise power in dBmV for 160 kSym/s is LE The RAMP pin is used to control the length of the burst on and off transients. By default, leaving the RAMP pin unconnected results in a transient that is fully compliant with DOCSIS 2.0 Section 6.2.21.2, Spurious Emissions During Burst On/Off Transients. DOCSIS requires that all between-burst transients must be dissipated no faster than 2 μs; and adding capacitance to the RAMP pin adds more time to the transient. various output power levels. These figures are useful for determining the in-band harmonic levels from 5 MHz to 65 MHz. Harmonics higher in frequency (above 42 MHz for DOCSIS and above 65 MHz for EuroDOCSIS) are sharply attenuated by the low-pass filter function of the diplexer. TE INITIAL POWER-UP B SO The BYP pin is used to decouple the output stage at midsupply. Typically, for normal DOCSIS operation, the BYP pin should be decoupled to ground with a 0.1 μF capacitor. However, in applications that require transient on/off times faster than 2 μs, smaller capacitors can be used, but it should be noted that the BYP pin should always be decoupled to ground. TRANSMIT ENABLE (TXEN) AND SLEEP O The asynchronous TXEN pin is used to place the AD8328 into between-burst mode. In this reduced current state, the output impedance of 75 Ω is maintained. Applying Logic 0 to the TXEN pin deactivates the on-chip amplifier, providing a 97.8% reduction in consumed power. For 5 V operation, the supply current is typically reduced from 120 mA to 2.6 mA. In this mode of operation, between-burst noise is minimized and high input to output isolation is achieved. In addition to the TXEN pin, the AD8328 also incorporates an asynchronous SLEEP pin, which can be used to further reduce the supply current to approximately 20 μA. Applying Logic 0 to the SLEEP pin places the amplifier into SLEEP mode. Transitioning into or out of SLEEP mode can result in a transient voltage at the output of the amplifier. DISTORTION, ADJACENT CHANNEL POWER, AND DOCSIS To deliver the DOCSIS required 58 dBmV of QPSK signal and 55 dBmV of 16 QAM signal, the PA is required to deliver up to 60 dBmV. This added power is required to compensate for losses associated with the diplex filter or other passive components that may be included in the upstream path of cable modems or set-top boxes. It should be noted that the AD8328 was characterized with a differential input signal. Figure 7 and Figure 10 show the AD8328 second and third harmonic distortion performance vs. the fundamental frequency for 2 ⎡ ⎛ ⎞⎤ ⎢20 × log⎜ ⎛⎜ 1.2 nV ⎞⎟ × 160 kHz ⎟⎥ + 60 = −66.4 dBmV ⎜⎜ ⎝ Hz ⎠ ⎟⎟⎥ ⎢ ⎝ ⎠⎦ ⎣ (1) Comparing the computed noise power of −66.4 dBmV to the +8 dBmV signal yields −74.4 dBc, which meets the required level set forth in DOCSIS Table 6-10. As the AD8328 gain is increased above this minimum value, the output signal increases at a faster rate than the noise, resulting in a signalto-noise ratio that improves with gain. In transmit disable mode, the output noise spectral density is 1.1 nV/√Hz, which results in −67 dBmV when computed over 160 kSym/s. The noise power was measured directly at the output of the AD8328AR-EVAL board. EVALUATION BOARD FEATURES AND OPERATION The AD8328 evaluation board and control software can be used to control the AD8328 upstream cable driver via the parallel port of a PC. A standard printer cable connected to the parallel port of the PC is used to feed all the necessary data to the AD8328 using the Windows®-based control software. This package provides a means of controlling the gain and the power mode of the AD8328. With this evaluation kit, the AD8328 can be evaluated in either a single-ended or differential input configuration. See Figure 26 for a schematic of the evaluation board. Rev. A | Page 12 of 20 AD8328 requires the removal of R2 and R3 to be shorted with R4 open, as well as the addition of 82.5 Ω at R1 and 39.2 Ω at R17 for 75 Ω termination. Table 7 shows the correct values for R11 and R12 for some common input configurations. Other input impedance configurations can be accommodated using Equation 4 and Equation 5. DIFFERENTIAL SIGNAL SOURCE Typical applications for the AD8328 use a differential input signal from a modulator or a DAC. See Table 7 for common values of R4, or calculate other input configurations using Equation 2. This circuit configuration will give optimal distortion results due to the symmetric input signals. Note that this configuration was used to characterize the AD8328. (2) 1.6 kΩ − Z IN (4) Z IN × R1 R1 + Z IN (5) R17 = VIN+ AD8328 VIN+ 03158-021 R4 VIN– AD8328 R1 TE ZIN Z IN × 800 800 − Z IN ZIN Figure 21. Differential Circuit R17 DIFFERENTIAL SIGNAL FROM SINGLE-ENDED SOURCE 03158-023 R4 = Z IN × 1.6 kΩ R1 = Figure 23. Single-Ended Circuit Table 7. Common Matching Resistors ZIN (Ω) 50 75 100 150 Differential Input Termination R2/R3 R4 (Ω) R1/R17 Open 51.1 Open/Open Open 78.7 Open/Open Open 107.0 Open/Open Open 165.0 Open/Open Single-Ended Input Termination R2 (Ω)/R3 (Ω) R4 (Ω) R1 (Ω)/R17 (Ω) 0/0 Open 53.6/25.5 0/0 Open 82.5/39.2 B SO LE The default configuration of the evaluation board implements a differential signal drive from a single-ended signal source. This configuration uses a 1:1 balun transformer to approximate a differential signal. Because of the nonideal nature of real transformers, the differential signal is not purely equal and opposite in amplitude. Although this circuit slightly sacrifices even-order harmonic distortion due to asymmetry, it does provide a convenient way to evaluate the AD8328 with a singleended source. The AD8328 evaluation board is populated with a TOKO 617DB-A0070 1:1 for this purpose (T1). Table 7 provides typical R4 values for common input configurations. Other input impedances can be calculated using Equation 3. See Figure 26 for a schematic of the evaluation board. To use the transformer for converting a single-ended source into a differential signal, the input signal must be applied to VIN+. R4 = Z IN × 1.6 kΩ (3) 1.6 kΩ − Z IN ZIN R4 AD8328 OVERSHOOT ON PC PRINTER PORTS The data lines on some PC parallel printer ports have excessive overshoot that can cause communication problems when presented to the CLK pin of the AD8328. The evaluation board was designed to accommodate a series resistor and shunt capacitor (R2 and C5 in Figure 26) to filter the CLK signal if required. INSTALLING VISUAL BASIC CONTROL SOFTWARE Install the CabDrive_28 software by running the setup.exe file on Disk One of the AD8328 evaluation software. Follow the onscreen directions and insert Disk Two when prompted. Choose the installation directory and then select the icon in the upper left to complete the installation. 03158-022 O VIN+ ZIN (Ω) 50 75 Figure 22. Single-to-Differential Circuit SINGLE-ENDED SOURCE Although the AD8328 was designed to have optimal DOCSIS performance when used with a differential input signal, the AD8328 can also be used as a single-ended receiver, or an IF digitally controlled amplifier. However, as with the singleended-to-differential configuration previously noted, evenorder harmonic distortion is slightly degraded. When operating the AD8328 in a single-ended input mode, VIN+ and VIN– should be terminated as shown in Figure 23. On the AD8328 evaluation boards, this termination method Rev. A | Page 13 of 20 AD8328 RUNNING AD8328 SOFTWARE TRANSMIT ENABLE AND SLEEP MODE To load the control software, go to Start, Programs, CABDRIVE_28 or select the AD8328.exe file from the installed directory. Once loaded, select the proper parallel port to communicate with the AD8328 (see Figure 24). The Transmit Enable and Transmit Disable buttons select the mode of operation of the AD8328 by asserting logic levels on the asynchronous TXEN pin. The Transmit Disable button applies Logic 0 to the TXEN pin, disabling forward transmission. The Transmit Enable button applies Logic 1 to the TXEN pin, enabling the AD8328 for forward transmission. Checking the Enable SLEEP Mode box applies Logic 0 to the asynchronous SLEEP pin, setting the AD8328 for SLEEP mode. MEMORY FUNCTIONS Figure 24. Parallel Port Selection TE LE 03158-024 The Memory section of the software provides a way to alternate between two gain settings. The X→M1 button stores the current value of the GAIN SLIDER into memory, while the RM1 button recalls the stored value, returning the gain SLIDER to the stored level. The same applies to the X→M2 and RM2 buttons. CONTROLLING GAIN/ATTENUATION OF THE AD8328 03158-025 O B SO The SLIDER controls the gain/attenuation of the AD8328, which is displayed in dB and in V/V. The gain scales 1 dB per LSB. The gain code from the position of the SLIDER is displayed in decimal, binary, and hexadecimal (see Figure 25). Figure 25. Control Software Interface Rev. A | Page 14 of 20 AD8328 VIN+_A C1A 0.1µF R2 TP9 TOKO 617DB-A0070 VIN–_A R4 78.7Ω C2A 0.1μF R3 1 2 3 R17 P1 2 TP1 R5 1kΩ 4 R6 0Ω 5 6 C3 7 8 P1 3 TP2 R7 1kΩ R8 0Ω P1 5 TP3 10 GND VCC VCC GND TXEN RAMP 16 VIN– VOUT– 15 GND BYP SDATA NC SLEEP CLK GND QSOP R10 0Ω R12 0Ω R14 0Ω 14 13 C12 0.1µF VCC1 1 6 2 3 12 CABLE_OA R16 4 11 B SO C7 P1 16 TOKO R15 458PT-1087 0Ω C13 0.1µF TP_AGND1 AGND1 TP5 R13 1kΩ C11 TP10 C6 P1 7 C10 0.1µF 17 LE P1 6 TP4 18 VOUT+ DATEN C9 0.1µF 19 VIN+ C5 R11 1kΩ 20 GND AD8328 C4 R9 1kΩ 9 GND VCC C8 10µF O Figure 26. AD8328 Evaluation Board Schematic Rev. A | Page 15 of 20 TP11 TP12 TP_VCC1 VCC1 P1 19 P1 20 P1 21 P1 22 P1 23 P1 24 P1 25 P1 26 P1 27 P1 28 P1 29 P1 30 P1 33 03158-026 T1 TE R1 03158-030 03158-027 TE AD8328 Figure 30. Internal Ground Plane Figure 31. Secondary Side 03158-029 03158-032 O Figure 28. Component Side Silkscreen 03158-031 03158-028 B SO LE Figure 27. Primary Side Figure 32. Secondary Side Silkscreen Figure 29. Internal Power Plane Rev. A | Page 16 of 20 AD8328 OUTLINE DIMENSIONS 0.60 MAX 4.00 BSC SQ 0.60 MAX TOP VIEW 1.00 0.85 0.80 SEATING PLANE 0.75 0.55 0.35 11 10 6 2.25 2.10 SQ 1.95 5 0.25 MIN 0.30 0.23 0.18 0.05 MAX 0.02 NOM 0.20 REF 0.50 BSC 20 1 3.75 BCS SQ 0.80 MAX 0.65 TYP 12° MAX 16 15 TE PIN 1 INDICATOR PIN 1 INDICATOR COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1 LE Figure 33. 20-Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-20-1) Dimensions shown in millimeters 0.345 0.341 0.337 11 B SO 20 1 0.158 0.154 0.150 10 0.244 0.236 0.228 PIN 1 0.065 0.049 0.010 0.004 0.069 0.053 0.025 BSC COPLANARITY 0.004 0.012 0.008 SEATING PLANE 0.010 0.006 8° 0° O COMPLIANT TO JEDEC STANDARDS MO-137-AD Figure 34. 20-Lead Shrink Small Outline Package [QSOP] (RQ-20) Dimensions shown in inches Rev. A | Page 17 of 20 0.050 0.016 AD8328 ORDERING GUIDE Package Description 20-Lead QSOP 20-Lead QSOP 20-Lead QSOP 20-Lead QSOP 20-Lead LFCSP_VQ 20-Lead LFCSP_VQ 20-Lead LFCSP_VQ 20-Lead LFCSP_VQ 20-Lead LFCSP_VQ 20-Lead LFCSP_VQ Evaluation Board Evaluation Board B SO LE Z = Pb-free part. O 1 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Option RQ-20 RQ-20 RQ-20 RQ-20 CP-20-1 CP-20-1 CP-20-1 CP-20-1 CP-20-1 CP-20-1 TE Model AD8328ARQ AD8328ARQ-REEL AD8328ARQZ 1 AD8328ARQZ-REEL1 AD8328ACP AD8328ACP-REEL AD8328ACP-REEL7 AD8328ACPZ1 AD8328ACPZ-REEL1 AD8328ACPZ-REEL71 AD8328ACP-EVAL AD8328ARQ-EVAL Rev. A | Page 18 of 20 AD8328 O B SO LE TE NOTES Rev. A | Page 19 of 20 AD8328 O B SO LE TE NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03158–0–10/05(A) Rev. A | Page 20 of 20