AD8333ACPZ-REEL

RFIP RFIN BIAS CH 1 ΦSEL LOGIC PH13 0° Medical imaging (CW ultrasound beamforming) Phased array systems (radar and adaptive antennas) Communication receivers Φ I1NO I1PO Φ Q1PO Q1NO Φ Q2NO Q2PO Φ I2PO I2NO COMM 90° 4LOP BUF ÷4 90° 4LON 0° PH23 PH22 CH 2 ΦSEL LOGIC 05543-001 PH12 RF2P RF2N APPLICATIONS ENBL FUNCTIONAL BLOCK DIAGRAM Dual integrated I/Q demodulator 16 phase select options on each output (22.5° per step) Quadrature demodulation accuracy Phase accuracy: ±0.1° Amplitude balance: ±0.05 dB Bandwidth 4 × LO: 10 kHz to 200 MHz RF: dc to 50 MHz Baseband: determined by external filtering Output dynamic range: 159 dB/Hz LO drive > 0 dBm (50 Ω); 4 × LO > 1 MHz Supply: ±5 V Power consumption: 190 mW/channel (380 mW total) Power-down PH11 FEATURES PH10 Data Sheet DC to 50 MHz, Dual I/Q Demodulator and Phase Shifter AD8333 Figure 1. GENERAL DESCRIPTION The AD8333 1 is a dual phase-shifter and I/Q demodulator that enables coherent summing and phase alignment of multiple analog data channels. It is the first solid-state device suitable for beamformer circuits, such as those used in high performance medical ultrasound equipment featuring CW Doppler. The RF inputs interface directly with the outputs of the dual-channel, low noise preamplifiers included in the AD8332. A divide-by-4 circuit generates the internal 0° and 90° phases of the local oscillator (LO) that drive the mixers of a pair of matched I/Q demodulators. The AD8333 can be applied as a major element in analog beamformer circuits in medical ultrasound equipment. The AD8333 features an asynchronous reset pin. When used in arrays, the reset pin sets all the LO dividers in the same state. Sixteen discrete phase rotations in 22.5° increments can be selected independently for each channel. For example, if Channel 1 is used as a reference and the RF signal applied to Channel 2 has an I/Q phase lead of 45°, Channel 2 can be phase aligned with Channel 1 by choosing the correct code. Phase shift is defined by the output of one channel relative to another. For example, if the code of Channel 1 is adjusted to 0000 and that of Channel 2 is adjusted to 0001 and the same signal is applied to both RF inputs, the output of Channel 2 leads that of Channel 1 by 22.5°. The I and Q outputs are provided as currents to facilitate summation. The summed current outputs are converted to voltages by a high dynamic range, current-to-voltage (I-V) converter, such as the AD8021, configured as a transimpedance amplifier. The resultant signal is then applied to a high resolution ADC, such as the AD7665 (16 bit/570 kSPS). The two I/Q demodulators can be used independently in other nonbeamforming applications. In that case, a transimpedance amplifier is needed for each of the I and Q outputs, four in total for the dual I/Q demodulator. The dynamic range is 159 dB/Hz at the I and Q outputs, but the following transimpedance amplifier is an important element in maintaining the overall dynamic range, and attention needs to be paid to optimal component selection and design. The AD8333 is available in a 32-lead LFCSP (5 mm × 5 mm) package for the industrial temperature range of −40°C to +85°C. 1 Protected by US Patent 7,760,833. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2005–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD8333 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Channel Summing ..................................................................... 21 Applications ....................................................................................... 1 Dynamic Range Inflation .......................................................... 23 Functional Block Diagram .............................................................. 1 Disabling the Current Mirror and Decreasing Noise ............ 23 General Description ......................................................................... 1 Applications Information .............................................................. 25 Revision History ............................................................................... 3 Logic Inputs and Interfaces ....................................................... 25 Specifications..................................................................................... 4 Reset Input .................................................................................. 25 Absolute Maximum Ratings ............................................................ 6 ESD Caution .................................................................................. 6 Connecting to the LNA of the AD8331/AD8332/AD8334/AD8335 VGAs............................ 25 Pin Configuration and Function Descriptions ............................. 7 Interfacing to Other Amplifiers ............................................... 26 Equivalent Input Circuits ................................................................ 8 LO Input ...................................................................................... 26 Typical Performance Characteristics ............................................. 9 Evaluation Board ............................................................................ 27 Test Circuits ..................................................................................... 15 Features and Options ................................................................. 27 Theory of Operation ...................................................................... 18 Measurement Setup.................................................................... 28 Quadrature Generation ............................................................. 18 Evaluation Board Schematic and Artwork.................................. 29 I/Q Demodulator and Phase Shifter ........................................ 18 Board Layout ............................................................................... 31 Dynamic Range and Noise ........................................................ 19 Outline Dimensions ....................................................................... 32 Summation of Multiple Channels (Analog Beamforming) .. 20 Ordering Guide .......................................................................... 32 Phase Compensation and Analog Beamforming ................... 20 Rev. F | Page 2 of 32 Data Sheet AD8333 REVISION HISTORY 5/2016—Rev. E to Rev. F Change to Features Section and General Description Section......... 1 Change to Quiescent Power Parameter, Table 1............................ 5 Changes to Figure 2 and Table 3 ..................................................... 7 Change to Figure 52 ........................................................................18 Change to Figure 61 ........................................................................28 Change to Figure 64 ........................................................................29 Updated Outline Dimensions ........................................................32 Changes to Ordering Guide ...........................................................32 8/2012—Rev. D to Rev. E Changes to Figure 1 and General Description Section ................ 1 Moved Revision History Section ..................................................... 3 Changes to Table 3 ............................................................................ 7 Changes to Table 5 ..........................................................................27 Updated Outline Dimensions ........................................................33 9/2010—Rev. C to Rev. D Change to I2NO, Q2NO, Q1NO, and I1NO Pin Description, Table 3 ................................................................................................. 6 Changes to Figure 62, Features and Options Section, Table 5, Phase Nibble Section, and Enable and Reset Switches Section ..............................................................................................26 Changes to Reset Input Section, Measurement Setup Section, and Figure 63 ...................................................................................27 Changes to Figure 64 ......................................................................28 Changes to Figure 65 ......................................................................29 Changes to Figure 66 Through Figure 70 ....................................30 Deleted Ordering Information Section ........................................37 Deleted Table 7; Renumbered Sequentially .................................37 9/2008—Rev. B to Rev. C Changes to Figure 1........................................................................... 1 Changes to General Description Section ....................................... 1 Change to Table 2 .............................................................................. 5 Changes to Figure 4 and Figure 6.................................................... 7 Change to Figure 18 .......................................................................... 9 Changes to Dynamic Range and Noise Section .......................... 18 Changes to Connecting to the LNA of the AD8331/AD8332/ AD8334/AD8335 VGAs Section ................................................... 24 Added Interfacing to Other Amplifiers Heading........................ 25 Changes to Figure 61 ...................................................................... 25 Incorporated AD8333-EVALZ Data Sheet .................................. 26 Changes to Evaluation Board Section .......................................... 26 Changes to Features and Options Section ................................... 26 Changes to Table 5 .......................................................................... 26 Replaced the Phase Bits Section with the Phase Nibble Section .............................................................................................. 26 Deleted Table 2 .................................................................................. 3 Changes to LNA Input Impedance Section ................................. 26 Changes to Current Summing Section......................................... 26 Changes to Measurement Setup Section ...................................... 27 Moved Figure 63; Changes to Figure 63....................................... 27 Changes to Figure 64 ...................................................................... 28 Moved Figure 70 .............................................................................. 30 Changes to Table 7 .......................................................................... 31 Deleted Figure 62; Renumbered Sequentially ............................. 26 Updated Outline Dimensions........................................................ 32 Changes to Ordering Guide ........................................................... 32 5/2007—Rev. A to Rev. B Changes to Features and Figure 1 ................................................... 1 Changes to Table 1 ............................................................................ 3 Changes to Figure 41 to Figure 43 ................................................ 14 Changes to Figure 44 to Figure 47 ................................................ 15 Changes to Figure 48 to Figure 51 ................................................ 16 Changes to Figure 55 ...................................................................... 20 Changes to Evaluation Board Section .......................................... 25 Changes to Ordering Guide ........................................................... 27 5/2006—Rev. 0 to Rev. A Changes to Figure 62 ...................................................................... 26 10/2005—Revision 0: Initial Version Rev. F | Page 3 of 32 AD8333 Data Sheet SPECIFICATIONS VS = ±5 V, TA = 25°C, f4LO = 20 MHz, fRF = 5.01 MHz, fBB = 10 kHz, PLO ≥ 0 dBm, single-ended, sine wave; per channel performance, dBm (50 Ω), unless otherwise noted (see Figure 41). Table 1. Parameter OPERATING CONDITIONS LO Frequency Range RF Frequency Range Baseband Bandwidth LO Input Level VSUPPLY (VS) Temperature Range DEMODULATOR PERFORMANCE RF Differential Input Impedance LO Differential Input Capacitance Transconductance Dynamic Range Maximum RF Input Swing Peak Output Current (No Filtering) Input P1dB Third-Order Intermodulation (IM3) Equal Input Levels Unequal Input Levels Third-Order Input Intercept (IP3) LO Leakage Conversion Gain Input-Referred Noise Output Current Noise Noise Figure Bias Current LO Common-Mode Voltage Range RF Common-Mode Voltage Output Compliance Range PHASE ROTATION PERFORMANCE Phase Increment Quadrature Phase Error I/Q Amplitude Imbalance Channel-to-Channel Matching Test Conditions/Comments Min 4× internal LO at Pin 4LOP and Pin 4LON Square wave Sine wave, see Figure 22 Mixing Limited by external filtering See Figure 22 0.01 2 DC DC ±4.5 −40 Demodulated IOUT/VIN, each I or Q output after low-pass filtering measured from RF inputs, all phases IP1dB, input-referred noise (dBm) Differential; inputs biased at 2.5 V; Pin RFxP and Pin RFxN 0° phase shift 45° phase shift Reference = 50 Ω Reference = 1 V rms fRF1 = 5.010 MHz, fRF2 = 5.015 MHz, fLO = 5.023 MHz Baseband tones: −7 dBm at 8 kHz and 13 kHz Baseband tones: −1 dBm at 8 kHz and −31 dBm at 13 kHz fRF1 = 5.010 MHz, fRF2 = 5.015 MHz, fLO = 5.023 MHz Measured at RF inputs, worst phase, measured into 50 Ω (limited by measurement) Measured at baseband outputs, worst phase, AD8021 disabled, measured into 50 Ω All codes Output noise/conversion gain Output noise ÷ 787 Ω With AD8332 LNA RS = 50 Ω, RFB = ∞ RS = 50 Ω, RFB = 1.1 kΩ RS = 50 Ω, RFB = 274 Ω Pin 4LOP and Pin 4LON Pin RFxP and Pin RFxN Pin 4LOP and Pin 4LON (each pin) For maximum differential swing; Pin RFxP and Pin RFxN (dc-coupled to AD8332 LNA output) Pin IxPO and Pin QxPO One channel is reference; the other channel is stepped 16 phase steps per channel I1xO to Q1xO and I2xO to Q2xO, 1σ I1xO to Q1xO and I2xO to Q2xO, 1σ Phase match I1xO/I2xO and Q1xO/Q2xO; −40°C < TA < 85°C Amplitude match I1xO/I2xO and Q1xO/Q2xO; −40°C < TA < 85°C Rev. F | Page 4 of 32 Typ 0 ±5 Max Unit 200 200 50 50 13 ±6 +85 MHz MHz MHz MHz dBm V °C 6.7||6.5 0.6 2.17 kΩ||pF pF mS 159 2.8 ±4.7 ±6.6 14.5 1.5 dB/Hz V p-p mA mA dBm dBV −75 −77 30