AD8335

Quad Low Noise, Low Cost Variable Gain Amplifier AD8335 FEATURES Low noise preamplifier (PrA) Voltage noise = 1.3 nV/√Hz typical Current noise = 2.4 pA/√Hz typical NF = 7 dB (RS = RIN = 50 Ω) Single-ended input; VIN max = 625 mV p-p Active input match Input SNR (noise bandwidth = 20 MHz) = 92 dB VGA Differential output VOUT max = 5 V p-p, RL = 500 Ω differential Gain range (8 dB output gain step) −10 dB to +38 dB—LO gain mode −2 dB to +46 dB—HI gain mode Accurate linear-in-dB gain control PrA + VGA performance −3 dB bandwidth of 70 MHz Excellent overload performance Supply: 5 V Power consumption 95 mW/channel (380 mW total) 65 mW/channel (PrA off; 260 mW total) Power-down FUNCTIONAL BLOCK DIAGRAM VCM2 VCM1 PON1 POP1 EN12 SP12 51 61 60 59 58 53 55 52 49 47 HL12 VIN1 VIP1 VOH1 PIP1 63 18dB PMD1 64 PMD2 1 18dB PIP2 2 PON2 4 POP2 5 VMD2 VMD1 ATTEN –48dB TO 0dB 20dB TO 28dB 46 VOL1 VGN1 SL12 VGN2 VOL2 INTERPOLATOR GAIN INT 56 50 INTERPOLATOR GAIN INT 54 43 VIP2 6 VIN2 7 ATTEN –48dB TO 0dB 20dB TO 28dB 42 VOH2 VOH3 AD8335 39 VIN3 10 VIP3 11 POP3 12 ATTEN –48dB TO 0dB 20dB TO 28dB 38 VOL3 VGN3 SL34 VGN4 VOL4 INTERPOLATOR PON3 13 PIP3 15 18dB PMD3 16 PMD4 17 18dB VMD4 VMD3 GAIN INT 27 31 INTERPOLATOR GAIN INT 25 35 APPLICATIONS Medical imaging (ultrasound, gamma cameras) Sonar Test and measurement Precise, stable wideband gain control PIP4 18 ATTEN –48dB TO 0dB 20dB TO 28dB 34 VOH4 20 21 22 23 28 26 29 30 32 04976-001 POP4 EN34 SP34 VIP4 PON4 VCM3 Figure 1. GENERAL DESCRIPTION The AD8335 is a quad variable gain amplifier (VGA) with low noise preamplifier intended for cost and power sensitive applications. Each channel features a gain range 48 dB, fully differential signal paths, active input preamplifier matching, and user-selectable maximum gains of 46 dB and 38 dB. Individual gain controls are provided for each channel. The preamplifier (PrA) has a single-ended to differential gain of ×8 (18.06 dB) and accepts input signals ≤ 625 mV p-p. PrA noise is 1.2 nV/√Hz and the combined input referred voltage noise of the PrA and VGA is 1.3 nV/√Hz at maximum gain. Assuming a 20 MHz noise bandwidth (NBW), the Nyquist frequency for a 40 MHz ADC, the input SNR is 92 dB. The HILO pin optimizes the output SNR for 10-bit and 12-bit ADCs with 1 V p-p or 2 V p-p full-scale (FS) inputs. Channels 1 and 2 are enabled through the EN12 pin while Channels 3 and 4 are enabled through the EN34 pin. For VGA only applications, the PrAs can be powered down, significantly reducing power consumption. The AD8335 is available in a 64-lead lead frame chip scale (9 mm × 9 mm) package for the industrial temperature range of −40°C to +85°C. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. VCM4 HL34 VIN4 AD8335 TABLE OF CONTENTS Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 Typical Performance Characteristics ............................................. 7 Test Circuits..................................................................................... 15 Theory of Operation ...................................................................... 16 Enable Summary......................................................................... 16 Preamp ......................................................................................... 17 Noise......................................................................................... 17 VGA.............................................................................................. 18 Optimizing the System Dynamic Range ............................. 18 Attenuator................................................................................ 18 Gain Control ........................................................................... 19 Output Stage ........................................................................... 19 VGA Noise .............................................................................. 19 Applications..................................................................................... 20 Ultrasound................................................................................... 20 Basic Connections ...................................................................... 21 Preamp Connections.................................................................. 21 Input Overdrive .......................................................................... 23 Input Overload Protection.................................................... 23 Logic Inputs................................................................................. 23 Common-Mode Pins ................................................................. 23 Driving ADCs ............................................................................. 23 Outline Dimensions ....................................................................... 24 Ordering Guide........................................................................... 24 REVISION HISTORY 9/04—Revision 0: Initial Version Rev. 0 | Page 2 of 24 AD8335 SPECIFICATIONS VS = 5 V, TA = 25°C, RL = 500 Ω, f = 5 MHz, CL = 10 pF, LO gain range (−10 dB to +38 dB), RFB = 249 Ω (PrA RIN = 50 Ω) and signal voltage specified differential, per channel performance, dBm (50 Ω), unless otherwise noted. Table 1. Parameter PrA CHARACTERISTICS Gain Input Voltage Range Input Resistance Conditions Single-ended input to differential output Single-ended input to single-ended output PrA output limited to 5 V p-p differential RFB = 249 Ω RFB = 374 Ω RFB = 499 Ω RFB = ∞, low frequency value into PIPx PIPx (Pins 2, 15, 18, 63) With RFB = 249 Ω RS = 0 Ω, RFB = ∞ Min Typ 18 12 625 50 75 100 14.7 1.5 110 1.15 2.4 7 4.4 70 85 250 350 1.3 7 4.5 5.0 1.3 33 80 5 1.2 VS/2 5 0 −69 −57 −57 −55 −58 −70 −55 −55 18 8 Max Unit dB dB mV p-p Ω Ω Ω kΩ pF MHz nV/√Hz pA/√Hz dB dB MHz MHz V/µs V/µs nV/√Hz dB dB dB dB nV/√Hz nV/√Hz V p-p Ω V mV mV dBc dBc dBc dBc dBc dBc dBc dBc dBm dBVpk Input Capacitance −3 dB Small Signal Bandwidth Input Voltage Noise Input Current Noise Noise Figure Active Termination Match Unterminated PrA + VGA CHARACTERISTICS −3 dB Small Signal Bandwidth Slew Rate Input Voltage Noise Noise Figure Active Termination Match Unterminated Output Referred Noise Peak Output Voltage Output Resistance Common-Mode Level Output Offset Voltage Harmonic Distortion HD2 HD3 HD2 HD3 Harmonic Distortion HD2 HD3 HD2 HD3 Output 1 dB Compression (OP1dB) RS = RIN = 50 Ω, RFB = 249 Ω RS = 50 Ω, RFB = ∞ Unterminated: RS = 50 Ω, RFB = ∞ Matched: RS = RIN = 50 Ω LO gain, VGN = 3 V, VOUT = 2 V p-p HI gain, VGN = 3 V, VOUT = 2 V p-p Pins VGNx = 3 V, RS = 0 Ω, RFB = ∞ Pins VGNx = 3 V, f = 1 MHz to 10 MHz RS = RIN = 50 Ω RS = RIN = 100 Ω RS = 50 Ω, RFB = ∞ RS = 500 Ω, RFB = ∞ LO gain; VGN < 2 V HI gain; VGN < 2 V Differential, RL ≥ 500 Ω f < 1 MHz, Pins VOHx, VOLx Set to midsupply for PrA and VGA Differential (VOHx−VOLx) full gain range Common-mode (VOHx−VCMx, VOLx−VCMx) VOUT = 1 V p-p, LO gain, VGN = 2 V f = 1 MHz f = 1 MHz f = 10 MHz f = 10 MHz VOUT = 1 V p-p, HI gain, VGN = 2 V f = 1 MHz f = 1 MHz f = 10 MHz f = 10 MHz VGN = 3 V VGN = 3 V −25 −20 35 20 Rev. 0 | Page 3 of 24 AD8335 Parameter Two-Tone IMD3 Distortion Conditions VOUT = 1 V p-p, VGN = 3 V f1 = 1 MHz, f2 = 1.05 MHz f1 = 10 MHz, f2 = 10.05 MHz VOUT = 1 V p-p, VGN = 3 V f = 1 MHz f = 10 MHz VOUT = 1 V p-p, f = 1 to 10 MHz Pra or VGA Full gain range, f = 1 MHz to 10 MHz Pins VGNx No gain foldover LO gain mode; (Pins HLxx = 0 V) HI gain mode; (Pins HLxx = VS) Nominal (Pins SL12 and SL34 = 2.5 V) Min Typ −69 −65 33 31 −80 10 3.0 0 0 3 VS Max Unit dBc dBc dBm dBm dBc ns ns V V dB dB dB/V µA MHz ns dB dB dB dB dB dB dB Output IP3 (OIP3) Channel-to-Channel Crosstalk Overload Recovery Group Delay Variation GAIN CONTROL INTERFACE Normal Operating Range Maximum Range Gain Range Scale Factor Bias Current Response Bandwidth Response Time GAIN ACCURACY Absolute Gain Error Gain Law Conformance Over Temperature Intercept Channel-to-Channel Matching LOGIC LEVEL—HILO, SHUTDOWN PREAMP, and ENABLE INTERFACES Logic Level High Logic Level Low BIAS CURRENT—HILO, ENABLE Logic high Logic low INPUT RESISTANCE—HILO, ENABLE BIAS CURRENT – SHUTDOWN PREAMP Logic high Logic low INPUT RESISTANCE—SHUTDOWN PREAMP HILO Response Time Enable Response Time POWER SUPPLY Supply Voltage Quiescent Current Over Temperature Quiescent Power Quiescent Current Quiescent Power Quiescent Current Disable Current PSRR 48 dB gain change Pins VGNx 0 ≤ VGN ≤ 0.4 V 0.4 ≤ VGN ≤ 2.6 V, 1σ 2.6 ≤ VGN ≤ 3 V 0.4 ≤ VGN ≤ 2.6 V; −40°C < TA < +85°C LO gain mode; PrA matched to 50 Ω HI gain mode; PrA matched to 50 Ω 0.4 ≤ VGN ≤ 2.6 V Pins HLxx, SPxx, and ENxx −10 to +38 −2 to +46 19.0 20.0 21.0 −0.3 5 350 1.25 −1.25 −7.5 7.5 +1.25 −1.25 ±0.2 ±0.75 −16.1 −8.1 0.15 2.75 0 80 −12 50 20 0 500 0.6 100 Pins VPPx and VPVx 4.5 Per channel—PrA and VGA enabled −40°C < TA < +85°C Per channel—PrA and VGA enabled Per channel—PrA disabled, VGA enabled Per channel—PrA disabled, VGA enabled All channels enabled All channels disabled VGN = 0 V, all bypass capacitors removed, 1 MHz 16 95 13 65 76 0.8 −60 5 19 5 1 V V µA µA kΩ µA µA kΩ µs µs 5.5 22.8 V mA mA mW mA mW mA mA dB Rev. 0 | Page 4 of 24 AD8335 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Voltage Supply VS Preamp Input VGA Inputs Enable, Shutdown Preamp, and HILO Interfaces Gain Power Dissipation (4-layer JEDEC Board (2S2P)) θJA θJC Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering 60 s) Rating 6V VS VS VS VS 2.46 W 26.4°C/W 6.8°C/W −40°C to +85°C −65°C to +150°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only ; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 5 of 24 AD8335 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PMD1 PIP1 VPP1 PON1 POP1 VIP1 VIN1 COM1 VGN1 VCM1 VGN2 VCM2 EN12 SP12 SL12 HL12 PMD2 PIP2 VPP2 PON2 POP2 VIP2 VIN2 COM2 COM3 VIN3 VIP3 POP3 PON3 VPP3 PIP3 PMD3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 IDENTIFIER AD8335 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 GND1 VOH1 VOL1 VPV1 VPV2 VOL2 VOH2 GND2 GND3 VOH3 VOL3 VPV3 VPV4 VOL4 VOH4 GND4 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Table 3. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Mnemonic PMD2 PIP2 VPP2 PON2 POP2 VIP2 VIN2 COM2 COM3 VIN3 VIP3 POP3 PON3 VPP3 PIP3 PMD3 PMD4 PIP4 VPP4 PON4 POP4 VIP4 VIN4 COM4 VGN4 VCM4 VGN3 VCM3 EN34 SP34 SL34 HL34 Function Preamp input common—Ch2 Preamp input—Ch2 Positive supply preamp—Ch2 Preamp output negative—Ch2 Preamp output positive—Ch2 VGA input positive—Ch2 VGA input negative—Ch2 Ground preamp—Ch2 Ground preamp—Ch3 VGA input negative—Ch3 VGA input positive—Ch3 Preamp output positive—Ch3 Preamp output negative—Ch3 Positive supply preamp—Ch3 Preamp input—Ch3 Preamp input common—Ch3 Preamp input common—Ch4 Preamp input—Ch4 Positive supply preamp—Ch4 Preamp output negative—Ch4 Preamp output positive—Ch4 VGA input positive—Ch4 VGA input negative—Ch4 Ground preamp—Ch4 Gain control—Ch4 Common-mode decoupling pin—Ch4 Gain control—Ch3 Common-mode decoupling pin—Ch3 Enable—Ch3 and Ch4 Shutdown—preamp3 and preamp4 Slope decoupling pin—Ch3 and Ch4 HILO pin—Ch3 and Ch4 Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Mnemonic GND4 VOH4 VOL4 VPV4 VPV3 VOL3 VOH3 GND3 GND2 VOH2 VOL2 VPV2 VPV1 VOL1 VOH1 GND1 HL12 SL12 SP12 EN12 VCM2 VGN2 VCM1 VGN1 COM1 VIN1 VIP1 POP1 PON1 VPP1 PIP1 PMD1 Function Ground VGA—Ch4 VGA output positive—Ch4 VGA output negative—Ch4 Positive supply VGA—Ch4 Positive supply VGA—Ch3 VGA output negative—Ch3 VGA output positive—Ch3 Ground VGA —Ch3 Ground VGA — Ch2 VGA output positive—Ch2 VGA output negative—Ch2 Positive supply VGA—Ch2 Positive supply VGA—Ch1 VGA output negative—Ch1 VGA output positive—Ch1 Ground VGA — Ch1 HILO pin—Ch1 and Ch2 Slope decoupling pin—Ch1 and Ch2 Shutdown—preamp1 and preamp2 Enable—Ch1 and Ch2 Common-mode decoupling pin—Ch2 Gain control—Ch2 Common-mode decoupling pin—Ch1 Gain control—Ch1 Ground preamp—Ch1 VGA input negative—Ch1 VGA input positive—Ch1 Preamp output positive—Ch1 Preamp output negative—Ch1 Positive supply preamp—Ch1 Preamp input—Ch1 Preamp input common—Ch1 PMD4 PIP4 VPP4 PON4 POP4 VIP4 VIN4 COM4 VGN4 VCM4 VGN3 VCM3 EN34 SP34 SL34 HL34 Figure 2. LFCSP Pin Configuration Rev. 0 | Page 6 of 24 04976-058 AD8335 TYPICAL PERFORMANCE CHARACTERISTICS VS = 5 V, TA = 25°C, RL = 500 Ω, f = 5 MHz, CL = 10 pF, LO gain range (−10 dB to +38 dB), RFB = 249 Ω (PrA RIN = 50 Ω) and signal voltage specified differential, per channel performance, unless other wise noted. 50 +85°C 40 16 20 18 420 CHANNELS (105 UNITS) VGAIN = 1.5V 30 GAIN (dB) HI GAIN 14 % OF UNITS 20 +25°C 10 –40°C 0 12 10 8 6 4 LO GAIN –10 2 04976-002 04976-005 04976-007 04976-006 –20 0 0.5 1.0 1.5 VGAIN (V) 2.0 2.5 3.0 0 –0.6 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 GAIN ERROR (dB) Figure 3. Gain vs. VGAIN at Three Temperatures (See Figure 49) 2.0 1.5 1.0 25 20 15 Figure 6. Gain Error Histogram 420 CHANNELS (105 UNITS) VGAIN = 1.0V GAIN ERROR (dB) % OF UNITS 0.5 0 –0.5 –1.0 –1.5 –2.0 0 +85°C, LO GAIN +85°C, HI GAIN +25°C, LO GAIN –40°C, LO GAIN 10 5 +25°C, HI GAIN 25 20 15 VGAIN = 2.0V CH 1 TO C H2 CH 1 TO C H4 CH 1 TO C H3 –40°C, HI GAIN 10 5 04976-003 0.5 1.0 1.5 VGAIN (V) 2.0 2.5 3.0 Figure 4. Gain Error vs. VGAIN at Three Temperatures (See Figure 49) 6.0 45 40 4.0 35 GAIN ERROR (dB) 2.0 5MHz % TOTAL 30 25 20 15 10 0 1MHz –2.0 20MHz 10MHz –4.0 5 04976-004 –6.0 0 0.5 1.0 1.5 VGAIN (V) 2.0 2.5 3.0 0 19.9 20.0 20.1 20.2 20.3 20.4 GAIN SCALING FACTOR Figure 5. Gain Error vs. VGAIN at Various Frequencies (See Figure 49) Rev. 0 | Page 7 of 24 Figure 8. Gain Scaling Factor Histogram for 0.5 V < VGAIN < 2.5 V –1.0 –0.9 –0.8 –0.7 –0.6 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 CHANNEL-TO-CHANNEL GAIN MATCH (dB) 0 –1.0 –0.9 –0.8 –0.7 –0.6 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 Figure 7. Gain Match Histogram for VGAIN = 1 V and 2 V 420 CHANNELS (105 UNITS) 0.5V < VGAIN < 2.5V AD8335 25 420 CHANNELS (105 UNITS) 0.5V < VGAIN < 2.5V 20 30 25 20 15 GAIN (dB) RFB = ∞ % TOTAL 15 RS = 50Ω VIN = 10mV p-p RFB = 249Ω 10 5 0 10 5 –5 0 –16.7 –16.6 –16.5 –16.4 –16.3 –16.2 –16.1 –16.0 –15.9 –15.8 –15.7 –15.6 –15.5 04976-008 1M 10M FREQUENCY (Hz) 100M 1G INTERCEPT (dB) Figure 9. Intercept Histogram Figure 12. Frequency Response for a Terminated and Unterminated 50 Ω Source (See Figure 49) –10 VOUT = 1V p-p 50 VGAIN = 3.0V VGAIN = 2.5V CROSSTALK (dB) 40 –20 –30 –40 –50 VGAIN = 2V –60 –70 –80 –90 04976-009 30 GAIN (dB) VGAIN = 2.0V 20 VGAIN = 1.5V 10 VGAIN = 1.0V 0 VGAIN = 0.5V –10 VGAIN = 0V –20 100k 1M 10M FREQUENCY (Hz) 100M 1G VGAIN = 1V VGAIN = 3V VGAIN = 1V VGAIN = 3V VGAIN = 2V 04976-012 04976-013 –100 100k 1M 10M FREQUENCY (Hz) 100M Figure 10. Frequency Response for Various Values of VGAIN (See Figure 49) Figure 13. Channel-to-Channel Crosstalk vs. Frequency for Various Values of VGAIN 80 70 60 GROUP DELAY (ns) 50 VGAIN = 3.0V VGAIN = 2.5V VGAIN = 2.0V 40 30 GAIN (dB) VGAIN = 1.5V 20 VGAIN = 1.0V 10 VGAIN = 0.5V 0 VGAIN = 0V –10 50 40 30 20 10 0 100k 1M 10M FREQUENCY (Hz) 100M 1G 04976-010 –20 100k 1M 10M FREQUENCY (Hz) 100M Figure 11. Frequency Response vs. Frequency for Various Values of VGAIN, HILO = HI (See Figure 49) Figure 14. Group Delay vs. Frequency Rev. 0 | Page 8 of 24 04976-011 –10 100k AD8335 25 20 15 OFFSET VOLTAGE (mV) 10 5 0 –5 –10 –15 –20 04976-014 04976-017 04976-019 04976-018 1k +85°C, HI +85°C, LO INPUT IMPEDANCE (Ω) RFB = 2.5kΩ RFB = 1kΩ RFB = 499Ω 100 –40°C, LO –40°C, HI +25°C, HI +25°C, LO RFB = 249Ω RSH = ∞, CSH = 0pF RSH = 49Ω, CSH = 22pF –25 0 0.5 1.0 1.5 VGAIN (V) 2.0 2.5 3.0 10 1M 10M FREQUENCY (Hz) 1G Figure 15. Differential Output Offset Voltage vs. VGAIN at Three Temperatures Figure 18. Preamp Input Resistance vs. Frequency for Various Values of RFB –1VIN = 10mV p-p 0 –20 –30 25j 50j 100j 25 20 15 OFFSET VOLTAGE (mV) 10 5 0 –5 –10 –15 –20 04976-015 CROSSTALK (dB) –40 –50 –60 –70 –80 –90 100MHz START 100kHz 0Ω 17Ω 50Ω STOP 1GHz 150Ω –25 0 0.5 1.0 1.5 VGAIN (V) 2.0 2.5 3.0 –100 100k –25j 1M 10M –50j FREQUENCY (Hz) –75j 100M Figure 16. Absolute Offset vs. VGAIN at Pins VOHx and VOLx Relative to Pins VCMx 100 VIN = 10mV p-p OUTPUT REFERRED NOISE (nV/ Hz) 250 Figure 19. Smith Chart S11 vs. Frequency, 100 kHz to 1 GHz VOHx R S = 0Ω RFB = ∞ 200 OUTPUT IMPEDANCE (Ω) 10 VOLx 150 100 HILO = HI 1 50 HILO = LO 04976-016 0.1 100k 0 0 0.5 1.0 1.5 VGAIN (V) 2.0 2.5 3.0 1M 10M FREQUENCY (Hz) 1G Figure 17. Output Resistance at Pins VOHx and VOLx vs. Frequency Figure 20. Output Referred Noise vs. VGAIN (See Figure 50) Rev. 0 | Page 9 of 24 AD8335 1.4 60 55 INPUT REFERRED NOISE (nV/ Hz) 1.2 VGAIN = 3.0V R S = 0Ω RFB = ∞ 50 45 NOISE FIGURE (dB) f = 10MHz 1.0 40 35 30 25 20 15 10 5 0.8 0.6 0.4 0.2 04976-020 1 10 FREQUENCY (MHz) 100 0 0.5 1.0 1.5 VGAIN (V) 2.0 2.5 3.0 Figure 21. Short-Circuit Input Referred Noise vs. Frequency at Maximum Gain (See Figure 50) 1k T = +85°C 100 Figure 24. Noise Figure vs. VGAIN for RS = RIN = 50 Ω –35 f = 10MHz VOUT = 1V p-p VGAIN = 1.5V HILO = LO HD2 HD3 –40 –45 DISTORTION (dBc) NOISE (nV/ Hz) –50 10 T = +25°C –55 HILO = HI HD2 HD3 1.0 T = –40°C –60 –65 0.1 0 0.5 1.0 1.5 VGAIN (V) 2.0 2.5 3.0 04976-021 400 600 800 1.0k 1.2k 1.4k 1.6k 1.8k 2.0k RLOAD (Ω) Figure 22. Input Referred Noise vs. VGAIN at Three Temperatures (See Figure 50) 10 f = 1MHz, VGAIN = 3V Figure 25. Harmonic Distortion vs. RLOAD (See Figure 50) –20 f = 10MHz VOUT = 1V p-p –30 INPUT NOISE (nV/ Hz) DISTORTION (dBc) –40 HILO = LO HD3 HILO = HI, HD3 1.0 –50 RS THERMAL NOISE ALONE –60 HILO = HI, HD2 –70 HILO = LO, HD2 04976-022 0.1 1 10 100 1k SOURCE RESISTANCE (Ω) 0 10 20 30 40 50 CLOAD (pF) Figure 23. Input Referred Noise vs. RS Figure 26. Harmonic Distortion vs. CLOAD (See Figure 53) Rev. 0 | Page 10 of 24 04976-200 –80 04976-025 –70 200 04976-062 0 0.1 0 AD8335 –20 LO GAIN VOUT = 1V p-p –30 f = 10MHz –30 –20 HI GAIN VOUT = 1V p-p DISTORTION (dBc) –40 DISTORTION (dBc) –40 –50 f = 5MHz –60 f = 1MHz –70 –50 f = 10MHz –60 f = 5MHz –70 f = 1MHz 04976-026 1.0 1.5 VGAIN (V) 2.0 2.5 3.0 1.0 1.5 VGAIN (V) 2.0 2.5 3.0 Figure 27. HD2 vs. VGAIN at Three Frequencies, LO Gain (See Figure 53) –20 LO GAIN VOUT = 1V p-p –30 Figure 30. HD3 vs. VGAIN at Three Frequencies, HI Gain (See Figure 53) –35 –40 –45 f = 1MHz DISTORTION (dBc) DISTORTION (dBc) –40 f = 10MHz –50 –50 2V p-p –55 –60 –65 –70 –75 1V p-p 0.5V p-p –60 f = 5MHz –70 f = 1MHz 1.0 1.5 VGAIN (V) 2.0 2.5 3.0 04976-027 1.0 1.5 VGAIN (V) 2.0 2.5 3.0 Figure 28. HD3 vs. VGAIN at Three Frequencies, LO Gain (See Figure 53) –20 HI GAIN VOUT = 1V p-p –30 Figure 31. HD2 vs. VGAIN at Three Output Voltages, LO Gain (See Figure 53) –20 f = 1MHz –30 2V p-p –40 DISTORTION (dBc) –40 f = 10MHz –50 DISTORTION (dBc) –50 1V p-p –60 –60 f = 5MHz f = 1MHz –70 –70 0.5V p-p –80 04976-029 1.0 1.5 VGAIN (V) 2.0 2.5 3.0 1.0 1.5 VGAIN (V) 2.0 2.5 3.0 Figure 29. HD2 vs. VGAIN at Three Frequencies, HI Gain (See Figure 53) Figure 32. HD3 vs. VGAIN, at Three Output Voltages, LO Gain (See Figure 53) Rev. 0 | Page 11 of 24 04976-032 –80 0.5 –90 0.5 04976-031 –80 0.5 –80 0.5 04976-030 –80 0.5 –80 0.5 AD8335 –35 f = 1MHz 40 VOUT = 1Vp-p 35 5MHz (HI) 30 –40 –45 DISTORTION (dBc) 25 5MHz (LO) –50 2V p-p –55 1V p-p IP3 (dBm) 20 15 –60 10 –65 0.5V p-p 5 0 04976-034 0 0.5 1.0 1.5 VGAIN (V) 2.0 2.5 3.0 0 0.5 1.0 1.5 VGAIN (V) 2.0 2.5 3.0 Figure 33. HD2 vs. VGAIN at Three Output Voltages, HI Gain, f = 1 MHz (See Figure 53) –20 f = 1MHz –30 Figure 36. Output Referred IP3 (OIP3) vs. VGAIN 5 0 f = 10MHz INPUT POWER (dBm) HILO = LO –40 –5 HILO = HI –10 DISTORTION (dBc) –50 2V p-p –60 1V p-p –70 0.5V p-p –80 –90 0 0.5 1.0 1.5 VGAIN (V) 2.0 2.5 3.0 –15 –20 –25 04976-035 0 0.5 1.0 1.5 VGAIN (V) 2.0 2.5 3.0 Figure 34. HD3 vs. VGAIN at Three Output Voltages, HI Gain (See Figure 53) 0 –10 –20 –30 VOUT = 1V p-p VGAIN = 3V Figure 37. Input P1dB (IP1dB) vs. VGAIN 10mV HARMONIC DISTORTION (dBc) 100 90 IM3 (dBc) –40 –50 –60 –70 –80 04976-036 IMD3 (HI) IMD3 (LO) 10 0 50m V 10 ns –90 1 10 FREQUENCY (MHz) 100 Figure 35. IMD3 vs. Frequency Figure 38. Small Signal Pulse Response, LO Gain (See Figure 51) Rev. 0 | Page 12 of 24 04976-039 04976-038 –30 04976-037 –70 AD8335 2V 10mV HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) 100 90 100 90 10 0 10 0 50m V 10 ns 04976-039 100mV 100 µs Figure 39. Large Signal Pulse Response, LO Gain (See Figure 51) Figure 42. Small Signal Enable Response (See Figure 51) 2 VGAIN = 2V CL = 47pF CL = 22pF CL = 10pF HARMONIC DISTORTION (dBc) 100 90 2V INPUT 1 CL = 0pF VOUT (V) 0 –1 10 0 INPUT IS NOT TO SCALE 0 10 20 30 40 50 TIME (ns) 60 70 80 90 100 04976-041 –2 1V 100 µs Figure 40. Large Signal Pulse Response for Various Capacitive Loads, CL = 0 pF, 10 pF, 20 pF, 47 pF Each Output (See Figure 51) Figure 43. Large Signal Enable Response (See Figure 51) 2V HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) 100 90 100 90 1V 10 0 04976-042 10 0 500mV 400ns 1µs Figure 41. Gain Response, VGAIN Stepped from 0 V to3 V, VOUT = 2 V p-p (See Figure 51) Figure 44. Preamp Overdrive Recovery, 50 mV p-p to 1.5 V p-p at Preamp Input (Measured at Preamp Output) Rev. 0 | Page 13 of 24 04976-045 04976-044 04976-043 AD8335 95 QUIESCENT SUPPLY CURRENT (mA) 1V 90 VGAIN = 2.5V 85 HARMONIC DISTORTION (dBc) 100 90 80 75 70 10 0 65 1µs 04976-046 –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 45. VGA Overdrive Recovery, 40 mV to 500 mV Input, VGAIN = 2.5 V Figure 47. Quiescent Supply Current vs. Temperature 0 –10 HARMONIC DISTORTION (dBc) 2V VGAIN = 2.5V –20 –30 –40 –50 –60 VGAIN = 0.5V VGAIN = 1.5V 100 90 PSRR (dB) 10 0 VGAIN = 0V –70 500mV 1µs 1M 10M FREQUENCY (Hz) 100M 04976-100 –80 100k Figure 46. PSRR vs. Frequency (All Bypass Capacitors Removed) Figure 48 HILO Response Time Rev. 0 | Page 14 of 24 04976-101 04976-047 60 –40 AD8335 TEST CIRCUITS NETWORK ANALYZER 50Ω OUT 18nF 249Ω 0.1µF 237Ω 28Ω 49.9Ω 22pF 0.1µF 237Ω 04976-048 50Ω IN SPECTRUM ANALYZER 0.1µF AD8335 0.1µF 1:1 AD8335 0.1µF IN 1:1 50Ω 28Ω 22pF 0.1µF 0.1µF Figure 49. Test Circuit for Gain and Bandwidth Measurements Figure 50. Test Circuit Used for Noise Measurements NETWORK ANALYZER 50Ω 50Ω IN 50Ω 18nF 249Ω 0.1µF 49.9Ω 50Ω 22pF 0.1µF 237Ω 0.1µF OSCILLOSCOPE OUT 18nF 249Ω 0.1µF AD8335 0.1µF 237Ω 28Ω IN 1:1 50Ω 0.1µF 49.9Ω 04976-049 AD8335 237Ω 28Ω 50Ω 1:1 28Ω Figure 51. Test Circuit for Transient Measurements Figure 52. Test Circuit Used for S11 Measurements 18nF 249Ω SIGNAL GENERATOR LPF 50Ω 0.1µF 50Ω 22pF 0.1µF 237Ω 0.1µF SPECTRUM ANALYZER AD8335 0.1µF 237Ω 28Ω IN 1:1 50Ω Figure 53. Test Circuit Used for Distortion Measurements Rev. 0 | Page 15 of 24 04976-051 28Ω 04976-052 28Ω 22pF 0.1µF 237Ω 0.1µF 04976-050 0.1µF 49Ω AD8335 THEORY OF OPERATION Figure 54 is a simplified block diagram of a single channel. Each channel consists of a low noise preamplifier (PrA) followed by a VGA with a user-selectable gain of 20 dB or 28 dB. Channels are enabled in pairs, Channels 1 and 2 and Channels 3 and 4. The preamps are enabled by grounding Pins SPxx and powered down by connecting them to the positive supply. The ENxx pins are connected to the positive supply to enable the VGAs and the overall channel. HILO configures VGA for a fixed gain of 20 dB or 28 dB, with 0 V or 5 V applied to the HLxx pins, respectively. Channels 1 and 2 share Pin HL12, and Channels 3 and 4 share Pin HL34. The HLxx pins are typically hardwired to adjust the VGA gain according to an ADC resolution of 12 bits for LO gain and 10 bits for HI gain. The signal path is fully differential throughout to maximize signal swing and reduce even-order distortion; however, the preamplifiers are designed to be driven from a single-ended signal source. Gain values are referenced from the single-ended PrA input to the differential output of either the PrA or the VGA. Again referring to Figure 54, the system gain is distributed as listed in Table 4. Table 4. Channel Gain Distribution Section PrA Attenuator Output Amp Aggregate LO Nominal Gain (dB) 18.06 0 to −48.16 20 −10.1 to +38.6 HI Nominal Gain (dB) 18.06 0 to −48.16 27.96 −2.14 to +46.02 In the remainder of this document, the gain values are rounded to −10 dB to +38 dB for LO gain mode and to −2 dB to +46 dB for HI gain mode. If desired, Equation 1 can be used to calculate the gain at value of VGAIN: Gain (dB ) = 20 dB VGN + ICPT V (1) where ICPT = −16.1 dB for LO gain mode with the preamp input matched to 50 Ω (RFB = 250 Ω) and −10.1 dB for the unmatched input case. For HI gain mode, these numbers are −8.1 dB and −2.1 dB, respectively. Power consumption is 95 mW/channel from a 5 V supply, or 380 mW for all four channels. Power is distributed 35% for the PrA, and 65% for the remainder of the circuit. The preamps can be shut down via the SP12 and SP34 pins if a user wants to use the VGAs only. However, to avoid feedthrough around the preamp, feedback resistors should not be installed. ENABLE SUMMARY Table 5 summarizes the enable/shutdown logic and resulting supply current. Table 5. Control Pin Logic and Power Consumption EN12 H H L L SP12 L H L H EN34 H H L L SP34 L H L H PrA12 On Off Off Off VGA12 On On Off Off PrA34 On Off Off Off VGA34 On On Off Off IS 76 mA 52 mA 0.8 mA 0.8 mA VINx PONx INTERPOLATOR RFB PIPx PMDx PrA 18dB ATTENx –48dB TO 0dB OUTPUT AMP 20dB TO 28dB +1 VOHx +1 RS +1 VOLx BIAS +1 +1 GAIN INTERFACE HILO POPx 04976-054 ENxx VIPx VCMx VGNx SLxx HLxx Figure 54. Simplified Block Diagram of Single Channel Rev. 0 | Page 16 of 24 AD8335 PREAMP Although the preamp signal path is fully differential, the design is optimized for single-ended input drive and signal source resistance matching. Thus, the negative input to the differential preamplifier Pins PMDx must be ac-grounded to provide a balanced differential signal at the PrA outputs. Detailed information regarding the preamplifier architecture is found in the LNA section of the AD8331/AD8332 data sheet. The preamplifier consists of a fixed gain amplifier with differential outputs. With the negative output available and a fixed gain of 8 (18.06 dB), an active input termination is synthesized by connecting a feedback resistor between the negative output and the positive input, Pin PIPx. This technique is well known and results in the input resistance shown in Equation 2. the lower frequency limit is determined by the size of the accoupling capacitors, and the upper limit is determined by the preamplifier BW. Furthermore, the input capacitance and RS limits the BW at higher frequencies. 1k RIN = 500Ω, RFB = 2.5kΩ RSH = ∞, CSH = 0pF INPUT IMPEDANCE (Ω) RIN = 200Ω, RFB = 1kΩ RSH = 50Ω, CSH = 22pF 100 RIN = 100Ω, RFB = 499Ω RIN = 50Ω, RFB = 249Ω RSH = ∞, CSH = 0pF RSH = 50Ω, CSH = 22pF 1M FREQUENCY (Hz) 10M 50M where A/2 is the single-ended gain, or the gain from the PIPx inputs to the PONx outputs. Since the amplifier has a gain of ×8 from its input to its differential output, it is important to note that the gain A/2 is the gain from Pin PIPx to Pin PONx, which is 6 dB lower, or 12.04 dB (×4). The input resistance is reduced by an internal bias resistor of 14.7 kΩ in parallel with the source resistance connected to Pin PIPx, with Pin PMDx ac-grounded. Equation 3 can be used to calculate the needed RFB for a desired RIN, and is used for higher values of RIN. R IN R = FB || 14.7 kΩ (1 + 4) Figure 55. RIN vs. Frequency for Various Values of RFB. Effects of RSH and CSH are also shown. Figure 55 shows RIN vs. frequency for various values of RFB. Note that at the lowest value, 50 Ω, RIN peaks at frequencies greater than 10 MHz. This is due to the BW roll-off of the PrA as mentioned earlier. The RSH and CSH network shown in Figure 58 reduces this peaking. However, as can be seen for larger RIN values, parasitic capacitance starts rolling off the signal BW before the PrA can produce peaking and the RSH/CSH network further degrades the match. Therefore RSH and CSH should not be used for values of RIN greater than 50 Ω. (3) For example, to set RIN = 200 Ω, the value of RFB is 1.013 kΩ. If the simplified Equation 2 is used to calculate RIN, the value is 197 Ω, resulting in a less than 0.1 dB gain error. Factors such as a widely var ying source resistance might influence the absolute gain accuracy more significantly. At higher frequencies, the input capacitance of the PrA needs to be considered. The user must determine the level of matching accuracy and adjust RFB accordingly. The bandwidths (BW) of the preamplifier and VGA are approximately 110 MHz each, resulting in a cascaded BW of approximately 80 MHz. Ultimately the BW of the PrA limits the accuracy of the synthesized RIN. For RIN = RS up to approximately 200 Ω, the best match is between 100 kHz and 10 MHz, where Noise The total input referred noise (IRN) is approximately 1.3 nV/√Hz. Allowing for a gain of ×8 in the preamp, the VGA noise is 0.46 nV/√Hz referred to the PrA input. The preamp noise is 1.2 nV/√Hz. It is important to note that these noise values include all amplifier noise sources, including the VGA and the preamplifier gain resistors. Frequently, manufacturer noise specifications exclude gain setting resistors, and the voltage noise spectral density of an op amp might be presented as 1 nV/√Hz. Including the gain resistors results in a much higher noise specification. Rev. 0 | Page 17 of 24 04976-102 R IN = R FB (1 + A 2) (2) 10 100k AD8335 Figure 56 shows the simulated noise figure (NF) vs. source resistance, and various values of preamplifier RIN from 50 Ω, to 14.7 kΩ, the value seen looking into Pins PIPx when RFB = ∞. As shown in the figure, the minimum NF for RIN = 50 Ω is slightly less than 7 dB. Note that, for this preamplifier, the NF is optimized for the RIN from 50 Ω to 200 Ω; for RFB = ∞, the minimum NF is at approximately 480 Ω. This optimum noise resistance can also be calculated by dividing the input referred voltage noise by the current noise. 16 14 12 10 8 6 4 2 SIMULATION 0 10 100 RS (Ω) 1k RIN = 14.7kΩ RFB = ∞ INCLUDES NOISE OF VGA f = 1MHz RIN = 50Ω RFB = 250Ω RIN = 75Ω RFB = 375Ω RIN = 100Ω RFB = 500Ω Optimizing the System Dynamic Range The VGA output gain switch of 8 dB (×2.5) optimizes the VGA noise floor for a 10-bit or 12-bit ADC, assuming a full-scale ADC input voltage of 1 V p-p. At low gain the ADC SNR should limit the system noise performance, while at high gains the noise is defined by the source and preamplifier. The maximum voltage swing is bounded by the full-scale peak-to-peak ADC input voltage (typically 1 V p-p to 2 V p-p). The noise performance is optimized by adjusting the noise floor of the VGA according to the ADC resolution. The SNR of a 12-bit converter is theoretically 12 dB better than a 10-bit; however, approximately 8 dB is typical in practice, accounting for the 8 dB gain option of the AD8335. The IRN and the power consumption of the VGA are unaffected by either gain setting; therefore, only the output referred noise (ORN) changes (by 8 dB) without affecting any other parameters. NOISE FIGURE (dB) Attenuator RIN = 200Ω RFB = 1kΩ Figure 56. Simulated Noise Figure vs. RS for Various Fixed Values of RIN, Actively Matched VGA As seen in Figure 54, the basic architecture, an X-AMPTM, consists of a ladder attenuator, followed by a fixed-gain amplifier with selectable input stages. Earlier examples of this architecture are to be found in the AD60x series, AD8331/ AD8332, and AD8367 VGAs. Through a proprietar y, temperature-compensated interpolator design, the bias currents to the input gm stages are continuously steered from right to left (decreasing attenuation) resulting in increasing gain. The HILO (HL12 and HL34) gain pins select one of two output amplifier networks consisting of the feedback resistors, amplifier stages, and buffers. The attenuator is an 8-stage differential R-2R ladder with a total attenuation of 48.16 dB – 6.02 dB per tap. The effective input resistance per side is 320 Ω nominally for a total differential resistance of 640 Ω. The common-mode voltage of the attenuator and the VGA is controlled by an amplifier that uses the same midsupply voltage derived in the preamplifier, permitting dc coupling of the PrA to the VGA without introducing large offsets due to common-mode differences. However, when dc coupling between the PrA and VGA, any offset from the PrA are amplified as the gain is increased, producing an exponentially increasing VGA output offset. When the PrA and the VGA are ac-coupled, the output offset is unchanged with changes in gain (see Figure 15). As a result, ac coupling is recommended for most applications. As can be seen from Figure 54, Pins VCMx connect to the respective midpoints on each channel and are used to ac decouple the common-mode node at high frequencies. It is ver y important that at least a 0.1 µF capacitor be used, with better decoupling at higher frequencies when another smaller capacitor (10 nF) is connected in parallel. The internal +1 buffer provides correct common-mode bias levels and any dynamic currents have to be absorbed by the external decoupling capacitors. Rev. 0 | Page 18 of 24 04976-066 AD8335 Gain Control The gain control interface has two inputs, VGAIN (Pins VGNx) and VSLP (Pins SLxx). The slope input is intended only as a decoupling pin, and the only guaranteed gain slope is the 20 dB/V default. However, if a voltage is applied to the VSLP inputs, the gain slope can be increased by reducing the slope voltage. For example, if a voltage of 1.67 V is applied to Pins SLxx, the gain slope changes to 30 dB/V. Use Equation 4 to calculate the gain slope. VSLP = 2.5 V× 20 dB/V Slope dynamic range, and the common-mode level is maintained automatically at half the supply voltage for maximum signal swing. The differential signal has the added benefit of suppressing the even order harmonics. The output amplifier is designed to drive a nominal differential load of 500 Ω or greater; the signal swing can be as large as 5 V p-p differential before clipping occurs. However, that distortion increases before reaching the clipping level. Distortion is shown in Figure 25 through Figure 34 for typical values of 1 V p-p or 2 V p-p (full-scale inputs for many ADCs). The output is ac-coupled to a differential anti-alias filter driving a differential ADC. Most modern ADCs have differential inputs and achieve optimum performance when driven differentially. For more information, see the Applications section. (4) VGAIN varies the gain of the VGA through the interpolator by selecting the appropriate input stages connected to the input attenuator. The nominal VGAIN range for 20 dB/V is 0 V to 3 V, with the best gain-linearity from approximately 0.5 V to 2.5 V, where the error is typically less than ±0.2 dB. For VGAIN voltages above 2.5 V and less than 0.5 V, the error increases (see Figure 4). The value of the VGAIN voltage can be increased to that of the supply voltage, without gain foldover. Each channel has separate gain control pins that can be connected to a common voltage-source such as found in most ultrasound applications. For control of individual channels, connect the appropriate gain control signal to each channel. VGA Noise As with all X-AMPs, the output noise of the VGA is constant with gain. This causes the input referred noise to increase as the gain is decreased. This characteristic is desirable in receiver applications where wide dynamic range input signals are compressed with a fixed ceiling and noise floor into an ADC. The VGA output noise is approximately 33 nV/√Hz in LO gain mode and 2.5 times higher than this, 83 nV/√Hz, in HI gain mode. As the gain increases, the noise of the preamplifier prevails and, at the maximum VGA gain, the output noise is approximately 90 nV/√Hz and 225 nV/√Hz for LO and HI gain modes, respectively. The output SNR is determined by the noise floor and the largest signal level, typically limited by the FS of the ADC. Modulation noise, essentially the noise introduced by the gain control input, can be troublesome. Normally one tends to look at the main amplifier signal path for noise, but a VGA is really a multiplier with the following function VOUT = VGAIN × VIN VREF Output Stage Duplicate output stages of the VGA provide an 8 dB (×2.5) gain switch. The gain switch is intended to optimize the output noise floor for either a 10-bit or 12-bit ADC. The VGA gain is 20 dB (×10) in LO gain mode and 28 dB (×25) in HI gain mode. The logic setting of the HILO (Pins HLxx) selects between output amplifiers including the gain resistors and feedback buffers. 100 MHz bandwidth is maintained between the amplifiers by changing the compensation capacitance as the gain switches gain settings. Power consumption is the same for either level of gain. In certain applications, power consumption can be reduced by lowering the supply voltage as much as possible; however, the output dynamic range is affected by the more limited swing. The fully differential signal path of the AD8335 restores 6 dB of (4) where VREF (bias) and VGAIN (gain control interface) are both noise contributors under certain conditions. It is therefore important that the gain control signals be kept clean, especially at higher gain control slopes. Rev. 0 | Page 19 of 24 AD8335 APPLICATIONS ULTRASOUND The primar y application for the AD8335 is medical ultrasound. Figure 57 shows a simplified block diagram of an ultrasound system. The most critical function of an ultrasound system is the time gain control (TGC) compensation for physiological signal attenuation. Because the attenuation of ultrasound signals is exponential with respect to distance (time), a linear-in-dB VGA is the optimal solution. Key requirements in an ultrasound signal chain are ver y low noise, active input termination, fast overload recover y, low power, and differential drive to an ADC. Because ultrasound machines use beamforming techniques requiring large binar y weighted numbers (for example, 32 to 512) of channels, the lowest power at the lowest possible noise is of key importance. Most modern machines use digital beamforming. In this technique, the signal is converted to digital format immediately following the TGC amplifier; beamforming is done digitally. Typical ADC resolution in general purpose machines is 10 bits with sampling rates greater than 40 MSPS, while high end systems use 12 bits. Power consumption and low cost are of primar y importance in low-end and portable ultrasound machines, and the AD8335 is designed for these criteria. For additional information regarding ultrasound systems, refer to “How Ultrasound System Considerations Influence FrontEnd Component Choice”, Analog Dialogue, Vol. 36, No. 3, May–July 2003. (http://www.analog.com/librar y/analogDialogue/archives/3603/ultrasound/index.html) TX HV AMPs TX BEAMFORMER BEAMFORMER CENTRAL CONTROL MULTICHANNEL TGC USES MANY VGAs HV MUX/ DEMUX AD8335 T/R SWITCHES LNAs VGAs Rx BEAMFORMER (B AND F MODES) TRANSDUCER ARRAY 128, 256 ETC. ELEMENTS BIDIRECTIONAL CABLE TGC TIME GAIN COMPENSATION CW (ANALOG) BEAMFORMER SPECTRAL DOPPLER PROCESSING MODE IMAGE AND MOTION PROCESSING (B MODE) COLOR DOPPLER (PW) PROCESSING (F MODE) Figure 57. Simplified Ultrasound System Block Diagram Rev. 0 | Page 20 of 24 04976-053 AUDIO OUTPUT DISPLAY AD8335 BASIC CONNECTIONS Figure 58 shows the basic connections for the AD8335. Input signals enter from the left and output signals exit from the right, providing straight-line signal paths. Of course, a device with four differential VGAs such as this requires a multilayer printed circuit board. Power supply isolation is shown for the preamps, and for the VGA sections. If components are mounted to both sides of the board, those in the signal path should be located on the top, with power-supply decoupling components on the wiring side. Table 6. Feedback Resistor Values for Various Input Resistances RIN (Ω) Exact RFB Value (Ω) Nearest Standard 1% Value (Ω) 200 500 1000 1014 2588 5365 5 × R IN R 1 − IN 14.7 k 1.02k 2.61k 5.36k R FB (Ω) = (5) PREAMP CONNECTIONS To configure the AD8335 for input matching a feedback resistor (RFB) is ac-coupled between Pin PONx and Pin PIPx. AC coupling accommodates dissimilar common-mode voltages at the input and output ports. For values of RSOURCE between 50 Ω and 200 Ω, RFB is simply 5 × RSOURCE. Table 6 lists a few larger values of source resistor (or RIN), along with the exact value and nearest standard 1% feedback resistor. For values other those than listed in Table 6, RFB can be calculated using Equation 5. For values larger than 1 kΩ, it may be advantageous to simply remove RFB. Rev. 0 | Page 21 of 24 AD8335 +5V 0.1µF PIP1 RSH1 49.9 Ω CSH1 22pF 0.1µF PIP2 RSH2 49.9 Ω CSH2 22pF 0.1µF RFB2 249 Ω VPP 0.1µF 1 0.1 µF RFB1 0.1µF 249 Ω 0.1µF 0.1µF VPP +5V VGN1 VGN2 SL12 0.1µF L 0.1µF H 1nF* 0.1µF 1nF* 0.1µF 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VOH1 0.1µF VPP1 PON1 POP1 VIN1 VIP1 COM1 VGN1 PIP1 VCM1 PMD1 VCM2 EN12 SP12 SL12 VGN2 HL12 PMD2 PIP2 VPP2 PON2 POP2 VIP2 VIN2 COM2 COM3 VIN3 VIP3 POP3 PON3 VPP3 PIP3 GND1 VOH1 VOL1 VPV1 VPV2 VOL2 VOH2 48 47 46 45 VPV 44 43 42 41 40 39 38 37 36 35 34 33 0.1µF 0.1µF +5V H 0.1µF 0.1µF VPV 0.1µF 0.1µF +5V VOL1 2 3 4 120nH FB 0.1µF 0.1µF 0.1µF 120nH FB +5V 0.1 µF VPP 5 6 7 8 9 10 VOL2 VOH2 AD8335 GND2 GND3 VOH3 VOL3 VPV3 VPV4 VOL4 VOH4 VOH3 VOL3 0.1µF 0.1µF 11 12 13 0.1µF PIP3 RFB3 249 Ω RSH3 49.9 Ω CSH3 22pF VPP 14 0.1µF VOL4 VOH4 15 16 COM4 PMD4 VCM4 PON4 POP4 VPP4 VGN3 VCM3 VGN4 PMD3 GND4 SP34 PIP4 17 0.1µF 0.1µF PIP4 RSH4 49.9 Ω *SEE TEXT 18 19 VPP 0.1µF 20 21 22 0.1µF 0.1µF 23 24 25 26 27 0.1µF 28 29 0.1µF 30 31 SL34 32 0.1µF L 1nF* VGN4 VGN3 1nF* +5V 04976-056 CSH4 22pF RFB4 249 Ω SL34 Figure 58. Basic Connections for RIN = 50 Ω The preamp PMD pins must be capacitively coupled to ground. Although the preamplifier is a differential design, the PMD pins are the internal input bias nodes and are made available for bypassing only. These pins may not be used as signal inputs. The PIPx inputs must be capacitively coupled from the signal source because they have a nominal dc level of more than half the supply voltage. AC coupling capacitors throughout the circuit should be as large as possible for the application. Although 0.1 µF capacitors are shown in Figure 58 (and used in most positions in the evaluation board), values of these capacitors should be determined by the application. Capacitors used for coupling PMDx and PIPx pins should be the same value. When synthesizing low values of RIN, the bandwidth of the preamplifier produces some peaking at the high end of the frequency response. The optional series RSHx/CSHx network shown in Figure 58 flattens the response (see Figure 55). With a 50 Ω source, the resistor and capacitor values should be 49.9 Ω and 22 pF. For RS values greater than 100 Ω, the network is not needed. The circuit is stable in either scenario. The starred capacitors in Figure 58 (*) on the VGNx pins may be removed when faster gain control signals are required. Rev. 0 | Page 22 of 24 HL34 VIP4 VIN4 0.1µF EN34 AD8335 INPUT OVERDRIVE Excellent overload behavior is of primar y importance in ultrasound. Both the preamplifier and VGA have built-in overdrive protection and quickly recover after an overload event. LOGIC INPUTS The enable Pins EN12 and EN34, the preamp shutdown Pins SP12 and SP34, and the HILO Pins HL12 and HL34 are all logic inputs of the AD8335. The enable inputs turn on and off each of the corresponding pairs of channels; the preamp shutdown pins do the same for the preamplifiers only ; inputs HL12 and HL34 set the HILO gain for Channels 1 and 2, and Channels 3 and 4, respectively. Shutting down the preamplifiers allows use of the VGAs alone, while reducing power consumption. The VGAs cannot be shut down independently. The SPxx (shutdown preamp) pins are logic high; thus the pins are grounded to enable the preamplifiers. The pins can be enabled by connecting to the supply or to ground for fixed enable or disable, or to the output of a logic device. Be sure to check the data sheet of the device for voltage and current requirements. Input Overload Protection As with any amplifier, voltage clamping prior to the inputs is highly recommended if the application is subject to high transient voltages. A block diagram of a simplified ultrasound transducer interface is shown in Figure 59. A common transducer element ser ves the dual functions of transmit and receive of ultrasound energy. During the transmit phase, high voltage pulses are applied to the ceramic elements. A typical T/R (transmit/receive) switch may consist of four high voltage diodes in a bridge configuration. Although they ideally block transmit pulses from the sensitive receiver input, diode characteristics are not ideal, and resulting leakage transients impinging on the PIPx inputs can be problematic. Since ultrasound is a pulse system, and time-of-flight is used to determine depth, quick recovery from input overloads is essential. Overload can occur in the preamp and the VGA. Immediately following a transmit pulse, the typical VGA gains are low, and the PrA is subject to overload from T/R switch leakage. With increasing gain, the VGA can become overloaded from strong echoes that occur with near field echoes and acoustically dense materials, such as bone. Figure 59 illustrates an external overload protection scheme. A pair of back-to-back Schottky diodes is installed prior to installing the ac-coupling capacitors. Although the BAS40 is shown, many types are available and merit investigation by the user. With such diodes, clamping levels of ±0.5 V or less greatly enhance the system overload performance. +HV OPTIONAL SCHOTTKY OVERLOAD CLAMP PIPx PMDx 2 TRANSDUCER –HV BAS40-04 1 04976-057 COMMON-MODE PINS The common-mode Pins VCMx are provided for bypassing the internal common-mode reference for each channel to ground. They require a capacitor at each of the four pins and can neither be connected together nor driven by an external source. DRIVING ADCs The AD8335 VGA is designed to drive 10-bit and 12-bit ADCs with minimal extra components. Because the AD8335 is a single supply 5 V part and many of the newest ADCs operate from a 3 V supply, dissimilar common-mode voltages exist between the VGA output and the ADC input. This level shift is most easily accommodated by ac coupling, especially if the signal is filtered, as is the case in most ultrasound and communications applications. When an anti-aliasing filter (AAF) is called for, it is advantageous to implement a differential configuration. A fully differential AAF requires approximately 1.5 times the number of components than a single-ended filter, because the components that in the single-ended case are tied to ground, now connect across the differential signal path. Although the series components double, the component count for the differential filter is more economical when compared to simply building a pair of single-ended filters requiring twice as many components. RFB PONx Rs 3 PrA 18dB POPx Figure 59. Input Overload Protection Rev. 0 | Page 23 of 24 AD8335 OUTLINE DIMENSIONS 9.00 BSC SQ 0.60 MAX 0.60 MAX 49 48 0.30 0.25 0.18 64 1 PIN 1 INDICATOR PIN 1 INDICATOR TOP VIEW 8.75 BSC SQ EXPOSED PAD (BOT T O M VIEW) 4.85 4.70 SQ* 4.55 0.45 0.40 0.35 33 32 16 17 1.00 0.85 0.80 12° MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC 7.50 REF SEATING PLANE 0.20 REF *COMPLIANT TO JEDEC STANDARDS MO-220-VMMD EXCEPT FOR EXPOSED PAD DIMENSION Figure 60. 64-Lead Lead Frame Chip Scale Package [LFCSP] (CP-64) Dimensions shown in millimeters ORDERING GUIDE Model AD8335ACPZ1 AD8335ACPZ-REEL1 AD8335ACPZ-REEL71 AD8335-EVAL Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description Lead Frame Chip Scale Package (LFCSP) Lead Frame Chip Scale Package (LFCSP) Lead Frame Chip Scale Package (LFCSP) Evaluation Board with AD8335ACP Package Option CP-64 CP-64 CP-64 1 Z = Pb-free part. © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04976–0–9/04(0) Rev. 0 | Page 24 of 24