1.5 GHz to 2.4 GHz
RF Vector Modulator
AD8341
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VPRF
QBBP QBBM
VPS2
90
RFOP
RFIP
RFIM
RFOM
0
CMOP
IBBP IBBM
DSOP
04700-001
Cartesian amplitude and phase modulation
1.5 GHz to 2.4 GHz frequency range
Continuous magnitude control of −4.5 dB to −34.5 dB
Continuous phase control of 0° to 360°
Output third-order intercept 17.5 dBm
Output 1 dB compression point 8.5 dBm
Output noise floor −150.5 dBm/Hz at full gain
Adjustable modulation bandwidth up to 230 MHz
Fast output power disable
4.75 V to 5.25 V single-supply voltage
Figure 1.
APPLICATIONS
RF PA linearization/RF predistortion
Amplitude and phase modulation
Variable attenuators and phase shifters
CDMA2000, WCDMA, GSM/EDGE linear power amplifiers
Smart antennas
GENERAL DESCRIPTION
The AD8341 vector modulator performs arbitrary amplitude
and phase modulation of an RF signal. Because the RF signal
path is linear, the original modulation is preserved. This part can
be used as a general-purpose RF modulator, a variable attenuator/
phase shifter, or a remodulator. The amplitude can be controlled
from a maximum of −4.5 dB to less than −34.5 dB, and the phase
can be shifted continuously over the entire 360° range. For maximum gain, the AD8341 delivers an OP1dB of 8.5 dBm, an OIP3
of 17.5 dBm, and an output noise floor of −150.5 dBm/Hz,
independent of phase. It operates over a frequency range of
1.5 GHz to 2.4 GHz.
The baseband inputs in Cartesian I and Q format control the
amplitude and phase modulation imposed on the RF input
signal. Both I and Q inputs are dc-coupled with a ±500 mV
differential full-scale range. The maximum modulation
Rev. B
bandwidth is 230 MHz, which can be reduced by adding external
capacitors to limit the noise bandwidth on the control lines.
Both the RF inputs and outputs can be used differentially or
single-ended and must be ac-coupled. The RF input and output
impedances are nominally 50 Ω over the operating frequency
range. The DSOP pin allows the output stage to be disabled
quickly in order to protect subsequent stages from overdrive.
The AD8341 operates off supply voltages from 4.75 V to 5.25 V
while consuming approximately 125 mA.
The AD8341 is fabricated on Analog Devices’ proprietary, high
performance 25 GHz SOI complementary bipolar IC process. It
is available in a 24-lead, lead-free LFCSP package and operates
over a −40°C to +85°C temperature range. Evaluation boards
are available.
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Tel: 781.329.4700 ©2004–2017 Analog Devices, Inc. All rights reserved.
Technical Support
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AD8341
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Noise and Distortion.................................................................. 11
Applications ....................................................................................... 1
Gain and Phase Accuracy.......................................................... 11
Functional Block Diagram .............................................................. 1
RF Frequency Range .................................................................. 11
General Description ......................................................................... 1
Applications Information .............................................................. 12
Revision History ............................................................................... 2
Using the AD8341 ...................................................................... 12
Specifications..................................................................................... 3
RF Input and Matching ............................................................. 12
Absolute Maximum Ratings ............................................................ 4
RF Output and Matching .......................................................... 13
ESD Caution .................................................................................. 4
Driving the I-Q Baseband Controls ......................................... 13
Pin Configuration and Function Descriptions ............................. 5
Interfacing to High Speed DACs .............................................. 14
Typical Performance Characteristics ............................................. 6
CDMA2000 Application............................................................ 14
Theory of Operation ...................................................................... 10
WCDMA Application ................................................................ 15
RF Quadrature Generator ......................................................... 10
Evaluation Board ............................................................................ 17
I-Q Attenuators and Baseband Amplifiers.............................. 11
Outline Dimensions ....................................................................... 20
Output Amplifier ........................................................................ 11
Ordering Guide .......................................................................... 20
REVISION HISTORY
9/2017—Rev. A to Rev. B
Change to Figure 2 ........................................................................... 5
Changed Applications Section to Applications Information
Section .............................................................................................. 12
Updated Outline Dimensions ...................................................... 20
Changes to Ordering Guide ......................................................... 20
11/2012—Rev. 0 to Rev. A
Changes to Figure 2 and Table 3 ..................................................... 5
Replaced Figure 42 and Figure 43 ................................................ 19
Updated Outline Dimensions ....................................................... 20
Changes to Ordering Guide .......................................................... 20
7/2004—Revision 0: Initial Version
Rev. B | Page 2 of 20
Data Sheet
AD8341
SPECIFICATIONS
VS = 5 V, TA = 25°C, ZO = 50 Ω, f = 1.9 GHz, single-ended, ac-coupled source drive to RFIP through 1.2 nH series inductor, RFIM
ac-coupled through 1.2 nH series inductor to common, differential-to-single-ended conversion at output using 1:1 balun.
Table 1.
Parameter
OVERALL FUNCTION
Frequency Range
Maximum Gain
Minimum Gain
Gain Control Range
Phase Control Range
Gain Flatness
Group Delay Flatness
RF INPUT STAGE
Input Return Loss
CARTESIAN CONTROL INTERFACE (I AND Q)
Gain Scaling
Modulation Bandwidth
Second Harmonic Distortion
Third Harmonic Distortion
Step Response
Recommended Common-Mode Level
RF OUTPUT STAGE
Output Return Loss
f = 1.9 GHz
Gain
Output Noise Floor
Output IP3
Adjacent Channel Power
Output 1 dB Compression Point
POWER SUPPLY
Positive Supply Voltage
Total Supply Current
OUTPUT DISABLE
Disable Threshold
Attenuation
Enable Response Time
Disable Response Time
Conditions
Min
Typ
Max
Unit
2.4
−4.5
−34.5
GHz
dB
dB
30
360
0.5
50
dB
Degrees
dB
ps
12
dB
2
230
41
47
45
1/V
MHz
dBc
dBc
ns
45
ns
0.5
V
7.5
dB
−4.5
−150.5
−149
17.5
−76
dB
dBm/Hz
dBm/Hz
dBm
dBm
8.5
dBm
1.5
Maximum gain setpoint for all phase setpoints
VBBI = VBBQ = 0 V differential
(at recommended common-mode level)
Relative to maximum gain
Over 30 dB control range
Over any 60 MHz bandwidth
Over any 60 MHz bandwidth
RFIM, RFIP (Pins 21 and 22)
From RFIP to CMRF (with 1.2 nH series inductors)
IBBP, IBBM, QBBP, QBBM (Pins 16, 15, 3, 4)
500 mV p-p, sinusoidal baseband input single-ended
500 mV p-p, 1 MHz, sinusoidal baseband input differential
500 mV p-p, 1 MHz, sinusoidal baseband input differential
For gain setpoint from 0.1 to 0.9
(VBBP = 0.5 V, VBBM = 0.55 V to 0.95 V)
For gain setpoint from 0.9 to 0.1
(VBBP = 0.5 V, VBBM = 0.95 V to 0.55 V)
RFOP, RFOM (Pins 9, 10)
Measured through balun
Maximum gain setpoint
Maximum gain setpoint, no input
PIN = 0 dBm, frequency offset = 20 MHz
f1 = 1900 MHz, f2 = 1897.5 MHz, maximum gain setpoint
CDMA2000, single carrier, POUT = -4 dBm,
maximum gain, phase setpoint = 45° (See Figure 35)
Maximum gain
VPS2 (Pins 5, 6, and 14), VPRF (Pins 19 and 24),
RFOP, RFOM (Pins 9 and 10)
Includes load current
DSOP (Pin 13)
(See Figure 24)
DSOP = 5 V
Delay following high-to-low transition until
RF output amplitude is within 10% of final value.
Delay following low-to-high transition until
device produces full attenuation
Rev. B | Page 3 of 20
4.75
105
5
125
5.25
145
V
mA
Vs/2
33
30
V
dB
ns
15
ns
AD8341
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameters
Supply Voltage VPRF, VPS2
DSOP
IBBP, IBBM, QBBP, QBBM
RFOP, RFOM
RF Input Power at Maximum Gain
(RFIP or RFIM, Single-Ended Drive)
Equivalent Voltage
Internal Power Dissipation
θJA (With Pad Soldered to Board)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature Range (Soldering 60 sec)
Rating
5.5 V
5.5 V
2.5 V
5.5 V
13 dBm, referenced
to 50 Ω
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
2.8 V p-p
825 mW
59 °C/W
125°C
−40°C to +85°C
−65°C to +150°C
300°C
Rev. B | Page 4 of 20
Data Sheet
AD8341
20 CMRF
19 VPRF
22 RFIP
21 RFIM
24 VPRF
23 CMRF
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
QFLP 1
18 IFLP
QFLM 2
17 IFLM
QBBP 3
AD8341
16 IBBP
QBBM 4
TOP VIEW
(Not to Scale)
15 IBBM
VPS2 5
14 VPS2
VPS2 6
04700-002
CMOP 12
CMOP 11
RFOP 9
RFOM 10
CMOP 8
CMOP 7
13 DSOP
NOTES
1. THE EXPOSED PADDLE SHOULD BE SOLDERED TO
A LOW IMPEDANCE GROUND PLANE.
Figure 2. 24-Lead Lead Frame Chip Scale Package (LFCSP)
Table 3. Pin Function Descriptions
Pin No.
1, 2
Mnemonic
QFLP, QFLM
3, 4
5, 6, 14, 19, 24
7, 8, 11, 12, 20, 23
9, 10
13
15, 16
17, 18
QBBP, QBBM
VPS2, VPRF
CMOP, CMRF
RFOP, RFOM
DSOP
IBBM, IBBP
IFLM, IFLP
21, 22
RFIM, RFIP
EP
Function
Q Baseband Input Filter Pins. Connect optional capacitor to reduce Q baseband channel low-pass
corner frequency.
Q Channel Differential Baseband Inputs.
Positive Supply Voltage. 4.75 V − 5.25 V.
Device Common. Connect via lowest possible impedance to external circuit common.
Differential RF Outputs. Must be ac-coupled. Differential impedance 50 Ω nominal.
Output Disable. Pull high to disable output stage.
I Channel Differential Baseband Inputs.
I Baseband Input Filter Pins. Connect optional capacitor to reduce I baseband channel low-pass
corner frequency.
Differential RF Inputs. Must be ac-coupled. Differential impedance 50 Ω nominal.
Exposed Paddle. The exposed paddle should be soldered to a low impedance ground plane.
Rev. B | Page 5 of 20
AD8341
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0
GAIN SETPOINT = 1.0
PHASE SETPOINT = 0°
0.5
PHASE SETPOINT = 270°
–15
PHASE SETPOINT = 180°
–20
PHASE SETPOINT = 90°
–25
–30
04700-003
–35
–40
0
0.1
0.2
0.3
0.4
0.6
0.5
GAIN SETPOINT
0.7
0.8
0.9
0
–0.5
–1.0
–1.5
–2.0
GAIN SETPOINT = 0.25
–2.5
–3.0
–3.5
GAIN SETPOINT = 0.1
–4.0
–4.5
1.0
0
135
180
225
270
315
360
Figure 6. Gain Conformance Error vs. Phase Setpoint at
Different Gain Setpoints, RF Frequency = 1900 MHz
360
6
PHASE SETPOINT = 315°
5
315
4
PHASE SETPOINT = 270°
3
GAIN SETPOINT = 0.25
270
PHASE SETPOINT = 0°
2
GAIN SETPOINT = 0.5
PHASE (Degrees)
PHASE SETPOINT = 45°
1
0
–1
PHASE SETPOINT = 225°
–2
–3
225
GAIN SETPOINT = 0.1
GAIN SETPOINT = 1.0
180
135
PHASE SETPOINT = 90°
–4
90
PHASE SETPOINT = 180°
–5
–6
–7
PHASE SETPOINT = 135°
–8
0
0.1
0.2
0.3
45
04700-004
GAIN CONFORMANCE ERROR (dB)
90
PHASE SETPOINT (Degrees)
Figure 3. Gain Magnitude vs. Gain Setpoint at Different
Phase Setpoints, RF Frequency = 1900 MHz
0.4
0.5 0.6
GAIN SETPOINT
0.7
0.8
0.9
0
0
1.0
Figure 4. Gain Conformance Error vs. Gain Setpoint at
Different Phase Setpoints, RF Frequency = 1900 MHz
45
90
135
180
225
270
PHASE SETPOINT (Degrees)
315
360
Figure 7. Phase vs. Phase Setpoint at
Different Gain Setpoints, RF Frequency = 1900 MHz
–2
25
GAIN SETPOINT = 1.0
–4
GAIN SETPOINT = 0.1
20
–6
PHASE ERROR (Degrees)
–8
GAIN SETPOINT = 0.5
–12
–14
GAIN SETPOINT = 0.25
–16
–18
–20
–22
GAIN SETPOINT = 0.1
–26
–28
0
45
90
135
180
225
270
315
GAIN SETPOINT = 0.25
10
5
0
GAIN SETPOINT = 0.5
GAIN SETPOINT = 1.0
–5
–10
04700-005
–24
15
04700-008
–10
GAIN (dB)
45
04700-007
GAIN (dB)
–10
GAIN SETPOINT = 0.5
04700-006
GAIN CONFORMANCE ERROR (dB)
–5
–15
360
0
PHASE SETPOINT (Degrees)
45
90
135
180
225
270
PHASE SETPOINT (Degrees)
315
360
Figure 8. Phase Error vs. Phase Setpoint at Different Gain Setpoints,
RF Frequency = 1900 MHz
Figure 5. Gain Magnitude vs. Phase Setpoint at Different
Gain Setpoints, RF Frequency = 1900 MHz
Rev. B | Page 6 of 20
Data Sheet
AD8341
–147
0
–1
–148
–40°C
–2
RF PIN = +5dBm
+25°C
–3
RF PIN = 0dBm
GAIN (dB)
–150
–151
–7
04700-009
–154
0.1
0.2
0.3
0.4
0.5
0.6
GAIN SETPOINT
0.7
0.8
0.9
–9
–10
1500
1.0
Figure 9. Output Noise Floor vs. Gain Setpoint, Noise in dBm/Hz, No Carrier,
and With 1900 MHz Carrier (Measured at 20 MHz Offset)
Pin = −5, 0, and +5 dBm
–8
GAIN SETPOINT = 0.5
GAIN (dB)
GAIN SETPOINT = 0.25
–14
–16
–18
–20
GAIN SETPOINT = 0.1
–22
04700-010
–24
–26
–28
1500
1600
1700
1800
2200
2300
2400
1900
2000
2100
2200
2300
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
100
2400
SECOND BASEBAND HARMONIC PRODUCT,
1898MHz, 1902MHz
200
THIRD BASEBAND HARMONIC PRODUCT,
1897MHz, 1903MHz
900
1000
300
400
500
600
700
800
DIFFERENTIAL BB LEVEL (mV p-p)
FREQUENCY (MHz)
Figure 10. Gain vs. Frequency at Different Gain Setpoints,
Phase Setpoint = 0°
Figure 13. Baseband Harmonic Distortion (I and Q Channel,
RF Input = 0 dBm, Output Balun and Cable Losses of Approximately
2 dB Not Accounted for in Plot)
–146
12
–147
–40°C
10
+25°C
–148
8
OP1dB (dBm)
–149
–150
–151
6
+85°C
4
–152
–154
1500
2
1600
1700
1800 1900 2000 2100
FREQUENCY (MHz)
2200
2300
0
1500
2400
04700-014
–153
04700-011
NOISE (dBm/Hz)
1800 1900 2000 2100
FREQUENCY (MHz)
FUNDAMENTAL POWER, 1899MHz, 1900MHz
–10
–12
1700
0
GAIN SETPOINT = 1.0
–4
–6
1600
Figure 12. Gain Magnitude vs. Frequency and Temperature,
Maximum Gain, Phase Setpoint = 0°
RF OUTPUT AM SIDEBAND POWER (dBm)
0
–2
04700-012
–8
NO RF INPUT
–153
0
–6
+85°C
RF PIN = –5dBm
–152
–4
–5
04700-013
NOISE (dBm/Hz)
–149
1600
1700
1800 1900 2000 2100
FREQUENCY (MHz)
2200
2300
2400
Figure 14. Output 1 dB Compression Point vs. Frequency and
Temperature, Maximum Gain, Phase Setpoint = 0°
Figure 11. Output Noise Floor vs. Frequency, Maximum Gain,
No RF Carrier, Phase Setpoint = 0°
Rev. B | Page 7 of 20
AD8341
Data Sheet
20
25
GAIN SETPOINT = 1.0
–40°C
15
20
GAIN SETPOINT = 0.5
+25°C
OIP3 (dBm)
OIP3 (dBm)
10
15
+85°C
10
GAIN SETPOINT = 0.25
5
0
GAIN SETPOINT = 0.1
5
1600
1700
1800 1900 2000 2100
FREQUENCY (MHz)
2200
2300
04700-018
0
1500
04700-015
–5
–10
0
2400
45
90
135
180
Figure 15. Output IP3 vs. Frequency and Temperature,
Maximum Gain, Phase Setpoint = 0°, 2.5 MHz Carrier Spacing
270
315
360
Figure 18. Output IP3 vs. Gain and Phase Setpoints,
RF Frequency = 1900 MHz, 2.5 MHz Carrier Spacing
RBW 30kHz
VBW 30kHz
SWT 100ms
–10
1V p-p BB INPUT
0
REF LVL
0dBm
RF ATT
20dB
UNIT
dBm
A
–15
–30
60
110
160
210
260
FREQUENCY (MHz)
310
360
–60
–70
–80
1SA
04700-019
–35
10
–50
SECOND BASEBAND HARMONIC
250mV p-p BB INPUT
–40
UNDESIRED SIDEBAND
OUTPUT POWER (dBm)
–25
–30
RF FEEDTHROUGH
–20
–20
DESIRED SIDEBAND
500mV p-p BB INPUT
SECOND BASEBAND HARMONIC
–10
04700-016
RF OUTPUT AM SIDEBAND POWER (dBm)
225
PHASE SETPOINT (Degrees)
–90
410
–100
CENTER 1.9GHz
500kHz/
SPAN 5MHz
FREQUENCY (MHz)
Figure 19. Single-Sideband Performance, RF Frequency = 1900 MHz,
RF Input = −10 dBm; 1 MHz, 500 mV p-p Differential BB Drive
Figure 16. I/Q Modulation Bandwidth vs. Baseband Magnitude
90
10
GAIN SETPOINT = 1.0
60
120
5
30
150
0
GAIN SETPOINT = 0.25
0
180
–5
1500MHz
–10
210
GAIN SETPOINT = 0.1
45
90
135
180
330
225
270
315
360
240
PHASE SETPOINT (Degrees)
300
270
Figure 17. Output 1 dB Compression Point vs. Gain and
Phase Setpoints, RF Frequency = 1900 MHz
S11 RF PORT WITH 1.2nH INDUCTORS
S11 RF PORT WITHOUT INDUCTORS
Figure 20. Input Impedance Smith Chart
Rev. B | Page 8 of 20
04700-020
–15
0
2400MHz
04700-017
OP1dB (dBm)
GAIN SETPOINT = 0.5
Data Sheet
AD8341
90
0
–5
60
120
RF OUTPUT POWER (dBm)
–10
30
0
180
1500MHz
2400MHz
210
–20
–25
–30
–35
–40
–45
330
04700-024
150
–15
–50
–55
0
240
300
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
DSOP VOLTAGE (V)
04700-021
270
SDD22 PORT DIFFERENTIAL
S22 WITH 1 TO 1 TRANSFORMER
Figure 24. Output Disable Attenuation,
RF Frequency = 1900 MHz, RF Input = −5 dBm
Figure 21. Output Impedance Smith Chart
0
2V/DIV
DSOP
–20
3
PHASE SETPOINT = 0
VOLTS
–30
–40
RF OUTPUT
PHASE SETPOINT = 45
–50
4
100mV/DIV
04700-022
–60
PHASE SETPOINT = 90
–70
0
0.1
0.2
0.3
0.4
0.5
0.6
GAIN SETPOINT
0.7
0.8
0.9
CH3 2.0V CH4 100mV M10.0ns 5.0GS/s A CH3
TIME (10ns/DIV)
1.0
Figure 22. Phase Error vs. Gain Setpoint by Phase Setpoint,
RF Frequency = 1900 MHz
Figure 25. Output Disable Response Time,
RF Frequency = 1900 MHz, RF Input = 0 dBm
127
VPOS = 5.00V
125
VPOS = 5.25V
124
123
VPOS = 4.75V
122
121
–40 –30 –20 –10
04700-023
SUPPLY CURRENT (mA)
126
0
10 20 30 40
TEMPERATURE (C)
50
60
70
80
Figure 23. Supply Current vs. Temperature
Rev. B | Page 9 of 20
04700-025
PHASE ERROR (Degrees)
–10
1.84V
AD8341
Data Sheet
THEORY OF OPERATION
VBBI
I CHANNEL INPUT
LINEAR
ATTENUATOR
V-I
SINGLE-ENDED OR
DIFFERENTIAL
50Ω INPUT Z
BBI
(
/ VO )2 + VBBQ / VO
)]
OUTPUT
DISABLE
LINEAR
ATTENUATOR
Q CHANNEL INPUT
VBBQ
Figure 26. Simplified Architecture of the AD8341
Vq
MAX GAIN
+0.5
A
|A|
θ
+0.5
–0.5
MIN GAIN
The correspondence between the desired gain and phase setpoints,
GainSP and PhaseSP, and the Cartesian inputs, VBBI and VBBQ, is
given by simple trigonometric identities
[(V
SINGLE-ENDED OR
DIFFERENTIAL
50Ω OUTPUT
I-V
V-I
A change in sign of VBBI or VBBQ can be viewed as a change in
sign of the gain or as a 180° phase change. The outermost circle
represents the maximum gain magnitude of unity. The circle
origin implies, in theory, a gain of 0. In practice, circuit mismatches
and unavoidable signal feedthrough limit the minimum gain to
approximately −34.5 dB. The phase angle between the resultant
gain vector and the positive x-axis is defined as the phase shift.
Note that there is a nominal, systematic insertion phase through
the AD8341 to which the phase shift is added. In the following
discussions, the systematic insertion phase is normalized to 0°.
GainSP =
0°/90°
04700-026
By controlling the relative amounts of I and Q components that
are summed, continuous magnitude and phase control of the
gain is possible. Consider the vector gain representation of the
AD8341 expressed in polar form in Figure 27. The attenuation
factors for the I and Q signal components are represented on
the x- and y-axis, respectively, by the baseband inputs, VBBI and
VBBQ. The resultant of their vector sum represents the vector
gain, which can also be expressed as a magnitude and phase. By
applying different combinations of baseband inputs, any vector
gain within the unit circle can be programmed.
Pure amplitude modulation is represented by radial movement of
the gain vector tip at a fixed angle, while pure phase modulation
is represented by rotation of the tip around the circle at a fixed
radius. Unlike traditional I-Q modulators, the AD8341 is designed
to have a linear RF signal path from input to output. Traditional
I-Q modulators provide a limited LO carrier path through which
any amplitude information is removed.
–0.5
Vi
04700-027
The AD8341 is a linear RF vector modulator with Cartesian
baseband controls. In the simplified block diagram given in
Figure 26, the RF signal propagates from the left to the right
while baseband controls are placed above and below. The RF
input is first split into in-phase (I) and quadrature (Q) components.
The variable attenuators independently scale the I and Q components of the RF input. The attenuator outputs are then summed
and buffered to the output.
Figure 27. Vector Gain Representation
RF QUADRATURE GENERATOR
2
PhaseSP = arctan(VBBQ / VBBI )
where:
VO is the baseband scaling constant (500 mV).
VBBI and VBBQ are the differential I and Q baseband voltages,
respectively.
Note that when evaluating the arctangent function, the proper
phase quadrant must be selected. For example, if the principal
value of the arctangent (known as the Arctangent(x)) is used,
quadrants 2 and 3 could be interpreted mistakenly as quadrants
4 and 1, respectively. In general, both VBBI and VBBQ are needed
in concert to modulate the gain and the phase.
The RF input is directly coupled differentially or single-ended
to the quadrature generator, which consists of a multistage RC
polyphase network tuned over the operating frequency range of
1.5 GHz to 2.4 GHz. The recycling nature of the polyphase network generates two replicas of the input signal, which are in
precise quadrature, i.e., 90°, to each other. Because the passive
network is perfectly linear, the amplitude and phase information
contained in the RF input is transmitted faithfully to both channels. The quadrature outputs are then separately buffered to drive
the respective attenuators. The characteristic impedance of the
polyphase network is used to set the input impedance of the
AD8341.
Rev. B | Page 10 of 20
Data Sheet
AD8341
I-Q ATTENUATORS AND BASEBAND AMPLIFIERS
GAIN AND PHASE ACCURACY
The proprietary linear-responding attenuator structure is an active
solution with differential inputs and outputs that offer excellent
linearity, low noise, and greater immunity from mismatches than
other variable attenuator methods. The gain, in linear terms, of
the I and Q channels is proportional to its control voltage with a
scaling factor designed to be 2/V, i.e., a full-scale gain setpoint of
1.0 (−4.5 dB) for a VBBI (or a VBBQ) of 500 mV. The control voltages
can be driven differentially or single-ended. The combination of
the baseband amplifiers and attenuators allows for maximum
modulation bandwidths in excess of 200 MHz.
There are numerous ways to express the accuracy of the
AD8341. Ideally, the gain and phase must precisely follow the
setpoints. Figure 4 illustrates the gain error in dB from a best fit
line, normalized to the gain measured at the gain setpoint = 1.0,
for the different phase setpoints. Figure 6 shows the gain error
in a different form, normalized to the gain measured at phase
setpoint = 0°; the phase setpoint is swept from 0° to 360° for
different gain setpoints. Figure 8 and Figure 22 show analogous
errors for the phase error as a function of gain and phase setpoints.
The accuracy clearly depends on the region of operation within
the vector gain unit circle. Operation very close to the origin
generally results in larger errors as the relative accuracy of the I
and Q vectors degrades.
OUTPUT AMPLIFIER
The output amplifier accepts the sum of the attenuator outputs
and delivers a differential output signal into the external load.
The output pins must be pulled up to an external supply,
preferably through RF chokes. When the 50 Ω load is taken
differentially, an output P1dB and IP3 of 8.5 dBm and 17.5 dBm
is achieved, respectively, at 1.9 GHz. The output can be taken in
single-ended fashion, albeit at lower performance levels.
NOISE AND DISTORTION
The output noise floor and distortion levels vary with the gain
magnitude but do not vary significantly with the phase. At the
higher gain magnitude setpoints, the OIP3 and the noise floor
vary in direct proportion with the gain. At lower gain magnitude
setpoints, the noise floor levels off while the OIP3 continues to
vary with the gain.
RF FREQUENCY RANGE
The frequency range on the RF input is limited by the internal
polyphase quadrature phase-splitter. The phase-splitter splits the
incoming RF input into two signals, 90° out of phase, as previously
described in the RF Quadrature Generator section. This polyphase
network has been designed to ensure robust quadrature accuracy
over standard fabrication process parameter variations for the
1.5 GHz to 2.4 GHz specified RF frequency range. Using the
AD8341 as a single-sideband modulator and measuring the
resul-ting sideband suppression is a good gauge of how well the
quadrature accuracy is maintained over RF frequency. A typical
plot of sideband suppression from 1.1 GHz to 2.7 GHz is shown
in Figure 28. The level of sideband suppression degradation
outside the 1.5 GHz to 2.4 GHz specified range is subject to
manufacturing process variations.
–20
–25
–30
–35
–40
–45
0.7
04700-028
SIDEBAND SUPPRESSION (dBc)
–15
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
FREQUENCY (GHz)
Figure 28. Sideband Suppression vs. Frequency
Rev. B | Page 11 of 20
2.5
2.7
AD8341
Data Sheet
APPLICATIONS INFORMATION
Different matching inductors can improve matching over a
narrower frequency range. The single-ended and differential
input impedances are exactly the same.
USING THE AD8341
The AD8341 is designed to operate in a 50 Ω impedance system.
Figure 30 illustrates an example where the RF input is driven in
a single-ended fashion while the differential RF output is converted
to a single-ended output with an RF balun. The baseband controls
for the I and Q channels are typically driven from differential
DAC outputs. The power supplies, VPRF and VPS2, must be
bypassed appropriately with 0.1 µF and 100 pF capacitors. Low
inductance grounding of the CMOP and CMRF common pins
is essential to prevent unintentional peaking of the gain.
100pF 1.2nH
RFIM
~1VDC
RC
PHASE
RF
04700-029
100pF 1.2nH
RFIP
50Ω
Figure 29. RF Input Interface to the AD8341 Showing
Coupling Capacitors and Matching Inductors
RF INPUT AND MATCHING
The RFIP and RFIM must be ac-coupled through low loss series
capacitors as shown in Figure 29. The internal dc levels are at
approximately 1 V. For single-ended operation, one input is
driven by the RF signal while the other input is ac grounded.
The input impedance of the AD8341 is defined by the characteristics of the polyphase network. The capacitive component of
the network causes its impedance to roll-off with frequency albeit
at a rate slower than 6 dB/octave. By using matching inductors
on the order of 1.2 nH in series with each of the RF inputs, RFIP
and RFIM, a 50 Ω match is achieved with a return loss of >10 dB
over the operating frequency range.
VP
C2
100pF
C1
0.1µF
IBBM
VP
IBBP
C12
(SEE TEXT)
C6
100pF
VPS2
IBBM
OUTPUT
DISABLE
DSOP
CMOP
CMRF
CMOP
RFIM
RFOM
C17
100pF
AD8341
RFOP
CMRF
CMOP
VPRF
C3
0.1µF
C4
100pF
QFLP
VPS2
VP
RFIP
QBBM
L4
1.2nH
QBBP
C5
100pF
QFLM
RF
INPUT
L3
1.2nH
IFLP
VPRF
IBBP
VP
B
IFLM
C7
100pF
C8
0.1µF
A
L1
120nH
ETC1-1-13
RF
OUTPUT
C18
L2
100pF
120nH
CMOP
VPS2
C14
0.1µF
VP
C10
0.1µF
QBBP
QBBM
C9
100pF
Figure 30. Basic Connections
Rev. B | Page 12 of 20
04700-030
C11
(SEE TEXT)
Data Sheet
AD8341
RF OUTPUT AND MATCHING
–2.5
RL2 = SHORT
–3.0
The RF outputs of the AD8341, RFOP, and RFOM, are open
collectors of a transimpedance amplifier, which need to be
pulled up to the positive supply, preferably with RF chokes as
shown in Figure 31. The nominal output impedance looking
into each individual output pin is 25 Ω. Consequently, the
differential output impedance is 50 Ω.
–3.5
–4.0
GAIN (dB)
–4.5
–5.0
RL2 = 50Ω
–5.5
–6.0
–6.5
VP
–7.0
120nH
RT
RFOM
±ISIG
GM
–8.0
1:1
100pF
RF
OUTPUT
1.0
04700-031
50Ω
DIFFERENTIAL
1.2
1.4
1.6
1.8
2.0
2.2
2.4
FREQUENCY (GHz)
2.6
2.8
3.0
Figure 32. Gain of the AD8341 Using a Single-Ended Output with Different
Dummy Loads, RL2, on the Unused Output
RFOP
RT
RL = 50Ω
–8.5
100pF
04700-032
RL2 = OPEN
–7.5
Figure 31. RF Output Interface to the AD8341 Showing
Coupling Capacitors, Pull-Up RF Chokes, and Balun
Because the output dc levels are at the positive supply, ac coupling
capacitors are usually be needed between the AD8341 outputs
and the next stage in the system.
A 1:1 RF broadband output balun, such as the ETC1-1-13
(M/A-COM), converts the differential output of the AD8341
into a single-ended signal. Note that the loss and balance of the
balun directly impact the apparent output power, noise floor,
and gain/phase errors of the AD8341. In critical applications,
narrow-band baluns with low loss and superior balance are
recommended.
If the output is taken in a single-ended fashion directly into a
50 Ω load through a coupling capacitor, there is an impedance
mismatch. This can be resolved with a 1:2 balun to convert the
single-ended 25 Ω output impedance to 50 Ω. If loss of signal
swing is not critical, a 25 Ω back termination in series with the
output pin can also be used. The unused output pin must still be
pulled up to the positive supply. The user may load it through a
coupling capacitor with a dummy load to preserve balance. The
gain of the AD8341 when the output is single-ended varies
slightly with dummy load value as shown in Figure 32.
The RF output signal can be disabled by raising the DSOP pin
to the positive supply. The output disable function provides
>30 dB attenuation of the input signal even at full gain. The
interface to DSOP is high impedance and the shutdown and
turn-on response times are
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