Active Receive Mixer,
400 MHz to 1.2 GHz
AD8344
Data Sheet
12
COMM 13
11
10
COMM
EXRB
PWDN
VPDC
FUNCTIONAL BLOCK DIAGRAM
9
COMM
RFCM 14
7
IFOP
RFIN 15
6
IFOM
5
COMM
2
3
4
COMM
1
LOIN
VPMX 16
04826-0-001
8
BIAS
LOCM
Broadband RF port: 400 MHz to 1.2 GHz
Conversion gain: 4.5 dB
Noise figure: 10.5 dB
Input IP3: 24 dBm
Input P1dB: 8.5 dBm
LO drive: 0 dBm
External control of mixer bias for low power operation
Single-ended, 50 Ω RF and LO input ports
Single-supply operation: 5 V at 84 mA
Power-down mode
Exposed paddle LFCSP: 3 mm × 3 mm
VPLO
FEATURES
Figure 1.
APPLICATIONS
Cellular base station receivers
ISM receivers
Radio links
RF Instrumentation
GENERAL DESCRIPTION
The AD8344 is a high performance, broadband active mixer. It
is well suited for demanding receive-channel applications that
require wide bandwidth on all ports and very low intermodulation
distortion and noise figure.
The AD8344 provides a typical conversion gain of 4.5 dB at
890 MHz. The integrated LO driver supports a 50 Ω input
impedance with a low LO drive level, helping to minimize
external component count.
The single-ended 50 Ω broadband RF port allows for easy
interfacing to both active devices and passive filters. The RF
input accepts input signals as large as 1.7 V p-p or 8.5 dBm
(re: 50 Ω) at P1dB.
Rev. A
The open-collector differential outputs provide excellent balance
and can be used with a differential filter or IF amplifier, such as
the AD8369 or AD8351. These outputs may also be converted
to a single-ended signal using a matching network or a transformer (balun). When centered on the VPOS supply voltage,
each of the differential outputs may swing 2.5 V p-p.
The AD8344 is fabricated on an Analog Devices proprietary,
high performance SiGe IC process. The AD8344 is available in a
16-lead LFCSP package. It operates over the −40°C to +85°C
temperature range. An evaluation board is also available.
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Tel: 781.329.4700 ©2004–2018 Analog Devices, Inc. All rights reserved.
Technical Support
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AD8344
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Circuit Description......................................................................... 13
Applications ....................................................................................... 1
AC Interfaces ................................................................................... 14
Functional Block Diagram .............................................................. 1
IF Port .......................................................................................... 14
General Description ......................................................................... 1
LO Considerations ..................................................................... 15
Revision History ............................................................................... 2
Bias Resistor Selection ............................................................... 16
Specifications..................................................................................... 3
Conversion Gain and IF Loading............................................. 16
AC Performance ............................................................................... 4
Low IF Frequency Operation.................................................... 17
Absolute Maximum Ratings............................................................ 5
Evaluation Board ............................................................................ 18
ESD Caution .................................................................................. 5
Outline Dimensions ....................................................................... 20
Pin Configuration and Function Descriptions ............................. 6
Ordering Guide .......................................................................... 20
Typical Performance Characteristics ............................................. 7
REVISION HISTORY
4/2018—Rev. 0 to Rev. A
Changes to Figure 2 and Table 4 ..................................................... 6
Updated Outline Dimensions ....................................................... 20
Changes to Ordering Guide .......................................................... 20
6/2004—Revision 0: Initial Version
Rev. A | Page 2 of 20
Data Sheet
AD8344
SPECIFICATIONS
VS = 5 V, TA = 25°C, fRF = 890 MHz, fLO = 1090 MHz, LO power = 0 dBm, ZO = 50 Ω, RBIAS = 2.43 kΩ, unless otherwise noted.
Table 1.
Parameter
RF INPUT INTERFACE
Return Loss
DC Bias Level
OUTPUT INTERFACE
Output Impedance
DC Bias Voltage
Power Range
LO INTERFACE
LO Power
Return Loss
DC Bias Voltage
POWER-DOWN INTERFACE
PWDN Threshold
PWDN Response Time
PWDN Input Bias Current
POWER SUPPLY
Positive Supply Voltage
Quiescent Current
VPDC
VPMX, IFOP, IFOM
VPLO
Total Quiescent Current
Power-Down Current
Conditions
(Pin 15, RFIN and Pin 14, RFCM)
Min
4.75
−10
9||1
VS
Internally generated; port must be ac-coupled
0
10
VS − 1.6
Device enabled, IF output to 90% of its final level
Device disabled, supply current < 5 mA
Device enabled
Device disabled
VS − 1.4
0.4
0.01
−80
100
4.75
Supply current for bias cells
Supply current for mixer, RBIAS = 2.43 kΩ
Supply current for LO limiting amplifier
73
Device disabled
Rev. A | Page 3 of 20
Max
10
2.6
Internally generated; port must be ac-coupled
Differential impedance, f = 200 MHz
Externally generated
Via a 4:1 balun
Typ
VS
5
44
35
84
500
Unit
dB
V
5.25
13
+4
kΩ||pF
V
dBm
dBm
dB
V
V
µs
µs
µA
µA
5.25
95
V
mA
mA
mA
mA
µA
AD8344
Data Sheet
AC PERFORMANCE
VS = 5 V, TA = 25°C, LO power = 0 dBm, ZO = 50 Ω, RBIAS = 2.43 kΩ, unless otherwise noted.
Table 2.
Parameter
RF Frequency Range
LO Frequency Range
IF Frequency Range
Conversion Gain
SSB Noise Figure
Input Third-Order Intercept
Input Second-Order Intercept
Input 1 dB Compression Point
LO to IF Output Feedthrough
LO to RF Input Leakage
RF to IF Output Feedthrough
IF/2 Spurious
Conditions
Min
400
470
70
High Side LO
fRF = 450 MHz, fLO = 550 MHz, fIF = 100 MHz
fRF = 890 MHz, fLO = 1090 MHz, fIF = 200 MHz
fRF = 450 MHz, fLO = 550 MHz, fIF = 100 MHz
fRF = 890 MHz, fLO = 1090 MHz, fIF = 200 MHz
fRF1 = 450 MHz, fRF2 = 451 MHz, fLO = 550 MHz,
fIF = 100 MHz, each RF tone = −10 dBm
fRF1 = 890 MHz, fRF2 = 891 MHz, fLO = 1090 MHz,
fIF = 200 MHz, each RF tone = −10 dBm
fRF1 = 450 MHz, fRF2 = 500 MHz, fLO = 550 MHz, fIF = 100 MHz
fRF1 = 890 MHz, fRF2 = 940 MHz, fLO = 1090 MHz, fIF = 200 MHz
fRF = 450 MHz, fLO = 550 MHz, fIF = 100 MHz
fRF = 890 MHz, fLO = 1090 MHz, fIF = 200 MHz
LO Power = 0 dBm, fRF = 890 MHz, fLO = 1090 MHz
LO Power = 0 dBm, fRF = 890 MHz, fLO = 1090 MHz
RF Power = −10 dBm, fRF = 890 MHz, fLO = 1090 MHz
RF Power = −10 dBm, fRF = 890 MHz, fLO = 1090 MHz
Rev. A | Page 4 of 20
Typ
Max
1200
1600
400
9.25
4.5
7.75
10.5
14
Unit
MHz
MHz
MHz
dB
dB
dB
dB
dBm
24
dBm
36
51
2.5
8.5
−23
−48
−32
−66
dBm
dBm
dBm
dBm
dBc
dBc
dBc
dBm
Data Sheet
AD8344
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage, VS
RF Input Level
LO Input Level
PWDN Pin
IFOP, IFOM Bias Voltage
Minimum Resistor from EXRB to COMM
Internal Power Dissipation
θJA
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature Range (Soldering 60 sec)
Rating
5.5 V
12 dBm
12 dBm
VS + 0.5 V
5.5 V
2.4 kΩ
580 mW
77°C/W
125°C
−40°C to +85°C
−65°C to +150°C
300°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. A | Page 5 of 20
AD8344
Data Sheet
13 COMM
14 RFCM
16 VPMX
15 RFIN
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VPLO 1
12 VPDC
LOCM 2
AD8344
11 PWDN
LOIN 3
TOP VIEW
(Not to Scale)
10 EXRB
IFOP 7
COMM 8
IFOM 6
COMM 5
NOTES
1. EXPOSED PAD. THE EXPOSED PAD
MUST BE CONNECTED TO AGND.
04826-0-002
9 COMM
COMM 4
Figure 2. 16-Lead LFCSP
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4, 5, 8, 9, 13
6, 7
10
Mnemonic
VPLO
LOCM
LOIN
COMM
IFOM, IFOP
EXRB
11
12
14
15
16
PWDN
VPDC
RFCM
RFIN
VPMX
EPAD
Function
Positive Supply Voltage for the LO Buffer: 4.75 V to 5.25 V.
AC Ground for Limiting LO Amplifier, AC-Coupled to Ground.
LO Input. Nominal input level 0 dBm, input level range −10 dBm to +4 dBm, re: 50 Ω, ac-coupled.
Device Common (DC Ground).
Differential IF Outputs; Open Collectors, Each Requires DC Bias of 5.00 V (Nominal).
Mixer Bias Voltage, Connect Resistor from EXRB to Ground, Typical Value of 2.43 kΩ
Sets Mixer Current to Nominal Value. Minimum resistor value from EXRB to ground = 2.4 kΩ.
Connect to Ground for Normal Operation. Connect pin to VS for disable mode.
Positive Supply Voltage for the DC Bias Cell: 4.75 V to 5.25 V.
AC Ground for RF Input, AC-Coupled to Ground.
RF Input. Must be ac-coupled.
Positive Supply Voltage for the Mixer: 4.75 V to 5.25 V.
Exposed Pad. The exposed pad must be connected to AGND.
Rev. A | Page 6 of 20
Data Sheet
AD8344
TYPICAL PERFORMANCE CHARACTERISTICS
12
10
IF = 70MHz
IF = 100MHz
IF = 200MHz
IF = 400MHz
10
RF = 450MHz
9
8
7
GAIN (dB)
GAIN (dB)
8
6
4
6
5
RF = 890MHz
4
3
2
04826-0-010
–2
400
500
600
700
800
900
1000
RF FREQUENCY (MHz)
1100
04826-0-011
2
0
1
0
80
1200
Figure 3. Conversion Gain vs. RF Frequency
120
160
200
240
280
IF FREQUENCY (MHz)
45
5.5
4.5
35
4.0
30
PERCENTAGE
3.5
3.0
2.5
2.0
1.5
25
20
15
10
04826-0-022
1.0
0.5
–8
–7
–6
–5 –4 –3 –2 –1
LO LEVEL (dBm)
0
1
2
3
5
0
3.6
4
Figure 4. Conversion Gain vs. LO Power, FRF = 890 MHz, FIF = 200 MHz
VS = 4.75V
VS = 5.0V
VS = 5.25V
6.0
5.5
5.0
4.5
4.0
3.5
04826-0-018
3.0
2.5
2.0
–40 –30 –20 –10
0
10 20 30 40
TEMPERATURE (°C)
50
60
70
3.8
4.0
4.2
4.4
4.6
GAIN (dB)
4.8
5.0
5.2
5.4
Figure 7. Conversion Gain Distribution, FRF = 890 MHz, FIF = 200 MHz
7.0
6.5
04826-0-031
GAIN (dB)
400
NORMAL (MEAN = 4.47,
STD DEV = 0.18)
GAIN PERCENTAGE
40
5.0
GAIN (dB)
360
Figure 6. Conversion Gain vs. IF Frequency
6.0
0
–10 –9
320
80
Figure 5. Conversion Gain vs. Temperature, FRF = 890 MHz, FLO = 1090 MHz
Rev. A | Page 7 of 20
AD8344
Data Sheet
28
30
IF = 70MHz
IF = 100MHz
IF = 200MHz
IF = 400MHz
26
28
26
20
18
16
22
20
18
16
14
RF = 450MHz
500
600
1000
900
800
700
RF FREQUENCY (MHz)
1100
04826-0-013
04826-0-012
14
12
10
400
RF = 890MHz
24
22
INPUT IP3 (dBm)
INPUT IP3 (dBm)
24
12
10
80
1200
Figure 8. Input IP3 vs. RF Frequency (RF Tone Spacing = 1 MHz)
120
160
200
240
280
IF FREQUENCY (MHz)
360
400
Figure 11. Input IP3 vs. IF Frequency (RF Tone Spacing = 1 MHz)
25.0
35
NORMAL (MEAN = 24.023,
STD DEV = 0.24)
IP3 PERCENTAGE
24.5
30
24.0
23.5
25
23.0
PERCENTAGE
INPUT IP3 (dBm)
320
22.5
22.0
21.5
20
15
10
04826-0-023
21.0
20.0
–10 –9
–8
–7
–6
–5 –4 –3 –2 –1
LO LEVEL (dBm)
0
1
2
3
5
0
23.0
4
30
VS = 4.75V
VS = 5.0V
VS = 5.25V
28
26
25
24
23
22
04826-0-019
INPUT IP3 (dBm)
27
21
20
–40 –30 –20 –10
0
10 20 30 40
TEMPERATURE (°C)
50
60
70
23.2
23.4
23.6
23.8 24.0 24.2
INPUT IP3 (dBm)
24.4
24.6
24.8
Figure 12. Input IP3 Distribution,
FRF1 = 890 MHz, FRF2 = 891 MHz, FLO = 1090 MHz
Figure 9. Input IP3 vs. LO Power,
FRF1 = 890 MHz, FRF2 = 891 MHz, FLO = 1090 MHz
29
04826-0-032
20.5
80
Figure 10. Input IP3 vs. Temperature,
FRF1 = 890 MHz, FRF2 = 891 MHz, FLO = 1090 MHz
Rev. A | Page 8 of 20
25.0
Data Sheet
AD8344
50
60
58
48
56
46
52
INPUT IP2 (dBm)
44
42
40
38
36
50
48
46
44
RF = 450MHz
42
40
38
IF = 70
IF = 100
IF = 200
IF = 400
32
30
400
500
600
700
800
900
1000
RF FREQUENCY (MHz)
1100
36
04826-0-033
34
04826-0-015
INPUT IP2 (dBm)
RF = 890MHz
54
34
32
30
1200
80
Figure 13. Input IP2 vs. RF Frequency (RF Tone Spacing = 50 MHz)
120
160
200
240
280
IF FREQUENCY (MHz)
320
360
400
Figure 16. Input IP2 vs. IF Frequency (RF Tone Spacing = 50 MHz)
60
35
NORMAL (MEAN = 48.96,
STD DEV = 01.17)
IIP2 PERCENTAGE
58
56
30
54
25
50
PERCENTAGE
INPUT IP2 (dBm)
52
48
46
44
42
40
20
15
10
38
04826-0-034
36
32
30
–10 –9
–8
–7
–6
–5 –4 –3 –2 –1
LO LEVEL (dBm)
0
1
2
3
5
0
44
4
4.75V
5.0V
5.25V
50
48
46
44
04826-0-037
INPUT IP2 (dBm)
52
42
40
–40 –30 –20 –10
0
10 20 30 40
TEMPERATURE (C)
50
60
70
45
46
47
48
49
50
51
INPUT IP2 (dBm)
52
53
Figure 17. Input IP2 Distribution, FRF = 890 MHz,
FLO = 1090 MHz (RF Tone Spacing = 50 MHz)
Figure 14. Input IP2 vs. LO Power,
FRF = 890 MHz, FLO = 1090 MHz (RF Tone Spacing = 50 MHz)
54
04826-0-035
34
80
Figure 15. Input IP2 vs. Temperature, FRF = 890 MHz,
FLO = 1090 MHz (RF Tone Spacing = 50 MHz)
Rev. A | Page 9 of 20
54
55
AD8344
Data Sheet
10
12
IF = 70MHz
IF = 100MHz
IF = 200MHz
IF = 400MHz
9
RF = 890MHz
8
7
8
INPUT P1dB (dBm)
INPUT P1dB (dBm)
10
6
4
6
5
4
3
RF = 450MHz
04826-0-016
0
400
500
600
900
1000
800
700
RF FREQUENCY (MHz)
1100
04826-0-017
2
2
1
0
80
1200
9.0
60
8.8
55
8.6
50
200
240
280
IF FREQUENCY (MHz)
320
360
400
NORMAL (MEAN = 8.50,
STD DEV = 0.38)
INPUT P1dB PERCENTAGE
45
8.4
40
8.2
PERCENTAGE
8.0
7.8
7.6
30
25
20
15
04826-0-024
7.4
7.2
7.0
–10 –9
35
–8
–7
–6
–5 –4 –3 –2 –1
LO LEVEL (dBm)
0
1
2
3
VS = 4.75V
VS = 5.0V
VS = 5.25V
8.5
8.0
7.5
7.0
6.5
04826-0-020
6.0
5.5
5.0
–40 –30 –20 –10
0
10 20 30 40
TEMPERATURE (°C)
50
60
70
7.5
8.0
8.5
9.0
INPUT P1dB (dBm)
9.5
10.0
Figure 22. Input P1dB Distribution, FRF = 890 MHz, FLO = 1090 MHz
10.0
9.0
5
0
7.0
4
Figure 19. Input P1dB vs. LO Power, FRF = 890 MHz, FLO = 1090 MHz
9.5
10
04826-0-036
INPUT P1dB (dBm)
160
Figure 21. Input P1dB vs. IF Frequency
Figure 18. Input P1dB vs. RF Frequency
INPUT P1dB (dBm)
120
80
Figure 20. Input P1dB vs. Temperature, FRF = 890 MHz, FLO = 1090 MHz
Rev. A | Page 10 of 20
Data Sheet
AD8344
25
INPUT IP3
95
12
90
85
CURRENT
80
15
75
70
10
65
NOISE FIGURE
10
INPUT P1dB (dBm)
SUPPLY CURRENT (mA)
20
8
6
4
2
04826-0-026
60
5
55
0
2.4
2.6
2.8
3.0
3.2
3.4
RBIAS (kΩ)
3.6
50
4.0
3.8
04826-0-025
NF AND IP3 (dBm)
14
100
0
–2
2.4
Figure 23. Noise Figure, Input IP3 and Supply Current vs. RBIAS, FRF1 = 890 MHz,
FRF2 = 891 MHz, FLO = 1090 MHz
2.6
2.8
3.0
3.2
3.4
RBIAS (kΩ)
3.6
3.8
4.0
Figure 26. Input P1dB vs. RBIAS, FRF = 890 MHz, FLO = 1090 MHz
14
11.0
10.5
13
890MHz
NOISE FIGURE SSB (dBm)
12
11
10
9
8
500
600
700
800
900
RF FREQUENCY (MHz)
1000
1100
8.5
8.0
7.5
6.5
6.0
70
1200
100
150
200
250
300
IF FREQUENCY (MHz)
350
400
Figure 27. Noise Figure vs. IF Frequency
13.5
100
13.0
95
VS = 4.75V
VS = 5.0V
VS = 5.25V
90
12.5
CURRENT (mA)
NOISE FIGURE SSB (dBm)
Figure 24. Noise Figure vs. RF Frequency
12.0
11.5
11.0
85
80
75
70
04826-0-029
10.5
10.0
–15
450MHz
–13
–11
–9
–7
–5
–3
LO POWER (dBm)
–1
1
3
5
Figure 25. Noise Figure vs. LO Power, FRF = 890 MHz, FLO = 1090 MHz
04826-0-021
6
400
9.0
04826-0-028
7
9.5
7.0
IF = 70
IF = 100
IF = 200
IF = 400
04826-0-027
NOISE FIGURE SSB (dBm)
10.0
65
60
–40 –30 –20 –10
0
10 20 30 40
TEMPERATURE (°C)
50
60
70
Figure 28. Total Supply Current vs. Temperature
Rev. A | Page 11 of 20
80
AD8344
Data Sheet
90
90
60
120
60
120
150
150
30
30
1.6GHz
400MHz
180
180
0
0
400MHz
300
270
Figure 32. LOIN Return Loss vs. LO Frequency
0
0
–5
–5
–10
–10
FEEDTHROUGH (dBc)
–15
–20
–25
–30
–15
–20
–25
–30
04826-0-053
–35
–40
500
600
900
1000
700
800
RF FREQUENCY (MHz)
1100
04826-0-054
FEEDTHROUGH (dBc)
300
270
Figure 29. RFIN Return Loss vs. RF Frequency
–45
400
330
240
04826-0-051
240
210
330
04826-0-052
1.2GHz
210
–35
–40
400
1200
Figure 30. RF to IF Feedthrough vs. RF Frequency,
FLO = 1090 MHz, RF Power = −10 dBm
600
800
1000
1200
LO FREQUENCY (MHz)
1400
1600
Figure 33. LO to IF Feedthrough vs. LO Frequency, LO Power = 0 dBm
0
14000
3.0
12000
2.5
10000
2.0
8000
1.5
6000
1.0
4000
0.5
–10
–30
–40
–50
CAPACITANCE (pF)
RESISTANCE (Ω)
LEAKAGE (dBc)
–20
–70
–80
400
600
800
1000
1200
LO FREQUENCY (MHz)
1400
2000
70
1600
Figure 31. LO to RF Leakage vs. LO Frequency, LO Power = 0 dBm
0
120
170
220
270
FREQUENCY (MHz)
320
370
Figure 34. IF Port Output Resistance and Capacitance vs. IF Frequency
Rev. A | Page 12 of 20
04826-0-030
04826-0-055
–60
Data Sheet
AD8344
CIRCUIT DESCRIPTION
The AD8344 also features a power-down function. Application
of a logic low at the PWDN pin allows normal operation. A high
logic level at the PWDN pin shuts down the AD8344. Power
consumption when the device is disabled is less than 10 mW.
The bias for the mixer is set with an external resistor from the
EXRB pin to ground. The value of this resistor directly affects
the dynamic range of the mixer. The external resistor must not
be lower than 2.4 kΩ. Permanent damage to the device occurs if
values below 2.4 kΩ are used.
VPMX
RFIN
RFCM
EXTERNAL
BIAS
RESISTOR
PWDN
BIAS
IFOP
SE
TO
DIFF
IFOM
LO
INPUT
VPLO
Figure 35. AD8344 Simplified Schematic
As shown in Figure 36, the IF output pins, IFOP and IFOM, are
directly connected to the open collectors of the NPN transistors
in the mixer core so the differential and single-ended impedances
looking into this port are relatively high, on the order of several
kΩ. A connection between the supply voltage and these output
pins is required for proper mixer core operation.
IFOP IFOM
LOIN
RFCM
RFIN
COMM
04826-0-003
The RF voltage to RF current conversion is done via an inductively
degenerated differential pair. When one side of the differential
pair is ac grounded, the other input can be driven single-ended.
The RF inputs can also be driven differentially. The voltage-tocurrent converter then drives the emitters of a four-transistor
switching core. This switching core is driven by an amplified
version of the local oscillator signal connected to the LO input.
There are three limiting gain stages between the external LO signal
and the switching core. The first stage converts the single-ended
LO drive to a well balanced differential drive. The differential
drive then passes through two more gain stages, which ensures
a limited signal drives the switching core. This affords the user a
lower LO drive requirement, while maintaining excellent distortion
and compression performance. The output signal of these three LO
gain stages drives the four transistors within the mixer core to
commutate at the rate of the local oscillator frequency. The output
of the mixer core is taken directly from these open collectors. The
open collector outputs present a high impedance at the IF frequency. The conversion gain of the mixer depends directly on the
impedance presented to these open collectors. In characterization,
a 200 Ω load was presented to the device via a 4:1 impedance
transformer.
VPDC
04826-0-003
The AD8344 is a down converting mixer optimized for operation
within the input frequency range of 400 MHz to 1.2 GHz. It has
a single-ended, 50 Ω RF input, as well as a single-ended, 50 Ω
local oscillator (LO) input. The IF outputs are differential open
collectors. The mixer current can be adjusted by the value of an
external resistor to optimize performance for gain compression
and intermodulation or for low power operation. Figure 35
shows the basic blocks of the mixer, which includes the LO
buffer, RF voltage-to-current converter, bias cell, and mixing
core.
Figure 36. Mixer Core Simplified Schematic
The AD8344 has three pins for the supply voltage: VPDC,
VPMX, and VPLO. These pins are separated to minimize or
eliminate possible parasitic coupling paths within the AD8344
that can cause spurious signals or reduced interport isolation.
Consequently, each of these pins are well bypassed and decoupled
as close to the AD8344 as possible.
Rev. A | Page 13 of 20
AD8344
Data Sheet
AC INTERFACES
The AD8344 is a high-side downconverter. It is designed to downconvert radio frequencies (RF) to lower intermediate frequencies
(IF) using a high-side local oscillator (LO). The LO is injected
into the mixer core at a frequency greater than the desired input
RF frequency. The difference between the LO and RF frequencies,
fLO − fRF, is the IF frequency, fIF. In addition to the desired RF signal,
an RF image is downconverted to the same IF frequency. The
image frequency is at fLO + fIF. The conversion gain of the AD8344
decreases with increasing input frequency. By choosing to use a
high-side LO the image frequency at fLO + fIF is translated with
less conversion gain than the desired RF signal at fLO − fIF. Additionally, any wideband noise present at the image frequency is
downconverted with less conversion gain than if a low-side LO
was applied. In general, use a high-side LO with the AD8344 to
ensure optimal noise performance and image rejection.
The AD8344 RFIN port presents a 50 Ω impedance relative to
RFCM. In order to ensure a good impedance match, the RFIN
ac-coupling capacitor must be large enough in value so that the
presented reactance is negligible at the intended RF frequency.
Additionally, the RFCM bypassing capacitor must be sufficiently
large to provide a low impedance return path to board ground.
Low inductance ceramic grade capacitors of no more than
330 pF are sufficient for most applications.
Similarly the LOIN port provides a 50 Ω load impedance with
common-mode decoupling on LOCM. Again, common grade
ceramic capacitors provide sufficient signal coupling and
bypassing of the LO interface.
60
120
150
30
10MHz
180
0
330
210
500MHz
240
300
270
04826-0-040
The AD8344 is designed to operate using RF frequencies in the
400 MHz to 1200 MHz frequency range, with high-side LO
injection within the 470 MHz to 1600 MHz range. It is essential
to ac-couple RF and LO ports to prevent dc offsets from skewing
the mixer core in an asymmetrical manner, potentially degrading
linear input swing and impacting distortion and input compression
characteristics.
90
Figure 37. IF Port Reflection Coefficient from 10 MHz to 500 MHz
IF PORT
The IF port uses an open collector differential output interface.
The NPN open collectors can be modeled as high impedance
current sources. The stray capacitance associated with the IC
package presents a slightly capacitive source impedance as in
Figure 37. In general, the IFOP and IFOM output ports can be
modeled as current sources with an impedance of ~10 kΩ in
parallel with ~1 pF of shunt capacitance. Circuit board traces
connecting the IF outputs to the load must be narrow and short
to prevent excessive capacitive loading. In order to maintain the
specified conversion gain of the mixer, the IF output ports must
be loaded into 200 Ω. It is not necessary to attempt to provide a
conjugate match to the IF port output source impedance. If the
IF signal needs to be delivered to a remote load, more than a
few centimeters away, it can be necessary to use an appropriate
buffer amplifier to present a real 200 Ω loading impedance at
the IF output interface. The buffer amplifier must have the
appropriate source impedance to match the characteristic
impedance of the selected transmission line. An example is
provided in Figure 38, where the AD8351 differential amplifier
is used to drive a pair of 75 Ω transmission lines. The gain of
the buffer can be independently set by choosing an appropriate
gain resistor, RG.
+VS
AD8344
+VS
COMM 8
RFC
IFOP 7
200Ω
RG
IFOM 6
+
AD8351
–
Tx LINE ZO = 75Ω
ZL
Tx LINE ZO = 75Ω
+VS
ZL = 200Ω
04826-0-041
RFC
COMM 5
Figure 38. AD8351 Used as Transmission Line Driver and Impedance Buffer
Rev. A | Page 14 of 20
Data Sheet
AD8344
The high input impedance of the AD8351 allows a shunt differential termination to provide the desired 200 Ω load to the
AD8344 IF output port.
+VS
AD8344
COMM 8
4:1
IFOP 7
IF OUT
ZO = 50Ω
IFOM 6
COMM 5
ZL = 200Ω
Figure 39. Biasing the IF Port Open Collector Outputs
Using a Center-Tapped Impedance Transformer
30
50MHz
REAL
CHOKES
180
0
50MHz
500MHz
IDEAL
CHOKES
330
210
500MHz
240
300
270
Figure 41. IF Port Loading Effects due to Finite-Q Pull-Up Inductors
(Murata BLM18HD601SN1D Chokes)
LO CONSIDERATIONS
The LO signal must have adequate phase noise characteristics and
reasonable low second harmonic content to prevent degradation of
the noise figure performance of the AD8344. A LO plagued with
poor phase noise can result in reciprocal mixing, a mechanism
that causes spectral spreading of the downconverted signal,
limiting the sensitivity of the mixer at frequencies close-in to any
large input signals. The internal LO buffer provides enough gain
to hard limit the input LO and provide fast switching of the mixer
core. Odd harmonic content present on the LO drive signal should
not impact mixer performance; however, even-order harmonics
cause the mixer core to commutate in an unbalanced manner,
potentially degrading noise performance. Simple, lumped element,
low-pass filtering can be applied to help reject the harmonic
content of a given local oscillator, as illustrated in Figure 42. The
filter depicted is a common 3-pole Chebyshev, designed to maintain a 1-to-1 source-to-load impedance ratio with no more than
0.5 dB of ripple in the pass band. Other filter structures can be
effective as long as the second harmonic of the LO is filtered to
negligible levels, e.g., ~30 dB below the fundamental. The
measured frequency response of the Chebyshev filter for a
1200 MHz −3 dB cutoff frequency is presented in Figure 43.
AD8344
+VS
LOCM LOIN COMM
AD8344
COMM 8
IF OUT+
IFOP 7
ZL = 200Ω
IFOM 6
IMPEDANCE
TRANSFORMING
NETWORK
C1
C3
IF OUT–
RFC
COMM 5
+VS
4
L2
LO
SOURCE
ZL
3
2
RS
RFC
RL
FOR RS = RL
1.864
C1 =
2πfcRL
L2 =
1.28RL
2πfc
C3 =
fC - FILTER CUTOFF FREQUENCY
Figure 40. Biasing the IF Port Open Collector Outputs
Using Pull-Up Choke Inductors
1.834
2πfcRL
04826-0-045
•
150
04826-0-043
•
Chris Bowick, RF Circuit Design, Newnes, Reprint Edition,
1997.
David M. Pozar, Microwave Engineering, Wiley Text Books,
Second Edition, 1997.
Guillermo Gonzalez, Microwave Transistor Amplifiers:
Analysis and Design, Prentice Hall, Second Edition, 1996.
04826-0-042
•
60
120
04826-0-044
It is necessary to bias the open collector outputs using one of
the schemes presented in Figure 39 and Figure 40. Figure 39
illustrates the application of a center-tapped impedance transformer. The turns ratio of the transformer must be selected to
provide the desired impedance transformation. In the case of a
50 Ω load impedance, use a 4-to-1 impedance ratio transformer
to transform the 50 Ω load into a 200 Ω differential load at the
IF output pins. Figure 40 illustrates a differential IF interface
where pull-up choke inductors are used to bias the open-collector
outputs. The shunting impedance of the choke inductors used
to couple dc current into the mixer core must be large enough
at the IF frequency of operation as to not load down the output
current before reaching the intended load. Additionally, the dc
current handling capability of the selected choke inductors must
be at least 45 mA. The self resonant frequency of the selected
choke must be higher than the intended IF frequency. A variety
of suitable choke inductors are commercially available from
manufacturers such as Murata and Coilcraft. An impedance
transforming network can be required to transform the final
load impedance to 200 Ω at the IF outputs. There are several
reference books that explain general impedance matching
procedures, including:
90
Figure 42. Using a Low-Pass Filter to Reduce LO Second Harmonic
Rev. A | Page 15 of 20
AD8344
Data Sheet
0
125
85
124
81
123
77
IDEAL LPF
–20
SFDR (dBc)
RESPONSE (dB)
–15
–25
–30
122
+VS
73
REAL LPF
RBIAS
–35
6.8nH
–40
–50
0.1
04826-0-046
–45
121
4.7pF
4.7pF
1
FREQUENCY (GHz)
12
69
9
10
11
VPDC PWDN EXRB COMM
120
2.4
10
Figure 43. Measured and Ideal LO Filter Frequency Response
AD8344
2.6
2.8
3.0
3.2
3.4
RBIAS (kΩ)
3.6
3.8
65
4.0
04826-0-047
–10
SUPPLY CURRENT (mA)
–5
Figure 44. Impact of RBIAS Resistor Selection vs. Spurious-Free
Dynamic Range and Power Consumption,
FRF = 890 MHz and FLO = 1090 MHz
BIAS RESISTOR SELECTION
An external bias resistor is used to set the dc current in the
mixer core. This provides the ability to reduce power consumption
at the expense of decreased dynamic range. Figure 44 shows the
spurious-free dynamic range (SFDR) of the mixer for a 1 Hz
noise bandwidth versus the RBIAS resistor value. SFDR was
calculated using NF and IIP3 data collected at 900 MHz.
By definition,
SFDR = 23 (IIP3 − NF − kT − 10log(B))
where IIP3 is the input third-order intercept in dBm. NF is the
noise figure in dB. kT is the thermal noise power density and is
−173.86 dBm/Hz at 298°K. B is the noise bandwidth in Hz.
In order to calculate the anticipated SFDR for a given application, it is necessary to factor in the actual noise bandwidth. For
instance, if the IF noise bandwidth is 5 MHz, the anticipated SFDR
using a 2.43 kΩ RBIAS is 6.66 log10 (5 MHz) less than the 1 Hz
data in Figure 44 or ~80 dBc. Using a 2.43 kΩ bias resistor sets
the quiescent power dissipation to ~415 mW for a 5 V supply. If
the RBIAS resistor value is raised to 3.9 kΩ, the SFDR for the same
5 MHz bandwidth is reduced to ~77.5 dBc and the power dissipation is reduced to ~335 mW. In low power portable applications,
it can be advantageous to reduce power consumption by using a
larger value of RBIAS, assuming reduced dynamic range performance is acceptable.
CONVERSION GAIN AND IF LOADING
The AD8344 is optimized for driving a 200 Ω differential load.
Although the device is capable of driving a wide variety of loads, in
order to maintain optimum distortion and noise performance,
it is advised that the presented load at the IF outputs is reasonably
close to 200 Ω. Figure 45 illustrates the effect of IF loading on
conversion gain. The mixer outputs behave like Norton equivalent
sources, where the conversion gain is the effective transconductance of the mixer multiplied by the loading impedance.
The linear differential voltage conversion gain of the mixer can
be modeled as
Av = −0.46 × RLOAD ×
gm
1 + j × g m × 37.70 × f RF
where RLOAD is the differential loading impedance. gm is the
mixer transconductance and is equal to 4070/RBIAS. fRF is the
frequency of the signal applied to the RF port in GHz.
Large impedance loads cause the conversion gain to increase,
resulting in a decrease in input linearity and allowable signal
swing. In order to maintain positive conversion gain and preserve
spurious-free dynamic range performance, the differential load
presented at the IF port must remain within a range of ~100 Ω
to 250 Ω.
Rev. A | Page 16 of 20
CONVERSION GAIN (dB)
20
15
10
MEASURED
5
–5
10
100
IF LOADING (Ω)
15
12
12
9
9
6
6
3
3
0
10
1000
Figure 45. Conversion Gain vs. IF Loading
15
20
25
30
35
IF FREQUENCY (MHz)
40
45
0
50
Figure 46. Conversion Gain, Input IP3, and P1dB vs.
IF Frequency, FRF = 450 MHz
The AD8344 can be used down to arbitrarily low IF frequencies.
The conversion gain, noise, and linearity characteristics remain
quite flat as IF frequency is reduced, as indicated in Figure 46
and Figure 47. Larger value pull-up inductors must be used at
the lower IF frequencies. A 1 µH choke inductor presents a
common-mode loading impedance of 63 Ω at an IF frequency
of 10 MHz, severely loading down the mixer outputs, reducing
conversion gain, and sacrificing output power. At low IF frequencies, use choke inductors of several hundred µH to bias the
IF outputs.
CONVERSION GAIN (dB)
LOW IF FREQUENCY OPERATION
8
28.0
7
24.5
6
21.0
5
17.5
4
14.0
3
10.5
2
10
15
20
25
30
35
IF FREQUENCY (MHz)
40
45
Figure 47. Conversion Gain, Input IP3, and P1dB vs.
IF Frequency, FRF = 890 MHz
Rev. A | Page 17 of 20
7.0
50
INPUT IP3 AND P1dB (dBm)
0
15
04826-0-050
MODELED
04826-0-048
20LOG–CONVERSION GAIN (dB)
25
INPUT IP3 AND P1dB (dBm)
AD8344
04826-0-049
Data Sheet
AD8344
Data Sheet
EVALUATION BOARD
An evaluation board is available for the AD8344. The
evaluation board is configured for single-ended signaling at the
IF output port via a balun transformer. The schematic for the
evaluation board is presented in Figure 48.
Table 5. Evaluation Board Configuration Options
Component
R1, R2, R7,
C2, C4, C5, C6,
C12, C13, C14,
C15
Function
Supply Decoupling.
Jumpers or power supply decoupling resistors and filter capacitors.
R3, R4
R6, C11
Jumpers in Single-Ended IF Output Circuit.
RBIAS resistor that sets the bias current for the mixer core.
The capacitor provides ac bypass for R6.
Jumper for pull down of the PWDN pin.
Jumper.
RF Input AC Coupling. Provides dc block for RF input.
RF Common AC Coupling. Provides dc block for RF input common connection.
LO Input AC Coupling. Provides dc block for the LO input.
LO Common AC Coupling. Provides dc block for LO input common connection.
Power Down. The device is on when the PWDN is connected to ground via SW1.
The device is disabled when PWDN is connected to the positive supply (VS) via SW1.
IF Output Balun Transformer. Converts differential, high impedance IF output to
single-ended. When loaded with 50 Ω, this balun presents a 200 Ω load to the
mixers collectors. The center tap of the primary is used to supply the bias voltage
(VS) to the IF output pins.
IF Output Interface—IFOP, IFOM. These positions can be used to modify the
impedance presented to the IF outputs.
R8
R9
C3
C1
C8
C7
SW1
T1
R11, Z3, Z4
R12, Z1, Z2
Rev. A | Page 18 of 20
Default Conditions
R1, R2, R7 = 0 Ω (Size 0603)
C4, C6, C13, C14 = 100 pF
(Size 0603)
C2, C5, C12, C15 = 0.1 µF
(Size 0603)
0 Ω (Size 0603)
R6 = 2.43 kΩ (Size 0603)
C11 = 100 pF (Size 0603)
R8 = 10 kΩ (Size 0603)
R9 = 0 Ω (Size 0603)
C3 = 100 pF (Size 0402)
C1 = 100 pF (Size 0402)
C8 = 100 pF (Size 0402)
C7 = 100 pF (Size 0402)
T1 = TC4-1W, 4:1 (Mini-Circuits)
R11 = 0 Ω (Size 0603)
Z3, Z4 = Open
R12 = 0 Ω (Size 0603)
Z1, Z2 = Open
Data Sheet
AD8344
POWER
DOWN
SW1
C11
100pF
COMMON
R8
10k
PWDN
VPDC
COMM
COMM
RFCM
IFOP
C1
100pF
C3
100pF
AD8344
RF INPUT
RFIN
R2
0
C5
0.1F
C6
100pF
R3
0
IF
OUTPUT
T1
TC4-1W
R4
0
Z4
OPEN
C7
100pF
COMM
LOIN
COMM
VPLO
C4
100pF
LOCM
VPMX
VPOS
Z2
OPEN
R11
0
Z3
OPEN
R1
0
C2
0.1F
IFOM
Z1
OPEN
R10
0
C14
100pF
C15
0.1F
C8
100pF
LO
INPUT
VPOS
04826-0-005
C13
100pF
EXRB
R9
0
VPOS
C12
0.1F
R6
2.43k
COMM
R7
0
Figure 49. Single-Ended Evaluation Board, Component Side Layout
04826-0-008
04826-0-007
Figure 48. Evaluation Board Schematic—Single-Ended IF Output
Figure 50. Single-Ended Evaluation Board, Component Side Silkscreen
Rev. A | Page 19 of 20
AD8344
Data Sheet
OUTLINE DIMENSIONS
PIN 1
INDICATOR
DETAIL A
(JEDEC 95)
0.30
0.25
0.20
0.50
BSC
13
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
16
12
1
1.65
1.50 SQ
1.45
EXPOSED
PAD
9
TOP VIEW
0.80
0.75
0.70
SIDE VIEW
PKG-004395
SEATING
PLANE
0.50
0.40
0.30
4
8
5
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.
02-06-2017-A
3.10
3.00 SQ
2.90
Figure 51. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-27)
Dimensions in millimeters
ORDERING GUIDE
Models 1, 2
AD8344ACPZ-REEL7
AD8344ACPZ-WP
AD8344-EVAL
1
2
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
Z = RoHS Compliant Part.
WP = Waffle pack.
©2004–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04826-0-4/18(A)
Rev. A | Page 20 of 20
Package Option
CP-16-27
CP-16-27
Marking Code
JHA
JHA
工商网监
湘ICP备2023018690号
