FEATURES
DC to >500 MHz operation
Differential ±1 V full-scale inputs
Differential ±4 mA full-scale output current
Low distortion (≤0.05% for 0 dBm input)
Supply voltages from ±4 V to ±9 V
Low power (280 mW typical at VS = ±5 V)
APPLICATIONS
High speed real time computation
Wideband modulation and gain control
Signal correlation and RF power measurement
Voltage controlled filters and oscillators
Linear keyers for high resolution television
Wideband true RMS
FUNCTIONAL BLOCK DIAGRAM
V TO I
AD834
X1 7
8.5mA
5
X2 8
DISTORTION
CANCELLATION
CURRENT
AMPLIFIER
(W)
DISTORTION
CANCELLATION
V TO I
W1
±4mA
FS
8.5mA
Y2 2
4
W2
Y1 1
00894-001
Data Sheet
500 MHz Four-Quadrant Multiplier
AD834
Figure 1.
GENERAL DESCRIPTION
The AD834 is a monolithic, laser-trimmed four-quadrant analog
multiplier intended for use in high frequency applications, with
a transconductance bandwidth (RL = 50 Ω) in excess of 500 MHz
from either of the differential voltage inputs. In multiplier
modes, the typical total full-scale error is 0.5%, dependent on
the application mode and the external circuitry. Performance
is relatively insensitive to temperature and supply variations due
to the use of stable biasing based on a band gap reference generator
and other design features.
To preserve the full bandwidth potential of the high speed bipolar
process used to fabricate the AD834, the outputs appear as a
differential pair of currents at open collectors. To provide a
single-ended ground referenced voltage output, some form of
external current-to-voltage conversion is needed. This may take
the form of a wideband transformer, balun, or active circuitry
such as an op amp. In some applications (such as power measurement), the subsequent signal processing may not need to have
high bandwidth.
The transfer function is accurately trimmed such that when
X = Y = ±1 V, the differential output is ±4 mA. This absolute
calibration allows the outputs of two or more AD834 devices
to be summed with precisely equal weighting, independent of
the accuracy of the load circuit.
The AD834J, available in 8-lead PDIP and plastic SOIC packages, is
specified over the commercial temperature range of 0°C to 70°C.
The AD834A is also available in 8-lead CERDIP and plastic SOIC
packages operating over the industrial temperature range of
−40°C to +85°C. The AD834SQ/883B, available in an 8-lead
CERDIP, operates over the military temperature range of −55°C
to +125°C. S-grade chips are also available.
Two application notes featuring the AD834 (AN-212 and AN-216)
can be found at www.analog.com. For additional applications
circuits, consult the AD811 data sheet.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
Combines high static accuracy (low input and output
offsets and accurate scale factor) with very high bandwidth.
As a four-quadrant multiplier or squarer, the response
extends from dc to an upper frequency limited by packaging
and external board layout considerations. Obtains a large
signal bandwidth of >500 MHz under optimum conditions.
Used in many high speed nonlinear operations, such as
square rooting, analog division, vector addition, and rmsto-dc conversion. In these modes, the bandwidth is limited
by the external active components.
Special design techniques result in low distortion levels
(better than −60 dB on either input) at high frequencies
and low signal feedthrough (typically −65 dB up to 20 MHz).
Exhibits low differential phase error over the input range—
typically 0.08° at 5 MHz and 0.8° at 50 MHz. The large
signal transient response is free from overshoot and has an
intrinsic rise time of 500 ps, typically settling to within 1%
in under 5 ns.
The nonloading, high impedance, differential inputs
simplify the application of the AD834.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.
AD834
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Test Circuits ........................................................................................8
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Explanation of Typical Performance Characteristics and Test
Circuits......................................................................................... 10
General Description ......................................................................... 1
Theory of Operation ...................................................................... 11
Product Highlights ....................................................................... 1
Transfer Function ....................................................................... 11
Revision History ............................................................................... 2
Biasing the Output ..................................................................... 12
Specifications..................................................................................... 3
Transformer Coupling ............................................................... 12
Absolute Maximum Ratings............................................................ 5
Wideband Multiplier Connections .......................................... 13
Thermal Characteristics .............................................................. 5
Power Measurement (Mean-Square and RMS) ......................... 14
Chip Dimensions and Bonding Diagram ................................. 5
Frequency Doubler .................................................................... 16
ESD Caution .................................................................................. 5
Wideband Three-Signal Multiplier/Divider ........................... 16
Pin Configuration and Function Descriptions ............................. 6
Outline Dimensions ....................................................................... 18
Typical Performance Characteristics ............................................. 7
Ordering Guide .......................................................................... 19
REVISION HISTORY
6/12—Rev. E to Rev. F
Changes to Figure 1 .......................................................................... 1
Change to Bias Current Parameter, Table 1 .................................. 3
Changes to Table 4 ............................................................................ 6
Changes to Ordering Guide .......................................................... 19
5/09—Rev. D to Rev E
Updated Format .................................................................. Universal
Deleted Temperature Range and Package Options Parameters,
Table 1 ................................................................................................ 4
Added Pin Configuration and Function Descriptions
Section ................................................................................................ 6
Added Figure 10, Renumbered Figures Sequentially .................. 9
Added Explanation of Typical Performance Characteristics and
Test Circuits Section....................................................................... 10
Changes to the Theory of Operation Section ............................. 11
Added Figure 13 and Figure 14 .................................................... 12
Changes to Wideband Multiplier Connections.......................... 13
Changes to Figure 18...................................................................... 13
Changes to Figure 20...................................................................... 15
Changes to Figure 21...................................................................... 16
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 18
4/02—Rev. C to Rev. D
Edits to Ordering Guide Model Nomenclature Corrected ..........3
Rev. F | Page 2 of 20
Data Sheet
AD834
SPECIFICATIONS
TA = 25°C and ±VS = ±5 V, unless otherwise noted; dBm assumes 50 Ω load. Specifications in boldface are tested on all production units
at final electrical test. Results from those tests are used to calculate outgoing quality levels.
Table 1.
Parameters
MULTIPLIER PERFORMANCE
Transfer Function
Total Error 1
vs. Temperature (AD834A/AD834S Only)
vs. Supplies (All Models) 2
Linearity 3
Bandwidth 4
Feedthrough, X
Feedthrough, Y
AC Feedthrough, X 5
AC Feedthrough, Y5
INPUTS (X1, X2, Y1, Y2)
Full-Scale Range
Clipping Level
Input Resistance
Offset Voltage
vs. Temperature
vs. Supplies2
Bias Current
Common-Mode Rejection
Nonlinearity, X
Nonlinearity, Y
Distortion, X
Distortion, Y
OUTPUTS (W1, W2)
Zero Signal Current
Differential Offset
vs. Temperature
All Models
AD834A/AD834S Only
Scaling Current
Output Compliance
Noise Spectral Density
Conditions
Min
Typ
W=
−1 V ≤ X, Y < +1 V
TMIN to TMAX
±4 V to ±6 V
Max
XY
(1 V )2 × 4 mA
±0.5
±1.5
0.1
±0.5
±2
±3
0.3
±1
0.2
0.1
0.3
0.2
500
X = ±1 V, Y = nulled
X = nulled, Y = ±1 V
X = 0 dBm, Y = nulled
f = 10 MHz
f = 100 MHz
X = nulled, Y = 0 dBm
f = 10 MHz
f = 100 MHz
Differential
Differential
Differential
±1.1
TMIN to TMAX
±4 V to ±6 V
dB
dB
–70
–50
dB
dB
±1
±1.3
25
0.5
10
V
V
kΩ
mV
μV/°C
mV
μV/V
µA
dB
% FS
% FS
dB
dB
40
Rev. F | Page 3 of 20
0.5
0.3
–65
–50
TMIN to TMAX
f = 10 Hz to 1 MHz
Outputs into 50 Ω Load
4
300
dB
dB
8.5
±20
3.96
4.75
3
−60
−44
Each output
X = 0, Y = 0
Differential
% FS
% FS
% FS/V
% FS
MHz
% FS
% FS
–65
–50
100
45
70
0.2
0.1
f ≤ 100 kHz; 1 V p-p
Y = 1 V; X = ±1 V
X = 1 V; Y = ±1 V
X = 0 dBm, Y = 1 V
f = 10 MHz
f = 100 MHz
X = 1 V, Y = 0 dBm
f = 10 MHz
f = 100 MHz
Unit
4
16
±60
±60
4.04
9
mA
μA
nA°C
μA
mA
V
nV/√Hz
AD834
Parameters
POWER SUPPLIES
Operating Range
Quiescent Current 6
+VS
–VS
Data Sheet
Conditions
Min
Typ
±4
Max
Unit
±9
V
14
35
mA
mA
TMIN to TMAX
11
28
Error is defined as the maximum deviation from the ideal output, and expressed as a percentage of the full-scale output. See Figure 16.
Both supplies taken simultaneously; sinusoidal input at f ≤10 kHz.
3
Linearity is defined as residual error after compensating for input offset voltage, output offset current, and scaling current errors.
4
Bandwidth is guaranteed when configured in squarer mode. See Figure 12.
5
Sine input; relative to full-scale output; zero input port nulled; represents feedthrough of the fundamental.
6
Negative supply current is equal to the sum of positive supply current, the signal currents into each output, W1 and W2, and the input bias currents.
1
2
Rev. F | Page 4 of 20
Data Sheet
AD834
ABSOLUTE MAXIMUM RATINGS
CHIP DIMENSIONS AND BONDING DIAGRAM
Y1
Y2
0°C to 70°C
−40°C to +85°C
−55°C to +125°C
−65°C to +150°C
−65°C to +125°C
300°C
500 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
–VS
θJA
110
165
99
2
7
3
X2
X1
0.054 (1.37)
6
4
+VS
5
NOTES
1. DIMENSIONS SHOWN IN INCHES AND (mm). CONTACT
FACTORY FOR LATEST DIMENSIONS.
Figure 2. Metallization Photograph
ESD CAUTION
Table 3.
θJA
110
165
99
8
W2
W1
0.054 (1.37)
THERMAL CHARACTERISTICS
Package
8-Lead CERDIP (Q)
8-Lead SOIC (R)
8-Lead PDIP (N)
1
ADI 1987 USA
Ratings
18 V
500 mW
+VS
A834PMD
Parameter
Supply Voltage (+VS to −VS)
Internal Power Dissipation
Input Voltages (X1, X2, Y1, Y2)
Operating Temperature Ranges
Commercial, AD834J Only
Industrial, AD834A Only
Military AD834S/883B Only
Storage Temperature Range (Q)
Storage Temperature Range (R, N)
Lead Temperature (Soldering, 60 sec)
ESD Rating
Unit
°C/W
°C/W
°C/W
Rev. F | Page 5 of 20
00894-003
Table 2.
AD834
Data Sheet
8
X2
Y2 2
AD834
7
X1
–VS 3
TOP VIEW
(Not to Scale)
6
+VS
5
W1
Y1 1
W2 4
00894-002
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
Y1
Y2
−VS
W2
W1
+VS
X1
X2
Description
Positive Y Input
Negative Y Input
Negative Power Supply
Open-Collector Output
Open-Collector Output
Positive Power Supply.
Positive X Input
Negative X Input
Rev. F | Page 6 of 20
Data Sheet
AD834
0
600
–10
400
200
100
80
60
40
20
10
1
10
100
FREQUENCY (MHz)
–20
–30
–40
–50
X FEEDTHROUGH
–60
Y FEEDTHROUGH
10
100
FREQUENCY (MHz)
00894-005
AC FEEDTHROUGH (dB)
–10
1
–40
X HARMONIC
DISTORTION
–50
–60
–70
Y HARMONIC
DISTORTION
1M
10M
100M
FREQUENCY (Hz)
Figure 6. Total Harmonic Distortion vs. Frequency
0
–80
–30
–80
1000
Figure 4. Mean-Square Output vs. Frequency
–70
–20
1000
Figure 5. AC Feedthrough vs. Frequency
Rev. F | Page 7 of 20
00894-006
TOTAL HARMONIC DISTORTION (dBc)
1000
800
00894-004
MEAN-SQUARE OUTPUT VOLTAGE (mV)
TYPICAL PERFORMANCE CHARACTERISTICS
1G
AD834
Data Sheet
TEST CIRCUITS
WAVETEK 2500A
SIGNAL GENERATOR
HP3362A
SIGNAL GENERATOR
LOW-PASS
FILTER
A
A/B
SWITCH
B
X
W1
AD834
Y
W2
CH1
CH2
HP54120A
DIGITIZING
MAINFRAME
HP54121A
SAMPLING
HEADS
HP330
COMPUTER
DATA PRECISION 8200
VOLTAGE CALIBRATOR
1024 POINT
FFT
00894-007
SUBTRACT
CH1 – CH2
Figure 7. Test Configuration for Measuring AC Feedthrough
and Total Harmonic Distortion
R4
75Ω
+5V
C1
0.1µF
SMA FROM
HP8656A
SIGNAL
GENERATOR
SMA TO
HP436A
POWER
METER
8
X2
7
6
5
X1 +VS W1
Y1
1
Y2 –VS
2
3
C3
560pF
C5
0.1µF
C4
560pF
C6
0.1µF
AD834
W2
4
R1
49.9Ω
TO
HP3456A
DVM
R2
49.9Ω
C2
0.1µF
R3
10Ω
DENOTES A SHORT DIRECT CONNECTION TO THE GROUND PLANE
Figure 8. Bandwidth Test Circuit
Rev. F | Page 8 of 20
–5V
00894-008
L1
1µH
Data Sheet
AD834
+15V
+5V
0.1µF
0.1µF
AD707
IW1
X
1kΩ
+
A1
0.1µF
8
X2
7
6
5
X1 +VS W1
Y1
1
Y2
2
AD834
–15V
–VS W2
3
4
+15V
1kΩ
1kΩ
0.1µF
Y
0.1µF
VOUT
AD707
IW2
–
A2
–5V
0.1µF
–15V
00894-009
1kΩ
NOTES
1. R1, R2 SHOULD BE PRECISION TYPE
RESISTOR (±0.1%).
2. ABSOLUTE VALUE ERRORS OF R1, R2
CAUSE A SMALL FACTOR ERROR.
3. R1, R2 MISMATCHES ARE EXPRESSED
AS LINEARITY ERRORS.
4. VOUT = IW1 R1 – UW2 R2
(IF R1 = R2, VOUT = >IW R1).
00894-109
Figure 9. Low Frequency Test Circuit
Figure 10. Example Layout for SOIC
Rev. F | Page 9 of 20
AD834
Data Sheet
EXPLANATION OF TYPICAL PERFORMANCE
CHARACTERISTICS AND TEST CIRCUITS
Figure 4 is a plot of the mean-square output vs. frequency for
the test circuit of Figure 8. Note that the rising response is due
to package resonances.
For frequencies above 1 MHz, ac feedthrough is dominated by
static nonlinearities in the transfer function and the finite offset
voltages. The offset voltages cause a small fraction of the fundamental to appear at the output, and can be nulled out (see
Figure 5).
THD data represented in Figure 6 is dominated by the second
harmonic, and is generated with 0 dBm input on the ac input
and 1 V on the dc input. For a given amplitude on the ac input,
THD is relatively insensitive to changes in the dc input amplitude. Varying the ac input amplitude while maintaining a
constant dc input amplitude affects THD performance.
The squarer configuration shown in Figure 8 is used to determine
wideband performance because it eliminates the need for (and
the response uncertainties of) a wideband measurement device
at the output. The wideband output of a squarer configuration
is a fluctuating current at twice the input frequency with a mean
value proportional to the square of the input amplitude.
By placing the capacitors, C3/C5 and C4/C6, across the load
resistors, R1 and R2, a simple low-pass filter is formed, and the
mean-square value is extracted. The mean-square response can
be measured using a DVM connected across R1 and R2.
Care should be taken when laying out the board. When using
the DIP package, mount the IC socket on a ground plane with a
clear area in the rectangle formed by the pins. This is important
because significant transformer action can arise if the pins pass
through individual holes in the board; improperly constructed test
jigs have caused oscillation at 1.3 GHz.
Rev. F | Page 10 of 20
Data Sheet
AD834
THEORY OF OPERATION
Figure 11 is a functional equivalent of the AD834. There are three
differential signal interfaces: the two voltage inputs (X = X1 −
X2 and Y = Y1 − Y2), and the current output (W) which flows
in the direction shown in Figure 11 when X and Y are positive.
The outputs (W1 and W2) each have a standing current of
typically 8.5 mA.
X2
X1
+VS
W1
8
7
6
5
AD834
V-I
8.5mA
X-DISTORTION
CANCELLATION
MULTIPLIER CORE
CURRENT
AMPLIFIER
(W)
Y-DISTORTION
CANCELLATION
±4mA
FS
8.5mA
V-I
voltage drop of about 150 mV. It is made large enough to reduce
the Q of the resonant circuit formed by the supply lead and the
decoupling capacitor. Slightly larger values can be used, particularly when using higher supply voltages. Alternatively, lossy RF
chokes or ferrite beads on the supply leads may be used.
For best performance, use termination resistors at the inputs, as
shown in Figure 12. Note that although the resistive component
of the input impedance is quite high (about 25 kΩ), the input
bias current of typically 45 μA can generate significant offset
voltages if not compensated. For example, with a source and
termination resistance of 50 Ω (net source of 25 Ω) the offset is
25 Ω × 45 μA = 1.125 mV. The offset can be almost fully cancelled
by including (in this example) another 25 Ω resistor in series with
the unused input. (In Figure 12, a 25 Ω resistor would be added
from X1 to GND and Y2 to GND.) To minimize crosstalk, ground
the input pins closest to the output (X1 and Y2); the effect is
merely to reverse the phase of the X input and thus alter the
polarity of the output.
+5V
3
4
Y1
Y2
–VS
W2
R3
62Ω
X-INPUT
±1V FS
Figure 11. Functional Block Diagram
The input voltages are first converted to differential currents
that drive the translinear core. The equivalent resistance of the
voltage-to-current (V-I) converters is about 285 Ω, which results
in low input related noise and drift. However, the low full-scale
input voltage results in relatively high nonlinearity in the V-I
converters. This is significantly reduced by the use of distortion
cancellation circuits, which operate by Kelvin sensing the voltages
generated in the core—an important feature of the AD834.
The current mode output of the core is amplified by a special
cascode stage that provides a current gain of nominally × 1.6,
trimmed during manufacturing to set up the full-scale output
current of ±4 mA. This output appears at a pair of open collectors that must be supplied with a voltage slightly above the
voltage on Pin 6. As shown in Figure 12, this can be arranged
by inserting a resistor in series with the supply to Pin 6 and
taking the load resistors to the full supply. With R3 = 60 Ω, the
voltage drop across it is about 600 mV. Using two 50Ω load
resistors, the full-scale differential output voltage is ±400 mV.
For best performance, the voltage on the output open-collectors
(Pin 4 and Pin 5) must be higher than the voltage on Pin 6 by
about 200 mV, as shown in Figure 12.
The full bandwidth potential of the AD834 can be realized only
when very careful attention is paid to grounding and decoupling.
The device must be mounted close to a high quality ground
plane and all lead lengths must be extremely short, in keeping
with UHF circuit layout practice. In fact, the AD834 shows
useful response to well beyond 1 GHz, and the actual upper
frequency in a typical application is usually determined by the
care with which the layout is affected. Note that R4 (in series
with the −VS supply) carries about 30 mA and thus introduces a
1µF
CERAMIC
TERMINATION
RESISTOR
8
X2
R1
49.9Ω
7
6
5
X1 +VS W1
AD834
Y1
1
Y2
2
–VS W2
3
4
W OUTPUT
±400mV FS
1µF
CERAMIC
TERMINATION
RESISTOR
Y-INPUT
±1V FS
R1
49.9Ω
R4
4.7Ω
–5V
Figure 12. Basic Connections for Wideband Operation
TRANSFER FUNCTION
The Output Current W is the linear product of input voltages (X
and Y) divided by (1 V)2 and multiplied by the scaling current of
4 mA:
W=
XY
(1 V )
2
4 mA
With the understanding that the inputs are specified in volts,
the following simplified expression can be used:
W = (XY)4 mA
Alternatively, the full transfer function can be written as
W=
XY
1
×
1 V 250 Ω
When both inputs are driven to their clipping level of about
1.3 V, the peak output current is roughly doubled to ±8 mA,
but distortion levels become very high.
Rev. F | Page 11 of 20
00894-011
2
00894-010
1
AD834
Data Sheet
BIASING THE OUTPUT
The current through RW is smaller for positive output swings.
The AD834 has two open collector outputs as shown in Figure 13.
The +VS pin, Pin 6, is tied to the base of the output NPN
transistors. The following general guidelines maximize
performance of the AD834.
HeadroomPOSITIVE SWING = (IPOS SUPPLY × RCC) − (4.5 mA × RW)
+5V
+5V
RW
49.9Ω
RW
49.9Ω
OUTPUT OF AD834
W1
TRANSFORMER COUPLING
RCC
75Ω
In many high frequency applications where baseband operation
is not required at either inputs or the output, transformer coupling
can be used. Figure 16 shows the use of a center-tapped output
transformer, which provides the necessary dc load condition
at the outputs, W1 and W2, and is designed to match into the
desired load impedance by appropriate choice of turns ratio.
The specific choice of the transformer design depends entirely
on the application. Transformers can also be used at the inputs.
Center-tapped transformers can reduce high frequency distortion
and lower HF feedthrough by driving the inputs with balanced
signals.
6
4
+VS
W2
+VS
AD834
MULTIPLIER
CORE
–VS
–5V
00894-113
BIAS
Figure 13. Output Stage Block Diagram
+5V
49.9Ω
SITUATION 1
12.5mA
NEGATIVE OUTPUT
VOTLAGE SWING
W BASE
+5V
RW
RCC
W COLLECTOR
+
HEADROOM
–
1µF
CERAMIC
IPOS SUPPLY
8.0mA TO 14mA
(GENERALLY 10.5mA)
+VS
X-INPUT
±1V FS
Y1
1
Figure 14 shows the currents at the input when the AD834
swings negative. Generally, +VS should be biased at +4 V or
higher. For best performance, use resistor values that do not
saturate the output transistors. Allowing for adequate transistor
headroom reduces distortion.
Y-INPUT
±1V FS
HeadroomNEGATIVE SWING = (IPOS SUPPLY × RCC) − (12.5 mA × RW)
Try to keep headroom at or above 200 mV to maintain adequate
range. Headroom ≥ 200 mV.
This recommendation addresses the positive swing of the
output as shown in Figure 15. It is sometimes difficult to meet
this for negative output swing.
RW
POSITIVE OUTPUT
VOTLAGE SWING
W BASE
W COLLECTOR
+
HEADROOM
–
RCC
IPOS SUPPLY
8.0mA TO 14mA
(GENERALLY 10.5mA)
+VS
1µF
CERAMIC
TERMINATION
RESISTOR
–5V
A particularly effective type of transformer is the balun 1, which
is a short length of transmission line wound onto a toroidal
ferrite core. Figure 17 shows this arrangement used to convert
the bal(anced) output to an un(balanced) one (therefore, the
use of the term). Although the symbol used is identical to that
for a transformer, the mode of operation is quite different. First,
the load should now be equal to the characteristic impedance of
the line (although this is usually not critical for short line lengths).
The collector load resistors, RW, can also be chosen to reverseterminate the line, but again this is only necessary when an
electrically long line is used. In most cases, RW is made as large
as the dc conditions allow to minimize power loss to the load.
The line can be a miniature coaxial cable or a twisted pair.
1
00894-115
4.5mA
LOAD
–VS W2
3
4
Figure 16. Transformer-Coupled Output
When either output swings negative, the maximum current
flows through the RW resistors. It is in this situation that
headroom is at a minimum.
+5V
Y2
2
4.7Ω
Headroom = Voltage at WCOLLECTOR − Voltage at WBASE
+5V
7
6
5
X1 +VS W1
AD834
Figure 14. Negative Swing
SITUATION 2
TERMINATION
RESISTOR
8
X2
00894-114
+5V
00894-012
5
+5V
For dc applications or applications where distortion is not a
concern, the headroom may be zero or as low as −200 mV.
However, for most cases, size the resistors to give the output
adequate headroom.
For a good treatment of baluns, see Transmission Line Transformers by Jerry
Sevick; American Radio Relay League publication.
Figure 15. Positive Output Swing
Rev. F | Page 12 of 20
Data Sheet
AD834
+5V
167Ω
1.5RW
8
X2
RW RW
49.9Ω
C
7
6
5
X1 +VS W1
OUTPUT
Y1
1
Y-INPUT
±1V FS
Y2
2
8
X2
Y1
1
RL
C
SEE
TEXT
Y
±1V
Y2
2
49.9Ω
–5V
49.9Ω
0.01µF
When operation down to dc and a ground based output are
necessary, the configuration shown in Figure 18 can be used.
The element values were chosen in this example to result in a
full-scale output of ±1 V at the load, so the overall multiplier
transfer function is
2.7Ω
LOAD
49.9Ω
3.01kΩ
10
8
OP AMP
3
1
7
4.7Ω
WIDEBAND MULTIPLIER CONNECTIONS
3.01kΩ
1µF
14
Figure 17. Using a Balun at the Output
Note that the upper bandwidth limit of the balun is determined
only by the quality of the transmission line; therefore, the upper
bandwidth of the balun usually exceeds that of the multiplier.
This is unlike a conventional transformer where the signal is
conveyed as a flux in a magnetic core and is limited by core
losses and leakage inductance. The lower limit on bandwidth is
determined by the series inductance of the line, taken as a
whole, and the load resistance (if the blocking capacitors, C, are
sufficiently large). In practice, a balun can provide excellent
differential-to-single-sided conversion over much wider
bandwidths than a transformer.
49.9Ω
261Ω
0.01µF
0.1µF
4.7Ω
–VS W2
3
4
49.9Ω
1µF
CERAMIC
TERMINATION
RESISTOR
261Ω
7
6
5
X1 +VS W1
AD834
BALUN
AD834
–VS W2
3
4
X
±1V
3.74kΩ
3.74kΩ
90.9Ω
1µF
2.7Ω
–5V
00894-014
1µF
CERAMIC
TERMINATION
RESISTOR
00894-013
X-INPUT
±1V FS
+5V
0.1µF
Figure 18. Sideband DC-Coupled Multiplier
Choose the op amp to support the desired output bandwidth.
The op amp originally used in Figure 18 was the AD5539,
providing an overall system bandwidth of 100 MHz. The
AD8009 should provide similar performance. Many other
choices are possible where lower post multiplication bandwidths are acceptable. The level shifting network places the
input nodes of the op amp to within a few hundred millivolts of
ground using the recommended balanced supplies. The output
offset can be nulled by including a 100 Ω trim pot between each
of the lower pair of resistors (3.74 kΩ) and the negative supply.
The pulse response for this circuit is shown in Figure 19; the
X input is a pulse of 0 V to 1 V and the Y input is 1 V dc. The
transition times at the output are about 4 ns.
W = (X1 − X2)(Y1 − Y2)
where the X1, X2, Y1, Y2 inputs and W output are in volts. The
polarity of the output can be reversed simply by reversing either
the X or Y input.
200mV
10ns
100
90
10
00894-015
0%
Figure 19. Pulse Response for the Circuit of Figure 18
Rev. F | Page 13 of 20
AD834
Data Sheet
POWER MEASUREMENT (MEAN-SQUARE AND RMS)
The AD834 is well-suited to measurement of average power in
high frequency applications, connected either as a multiplier for
the determination of the V × I product, or as a squarer for use
with a single input. In these applications, the multiplier is followed
by a low-pass filter to extract the long-term average value. Where
the bandwidth extends to several hundred megahertz, the first
pole of this filter should be formed by grounded capacitors
placed directly at the output pins, W1 and W2. This pole can
be at a few kilohertz. The effective multiplication or squaring
bandwidth is then limited solely by the AD834, because the active
circuitry that follows the multiplier is required to process only
low frequency signals. Using the device as a squarer, like the
circuit shown in Figure 8, the wideband output in response to a
sinusoidal stimulus is a raised cosine.
sin2 ωt = (1 − cos 2 ωt)/2
Recall that the full-scale output current (when full-scale input
voltages of 1 V are applied to both X and Y) is 4 mA. In a 50 Ω
system, a sinusoid power of +10 dBm has a peak value of 1 V.
Thus, at this drive level, the peak output voltage across the
differential 50 Ω load in the absence of the filter capacitors is
400 mV (that is, 4 mA × 50 Ω × 2), whereas the average value of
the raised cosine is only 200 mV. The averaging configuration is
useful in evaluating the bandwidth of the AD834, because a dc
voltage is easier to measure than a wideband differential output.
In fact, the squaring mode is an even more critical test than the
direct measurement of the bandwidth of either channel taken
independently (with a dc input on the nonsignal channel),
because the phase relationship between the two channels also
affects the average output. For example, a time delay difference
of only 250 ps between the X and Y channels results in zero
output when the input frequency is 1 GHz, at which frequency
the phase angle is 90 degrees and the intrinsic product is now
between a sine and cosine function, which has zero average value.
The physical construction of the circuitry around the IC is
critical to realizing the bandwidth potential of the device. The
input is supplied from an HP 8656A signal generator (100 kHz
to 990 MHz) via an SMA connector and terminated by an
HP 436A power meter using an HP 8482A sensor head
connected via a second SMA connector. Because neither the
generator nor the sensor provide a dc path to ground, a lossy
1 μH inductor, L1, formed by a 22-gauge wire passing through
a ferrite bead (Fair-Rite Type 2743001112) is included. This
provides adequate impedance down to about 30 MHz. The IC
socket is mounted on a ground plane with a clear area in the
rectangle formed by the pins. This is important because significant
transformer action can arise if the pins pass through individual
holes in the board; it can cause an oscillation at 1.3 GHz in
improperly constructed test jigs. The filter capacitors must be
connected directly to the same point on the ground plane via the
shortest possible leads. Parallel combinations of large and small
capacitors are used to minimize the impedance over the full
frequency range. Refer to Figure 4 for mean-square response for
the AD834 in a CERDIP package, using the configuration of
Figure 8.
To provide a square root response and thus generate the rms
value at the output, a second AD834, also connected as a
squarer, can be used, as shown in Figure 20. Note that an
attenuator is inserted both in the signal input and in the feedback path to the second AD834. This increases the maximum
input capability to +15 dBm and improves the response flatness
by damping some of the resonances. The overall gain is unity;
that is, the output voltage is exactly equal to the rms value of the
input signal. The offset potentiometer at the AD834 outputs
extends the dynamic range and is adjusted for a dc output of
125.7 mV when a 1 MHz sinusoidal input at −5 dBm is applied.
Additional filtering is provided; the time constants were chosen
to allow operation down to frequencies as low as 1 kHz and to
provide a critically damped envelope response, which settles
typically within 10 ms for a full-scale input (and proportionally
slower for smaller inputs). The 5 μF and 0.1 μF capacitors can
be scaled down to reduce response time if accurate rms operation at low frequencies is not required. The output op amp must
be specified to accept a common-mode input near its supply.
Note that the output polarity can be inverted by replacing the
NPN transistor with a PNP type.
Rev. F | Page 14 of 20
Data Sheet
AD834
49.9Ω
+5V
1µF
24.9Ω
75Ω
49.9Ω
8
X2
7
6
5
X1 +VS W1
Y1
1
Y2
2
100Ω
5µF
AD834
INPUT
–VS W2
3
4
0.1µF
5µF
100Ω
49.9Ω
1µF
24.91Ω
47.5kΩ
15kΩ
10kΩ
15kΩ
49.9kΩ
8
X2
10Ω
7
ADA4000-1 5
2 –
7
6
5
X1 +VS W1
2N3904
4
0.1µF
OUTPUT
AD834
Y1
1
Y2
2
–VS W2
3
4
10Ω
80Ω
3 +
80Ω
10Ω
49.9kΩ
–5V
Figure 20. Connections for Wideband RMS Measurement
Rev. F | Page 15 of 20
00894-016
49.9Ω
AD834
Data Sheet
FREQUENCY DOUBLER
WIDEBAND THREE-SIGNAL MULTIPLIER/DIVIDER
Figure 21 shows another squaring application. In this case, the
output filter has been removed and the wideband differential
output is converted to a single-sided signal using a balun, which
consists of a length of 50 Ω coaxial cable fed through a ferrite
core (Fair-Rite Type 2677006301). No attempt is made to reverse
terminate the output. Higher load power can be achieved by
replacing the 50 Ω load resistors with ferrite bead inductors.
The same precautions should be observed with regard to printed
circuit board (PCB) layout as recommended in the Power
Measurement (Mean-Square and RMS) section. The output
spectrum shown in Figure 22 is for an input power of +10 dBm
at a frequency of 200 MHz. The second harmonic component at
400 MHz has an output power of −15 dBm. Some feedthrough
of the fundamental occurs; it is 15 dB below the main output. A
spurious output at 600 MHz is also present, but it is 30 dB
below the main output. At an input frequency of 100 MHz,
the measured power level at 200 MHz is −16 dBm, while the
fundamental feedthrough is reduced to 25 dB below the main
output; at an output of 600 MHz the power is −11 dBm and the
third harmonic at 900 MHz is 32 dB below the main output.
Two AD834 devices and a wideband op amp can be connected
to make a versatile multiplier/divider having the transfer
function
0.1µF
SMA FROM
HP8656A
GENERATOR
25Ω
75Ω
+5V
125Ω
8
X2
SMA TO
HP8656A
SPECTRUM
ANALYZER
0.1µF
7
6
5
X1 +VS W1
49.9Ω
560pF
AD834
25Ω
Y2
2
–VS W2
3
4
49.9Ω
125Ω
560pF
BALUN
0.1µF
–5V
10Ω
0.1µF
00894-017
Y1
1
Figure 21. Frequency Doubler Connections
0
–10
–30
The op amp is internally compensated to be stable without the
use of any additional HF compensation. As Input U is reduced,
the bandwidth falls because the feedback around the op amp is
proportional to Input U. Note that, this circuit was originally
characterized using the AD840 op amp; some alternative op
amps include the AD818 and the AD8021.
This circuit can be modified in several ways. For example, if the
differential input feature is not needed, the unused input can be
connected to ground through a single resistor, equal to the parallel
sum of the resistors in the attenuator section. The full-scale input
levels on X, Y, and U can be adapted to any full-scale voltage
down to ±1 V by altering the attenuator ratios. Note, however,
that precautions must be taken if the attenuator ratio from the
output of A3 back to the second AD834 (A2) is lowered. First,
the HF compensation limit of the op amp may be exceeded if
the negative feedback factor is too high. Second, if the attenuated
output at the AD834 exceeds its clipping level of ±1.3 V, feedback
control is lost and the output suddenly jumps to the supply rails.
However, with these limitations understood, it is possible to adapt
the circuit to smaller full-scale inputs and/or outputs, for use
with lower supply voltages.
–40
–50
–60
–70
–80
–90
–100
150
200
250
300
350
400
450
500
550
600
(X1 − X2 )(Y1 − Y2 ) + Z
(U1 − U2)
with a denominator range of about 100:1. The denominator
input U = U1 − U2 must be positive and in the range 100 mV
to 10 V; X, Y, and Z inputs may have either polarity. Figure 23
shows a general configuration that may be simplified to suit a
particular application. This circuit accepts full-scale input voltages
of 10 V, and delivers a full-scale output voltage of 10 V. The optional
offset trim at the output of the AD834 improves the accuracy for
small denominator values. It is adjusted by nulling the output
voltage when the X and Y inputs are zero and U = 100 mV.
00894-018
OUTPUT POWER (dBm)
–20
W=
650
FREQUENCY (MHz)
Figure 22. Output Spectrum for Configuration of Figure 21
Rev. F | Page 16 of 20
Data Sheet
AD834
X1
75Ω
909Ω
100Ω
7.5V
+15V
0.1µF
100Ω
X2
909Ω
4.7Ω
8
X2
7
6
5
X1 +VS W1
Y1
Y2
1
2
AD834
Y1
909Ω
3
100Ω
4
100Ω
U1
100Ω
0.1µF
100Ω
Y2
0.1µF
–VS W2
20kΩ
5
909Ω
909Ω
4
100Ω
909Ω
(A3)
6
W
±10V
0.1µF
100Ω
U2
11
OP AMP 10
0.1µF
8
X2
7
6
5
X1 +VS W1
Y1
Y2
1
2
10kΩ
AD834
100Ω
–VS W2
3
4
4.7Ω
0.1µF
7.5V
100Ω
909Ω
Figure 23. Wideband Three-Signal Multiplier/Divider
Rev. F | Page 17 of 20
–15V
00894-019
Z
909Ω
AD834
Data Sheet
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
1
5
4
0.015
(0.38)
MIN
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.005 (0.13)
MIN
5
0.310 (7.87)
0.220 (5.59)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
1
0.060 (1.52)
MAX
0.210 (5.33)
MAX
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
8
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.100 (2.54)
BSC
0.055 (1.40)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
4
0.100 (2.54) BSC
0.320 (8.13)
0.290 (7.37)
0.405 (10.29) MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.430 (10.92)
MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
0.023 (0.58)
0.014 (0.36)
5.00 (0.1968)
4.80 (0.1890)
8
1
5
6.20 (0.2441)
5.80 (0.2284)
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
0.015 (0.38)
0.008 (0.20)
Figure 25. 8-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-8)
Dimensions shown in inches and (millimeters)
Figure 24. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-8)
Dimensions shown in inches and (millimeters)
4.00 (0.1574)
3.80 (0.1497)
15°
0°
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
070606-A
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
SEATING
PLANE
0.070 (1.78)
0.030 (0.76)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 26. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Rev. F | Page 18 of 20
012407-A
8
0.005 (0.13)
MIN
Data Sheet
AD834
ORDERING GUIDE
Model 1
AD834JNZ
AD834JRZ
AD834JRZ-RL
AD834JRZ-R7
AD834AR-REEL
AD834AR-REEL7
AD834ARZ
AD834ARZ-RL
AD834ARZ-R7
AD834AQ
AD834SQ/883B
1
Temperature Range
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−55°C to +125°C
Package Description
8-Lead PDIP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead CERDIP
8-Lead CERDIP
Z = RoHS Compliant Part.
Rev. F | Page 19 of 20
Package Option
N-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
Q-8
Q-8
AD834
Data Sheet
NOTES
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00894-0-6/12(F)
Rev. F | Page 20 of 20
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