LF to 2.5 GHz
TruPwr™ Detector
AD8361
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Calibrated rms response
Excellent temperature stability
Up to 30 dB input range at 2.5 GHz
700 mV rms, 10 dBm, re 50 Ω maximum input
±0.25 dB linear response up to 2.5 GHz
Single-supply operation: 2.7 V to 5.5 V
Low power: 3.3 mW at 3 V supply
Rapid power-down to less than 1 µA
VPOS
INTERNAL FILTER
i
χ2
TRANSCONDUCTANCE
CELLS
χ2
FLTR
AD8361
ERROR
AMP
i
× 7.5
BUFFER
ADD
OFFSET
BAND-GAP
REFERENCE
PWDN
VRMS
SREF
APPLICATIONS
COMM
Measurement of CDMA, W-CDMA, QAM, other complex
modulation waveforms
RF transmitter or receiver power measurement
IREF
01088-C-002
RFIN
Figure 2. 8-Lead MSOP
VPOS
RFIN
The AD8361 is a mean-responding power detector for use in
high frequency receiver and transmitter signal chains, up to
2.5 GHz. It is very easy to apply. It requires a single supply only
between 2.7 V and 5.5 V, a power supply decoupling capacitor,
and an input coupling capacitor in most applications. The
output is a linear-responding dc voltage with a conversion gain
of 7.5 V/V rms. An external filter capacitor can be added to
increase the averaging time constant.
TRANSCONDUCTANCE
CELLS
χ2
PWDN
2.4
2.2
INTERNAL
REFERENCE MODE
V rms (Volts)
2.0
1.8
1.4
GROUND
REFERENCE MODE
1.0
0.6
0.2
0.1
0.3
0.2
RFIN (V rms)
0.4
0.5
01088-C-001
0.4
0
Figure 1. Output in the Three Reference Modes, Supply 3 V, Frequency 1.9 GHz
(6-Lead SOT-23 Package Ground Reference Mode Only)
Rev. F
VRMS
BAND-GAP
REFERENCE
IREF
Figure 3. 6-Lead SOT-23
1.
2.
0.8
0.0
× 7.5
BUFFER
The AD8361 has three operating modes to accommodate a
variety of analog-to-digital converter requirements:
1.6
1.2
i
The AD8361 is intended for true power measurement of simple
and complex waveforms. The device is particularly useful for
measuring high crest-factor (high peak-to-rms ratio) signals,
such as CDMA and W-CDMA.
SUPPLY
REFERENCE MODE
2.6
AD8361
ERROR
AMP
COMM
3.0
2.8
FLTR
01088-C-003
GENERAL DESCRIPTION
INTERNAL FILTER
i
χ2
3.
Ground reference mode, in which the origin is zero.
Internal reference mode, which offsets the output 350 mV
above ground.
Supply reference mode, which offsets the output to VS/7.5.
The AD8361 is specified for operation from −40°C to +85°C
and is available in 8-lead MSOP and 6-lead SOT-23 packages. It
is fabricated on a proprietary high fT silicon bipolar process.
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Tel: 781.329.4700 ©1999–2015 Analog Devices, Inc. All rights reserved.
Technical Support
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AD8361
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................6
Applications ....................................................................................... 1
Circuit Description......................................................................... 11
General Description ......................................................................... 1
Application Information ................................................................ 12
Functional Block Diagrams ............................................................. 1
Output Reference Temperature Drift Compensation ........... 16
Revision History ............................................................................... 2
Evaluation Board ............................................................................ 19
Specifications..................................................................................... 3
Characterization Setups............................................................. 21
Absolute Maximum Ratings ............................................................ 4
Outline Dimensions ....................................................................... 22
ESD Caution .................................................................................. 4
Ordering Guide .......................................................................... 22
Pin Configuration and Function Descriptions ............................. 5
REVISION HISTORY
7/15—Rev. E to Rev. F
Change to Ordering Guide ............................................................ 22
5/15—Rev. D to Rev. E
Deleted Dynamic Range Extension for the AD8361 Section,
Figure 60, Renumbered Sequentially ........................................... 19
Deleted Figure 61, Figure 62, Figure 63, and Figure 64 ............ 20
8/04—Rev. B to Rev. C
Changed Trimpots to Trimmable Potentiometers ......... Universal
Changes to Specifications .................................................................3
Changed Using the AD8361 Section Title to Applications....... 12
Changes to Figure 43...................................................................... 14
Changes to Ordering Guide .......................................................... 24
Updated Outline Dimensions ....................................................... 24
3/14—Rev. C to Rev. D
Changes to Ordering Guide .......................................................... 24
Updated Outline Dimensions ....................................................... 24
Rev. F | Page 2 of 22
Data Sheet
AD8361
SPECIFICATIONS
TA = 25°C, VS = 3 V, fRF = 900 MHz, ground reference output mode, unless otherwise noted.
Table 1.
Parameter
SIGNAL INPUT INTERFACE
Frequency Range1
Linear Response Upper Limit
Input Impedance2
RMS CONVERSION
Conversion Gain
Dynamic Range
±0.25 dB Error4
±1 dB Error
±2 dB Error
Intercept-Induced Dynamic
Range Reduction5, 6
Deviation from CW Response
OUTPUT INTERCEPT5
Ground Reference Mode (GRM)
Internal Reference Mode (IRM)
Supply Reference Mode (SRM)
POWER-DOWN INTERFACE
PWDN HI Threshold
PWDN LO Threshold
Power-Up Response Time
PWDN Bias Current
POWER SUPPLIES
Operating Range
Quiescent Current
Power-Down Current
Condition
(Input RFIN)
Min
VS = 3 V
Equivalent dBm, re 50 Ω
VS = 5 V
Equivalent dBm, re 50 Ω
Typ
Max
Unit
2.5
GHz
mV rms
dBm
mV rms
dBm
Ω||pF
390
4.9
660
9.4
225||1
(Input RFIN to Output V rms)
7.5
fRF = 100 MHz, VS = 5 V
Error Referred to Best Fit Line3
CW Input, −40°C < TA < +85°C
CW Input, −40°C < TA < +85°C
CW Input, −40°C < TA < +85°C
CW Input, VS = 5 V, −40°C < TA < +85°C
Internal Reference Mode
Supply Reference Mode, VS = 3.0 V
Supply Reference Mode, VS = 5.0 V
5.5 dB Peak-to-Average Ratio (IS95 Reverse Link)
12 dB Peak-to-Average Ratio (W-CDMA 4 Channels)
18 dB Peak-to-Average Ratio (W-CDMA 15 Channels)
Inferred from Best Fit Line3
0 V at SREF, VS at IREF
fRF = 100 MHz, VS = 5 V
0 V at SREF, IREF Open
fRF = 100 MHz, VS = 5 V
3 V at IREF, 3 V at SREF
VS at IREF, VS at SREF
fRF = 100 MHz, VS = 5 V
6.5
14
23
26
30
1
1
1.5
0.2
1.0
1.2
+150
350
300
500
400
VS/7.5
590
VS − 0.5
−40°C < TA < +85°C
0 mV rms at RFIN, PWDN Input LO7
GRM or IRM, 0 mV rms at RFIN, PWDN Input HI
SRM, 0 mV rms at RFIN, PWDN Input HI
2.7
750
0.1
5
320
10 mA), the AD8051, which
also has rail-to- rail capability, can be used down to a supply
voltage of 3 V. It can deliver up to 45 mA of output current.
5V
100pF
0.01µF
0.01µF
VPOS
VOUT
AD8031
AD8361
15V/V rms
OUTPUT REFERENCE TEMPERATURE DRIFT
COMPENSATION
The error due to low temperature drift of the AD8361 can be
reduced if the temperature is known. Many systems incorporate
a temperature sensor; the output of the sensor is typically
digitized, facilitating a software correction. Using this information,
only a two-point calibration at ambient is required.
The output voltage of the AD8361 at ambient (25°C) can be
expressed by the equation
VOUT = (GAIN × VIN ) + ς ΟΣ
where GAIN is the conversion gain in V/V rms and VOS is the
extrapolated output voltage for an input level of 0 V. GAIN and
VOS (also referred to as intercept and output reference) can be
calculated at ambient using a simple two-point calibration by
measuring the output voltages for two specific input levels.
Calibration at roughly 35 mV rms (−16 dBm) and 250 mV rms
(+1 dBm) is recommended for maximum linear dynamic range.
However, alternative levels and ranges can be chosen to suit the
application. GAIN and VOS are then calculated using the
equations
COMM PWDN
GAIN =
01088-C-049
5kΩ
5kΩ
5V
100pF
10kΩ
VPOS
VOUT
0.01µF
5kΩ
5kΩ
AD8031
3.75V/V rms
01088-C-050
AD8361
COMM PWDN
Figure 50. Output Buffering Options, Slope of 3.75 V/V rms
5V
0.01µF
100pF
Both GAIN and VOS drift over temperature. However, the drift
of VOS has a bigger influence on the error relative to the output.
This can be seen by inserting data from Figure 18 and Figure 21
(intercept drift and conversion gain) into the equation for VOUT.
These plots are consistent with Figure 14 and Figure 15, which
show that the error due to temperature drift decreases with
increasing input level. This results from the offset error having a
diminishing influence with increasing level on the overall
measurement error.
From Figure 18, the average intercept drift is 0.43 mV/°C from
−40°C to +25°C and 0.17 mV/°C from +25°C to +85°C. For a
less rigorous compensation scheme, the average drift over the
complete temperature range can be calculated as
0.010 V − (− 0.028 V )
DRIFTVOS (V/°C ) =
= 0.000304 V/°C
+ 85°C − (− 40°C )
0.01µF
VPOS
VOUT
AD8031
7.5V/V rms
COMM PWDN
With the drift of VOS included, the equation for VOUT becomes
VOUT = (GAIN × VIN) + VOS + DRIFTVOS × (TEMP − 25°C)
01088-C-051
AD8361
VIN2 − VIN1
VOS = VOUT1 − (GAIN × VIN1 )
Figure 49. Output Buffering Options, Slope of 15 V/V rms
0.01µF
(VOUT2 − VOUT1 )
Figure 51. Output Buffering Options, Slope of 7.5 V/V rms
Rev. F | Page 16 of 22
Data Sheet
AD8361
Extended Frequency Characterization
The equation can be rewritten to yield a temperature
compensated value for VIN:
VIN =
(VOUT − VOS − DRIFTVOS × (TEMP − 25°C ))
GAIN
Figure 52 shows the output voltage and error (in dB) as a
function of input level for a typical device (note that output
voltage is plotted on a logarithmic scale). Figure 53 shows the
error in the calculated input level after the temperature
compensation algorithm has been applied. For a supply voltage
of 5 V, the part exhibits a worst-case linearity error over
temperature of approximately ±0.3 dB over a dynamic range of
35 dB.
10
2.5
2.0
1.5
+85°C
1.0
0
VOUT (V)
+25°C
0.5
–0.5
–40°C
–1.0
–1.5
–20
–15
–10
–5
PIN (dBm)
0.1
10
5
0
In order to characterize the AD8361 at frequencies greater than
2.5 GHz, a small collection of devices were tested. Dynamic
range, conversion gain, and output intercept were measured at
several frequencies over a temperature range of −30°C to
+80°C. Both CW and 64 QAM modulated input wave forms
were used in the characterization process in order to access
varying peak-to-average waveform performance.
The dynamic range of the device is calculated as the input
power range over which the device remains within a
permissible error margin to the ideal transfer function. Devices
were tested over frequency and temperature. After identifying
an acceptable error margin for a given application, the usable
dynamic measurement range can be identified using the plots in
Figure 54 through Figure 57. For instance, for a 1 dB error
margin and a modulated carrier at 3 GHz, the usable dynamic
range can be found by inspecting the 3 GHz plot of Figure 57.
Note that the −30°C curve crosses the −1 dB error limit at
−17 dBm. For a 5 V supply, the maximum input power should
not exceed 6 dBm in order to avoid compression. The resultant
usable dynamic range is therefore
Figure 52. Typical Output Voltage and Error vs.
Input Level, 800 MHz, VPOS = 5 V
6 dBm − (−17 dBm)
or 23 dBm over a temperature range of −30°C to +80°C.
2.0
2.0
1.0
+25°C
+85°C
+80°C
0.5
1.5
0
1.0
–0.5
0.5
+25°C
–40°C
–1.5
0
1
–0.5
VOUT (V)
ERROR (dB)
–30°C
–1.0
–1.0
–2.0
–1.5
–25
–20
–15
–10
–5
PIN (dBm)
0
5
10
01088-C-053
–2.5
–3.0
–30
10
2.5
1.5
–2.0
–2.5
–25
Figure 53. Error after Temperature Compensation of
Output Reference,800 MHz, VPOS = 5 V
0.1
–20
–15
–10
–5
0
5
10
PIN (dBm)
Figure 54. Transfer Function and Error Plots Measured at
1.5 GHz for a 64 QAM Modulated Signal
Rev. F | Page 17 of 22
01088-0-054
–2.5
–25
01088-C-052
–2.0
ERROR (dB)
ERROR (dB)
1.0
Although the AD8361 was originally intended as a power
measurement and control device for cellular wireless
applications, the AD8361 has useful performance at higher
frequencies. Typical applications may include MMDS, LMDS,
WLAN, and other noncellular activities.
AD8361
Data Sheet
2.5
10
2.5
2.0
10
2.0
+80°C
1.5
1.5
+25°C
1.0
1.0
CW
ERROR (dB)
0
–0.5
–1.0
–1.0
–1.5
–1.5
–2.0
–2.0
–2.5
–25
0.1
–20
–15
–10
–5
PIN (dBm)
0
5
10
64 QAM
0.1
–2.5
–25
–20
–15
–10
–5
PIN (dBm)
0
5
10
Figure 58. Error from CW Linear Reference vs. Input Drive Level for CW
and 64 QAM Modulated Signals at 3.0 GHz
Figure 55. Transfer Function and Error Plots Measured at
2.5 GHz for a 64 QAM Modulated Signal
10
2.5
1
VOUT (V)
1
01088-C-058
VOUT (V)
0
–0.5
0.5
01088-C-055
ERROR (dB)
–30°C
0.5
8.0
2.0
+80°C
7.5
CONVERSION GAIN (V/V rms)
1.5
+25°C
1.0
0
VOUT (V)
ERROR (dB)
–30°C
0.5
1
–0.5
–1.0
–1.5
7.0
6.5
6.0
5.5
0.1
–20
–15
0
–5
–10
PIN (dBm)
5
10
5.0
Figure 56. Transfer Function and Error Plots Measured at
2.7 GHz for a 64 QAM Modulated Signal
2.5
10
+80°C
+25°C
1.0
0
1
VOUT (V)
0.5
–1.0
–1.5
–2.0
–2.5
–25
0.1
–20
–15
–10
–5
PIN (dBm)
0
5
10
Figure 57. Transfer Function and Error Plots Measured at
3.0 GHz for a 64 QAM Modulated Signal
01088-C-057
ERROR (dB)
–30°C
–0.5
200
400
800 1200 1600 2200 2500 2700 3000
FREQUENCY (MHz)
Figure 59. Conversion Gain vs. Frequency for a
Typical Device, Supply 3 V, Ground Reference Mode
2.0
1.5
100
01088-C-059
–2.5
–25
01088-C-056
–2.0
The transfer functions and error for a CW input and a 64 QAM
input waveform is shown in Figure 58. The error curve is generated
from a linear reference based on the CW data. The increased
crest factor of the 64 QAM modulation results in a decrease in
output from the AD8361. This decrease in output is a result of
the limited bandwidth and compression of the internal gain stages.
This inaccuracy should be accounted for in systems where
varying crest factor signals need to be measured. The conversion
gain is defined as the slope of the output voltage vs. the input
rms voltage. An ideal best fit curve can be found for the measured
transfer function at a given supply voltage and temperature. The
slope of the ideal curve is identified as the conversion gain for a
particular device. The conversion gain relates the measurement
sensitivity of the AD8361 to the rms input voltage of the RF
waveform. The conversion gain was measured for a number of
devices over a temperature range of −30°C to +80°C. The
conversion gain for a typical device is shown in Figure 59.
Although the conversion gain tends to decrease with increasing
frequency, the AD8361 provides measurement capability at
frequencies greater than 2.5 GHz. However, it is necessary to
calibrate for a given application to accommodate for the change
in conversion gain at higher frequencies.
Rev. F | Page 18 of 22
Data Sheet
AD8361
EVALUATION BOARD
Figure 60 and Figure 63 show the schematic of the AD8361
evaluation board. Note that uninstalled components are drawn
in as dashed. The layout and silkscreen of the component side
are shown in Figure 61, Figure 62, Figure 64, and Figure 65. The
board is powered by a single supply in the 2.7 V to 5.5 V range.
The power supply is decoupled by 100 pF and 0.01 µF
capacitors. Additional decoupling, in the form of a series
resistor or inductor in R6, can also be added. Table 8 details the
various configuration options of the evaluation board.
Table 8. Evaluation Board Configuration Options
Component
TP1, TP2
SW1
SW2/SW3
C1, R2
C2, C3, R6
C5
C4, R5
Function
Ground and Supply Vector Pins.
Device Enable. When in Position A, the PWDN pin is connected to +VS and the AD8361 is in powerdown mode. In Position B, the PWDN pin is grounded, putting the device in operating mode.
Operating Mode. Selects either ground reference mode, internal reference mode or supply
reference mode. See Table 4 for more details.
Input Coupling. The 75 Ω resistor in Position R2 combines with the AD8361’s internal input
impedance to give a broadband input impedance of around 50 Ω. For more precise matching
at a particular frequency, R2 can be replaced by a different value (see Input Coupling and
Matching and Figure 43 through Figure 46).
Capacitor C1 ac couples the input signal and creates a high-pass input filter whose corner
frequency is equal to approximately 8 MHz. C1 can be increased for operation at lower
frequencies. If resistive attenuation is desired at the input, series resistor R1, which is
nominally 0 Ω, can be replaced by an appropriate value.
Power Supply Decoupling. The nominal supply decoupling of 0.01 µF and 100 pF. A series
inductor or small resistor can be placed in R6 for additional decoupling.
Filter Capacitor. The internal 50 pF averaging capacitor can be augmented by placing a
capacitance in C5.
Output Loading. Resistors and capacitors can be placed in C4 and R5 to load test V rms.
Rev. F | Page 19 of 22
Default Condition
Not Applicable
SW1 = B
SW2 = A, SW3 = B
(Ground Reference Mode)
R2 = 75 Ω (Size 0402)
C1 = 100 pF (Size 0402)
C2 = 0.01 µF (Size 0402)
C3 = 100 pF (Size 0402)
R6 = 0 Ω (Size 0402)
C5 = 1 nF (Size 0603)
C4 = R5 = Open (Size 0603)
AD8361
Data Sheet
VPOS
C3
100pF
VS
A
VS
C3
100pF
SW3
AD8361
SW2
B
C1
100pF
RFIN
1
VPOS
SREF 8
2
IREF
VRMS 7
C5
3
VPOS
RFIN
VPOS
FLTR 6
PWDN
R5
B
(OPEN)
(OPEN)
1
VRMS
VPOS
6
2
COMM
RFIN
5
3
FLTR
PWDN
4
R5
C4
(OPEN)
(OPEN)
TP2 VPOS
J1
R4
0Ω
Vrms
C1
100pF
R2
75Ω
C5
1nF
TP1
COMM 5
3
1
J3
SW1
TP1
A
SW1
2
R7
50Ω
Figure 63. Evaluation Board Schematic, SOT-23
Figure 60. Evaluation Board Schematic, MSOP
01088-C-069
01088-C-066
Figure 61. Layout of Component Side, MSOP
Figure 64. Layout of the Component Side, SOT-23
01088-C-067
B
AD8361
C4
1nF
4
R4
0Ω
A
01088-C-065
R2
75Ω
J2
Figure 62. Silkscreen of Component Side, MSOP
Figure 65. Silkscreen of the Component Side, SOT-23
Rev. F | Page 20 of 22
01088-C-068
C2
0.01µF
R6
0Ω
C2
0.01µF
01088-C-070
TP2
Data Sheet
AD8361
Problems caused by impedance mismatch may arise using the
evaluation board to examine the AD8361 performance. One
way to reduce these problems is to put a coaxial 3 dB attenuator
on the RFIN SMA connector. Mismatches at the source, cable,
and cable interconnection, as well as those occurring on the
evaluation board, can cause these problems.
A simple (and common) example of such a problem is triple
travel due to mismatch at both the source and the evaluation
board. Here the signal from the source reaches the evaluation
board and mismatch causes a reflection. When that reflection
reaches the source mismatch, it causes a new reflection, which
travels back to the evaluation board, adding to the original
signal incident at the board. The resultant voltage varies with
both cable length and frequency dependence on the relative
phase of the initial and reflected signals. Placing the 3 dB pad at
the input of the board improves the match at the board and thus
reduces the sensitivity to mismatches at the source. When such
precautions are taken, measurements are less sensitive to cable
length and other fixture issues. In an actual application when
the distance between AD8361 and source is short and well
defined, this 3 dB attenuator is not needed.
Analysis
The conversion gain and output reference are derived using the
coefficients of a linear regression performed on data collected
in its central operating range (35 mV rms to 250 mV rms). This
range was chosen to avoid areas of operation where offset
distorts the linear response. Error is stated in two forms error
from linear response to CW waveform and output delta from
2°C performance.
The error from linear response to CW waveform is the
difference in output from the ideal output defined by the
conversion gain and output reference. This is a measure of both
the linearity of the device response to both CW and modulated
waveforms. The error in dB uses the conversion gain multiplied
by the input as its reference. Error from linear response to CW
waveform is not a measure of absolute accuracy, since it is
calculated using the gain and output reference of each device.
However, it does show the linearity and effect of modulation on
the device response. Error from 25°C performance uses the
performance of a given device and waveform type as the
reference; it is predominantly a measure of output variation
with temperature.
CHARACTERIZATION SETUPS
C4
0.1F
Equipment
C2
100pF
AD8361
VPOS
1
VPOS
SREF 8
IREF
2
IREF
VRMS 7
SREF
VRMS
C3
RFIN
R1
75
C1
0.1F
FLTR 6
3
RFIN
4
PWDN
01088-C-071
The primary characterization setup is shown in Figure 67. The
signal source used was a Rohde & Schwarz SMIQ03B, version
3.90HX. The modulated waveforms used for IS95 reverse link,
IS95 nine active channels forward (forward link 18 setting),
and W-CDMA 4-channel and 15-channel were generated using
the default settings coding and filtering. Signal levels were
calibrated into a 50 Ω impedance.
COMM 5
PWDN
Figure 66. Characterization Board
AD8361
CHARACTERIZATION
BOARD
SMIQ038B
RF SOURCE
DC OUTPUT
RF SIGNAL
VRMS
RFIN
3dB
ATTENUATOR
PRUP
+VS
SREF
IREF
DC SOURCES
PC CONTROLLER
DC MATRIX / DC SUPPLIES / DMM
Figure 67. Characterization Setup
Rev. F | Page 21 of 22
01088-C-072
IEEE BUS
AD8361
Data Sheet
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
3.20
3.00
2.80
5.15
4.90
4.65
5
1
4
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.23
0.09
6°
0°
0.40
0.25
10-07-2009-B
0.15
0.05
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 68. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
3.00
2.90
2.80
1.70
1.60
1.50
6
5
4
1
2
3
3.00
2.80
2.60
PIN 1
INDICATOR
0.95 BSC
1.90
BSC
1.45 MAX
0.95 MIN
0.15 MAX
0.05 MIN
0.50 MAX
0.30 MIN
0.20 MAX
0.08 MIN
SEATING
PLANE
10°
4°
0°
0.60
BSC
COMPLIANT TO JEDEC STANDARDS MO-178-AB
0.55
0.45
0.35
12-16-2008-A
1.30
1.15
0.90
Figure 69. 6-Lead Small Outline Transistor Package [SOT-23]
(RJ-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD8361ARM
AD8361ARM-REEL7
AD8361ARMZ
AD8361ARMZ-REEL
AD8361ARMZ-REEL7
AD8361ARTZ-RL7
AD8361-EVALZ
AD8361ART-EVAL
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
8-Lead MSOP, Tube
8-Lead MSOP, 7" Tape and Reel
8-Lead MSOP, Tube
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
6-Lead SOT-23, 7" Tape and Reel
Evaluation Board MSOP
Evaluation Board SOT-23-6L
Z = RoHS Compliant Part.
©1999–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01088–0–7/15(F)
Rev. F | Page 22 of 22
Package Option
RM-8
RM-8
RM-8
RM-8
RM-8
RJ-6
Branding
J3A
J3A
J3A
J3A
J3A
J3A
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