AD8366

Preliminary Technical Data FEATURES Matched Pair of Differential Digitally-Controlled VGAs Gain Range: 4.5 dB to 20.5 dB Step 0.25 dB Operating frequency DC to 500MHz 800MHz 3-dB bandwidth NF 10.5 dB @ max. gain, 18dB @ min. gain at 10MHz OIP3 36dBVrms at 10MHz HD2, HD3 > 88dBc for 2Vpp output at 10MHz at max gain Differential Input and Output Adjustable output common-mode Optional DC output offset correction Serial/Parallel Port Programmable Power-down Feature Single 5V Supply Operation DC to 500 MHz, Dual Digital Gain Trim Amplifier AD8366 FUNCTIONAL BLOCK DIAGRAM Ch. A Data Enable Ch. B Data Enable AD8366 IAN DC OFFSET CANCELLATION OAN IAP VCMA OAP VCMB IBP DC OFFSET CANCELLATION OBP APPLICATIONS Baseband I/Q receivers Diversity receivers ADC drivers W-CDMA/CDMA/CDMA2000/GSM Point-to-(Multi)Point Radio CATV Wireless local loop WiMax IBN OBN CHANNEL GAIN CONTROL B0 B1 B2 B3 B4 B5 Serial / Parallel Figure 1. Functional Block Diagram GENERAL DESCRIPTION The AD8366 is a matched pair of fully differential low-noise and low-distortion digitally programmable variable gain amplifiers. The gain of each amplifier can be programmed separately or simultaneously over a range of 5 dB to 21 dB in steps of 0.25 dB. The amplifier offers flat frequency performance and group delay from DC out to 150 MHz, independent of gain code. The AD8366 offers excellent spurious-free dynamic range, suitable for driving 12-bit ADCs. The NF at max gain is 10.5 dB at 10 MHz and increases 2dB for every 4dB decrease in gain. Over the entire gain range, the HD3 and HD2 are >88dBc for 2 V p-p at the output at 10 MHz into 500 Ω. The 2-tone intermodulation distortion of -90dBc into 200 Ω translates to an OIP3 of 43 dBm. The differential input impedance is 200 Ω to provide a well-defined termination. The differential output is voltage-mode with a low impedance of 30 Ω. Rev. PrC Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. The output common-mode defaults to Vps/2 but can be programmed via pins VCMA and VCMB over a range of voltages. The built-in DC-offset compensation loop can be disabled if DC-coupled operation is desired. The high-pass corner is defined by external capacitors on pins OFSA and OFSB. The input common mode also defaults to Vps/2 but can be driven from 1.2V to 3.4V. The digital interface allows for parallel or serial gain programming. The AD8366 operates off a 4.5V to 5.5V supply and consumes a supply current of 175mA. When disabled, it consumes ~ 4mA. The AD8366 is fabricated using Analog Devices’ advanced Silicon-Germanium bipolar process and is available in a 32-lead exposed paddle LFCSP package. Performance is specified over a -40oC to +85oC temperature range. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. AD8366 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Preliminary Technical Data ESD Caution...................................................................................5 Pin Configuration and Function Descriptions..............................6 Typical Performance Characteristics ..............................................7 APPLICATIONS SCHEMATIC......................................................8 Parallel and SERIAL Interface timing.............................................9 Outline Dimensions ....................................................................... 13 REVISION HISTORY 10/07—Revision PrA: Initial Version 02/08—Revision PrB: Updated Performance Specifications 06/08—Revision PrC: Evaluation Board Section Rev. PrC | Page 2 of 13 Preliminary Technical Data SPECIFICATIONS VS. = 5 V, TA = 25°C, Zs = 200 Ω, ZL = 200 Ω, f = 10 MHz, unless otherwise noted Table 1. Parameter DYNAMIC PERFORMANCE Bandwidth Slew Rate INPUT STAGE Maximum Input Swing Differential Input Impedance Input Common Mode Range GAIN Voltage Gain Range Gain Step Size 0.1dB Gain Flatness Mismatch Group Delay Flatness Mismatch Gain Step Response Common-mode Rejection Ratio OUTPUT STAGE Maximum Output Swing Differential Output Impedance Output DC offset Output Common Mode Range Common-Mode Setpoint Input Impedance NOISE/DISTORTION 10 MHz Noise Figure 2nd Harmonic 3rd Harmonic OIP3 Output 1 dB Compression Point 50 MHz Noise Figure 2nd Harmonic 3rd Harmonic Conditions 3dB; all gain codes 1dB; all gain codes Max. Gain Min. Gain IPPA, IPMA, IPPB, IPMB At minimum gain Av=4.5dB 1Vp-p Input Input pins left floating TBD Vps/2 4.5 All gain codes Max. Gain Channels A and B at same gain code All gain codes, 20% frac. bandwidth, fc