AD8367

500 MHz, Linear-in-dB VGA with AGC Detector AD8367 FEATURES Broad-range analog variable gain: −2.5 dB to +42.5 dB 3 dB cutoff frequency of 500 MHz Gain up and gain down modes Linear-in-dB, scaled 20 mV/dB Resistive ground referenced input Nominal ZIN = 200 Ω On-chip, square-law detector Single-supply operation: 2.7 V to 5.5 V FUNCTIONAL BLOCK DIAGRAM VPSI 12 VPSO 11 ENBL 2 14 ICOM ICOM 1 INPT 3 AD8367 9-STAGE ATTENUATOR BY 5dB BIAS 9 DECL 13 HPFL gm CELLS SQUARE LAW DETECTOR 10 VOUT GAUSSIAN INTERPOLATOR ICOM 7 8 4 5 6 OCOM 02710-001 APPLICATIONS Cellular base stations Broadband access Power amplifier control loops Complete, linear IF AGC amplifiers High speed data I/O MODE GAIN DETO Figure 1. GENERAL DESCRIPTION The AD8367 is a high performance 45 dB variable gain amplifier with linear-in-dB gain control for use from low frequencies up to several hundred megahertz. The range, flatness, and accuracy of the gain response are achieved using Analog Devices’ X-AMP® architecture, the most recent in a series of powerful proprietary concepts for variable gain applications, which far surpasses what can be achieved using competing techniques. The input is applied to a 9-stage, 200 Ω resistive ladder network. Each stage has 5 dB of loss, giving a total attenuation of 45 dB. At maximum gain, the first tap is selected; at progressively lower gains, the tap moves smoothly and continuously toward higher attenuation values. The attenuator is followed by a 42.5 dB fixed gain feedback amplifier—essentially an operational amplifier with a gain bandwidth product of 100 GHz—and is very linear, even at high frequencies. The output third order intercept is +20 dBV at 100 MHz (+27 dBm, re 200 Ω), measured at an output level of 1 V p-p with VS = 5 V. The analog gain-control input is scaled at 20 mV/dB and runs from 50 mV to 950 mV. This corresponds to a gain of −2.5 dB to +42.5 dB, respectively, when the gain up mode is selected and +42.5 dB to −2.5 dB, respectively, when gain down mode is selected. The gain down, or inverse, mode must be selected when operating in AGC in which an integrated square-law detector with an internal setpoint is used to level the output to 354 mV rms, regardless of the crest factor of the output signal. A single external capacitor sets up the loop averaging time. The AD8367 can be powered on or off by a voltage applied to the ENBL pin. When this voltage is at a logic LO, the total power dissipation drops to the milliwatt range. For a logic HI, the chip powers up rapidly to its normal quiescent current of 26 mA at 25°C. The AD8367 is available in a 14-lead TSSOP package for the industrial temperature range of −40°C to +85°C. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. AD8367 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ...................................................................... 11 Input Attenuator and Gain Control ......................................... 11 Input and Output Interfaces...................................................... 11 Power and Voltage Metrics........................................................ 12 Noise and Distortion.................................................................. 12 Output Centering ....................................................................... 12 RMS Detection ........................................................................... 13 Applications..................................................................................... 14 Input and Output Matching...................................................... 14 VGA Operation .......................................................................... 15 Modulated Gain Mode .............................................................. 15 AGC Operation .......................................................................... 15 Modifying the AGC Setpoint.................................................... 16 Evaluation Board ........................................................................ 19 Characterization Setup and Methods ...................................... 20 Outline Dimensions ....................................................................... 21 Ordering Guide .......................................................................... 21 REVISION HISTORY 7/05—Rev. 0 to Rev. A Changes to Format .............................................................Universal Changes to General Description .................................................... 1 Changes to Table 1............................................................................ 3 Changes to Table 3............................................................................ 6 Changes to Figure 8.......................................................................... 7 Changes to Figure 9, Figure 12, and Figure 14 ............................. 8 Changes to Input and Output Interfaces Section ....................... 11 Changes to Output Centering Section and Figure 31................ 12 Changes to RMS Detection Section ............................................. 13 Changes to Figure 32, Table 4, and Table 5 ................................. 14 Changes to Figure 33, Figure 34, and AGC Operation Section................................................................. 15 Changes to the Modifying the AGC Set Point Section.............. 16 Changes to Figure 38...................................................................... 17 Changes to Figure 42...................................................................... 19 Changes to Table 7.......................................................................... 20 Moved Table 7 to Page ................................................................... 20 Moved Characterization Setup and Methods Section to Page . 20 Moved Figure 45 to Page ............................................................... 20 Changes to Ordering Guide .......................................................... 21 Updated Outline Dimensions ....................................................... 21 10/01—Revision 0: Initial Version Rev. A | Page 2 of 24 AD8367 SPECIFICATIONS VS = 5 V, TA = 25°C, system impedance ZO = 200 Ω, VMODE = 5 V, f = 10 MHz, unless otherwise noted. Table 1. Parameter OVERALL FUNCTION Frequency Range GAIN Range INPUT STAGE Maximum Input Input Resistance GAIN CONTROL INTERFACE Scaling Factor Gain Law Conformance Maximum Gain Minimum Gain VGAIN Step Response Small Signal Bandwidth OUTPUT STAGE Maximum Output Voltage Swing Output Source Resistance Output Centering Voltage 1 SQUARE LAW DETECTOR Output Set Point AGC Small Signal Response Time POWER INTERFACE Supply Voltage Total Supply Current Disable Current vs. Temperature MODE CONTROL INTERFACE Mode LO Threshold Mode HI Threshold ENABLE INTERFACE Enable Threshold Enable Response Time Enable Input Bias Current f = 70 MHz Gain Gain Scaling Factor Gain Intercept Noise Figure Output IP3 Output 1 dB Compression Point Conditions Min LF 45 Pins INPT and ICOM To avoid input overload From INPT to ICOM Pin GAIN VMODE = 5 V, 50 mV ≤ VGAIN ≤ 950 mV VMODE = 0 V, 50 mV ≤ VGAIN ≤ 950 mV 100 mV ≤ VGAIN ≤ 900 mV VGAIN = 0.95 V VGAIN = 0.05 V From 0 dB to 30 dB From 30 dB to 0 dB VGAIN = 0.5 V Pin VOUT RL = 1 kΩ RL = 200 Ω Series resistance of output buffer Pin DETO CAGC = 100 pF, 6 dB gain step Pins VPSI, VPSO, ICOM, and OCOM 2.7 ENBL high, maximum gain, RL = 200 Ω (includes load current) ENBL low −40°C ≤ TA ≤ +85°C Pin MODE Device in negative slope mode of operation Device in positive slope mode of operation Pin ENBL Time delay following LO to HI transition until device meets full specifications. ENBL at 5 V ENBL at 0 V Maximum gain Minimum gain 26 1.3 354 1 5.5 30 1.6 1.8 mV rms μs V mA mA mA V V V μs μA nA dB dB mV/dB dB dB dBm dBV rms dBm dBV rms 700 200 +20 −20 ±0.2 +42.5 −2.5 300 300 5 4.3 3.5 50 VS/2 Typ Max 500 Unit MHz dB mV p-p Ω mV/dB mV/dB dB dB dB ns ns MHz V p-p V p-p Ω V 175 225 1.2 1.4 2.5 1.5 27 32 +42.5 −3.7 19.9 −5.6 6.2 36.5 29.5 8.5 1.5 Maximum gain f1 = 70 MHz, f2 = 71 MHz, VGAIN = 0.5 V VGAIN = 0.5 V Rev. A | Page 3 of 24 AD8367 Parameter f = 140 MHz Gain Gain Scaling Factor Gain Intercept Noise Figure Output IP3 Output 1 dB Compression Point f = 190 MHz Gain Gain Scaling Factor Gain Intercept Noise Figure Output IP3 Output 1 dB Compression Point f = 240 MHz Gain Gain Scaling Factor Gain Intercept Noise Figure Output IP3 Output 1 dB Compression Point Conditions Maximum gain Minimum gain Min Typ +43.5 −3.6 19.7 −5.3 7.4 32.7 25.7 8.4 1.4 +43.5 −3.8 19.6 −5.3 7.5 30.9 23.9 8.4 1.4 +43 −4.1 19.7 −5.2 7.6 29.2 22.2 8.1 1.1 Max Unit dB dB mV/dB dB dB dBm dBV rms dBm dBV rms dB dB mV/dB dB dB dBm dBV rms dBm dBV rms dB dB mV/dB dB dB dBm dBV rms dBm dBV rms Maximum gain f1 = 140 MHz, f2 = 141 MHz, VGAIN = 0.5 V VGAIN = 0.5 V Maximum gain Minimum gain Maximum gain f1 = 190 MHz, f2 = 191 MHz, VGAIN = 0.5 V VGAIN = 0.5 V Maximum gain Minimum gain Maximum gain f1 = 240 MHz, f2 = 241 MHz, VGAIN = 0.5 V VGAIN = 0.5 V 1 The output dc centering voltage is normally set at VS/2 and can be adjusted by applying a voltage to DECL. Rev. A | Page 4 of 24 AD8367 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage VPSO, VPSI ENBL Voltage MODE Select Voltage VGAIN Control Voltage Input Voltage Internal Power Dissipation θJA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering 60 sec) Rating 5.5 V VS + 200 mV VS + 200 mV 1.2 V ±600 mV 250 mW 150°C/W 125°C −40°C to +85°C −65°C to +150°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 5 of 24 AD8367 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ICOM 1 ENBL 2 INPT 3 MODE 4 DETO 6 ICOM 7 14 13 ICOM HPFL VPSI AD8367 12 11 VPSO TOP VIEW GAIN 5 (Not to Scale) 10 VOUT 02710-002 9 8 DECL OCOM Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1, 7, 14 2 3 4 5 6 8 9 10 11 12 13 Mnemonic ICOM ENBL INPT MODE GAIN DETO OCOM DECL VOUT VPSO VPSI HPFL Description Signal Common. Connect to low impedance ground. A HI Activates the Device. Signal Input. 200 Ω to ground. Gain Direction Control. HI for positive slope; LO for negative slope. Gain Control Voltage Input. Detector Output. Provides output current for RSSI function and AGC control. Power Common. Connect to low impedance ground. Output Centering Loop Decoupling Pin. Signal Output. To be externally ac-coupled to load. Positive Supply Voltage. 2.7 V to 5.5 V. VPSI and VPSO are tied together internally with back-to-back PN junctions. They should be tied together externally and properly bypassed. Positive Supply Voltage. 2.7 V to 5.5 V. High-Pass Filter Connection. A capacitor to ground sets the corner frequency of the output offset control loop. Rev. A | Page 6 of 24 AD8367 TYPICAL PERFORMANCE CHARACTERISTICS VS = 5 V, TA = 25°C, system impedance ZO = 200 Ω, VMODE = 5 V, unless otherwise noted. 50 1V 0.9V 0.8V 30 GAIN (dB) 10 +85°C 9 +25°C NOISE FIGURE (dB) 40 0.7V 0.6V 8 –40°C 7 20 0.5V 0.4V 10 0.3V 0.2V 6 0 0.1V 02710-003 5 02710-006 –10 10 100 FREQUENCY (MHz) 1000 4 70 90 110 130 150 170 190 210 230 250 FREQUENCY (MHz) ` Figure 3. Gain vs. Frequency for Values of VGAIN 45 40 35 Figure 6. NF (re 200 Ω) vs. Frequency at Maximum Gain 60 50 NOISE FIGURE (dB) 02710-004 30 GAIN (dB) 25 20 15 10 5 0 –5 0 0.1 0.2 0.3 0.4 0.5 VGAIN (V) 0.6 0.7 0.8 0.9 1.0 MODE = 5V 10MHz 70MHz 140MHz 240MHz MODE = 0V 10MHz 70MHz 140MHz 240MHz 40 30 20 10 02710-007 0 0 0.1 0.2 0.3 0.4 0.5 VGAIN (V) 0.6 0.7 0.8 0.9 1.0 Figure 4. Gain vs. VGAIN (Mode LO and Mode HI) 45 40 35 30 –40°C +25°C +85°C 15 10 5 0 –5 0 0.1 0.2 0.3 0.4 0.5 VGAIN (V) 0.6 0.7 0.8 0.9 –0.4 –0.8 –1.2 –1.6 –2.0 1.0 02710-005 Figure 7. NF (re 200 Ω) vs. VGAIN at 70 MHz 2.0 1.6 1.2 0.8 0.4 0 40 35 30 25 20 15 10 02710-008 70MHz 10MHz LINEARITY ERROR (dB) 140MHz 240MHz 20 OIP3 (dBm) GAIN (dB) 25 5 0 0 0.1 0.2 0.3 0.4 0.5 VGAIN (V) 0.6 0.7 0.8 0.9 1.0 Figure 5. Gain Conformance at 70 MHz for T = −40°C, +25°C, and +85°C Figure 8. OIP3 vs. VGAIN Rev. A | Page 7 of 24 AD8367 40 33 0 –10 35 28 –20 OIP3 (dBV rms) 30 23 OUTPUT IMD3 (dBc) OIP3 (dBm re 200Ω) –30 –40 240MHz –50 10MHz –60 70MHz 140MHz 25 18 20 13 15 8 02710-009 02710-012 –70 –80 0 0.1 0.2 0.3 0.4 0.5 VGAIN (V) 0.6 0.7 0.8 0.9 10 10 100 FREQUENCY (MHz) 3 1000 1.0 Figure 9. OIP3 vs. Frequency for VGAIN = 500 mV 4 OUTPUT 1dB COMPRESSION (dBV rms) Figure 12. IMD3 vs. Gain (VOUT = 1 V p-p Composite) 11 OUTPUT 1dB COMPRESSION (dBm re 200Ω) OUTPUT 1dB COMPRESSION (dBV rms) 2 140MHz 0 200MHz –2 9 2 9 7 0 7 5 –2 5 –4 3 –4 3 –6 1 –6 1 02710-010 OUTPUT 1dB COMPRESSION (dBm re 200Ω) 10MHz 70MHz 4 11 –8 0 0.1 0.2 0.3 0.4 0.5 VGAIN (V) 0.6 0.7 0.8 0.9 –1 1.0 –8 2.5 3.0 3.5 4.0 VS (V) 4.5 5.0 –1 5.5 Figure 10. Output P1dB vs. VGAIN Figure 13. Output Compression Point vs. Supply Voltage at 70 MHz, VGAIN = 500 mV 12 11 10 9 8 7 6 5 4 3 2 1000 OUTPUT 1dB COMPRESSION (dBm re 200Ω) 5 OUTPUT 1dB COMPRESSION (dBV rms) 40 35 OUTPUT IP3 (dBm re 200Ω) 33 28 23 18 13 8 3 02710-014 4 3 2 1 0 –1 –2 –3 –4 –5 10 25 20 15 10 5 0 2.5 02710-011 –2 –7 5.5 100 FREQUENCY (MHz) 3.0 3.5 4.0 VS (V) 4.5 5.0 Figure 11. Output P1dB vs. Frequency at VGAIN = 500 mV Figure 14. Output Third-Order Intercept vs. Supply Voltage at 70 MHz, VGAIN = 500 mV Rev. A | Page 8 of 24 OUTPUT IP3 (dBV rms) 30 02710-013 AD8367 250 0 120 90 60 200 –25 SERIES REACTANCE (Ω) RESISTANCE (Ω) 150 500mV 180 700mV 300mV 30 150 –47 100 –73 0 50 –95 02710-015 210 330 0 0 100 200 300 400 FREQUENCY (MHz) –120 500 240 300 270 02710-018 Figure 15. Input Resistance and Series Reactance vs. Frequency at VGAIN = 500 mV 90 120 60 Figure 18. Output Reflection Coefficient vs. Frequency from 10 MHz to 500 MHz for Multiple Values of VGAIN 0.5 VGAIN 0.4 150 30 0.3 VOUT 0.2 180 0 V (V) 0.1 0 210 300mV 500mV 700mV 240 300 330 –0.1 02710-019 –0.2 02710-016 –0.3 TIME (200ns/DIV) 270 Figure 16. Input Reflection Coefficient vs. Frequency from 10 MHz to 500 MHz for Multiple Values of VGAIN 70 20 25 Figure 19. AGA Time Domain Response (3 dB Steps) 65 15 SERIES REACTANCE (Ω) 20 10nF RESISTANCE (Ω) 60 10 GAIN (dB) 15 1nF 10pF 10 100pF 55 5 50 0 45 –5 02710-017 5 NO CAP 0 0.1 1 10 100 1k 10k 02710-020 40 0 100 200 300 400 FREQUENCY (MHz) –10 500 100k FREQUENCY (kHz) Figure 17. Output Resistance and Series Reactance vs. Frequency at VGAIN = 500 mV Figure 20. Gain vs. Frequency for Multiple Values of HPFL Capacitor at VGAIN = 500 mV Rev. A | Page 9 of 24 AD8367 1.0 0.9 0.8 0.7 RSSI (V) 2.0 1.5 140MHz 10MHz 70MHz 140MHz 240MHz 1.0 0.5 0 240MHz 10MHz –0.5 –1.0 –1.5 –2.0 02710-021 0.8 VAGC LINEARITY ERROR (dB) 70MHz 0.7 CAGC = 100pF 0.6 0.5 0.4 0.3 0.2 0.1 0 –60 V (V) 0.6 VOUT 0.5 02710-024 –2.5 –3.0 –50 –40 –30 –20 –10 0 INPUT LEVEL (dBV rms) 0.4 –2–5 –1–5 0 TIME (Seconds) 1–5 2–5 Figure 21. AGC RSSI (Voltage on DETO Pin) vs. Input Power at 10 MHz, 70 MHz, 140 MHz, and 240 MHz 1.0 0.9 0.8 0.7 RSSI (V) Figure 24. AGC Time Domain Response (3 dB Step) 2.0 +25°C –40°C +85°C +85°C +25°C 1.5 1.0 0.5 0 –0.5 –40°C –1.0 –1.5 –2.0 –2.5 –3.0 –50 –40 –30 –20 –10 0 INPUT LEVEL (dBV rms) 02710-022 0.6 0.5 0.4 0.3 0.2 0.1 0 –60 LINEARITY ERROR (dB) 19.0097 19.7297 19.9097 20.0897 20.2697 GAIN SCALING (mV/dB) Figure 22. AGC RSSI (Voltage on DETO Pin) vs. Input Power over Temperature at 70 MHz 1.0 0.9 0.8 0.7 WCDMA 256QAM 64QAM 16QAM SINE Figure 25. Gain Scaling Distribution at 70 MHz 2.5 2.0 1.5 1.0 0.5 0 –0.5 RSSI (V) 0.6 0.5 0.4 0.3 0.2 0.1 0 –60 IS95FWD –1.0 –1.5 –2.5 –50 –40 –30 –20 –10 0 INPUT LEVEL (dBV rms) –6.4 –6.2 –6.0 –5.8 –5.6 –5.4 –5.2 –5.0 –4.8 INTERCEPT (dB) Figure 23. AGC RSSI (Voltage on DETO Pin) vs. Input Power for Various Modulation Schemes Figure 26. Gain Intercept Distribution at 70 MHz Rev. A | Page 10 of 24 02710-026 –2.0 02710-023 LINEARITY ERROR (dB) 02710-025 AD8367 THEORY OF OPERATION The AD8367 is a variable gain, single-ended, IF amplifier based on Analog Devices’ patented X-AMP architecture. It offers accurate gain control with a 45 dB span and a 3 dB bandwidth of 500 MHz. It can be configured as a traditional VGA with 50 dB/V gain scaling or as an AGC amplifier by using the built in rms detector. Figure 27 is a simplified block diagram of the amplifier. The main signal path consists of a voltage controlled 0 dB to 45 dB variable attenuator followed by a 42.5 dB fixed gain amplifier. The AD8367 is designed to operate optimally in a 200 Ω impedance system. INTEGRATOR GAIN gm GAIN INTERPOLATOR gm gm –10dB gm –45dB VOUT –42.5dB OUTPUT BUFFER VOUT deviation from Equation 1, that is, the gain conformance error, is also illustrated in Figure 28. The ripples in the error are a result of the interpolation action between tap points. The AD8367 provides better than ±0.5 dB of conformance error over >40 dB gain range at 200 MHz and ±1 dB at 400 MHz. 44 40 LO MODE 36 32 28 50dB/V GAIN SLOPE 2.0 1.6 1.2 0.4 0 –0.4 –0.8 –1.2 –1.6 HI MODE 24 20 16 12 8 4 0dB –5dB INPT 200Ω 02710-027 0 –2.4 –4 0 0.1 0.2 0.3 0.4 0.5 VGAIN (V) 0.6 0.7 0.8 0.9 1.0 ATTENUATOR LADDER Figure 27. Simplified Architecture INPUT ATTENUATOR AND GAIN CONTROL The variable attenuator consists of a 200 Ω single-ended resistive ladder that comprises of nine 5 dB sections and an interpolator that selects the attenuation factor. Each tap point down the ladder network further attenuates the input signal by a fixed decibel factor. Gain control is achieved by sensing different tap points with variable transconductance stages. Based on the gain control voltage, an interpolator selects which stage(s) are active. For example, if only the first stage is active, the 0 dB tap point is sensed; if the last stage is active, the 45 dB tap point is sensed. Attenuation levels that fall between tap points are achieved by having neighboring gm stages active simultaneously, creating a weighted average of the discrete tap point attenuations. In this way, a smooth, monotonic attenuation function is synthesized, that is, linear-in-dB with a very precise scaling. The gain of the AD8367 can be an increasing or decreasing function of the control voltage, VGAIN, depending on whether the MODE pin is pulled up to the positive supply or down to ground. When the MODE pin is high, the gain increases with VGAIN, as shown in Figure 28. The ideal linear-in-dB scaled transfer function is given by Gain (dB) = 50 × VGAIN − 5 where VGAIN is expressed in volts. Equation 1 contains the gain scaling factor of 50 dB/V (20 mV/dB) and the gain intercept of −5 dB, which represents the extrapolated gain for VGAIN = 0 V. The gain ranges from −2.5 dB to +42.5 dB for VGAIN ranging from 50 mV to 950 mV. The (1) Figure 28. The gain function can be either an increasing or decreasing function of VGAIN, depending on the MODE pin. The gain is a decreasing function of VGAIN when the MODE pin is low. Figure 28 also illustrates this mode, which is described by Gain (dB) = 45 − 50 × VGAIN (2) This gain mode is required in AGC applications using the builtin, square-law level detector. INPUT AND OUTPUT INTERFACES The AD8367 was designed to operate best in a 200 Ω impedance system. Its gain range, conformance law, noise, and distortion assume that 200 Ω source and load impedances are used. Interfacing the AD8367 to other common impedances (from 50 Ω used at radio frequencies to 1 kΩ presented by data converters) can be accomplished using resistive or reactive passive networks, whose design depends on specific system requirements, such as bandwidth, return loss, noise figure, and absolute gain range. The input impedance of the AD8367 is nominally 200 Ω, determined by the resistive ladder network. This presents a 200 Ω dc resistance to ground, and, in cases where an elevated signal potential is used, ac coupling is necessary. The input signal level must not exceed 700 mV p-p to avoid overloading the input stage. The output impedance is determined by an internal 50 Ω damping resistor, as shown in Figure 29. Despite the fact that the output impedance is 50 Ω, the AD8367 should still be presented with a load of 200 Ω. This implies that the load is mismatched, but doing so preserves the distortion performance of the amplifier. Rev. A | Page 11 of 24 02710-028 –2.0 LINEARITY ERROR (dB) 0.8 GAIN (dB) AD8367 60 50 VB1 FROM INTEGRATOR VB2 02710-029 60 50 NF 40 30 20 IIP3 10 0 –10 –20 –30 1.0 02710-030 50Ω 40 VOUT 30 IIP3 (dBV) 20 10 0 –10 Figure 29. A 50 Ω resistor is added to the output to prevent package resonance. POWER AND VOLTAGE METRICS Although power is the traditional metric used in the analysis of cascaded systems, most active circuit blocks fundamentally respond to voltage. The relationship between power and voltage is defined by the impedance level. When input and output impedance levels are the same, power gain and voltage gain are identical. However, when impedance levels change between input and output, they differ. Thus, one must be very careful to use the appropriate gain for system chain analyses. Quantities such as OIP3 are quoted in dBV rms as well as dBm referenced to 200 Ω. The dBV rms unit is defined as decibels relative to 1 V rms. In a 200 Ω environment, the conversion from dBV rms to dBm requires the addition of 7 dB to the dBV rms value. For example, a 2 dBV rms level corresponds to 9 dBm. –20 –30 0 0.1 0.2 0.3 0.4 0.5 VGAIN (V) 0.6 0.7 0.8 0.9 Figure 30. Noise Figure and Input Third-Order Intercept vs. Gain (RSOURCE = 200 Ω) OUTPUT CENTERING To maximize the ac swing at the output of the AD8367, the output level is centered midway between ground and the supply. This is achieved when the DECL pin is bypassed to ground via a shunt capacitor. The loop acts to suppress deviations from the reference at outputs below its corner frequency while not affecting signals above it, as shown in Figure 31. The maximum corner frequency with no external capacitor is 500 kHz. The corner frequency can be lowered arbitrarily by adding an external capacitor, CHP: NOISE AND DISTORTION Since the AD8367 consists of a passive variable attenuator followed by a fixed gain amplifier, the noise and distortion characteristics as a function of the gain voltage are easily predicted. The input-referred noise increases in proportion to the attenuation level. Figure 30 shows noise figure, NF, as a function of VGAIN for the MODE pin pulled high. The minimum NF of 7.5 dB occurs at maximum gain and increases 1 dB for every 1 dB reduction in gain. In receiver applications, the minimum NF should occur at the maximum gain where the received signal presumably is weak. At higher levels, a lower gain is needed, and the increased NF becomes less important. The input-referred distortion varies in a similar manner to the noise. Figure 30 illustrates how the third-order intercept point at the input, IIP3, behaves as a function of VGAIN. The highest IIP3 of 20 dBV rms (27 dBm re 200 Ω) occurs at minimum gain. The IIP3 then decreases 1 dB for every 1 dB increase in gain. At lower levels, a degraded IIP3 is acceptable. Overall, the dynamic range, represented by the difference between IIP3 and NF, remains reasonably constant as a function of gain. The output distortion and compression are essentially independent of the gain. At low gains, when the input level is high, input overload can occur, causing premature distortion. f HP (kHz) = 10 C HP (nF) + 0.02 A 100 Ω in series with the CHP capacitor is recommended to de-Q the resonant tank that is formed by the bond-wire inductance and CHP. Failure to insert this capacitor can potentially cause oscillations at higher frequencies at high gain settings. MAIN AMPLIFIER FROM INPUT gm HPFL CHP RHP DECL VMID AV = 1 02710-031 VOUT Figure 31. The dc output level is centered to midsupply by a control loop whose corner frequency is determined by CHP. Rev. A | Page 12 of 24 NF (dB) (3) AD8367 RMS DETECTION The AD8367 contains a square-law detector that senses the output signal and compares it to a calibrated setpoint of 354 mV rms, which corresponds to a 1 V p-p sine wave. This setpoint is internally set and cannot be modified to change the AGC setpoint and the resulting VOUT level without using additional external components. This is described in the Modifying the AGC Setpoint section. Any difference between the output and setpoint generates a current that is integrated by an external capacitor, CAGC, connected from the DETO pin to ground, to provide an AGC control voltage. There is also an internal 5 pF capacitor on the DETO pin. The resulting voltage is used as an AGC bias. For this application, the MODE pin is pulled low and the DETO pin is tied to the GAIN pin. The output signal level is then regulated to 354 mV rms. The AGC bias represents a calibrated rms measure of the received signal strength (RSSI). Since in AGC mode the output signal is forced to the 354 mV rms setpoint (−9.02 dBV rms), Equation 2 can be recast to express the strength of the received signal, VIN-RMS, in terms of the AGC bias VDETO. VIN − RMS (dBV rms) = 54.02 + 50 × VDETO where −54.02 dBV rms = −45 dB − 9.02 dBV rms. For small changes in input signal level, VDETO responds with a characteristic single-pole time constant, τAGC, which is proportional to CAGC. τAGC (μs) = 10 × CAGC (nf) where the internal 5 pF capacitor is lumped with the external capacitor to give CAGC. (5) (4) Rev. A | Page 13 of 24 AD8367 APPLICATIONS The AD8367 can be configured either as a VGA whose gain is controlled externally through the GAIN pin or as an AGC amplifier, using a supply voltage of 2.7 V to 5.5 V. The supply to the VPSO and VPSI pins should be decoupled using a low inductance, 0.1 μF surface-mount, ceramic capacitor as close as possible to the device. Additional supply decoupling can be provided by a small series resistor. A 10 nF capacitor from Pin DECL to Pin OCOM is recommended to decouple the output reference voltage. Minimum-loss, L-pad networks are used on the evaluation board (see Figure 45) to allow easy interfacing to standard 50 Ω test equipment. Each pad introduces an 11.5 dB power loss (5.5 dB voltage loss). 1 0.3333 3 INPUT AND OUTPUT MATCHING The AD8367 is designed to operate in a 200 Ω impedance system. The output amplifier is a low output impedance voltage buffer with a 50 Ω damping resistor to desensitize it from load reactance and parasitics. The quoted performance includes the voltage division between the 50 Ω resistor and the 200 Ω load. The AD8367 can be reactively matched to an impedance other than 200 Ω by using traditional step-up and step down matching networks or high quality transformers. Table 4 lists the 50 Ω S-parameters for the AD8367 at a VGAIN = 750 mV. Figure 32 illustrates an example where the AD8367 is matched to 50 Ω at 140 MHz. As shown in the Smith Chart, the input matching network shifts the input impedance from ZIN to 50 Ω with an insertion loss of