AD8402AN1

a FEATURES 256 Position Replaces 1, 2 or 4 Potentiometers 1 k , 10 k , 50 k , 100 k Power Shut Down—Less than 5 A 3-Wire SPI Compatible Serial Data Input 10 MHz Update Data Loading Rate +2.7 V to +5.5 V Single-Supply Operation Midscale Preset APPLICATIONS Mechanical Potentiometer Replacement Programmable Filters, Delays, Time Constants Volume Control, Panning Line Impedance Matching Power Supply Adjustment GENERAL DESCRIPTION VDD DGND 1-/2-/4-Channel Digital Potentiometers AD8400/AD8402/AD8403 FUNCTIONAL BLOCK DIAGRAM AD8403 8-BIT LATCH CK 1 DAC 2 SELECT 3 A1, A0 2 8 8 RDAC3 A3 W3 SHDN B3 AGND3 4 CK RS SHDN 8-BIT LATCH 8 RDAC2 A2 W2 B2 AGND2 RS 8 RDAC1 A1 W1 B1 SHDN AGND1 10-BIT SERIAL LATCH SDI CLK CS D CK Q RS 8-BIT LATCH CK RS 8-BIT LATCH CK RS 8 RDAC4 A4 W4 B4 AGND4 SHDN The AD8400/AD8402/AD8403 provide a single, dual or quad channel, 256 position digitally controlled variable resistor (VR) device. These devices perform the same electronic adjustment function as a potentiometer or variable resistor. The AD8400 contains a single variable resistor in the compact SO-8 package. The AD8402 contains two independent variable resistors in space saving SO-14 surface mount package. The AD8403 contains four independent variable resistors in 24-lead PDIP, SOIC and TSSOP packages. Each part contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the controlling serial input register. The resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the VR latch. Each variable resistor offers a completely programmable value of resistance, between the A terminal and the wiper or the B terminal and the wiper. The fixed A to B terminal resistance of 1 kΩ, 10 kΩ, 50 kΩ or 100 kΩ has a ± 1% channel-to-channel matching tolerance with a nominal temperature coefficient of 500 ppm/°C. A unique switching circuit minimizes the high glitch inherent in traditional switched resistor designs avoiding any make-before-break or break-beforemake operation. Each VR has its own VR latch that holds its programmed resistance value. These VR latches are updated from an SPI compatible serial-to-parallel shift register that is loaded from a standard 3-wire serial-input digital interface. Ten data bits make up the data word clocked into the serial input register. The data word is decoded where the first two bits determine the address of the VR latch to be loaded, the last eight bits are data. A serial data output pin at the opposite end of the serial register allows simple daisy-chaining in multiple VR applications without additional external decoding logic. R EV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. SDO RS SHDN The reset (RS) pin forces the wiper to the midscale position by loading 80H into the VR latch. The SHDN pin forces the resistor to an end-to-end open circuit condition on the A terminal and shorts the wiper to the B terminal, achieving a microwatt power shutdown state. When SHDN is returned to logic high, the previous latch settings put the wiper in the same resistance setting prior to shutdown. The digital interface is still active in shutdown so that code changes can be made which will produce new wiper positions when the device is taken out of shutdown. The AD8400 is available in both the SO-8 surface mount and the 8-lead plastic DIP package. The AD8402 is available in both surface mount (SO-14) and the 14-lead plastic DIP package, while the AD8403 is available in a narrow body 24-lead plastic DIP and the 24-lead surface mount package. The AD8402/AD8403 are also offered in the 1.1 mm thin TSSOP-14/TSSOP-24 package for PCMCIA applications. All parts are guaranteed to operate over the extended industrial temperature range of –40°C to +85°C. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1997 AD8400/AD8402/AD8403–SPECIFICATIONS 10 k VERSION ELECTRICAL CHARACTERISTICS Parameter Symbol (VDD = +3 V 10% or + 5 V otherwise noted) Conditions 10%, VA = +VDD, VB = 0 V, –40 C ≤ TA ≤ +85 C unless Min –1 –2 8 Typ1 ± 1/4 ± 1/2 10 500 50 0.2 Max +1 +2 12 100 1 Units LSB LSB kΩ ppm/°C Ω % Bits LSB LSB LSB LSB ppm/°C LSB LSB V pF pF µA Ω V V V V V V µA pF V µA mA µW %/% %/% kHz % µs nV/√Hz dB DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs Resistor Differential NL2 R-DNL RWB, VA = NC R-INL RWB, VA = NC Resistor Nonlinearity2 Nominal Resistance3 R TA = +25°C, Model: AD840XYY10 VAB = VDD, Wiper = No Connect Resistance Tempco ∆RAB/∆T Wiper Resistance RW IW = 1 V/R Nominal Resistance Match ∆R/RO CH 1 to 2, 3, or 4, VAB = VDD, TA = +25°C DC CHARACTERISTICS POTENTIOMETER DIVIDER Specifications Apply to All VRs Resolution N INL Integral Nonlinearity4 Differential Nonlinearity4 DNL VDD = +5 V TA = +25°C DNL VDD = +3 V DNL VDD = +3 V TA = –40°C, +85°C Code = 80H Voltage Divider Tempco ∆VW/∆T Full-Scale Error VWFSE Code = FFH Zero-Scale Error VWZSE Code = 00H RESISTOR TERMINALS Voltage Range5 Capacitance6 Ax, Bx Capacitance6 Wx Shutdown Current7 Shutdown Wiper Resistance DIGITAL INPUTS & OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Output Logic High Output Logic Low Input Current Input Capacitance6 POWER SUPPLIES Power Supply Range Supply Current (CMOS) Supply Current (TTL)8 Power Dissipation (CMOS)9 Power Supply Sensitivity DYNAMIC CHARACTERISTICS6, 10 Bandwidth –3 dB Total Harmonic Distortion VW Settling Time Resistor Noise Voltage Crosstalk11 VA, B, W CA, B CW IA_SD RW_SD VIH VIL VIH VIL VOH VOL IIL CIL VDD Range IDD IDD PDISS PSS PSS BW_10K THDW tS eNWB CT 8 –2 –1 –1 –1.5 –4 0 0 ± 1/2 ± 1/4 ± 1/4 ± 1/2 15 –2.8 +1.3 +2 +1 +1 +1.5 0 +2 VDD f = 1 MHz, Measured to GND, Code = 80H f = 1 MHz, Measured to GND, Code = 80H VA = VDD, VB = 0 V, SHDN = 0 VA = VDD, VB = 0 V, SHDN = 0, VDD = +5 V VDD = +5 V VDD = +5 V VDD = +3 V VDD = +3 V RL = 1 kΩ to VDD IOL = 1.6 mA, VDD = +5 V VIN = 0 V or +5 V, VDD = +5 V 2.4 75 120 0.01 100 5 200 0.8 2.1 0.6 VDD–0.1 0.4 ±1 5 2.7 5.5 5 4 27.5 0.0002 0.001 0.006 0.03 0.01 0.9 600 0.003 2 9 –65 VIH = VDD or VIL = 0 V VIH = 2.4 V or 0.8 V, VDD = +5.5 V VIH = VDD or VIL = 0 V, VDD = +5.5 V VDD = +5 V ± 10% VDD = +3 V ± 10% R = 10 kΩ VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz VA = VDD, VB = 0 V, ± 1% Error Band RWB = 5 kΩ, f = 1 kHz, RS = 0 VA = VDD, VB = 0 V NOTES FOR 10 k Ω VERSION 1 Typicals represent average readings at +25 °C and VDD = +5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 30 test circuit. IW = 50 µA for VDD = +3 V and IW = 400 µA for VDD = +5 V for the 10 kΩ versions. 3 VAB = VDD, Wiper (VW) = No Connect. 4 INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V. DNL Specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 29 test circuit. 5 Resistor terminals A, B, W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining resistor terminals are left open circuit. 7 Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode. 8 Worst case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See Figure 21 for a plot of I DD versus logic voltage. 9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 10 All Dynamic Characteristics use V DD = +5 V. 11 Measured at a V W pin where an adjacent V W pin is making a full-scale voltage change. Specifications subject to change without notice. –2– REV. B SPECIFICATIONS 50 k & 100 k VERSION ELECTRICAL CHARACTERISTICS Parameter Symbol AD8400/AD8402/AD8403 (VDD = +3 V 10% or + 5 V otherwise noted) Conditions 10%, VA = +VDD, VB = 0 V, –40 C ≤ TA ≤ +85 C unless Min –1 –2 35 70 Typ1 ± 1/4 ± 1/2 50 100 500 53 0.2 Max +1 +2 65 130 100 1 Units LSB LSB kΩ kΩ ppm/°C Ω % Bits LSB LSB LSB LSB ppm/°C LSB LSB V pF pF µA Ω V V V V V V µA pF V µA mA µW %/% %/% kHz kHz % µs µs nV/√Hz nV/√Hz dB DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs Resistor Differential NL2 R-DNL RWB, VA = NC Resistor Nonlinearity2 R-INL RWB, VA = NC R TA = +25°C, Model: AD840XYY50 Nominal Resistance3 R TA = +25°C, Model: AD840XYY100 Resistance Tempco ∆RAB/∆T VAB = VDD, Wiper = No Connect IW = 1 V/R Wiper Resistance RW Nominal Resistance Match ∆R/RO CH 1 to 2, 3, or 4, VAB = VDD, TA = +25°C DC CHARACTERISTICS POTENTIOMETER DIVIDER Specifications Apply to All VRs Resolution N INL Integral Nonlinearity4 Differential Nonlinearity4 DNL VDD = +5 V TA = +25°C DNL VDD = +3 V DNL VDD = +3 V TA = –40°C, +85°C Voltage Divider Tempco ∆VW/∆T Code = 80H Code = FFH Full-Scale Error VWFSE Zero-Scale Error VWZSE Code = 00H RESISTOR TERMINALS Voltage Range5 Capacitance6 Ax, Bx Capacitance6 Wx Shutdown Current7 Shutdown Wiper Resistance DIGITAL INPUTS & OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Output Logic High Output Logic Low Input Current Input Capacitance6 POWER SUPPLIES Power Supply Range Supply Current (CMOS) Supply Current (TTL)8 Power Dissipation (CMOS)9 Power Supply Sensitivity DYNAMIC CHARACTERISTICS6, 10 Bandwidth –3 dB Total Harmonic Distortion VW Settling Time Resistor Noise Voltage Crosstalk11 VA, B, W CA, B CW IA_SD RW_SD VIH VIL VIH VIL VOH VOL IIL CIL VDD Range IDD IDD PDISS PSS PSS BW_50K BW_100K THDW tS_50K tS_100K eNWB_50K eNWB _100K CT 8 –4 –1 –1 –1.5 –1 0 0 ±1 ± 1/4 ± 1/4 ± 1/2 15 –0.25 +0.1 +4 +1 +1 +1.5 0 +1 VDD f = 1 MHz, Measured to GND, Code = 80H f = 1 MHz, Measured to GND, Code = 80H VA = VDD, VB = 0 V, SHDN = 0 VA = VDD, VB = 0 V, SHDN = 0, VDD = +5 V VDD = +5 V VDD = +5 V VDD = +3 V VDD = +3 V RL = 1 kΩ to VDD IOL = 1.6 mA, VDD = +5 V VIN = 0 V or +5 V, VDD = +5 V 2.4 15 80 0.01 100 5 200 0.8 2.1 0.6 VDD–0.1 0.4 ±1 5 2.7 5.5 5 4 27.5 0.0002 0.001 0.006 0.03 0.01 0.9 125 71 0.003 9 18 20 29 –65 VIH = VDD or VIL = 0 V VIH = 2.4 V or 0.8 V, VDD = +5.5 V VIH = VDD or VIL = 0 V, VDD = +5.5 V VDD = +5 V ± 10% VDD = +3 V ± 10% R = 50 kΩ R = 100 kΩ VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz VA = VDD, VB = 0 V, ± 1% Error Band VA = VDD, VB = 0 V, ± 1% Error Band RWB = 25 kΩ, f = 1 kHz, RS = 0 RWB = 50 kΩ, f = 1 kHz, RS = 0 VA = VDD, VB = 0 V NOTES FOR 50 kΩ and 100 kΩ VERSIONS 1 Typicals represent average readings at +25 °C and VDD = +5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 30 test circuit. IW = VDD/R for VDD = +3 V or +5 V for the 50 k Ω and 100 kΩ versions. 3 VAB = VDD, Wiper (VW) = No Connect. 4 INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V. DNL Specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 29 test circuit. 5 Resistor terminals A, B, W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining resistor terminals are left open circuit. 7 Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode. 8 Worst case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See Figure 21 for a plot of I DD versus logic voltage. 9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 10 All Dynamic Characteristics use V DD = +5 V. 11 Measured at a V W pin where an adjacent V W pin is making a full-scale voltage change. Specifications subject to change without notice. REV. B –3– AD8400/AD8402/AD8403–SPECIFICATIONS 1 k VERSION ELECTRICAL CHARACTERISTICS Parameter Symbol (VDD = +3 V 10% or + 5 V otherwise noted) Conditions 10%, VA = +VDD, VB = 0 V, –40 C ≤ TA ≤ +85 C unless Min –5 –4 0.8 Typ1 –1 ± 1.5 1.2 700 53 0.75 Max +3 +4 1.5 100 2 Units LSB LSB kΩ ppm/°C Ω % Bits LSB LSB LSB ppm/°C LSB LSB V pF pF µA Ω V V V V V V µA pF V µA mA µW %/% %/% kHz % µs nV/√Hz dB DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs Resistor Differential NL2 R-DNL RWB, VA = NC R-INL RWB, VA = NC Resistor Nonlinearity2 Nominal Resistance3 R TA = +25°C, Model: AD840XYY1 VAB = VDD, Wiper = No Connect Resistance Tempco ∆RAB/∆T Wiper Resistance RW IW = 1 V/RAB Nominal Resistance Match ∆R/RO CH 1 to 2, VAB = VDD, TA = +25°C DC CHARACTERISTICS POTENTIOMETER DIVIDER Specifications Apply to All VRs Resolution N INL Integral Nonlinearity4 Differential Nonlinearity4 DNL VDD = +5 V DNL VDD = +3 V, TA = +25°C Voltage Divider Temperature Coefficent ∆VW/∆T Code = 80H Code = FFH Full-Scale Error VWFSE Zero-Scale Error VWZSE Code = 00H RESISTOR TERMINALS Voltage Range5 Capacitance6 Ax, Bx Capacitance6 Wx Shutdown Supply Current7 Shutdown Wiper Resistance DIGITAL INPUTS & OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Output Logic High Output Logic Low Input Current Input Capacitance6 POWER SUPPLIES Power Supply Range Supply Current (CMOS) Supply Current (TTL)8 Power Dissipation (CMOS)9 Power Supply Sensitivity DYNAMIC CHARACTERISTICS6, 10 Bandwidth –3 dB Total Harmonic Distortion VW Settling Time Resistor Noise Voltage Crosstalk11 VA, B, W CA, B CW IDD_SD RW_SD VIH VIL VIH VIL VOH VOL IIL CIL VDD Range IDD IDD PDISS PSS PSS BW_1K THDW tS eNWB CT 8 –6 –4 –5 –20 0 0 ±2 –1.5 –2 25 –12 6 +6 +2 +5 0 10 VDD f = 1 MHz, Measured to GND, Code = 80H f = 1 MHz, Measured to GND, Code = 80H VA = VDD, VB = 0 V, SHDN = 0 VA = VDD, VB = 0 V, SHDN = 0, VDD = +5 V VDD = +5 V VDD = +5 V VDD = +3 V VDD = +3 V RL = 1 kΩ to VDD IOL = 1.6 mA, VDD = +5 V VIN = 0 V or +5 V, VDD = +5 V 2.4 75 120 0.01 50 5 100 0.8 2.1 0.6 VDD–0.1 0.4 ±1 5 2.7 5.5 5 4 27.5 0.0035 0.008 0.05 0.13 0.01 0.9 5,000 0.015 0.5 3 –65 VIH = VDD or VIL = 0 V VIH = 2.4 V or 0.8 V, VDD = +5.5 V VIH = VDD or VIL = 0 V, VDD = +5.5 V ∆VDD = +5 V ± 10% ∆VDD = +3 V ± 10% R = 1 kΩ VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz VA = VDD, VB = 0 V, ± 1% Error Band RWB = 500 Ω, f = 1 kHz, RS = 0 VA = VDD, VB = 0 V NOTES FOR 1 k Ω VERSION 1 Typicals represent average readings at +25 °C and VDD = +5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. See Figure 30 test circuit. IW = 500 µA for VDD = +3 V and IW = 4 mA for VDD = +5 V for 1 k Ω version. 3 VAB = VDD, Wiper (VW) = No Connect. 4 INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V. DNL Specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 29 test circuit. 5 Resistor terminals A, B, W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining resistor terminals are left open circuit. 7 Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode. 8 Worst case supply current consumed when input logic level at 2.4 V, standard characteristic of CMOS logic. See Figure 21 for a plot of I DD versus logic voltage. 9 PDISS is calculated from (I DD × VDD). CMOS logic level inputs result in minimum power dissipation. 10 All Dynamic Characteristics use V DD = +5 V. 11 Measured at a VW pin where an adjacent V W pin is making a full-scale voltage change. Specifications subject to change without notice. –4– REV. B AD8400/AD8402/AD8403–SPECIFICATIONS All VERSIONS (V = +3 V 10% or + 5 V ELECTRICAL CHARACTERISTICS otherwise noted) DD 10%, VA = +VDD, VB = 0 V, –40 C ≤ TA ≤ +85 C unless Min 10 5 5 1 10 10 50 0 10 Typ1 Max Units ns ns ns ns ns ns ns ns ns Parameter SWITCHING CHARACTERISTICS Input Clock Pulse Width Data Setup Time Data Hold Time CLK to SDO Propagation Delay4 CS Setup Time CS High Pulse Width Reset Pulse Width CLK Fall to CS Rise Hold Time CS Rise to Clock Rise Setup 2, 3 Symbol tCH, tCL tDS tDH tPD tCSS tCSW tRS tCSH tCS1 Conditions Clock Level High or Low RL = 1 kΩ to +5 V, CL ≤ 20 pF 25 NOTES 1 Typicals represent average readings at +25 °C and VDD = +5 V. 2 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining resistor terminals are left open circuit. 3 See timing diagram for location of measured values. All input control voltages are specified with t R = tF = 1 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. Switching characteristics are measured using V DD = +3 V or +5 V. To avoid false clocking a minimum input logic slew rate of 1 V/ µs should be maintained. 4 Propagation Delay depends on value of V DD, RL and CL–see applications text. Specifications subject to change without notice. 1 SDI 0 1 CLK 0 DAC REGISTER LOAD 1 CS 0 VOUT VDD 0V VOUT VDD VDD/2 ±1% ERROR BAND 1 RS 0 tRS A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 tS ±1% Figure 1c. Reset Timing Diagram ABSOLUTE MAXIMUM RATINGS* Figure 1a. Timing Diagram SDI (DATA IN) 1 Ax OR Dx 0 1 A'x OR D'x 0 A'x OR D'x Ax OR Dx (TA = +25 °C, unless otherwise noted) tDS tDH SDO (DATA OUT) tPD_MIN 1 CLK 0 1 CS 0 VDD VOUT 0V tPD_MAX tCH tCS1 tCL tCSS tCSH tCSW tS ±1 % ±1 % ERROR BAND VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD AX–BX, AX–WX, BX–WX . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Digital Input and Output Voltage to GND . . . . . . . 0 V, +8 V Operating Temperature Range . . . . . . . . . . . . –40°C to +85°C Maximum Junction Temperature (TJ max) . . . . . . . . . +150°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C Package Power Dissipation . . . . . . . . . . . . . . (TJ max–TA)/θJA Thermal Resistance (θJA) P-DIP (N-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +83°C/W P-DIP (N-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +63°C/W SOIC (SO-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . +70°C/W SOIC (SOL-24) . . . . . . . . . . . . . . . . . . . . . . . . . +120°C/W TSSOP-14 (RU-14) . . . . . . . . . . . . . . . . . . . . . . +180°C/W TSSOP-24 (RU-24) . . . . . . . . . . . . . . . . . . . . . . +143°C/W *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 1b. Detail Timing Diagram CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8400/AD8402/AD8403 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE –5– REV. B AD8400/AD8402/AD8403 ORDERING GUIDE Model AD8400AN10 AD8400AR10 AD8402AN10 AD8402AR10 AD8402ARU10 AD8403AN10 AD8403AR10 AD8403ARU10 AD8400AN50 AD8400AR50 AD8402AN50 AD8402AR50 AD8403AN50 AD8403AR50 AD8400AN100 AD8400AR100 AD8402AN100 AD8402AR100 AD8402ARU100 AD8403AN100 AD8403AR100 AD8403ARU100 AD8400AN1 AD8400AR1 AD8402AN1 AD8402AR1 AD8403AN1 AD8403AR1 AD8403ARU1 #CHs/ k X1/10 X1/10 X2/10 X2/10 X2/10 X4/10 X4/10 X4/10 X1/50 X1/50 X2/50 X2/50 X4/50 X4/50 X1/100 X1/100 X2/100 X2/100 X2/100 X4/100 X4/100 X4/100 X1/1 X1/1 X2/1 X2/1 X4/1 X4/1 X4/1 Temperature Range -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C Package Package Description Option* PDIP-8 SO-8 PDIP-14 SO-14 TSSOP-14 PDIP-24 SOIC-24 TSSOP-24 PDIP-8 SO-8 PDIP-14 SO-14 PDIP-24 SOIC-24 PDIP-8 SO-8 PDIP-14 SO-14 TSSOP-14 PDIP-24 SOIC-24 TSSOP-24 PDIP-8 SO-8 PDIP-14 SO-14 PDIP-24 SOIC-24 TSSOP-24 N-8 SO-8 N-14 SO-14 RU-14 N-24 SOL-24 RU-24 N-8 SO-8 N-14 SO-14 N-24 SOL-24 N-8 SO-8 N-14 SO-14 RU-14 N-24 SOL-24 RU-24 N-8 SO-8 N-14 SO-14 N-24 SOL-24 RU-24 Table I. Serial Data Word Format ADDR B9 B8 A1 MSB 29 A0 LSB 28 B7 B6 DATA B5 B4 D5 D4 B3 D3 B2 D2 B1 D1 B0 D0 LSB 20 D7 D6 MSB 27 PIN CONFIGURATIONS B1 1 GND 2 8 A1 7 W1 TOP VIEW CS 3 (Not to Scale) 6 VDD 5 CLK AD8400 SDI 4 AGND 1 B2 2 A2 3 W2 4 DGND 5 SHDN 6 CS 7 14 B1 13 A1 AD8402 12 W1 TOP VIEW 11 VDD (Not to Scale) 10 RS 9 CLK 8 SDI AGND2 1 B2 2 A2 3 W2 4 AGND4 5 B4 6 24 B1 23 A1 22 W1 21 AGND1 AD8403 20 B3 *N = Plastic DIP; SO = Small Outline; RU = Thin Shrink SO. The AD8400, AD8402 and the AD8403 contain 720 transistors. TOP VIEW 19 A3 A4 7 (Not to Scale) 18 W3 W4 8 DGND 9 SHDN 10 CS 11 SDI 12 17 AGND3 16 VDD 15 RS 14 CLK 13 SDO –6– REV. B AD8400/AD8402/AD8403 AD8400 PIN DESCRIPTIONS AD8403 PIN DESCRIPTIONS Pin 1 2 3 Name B1 GND CS Description Terminal B RDAC Ground Chip Select Input, Active Low. When CS returns high data in the serial input register is loaded into the DAC register. Serial Data Input Serial Clock Input, positive edge triggered Positive power supply, specified for operation at both +3 V and +5 V. Wiper RDAC, addr = 002 Terminal A RDAC Pin 1 2 3 4 5 6 7 8 9 10 Name AGND2 B2 A2 W2 AGND4 B4 A4 W4 DGND SHDN Description Analog Ground #2* Terminal B RDAC #2 Terminal A RDAC #2 Wiper RDAC #2, addr = 012 Analog Ground #4* Terminal B RDAC #4 Terminal A RDAC #4 Wiper RDAC #4, addr = 112 Digital Ground* Active Low Input. Terminal A open circuit. Shutdown controls variable resistors #1 through #4 Chip Select Input, Active Low. When CS returns high data in the serial input register is decoded based on the address bits and loaded into the target DAC register. Serial Data Input Serial Data Output, Open Drain transistor requires pull-up resistor Serial Clock Input, positive edge triggered Active low reset to midscale; sets RDAC registers to 80H Positive power supply, specified for operation at both +3 V and +5 V Analog Ground #3* Wiper RDAC #3, addr = 102 Terminal A RDAC #3 Terminal B RDAC #3 Analog Ground #1* Wiper RDAC #1, addr = 002 Terminal A RDAC #1 Terminal B RDAC #1 4 5 6 7 8 SDI CLK VDD W1 A1 11 AD8402 PIN DESCRIPTIONS CS Pin 1 2 3 4 5 6 7 Name AGND B2 A2 W2 DGND SHDN CS Description Analog Ground* Terminal B RDAC #2 Terminal A RDAC #2 Wiper RDAC #2, Addr = 012 Digital Ground* Terminal A open circuit. Shutdown controls Variable Resistors #1 and #2 Chip Select Input, Active Low. When CS returns high data in the serial input register is decoded based on the address bits and loaded into the target DAC register. Serial Data Input Serial Clock Input, positive edge triggered Active low reset to midscale; sets RDAC registers to 80H Positive power supply, specified for operation at both +3 V and +5 V Wiper RDAC #1, addr = 002 Terminal A RDAC #1 Terminal B RDAC #1 12 13 14 15 16 17 18 19 20 21 22 23 24 SDI SDO CLK RS VDD AGND3 W3 A3 B3 AGND1 W1 A1 B1 8 9 10 11 12 13 14 SDI CLK RS VDD W1 A1 B1 *All AGNDs must be connected to DGND. *All AGNDs must be connected to DGND. REV. B –7– AD8400/AD8402/AD8403–Typical Performance Characteristics 10 VDD = +3V OR +5V 8 RESISTANCE – kΩ VWB VOLTAGE – V 5 80H FFH 60 SS = 184 UNITS VDD = 4.5V TA = +25°C 4 40H 3 20H CODE = 10H 2 FREQUENCY 6 7 48 6 36 4 24 2 RWB RWA 1 05H 0 0 TA = +25°C VDD = +5V 12 0 0 32 64 96 128 160 192 224 CODE – Decimal 256 1 2 3 4 5 IWA CURRENT – mA 0 40.0 42.5 45.0 47.5 50.0 52.5 55.0 57.5 60.0 62.5 65.0 WIPER RESISTANCE – Ω Figure 2. Wiper to End Terminal Resistance vs. Code Figure 3. Resistance Linearity vs. Conduction Current Figure 4. 100 kΩ Wiper-ContactResistance Histogram 1 VDD = +5V 0.5 60 SS = 1205 UNITS VDD = 4.5V 10 RAB (END-TO-END) R-INL ERROR – LSB TA = +85°C FREQUENCY NOMINAL RESISTANCE – Ω 48 TA = +25°C 8 36 6 0 TA = –40°C –0.5 TA = +25°C 24 4 RWB (WIPER-TO-END) CODE = 80H 12 2 –1 0 64 96 128 160 192 224 32 DIGITAL INPUT CODE – Decimal 256 0 40.0 42.5 45.0 47.5 50.0 52.5 55.0 57.5 60.0 62.5 65.0 WIPER RESISTANCE – Ω 0 25 50 75 –75 –50 –25 0 TEMPERATURE – °C 100 125 Figure 5. Resistance Step Position Nonlinearity Error vs. Code Figure 6. 10 kΩ Wiper-ContactResistance Histogram Figure 7. Nominal Resistance vs. Temperature INL NONLINEARITY ERROR – LSB VDD = +5V 0.5 FREQUENCY POTENTIOMETER MODE TEMPCO – ppm/C° 1 60 SS = 184 UNITS VDD = 4.5V TA = +25°C 70 60 50 40 30 20 10 0 –10 VDD = +5V TA = –40°C/+85°C VA = 2.00V VB = 0V 48 TA = +25°C TA = –40°C 0 36 24 –0.5 TA = +85°C 12 –1 0 32 64 96 128 160 192 224 DIGITAL INPUT CODE – Decimal 256 0 35 37 39 41 43 45 47 49 51 53 55 0 32 64 WIPER RESISTANCE – Ω 96 128 160 192 224 256 CODE – DECIMAL Figure 8. Potentiometer Divider Nonlinearity Error vs. Code Figure 9. 50 kΩ Wiper-ContactResistance Histogram Figure 10. VWB / T Potentiometer Mode Tempco –8– REV. B AD8400/AD8402/AD8403 700 RHEOSTAT MODE TEMPCO – ppm/C° 600 500 400 300 200 100 0 –100 VDD = +5V TA = –40°C/+85°C VA = NO CONNECT RWB MEASURED 6 0 –6 CODE = FF 80 40 20 10 08 –30 –36 –42 –48 0 32 64 96 128 160 192 224 256 CODE – DECIMAL –54 TA = +25°C SEE TEST FIGURE 33 10 100 04 02 01 GAIN – dB RW (20mV/DIV) –12 –18 –24 CS (5V/DIV) TIME 500ns/DIV 1k 10k 100k FREQUENCY – Hz 1M Figure 11. Tempco RWB / T Rheostat Mode Figure 12. One Position Step Change at Half-Scale (Code 7FH to 80H) Figure 13. Gain vs. Frequency for R = 10 kΩ 0.75 CODE = 80H 0.5 VDD = +5V SS = 158 UNITS 0.25 AVG + 2 SIGMA 6 0 –6 CODE = FFH ∆RWB RESISTANCE – % OUTPUT GAIN – dB –12 –18 –24 –30 –36 80H 40H 20H 10H 08H 04H 02H 0 –0.25 AVG AVG – 2 SIGMA –0.5 INPUT –42 –48 –0.75 0 100 200 300 400 500 HOURS OF OPERATION AT 150°C 600 TIME = 5µ s/DIV –54 1k 10k 100k FREQUENCY – Hz 01H 1M Figure 14. Long-Term Drift Accelerated by Burn-In Figure 15. Large Signal Settling Time Figure 16. 50 kΩ Gain vs. Frequency vs. Code 10 FILTER = 22kHz VDD = +5V 1 THD + NOISE – % 6 0 –6 –12 GAIN – dB CODE = FFH 80H 40H 20H 10H 08H 04H 02H 01H TA = +25°C –18 –24 –30 –36 0.1 SEE TEST CIRCUIT FIGURE 32 0.01 VOUT (50mV/DIV) –42 SEE TEST CIRCUIT FIGURE 31 0.001 10 –48 –54 100 1k 10k FREQUENCY – Hz 100k 1k TIME 200ns/DIV 100k 10k FREQUENCY – Hz 1M Figure 17. Total Harmonic Distortion Plus Noise vs. Frequency Figure 18. Digital Feedthrough vs. Time Figure 19. 100 kΩ Gain vs. Frequency vs. Code REV. B –9– AD8400/AD8402/AD8403 NORMALIZED GAIN FLATNESS – 0.1dB/DIV 10 SEE TEST CIRCUIT 33 CODE = 80H VDD = +5V TA = +25°C R = 10kΩ IDD – SUPPLY CURRENT – mA 80 TA = +25°C VDD = +5V DC ± 1V p-p AC TA = +25°C CODE = 80H CL = 10pF VA = 4V, VB = 0V 60 1 PSRR – dB VDD = +5V 0.1 40 R = 50kΩ 20 VDD = +3V R = 100kΩ 0.01 SEE TEST CIRCUIT FIGURE 32 5 10 100 10k 1k 100k FREQUENCY – Hz 1M 0 1 2 3 4 INPUT LOGIC VOLTAGE – Volts 0 100 1k 10k 100k FREQUENCY – Hz 1M Figure 20. Normalized Gain Flatness vs. Frequency Figure 21. Supply Current vs. Logic Input Voltage Figure 22. Power Supply Rejection vs. Frequency 12 6 0 –6 f–3dB = 71kHz, R = 100kΩ IDD – SUPPLY CURRENT – µA 1200 f–3dB = 700kHz, R = 10kΩ 1000 A – VDD = 5.5V CODE = 55H B – VDD = 3.3V CODE = 55H C – VDD = 5.5V CODE = FFH D – VDD = 3.3V CODE = FFH 160 TA = +25°C 140 VDD = +2.7V 120 100 RON – Ω 80 60 A B 40 C D 1k 10k 100k 1M FREQUENCY – Hz 10M 20 0 TA = +25°C 800 GAIN – dB –12 –18 –24 –30 –36 –42 1k 600 f–3dB = 125kHz, R = 50kΩ VIN = 100mV rms VDD = +5V RL = 1MΩ VDD = +5.5V 400 200 0 SEE TEST CIRCUIT FIGURE 36 100k 10k FREQUENCY – Hz 1M 0 1 2 3 VDD 4 5 6 Figure 23. –3 dB Bandwidths Figure 24. Supply Current vs. Clock Frequency Figure 25. AD8403 Incremental Wiper ON Resistance vs. VDD 100 1 VDD = +5V GAIN – dB 0 –10 –20 IA SHUTDOWN CURRENT – nA IDD – SUPPLY CURRENT –µA LOGIC INPUT VOLTAGE = 0, VDD 0.1 PHASE – Degrees 0 –45 –90 VDD = +5V TA = +25°C WIPER SET AT HALF-SCALE 80H 10 VDD = +5.5V 0.01 VDD = +3.3V 100k 200k 400k 1M 2M 4M 6M 10M 1 –55 –35 –15 FREQUENCY – Hz 5 25 45 65 85 105 125 TEMPERATURE – °C 0.001 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE – °C Figure 26. 1 kΩ Gain and Phase vs. Frequency Figure 27. Shutdown Current vs. Temperature Figure 28. Supply Current vs. Temperature –10– REV. B Parametric Test Circuits–AD8400/AD8402/AD8403 DUT A V+ B W V+ = VDD 1LSB = V+/256 VMS A DUT B W +5V VOUT OP279 2.5V DC ~ VIN OFFSET GND Figure 29. Potentiometer Divider Nonlinearity Error Test Circuit (INL, DNL) Figure 33. Inverting Programmable Gain Test Circuit +5V NO CONNECT OP279 DUT A B VMS W OFFSET GND 2.5V A DUT B IW VIN VOUT ~ W Figure 30. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) Figure 34. Noninverting Programmable Gain Test Circuit IMS DUT A V+ B VMS W VW IW = 1V/RNOMINAL V+ ≈ VDD VW2 – [VW1 + IW (RAWII RBW)] RW = –––––––––––––––––––––––––– IW WHERE VW1 = VMS WHEN IW = 0 AND VW2 = VMS WHEN IW = 1/R A VIN OFFSET GND +15V W OP42 ~ DUT B 2.5V VOUT –15V Figure 31. Wiper Resistance Test Circuit Figure 35. Gain vs. Frequency Test Circuit VA DUT V+ ~ VDD A W B VMS RSW = 0.1V ISW W B CODE = ØØH ISW → V+ = VDD ± 10% PSRR (dB) = 20LOG ∆VMS% PSS (%/%) = ––––––– ∆VDD% MS ( ––––– ) ∆V DD ∆V 0.1V 0 toVDD Figure 32. Power Supply Sensitivity Test Circuit (PSS, PSRR) Figure 36. Incremental ON Resistance Test Circuit REV. B –11– AD8400/AD8402/AD8403 OPERATION The AD8400/AD8402/AD8403 provide a single, dual and quad channel, 256 position digitally controlled variable resistor (VR) device. Changing the programmed VR settings is accomplished by clocking in a 10-bit serial data word into the SDI (Serial Data Input) pin. The format of this data word is two address bits, MSB first, followed by eight data bits, MSB first. Table I provides the serial register data word format. The AD8400/ AD8402/AD8403 has the following address assignments for the ADDR decode, which determines the location of VR latch receiving the serial register data in Bits B7 through B0: VR# = A1 × 2 + A0 + 1 Equation 1 The single-channel AD8400 requires A1 = A0 = 0. The dualchannel AD8402 requires A1 = 0. VR settings can be changed one at a time in random sequence. The serial clock running at 10 MHz makes it possible to load all 4 VRs in under 4 µs (10 × 4 × 100 ns) for the AD8403. The exact timing requirements are shown in Figures 1a, 1b and 1c. The AD8402/AD8403 resets to midscale by asserting the RS pin, simplifying initial conditions at power up. Both parts have a power shutdown SHDN pin that places the VR in a zero power consumption state where terminals Ax are open circuited and the wiper Wx is connected to Bx resulting in only leakage currents being consumed in the VR structure. In shutdown mode the VR latch settings are maintained so that returning to operational mode from power shutdown, the VR settings return to their previous resistance values. The digital interface is still active in shutdown, except that SDO is deactivated. Code changes in the registers can be made that will produce new wiper positions when the device is taken out of shutdown. RS Ax PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation The nominal resistance of the VR (RDAC) between terminals A and B are available with values of 1 kΩ, 10 kΩ, 50 kΩ and 100 kΩ. The final digits of the part number determine the nominal resistance value, e.g., 10 kΩ = 10; 100 kΩ = 100. The nominal resistance (RAB) of the VR has 256 contact points accessed by the wiper terminal, plus the B terminal contact. The 8-bit data word in the RDAC latch is decoded to select one of the 256 possible settings. The wiper’s first connection starts at the B terminal for data 00H. This B terminal connection has a wiper contact resistance of 50 Ω. The second connection (10 kΩ part) is the first tap point located at 89 Ω [= RBA (nominal resistance)/256 + RW = 39 Ω + 50 Ω] for data 01H. The third connection is the next tap point representing 78 + 50 = 128 Ω for data 02H. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10011 Ω. The wiper does not directly connect to the B terminal. See Figure 37 for a simplified diagram of the equivalent RDAC circuit. The AD8400 contains one RDAC, the AD8402 contains two independent RDACs and the AD8403 contains four independent RDACs. The general transfer equation that determines the digitally programmed output resistance between Wx and Bx is: RWB (Dx) = (Dx)/256 × RBA + RW Equation 2 where Dx is the data contained in the 8-bit RDAC# latch, and RBA is the nominal end-to-end resistance. For example, when VB = 0 V and A terminal is open circuit, the following output resistance values will be set for the following RDAC latch codes (applies to 10 kΩ potentiometers): D (Dec) 255 128 1 0 RWB (Ω) 10011 5050 89 50 Output State Full Scale Midscale (RS = 0 Condition) 1 LSB Zero-Scale (Wiper Contact Resistance) SHDN D7 D6 D5 D4 D3 D2 D1 D0 RS RS Wx RDAC LATCH & DECODER RS RS = RNOMINAL/256 Bx Note in the zero-scale condition a finite wiper resistance of 50 Ω is present. Care should be taken to limit the current flow between W and B in this state to a maximum value of 5 mA to avoid degradation or possible destruction of the internal switch contact. Like the mechanical potentiometer the RDAC replaces, it is totally symmetrical. The resistance between the wiper W and terminal A also produces a digitally controlled resistance RWA. When these terminals are used the B terminal should be tied to the wiper. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the RDAC latch is increased in value. The general transfer equation for this operation is: RWA (Dx) = (256–Dx)/256 × RBA + RW Equation 3 Figure 37. AD8402/AD8403 Equivalent VR (RDAC) Circuit –12– REV. B AD8400/AD8402/AD8403 where Dx is the data contained in the 8-bit RDAC# latch, and RBA is the nominal end-to-end resistance. For example, when VA = 0 V and B terminal is open circuit, the following output resistance values will be set for the following RDAC latch codes (applies to 10 kΩ potentiometers): D (Dec) 255 128 1 0 RWA (Ω) 89 5050 10011 10050 Output State Full Scale Midscale (RS = 0 Condition) 1 LSB Zero Scale SDI suitable means. The Figure 38 block diagrams show more detail of the internal digital circuitry. When CS is taken active low, the clock loads data into the 10-bit serial register on each positive clock edge (see Table II). CS CLK EN ADDR DEC D7 R DAC LAT #1 VDD A1 W1 B1 A1 A0 D7 10-BIT SER REG DI D0 8 D0 AD8400 The typical distribution of RBA from channel-to-channel matches within ± 1%. However, device-to-device matching is process lot dependent having a ± 20% variation. The change in RBA with temperature has a positive 500 ppm/°C temperature coefficient. The wiper-to-end-terminal resistance temperature coefficient has the best performance over the 10% to 100% of adjustment range where the internal wiper contact switches do not contribute any significant temperature related errors. The graph in Figure 11 shows the performance of RWB tempco vs. code, using the trimmer with codes below 32 results in the larger temperature coefficients plotted. PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation GND a. CS CLK EN ADDR DEC D7 R DAC LAT #1 R AD8402 VDD A1 W1 B1 A1 A0 D7 10-BIT SER REG SDI DI D0 8 D0 The digital potentiometer easily generates an output voltage proportional to the input voltage applied to a given terminal. For example, connecting A terminal to +5 V and B terminal to ground produces an output voltage at the wiper starting at zero volts up to 1 LSB less than +5 V. Each LSB of voltage is equal to the voltage applied across terminal AB divided by the 256 position resolution of the potentiometer divider. The general equation defining the output voltage with respect to ground for any given input voltage applied to terminals AB is: VW (Dx) = Dx/256 × VAB + VB Equation 4 CS CLK D7 R DAC LAT #2 R A4 W4 B4 D0 SHDN DGND RS AGND b. VDD D7 EN ADDR DEC R DAC LAT #1 R A1 W1 B1 Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. Here the output voltage is dependent on the ratio of the internal resistors, not the absolute value; therefore, the temperature drift improves to 15 ppm/°C. At the lower wiper position settings, the potentiometer divider temperature coefficient increases due to the contributions of the CMOS switch wiper resistance becoming an appreciable portion of the total resistance from terminal B to the wiper. See Figure 10 for a plot of potentiometer tempco performance versus code setting. DIGITAL INTERFACING SDO DO A1 A0 D7 D0 SER REG AD8403 SDI DI D0 D7 R DAC LAT #4 R A4 W4 B4 The AD8400/AD8402/AD8403 contains a standard SPI compatible three-wire serial input control interface. The three inputs are clock (CLK), CS and serial data input (SDI). The positiveedge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. For best results use logic transitions faster than 1 V/µs. Standard logic families work well. If mechanical switches are used for product evaluation, they should be debounced by a flip-flop or other 8 D0 SHDN DGND RS AGND c. Figure 38. Block Diagrams REV. B –13– AD8400/AD8402/AD8403 Table II. Input Logic Control Truth Table AD8403 CS ADDR DECODE RDAC 1 RDAC 2 CLK CS L P L L RS H H SHDN Register Activity H H No SR effect, enables SDO pin. Shift One bit in from the SDI pin. The tenth previously entered bit is shifted out of the SDO pin. Load SR data into RDAC latch based on A1, A0 decode (Table III). No Operation. Sets all RDAC latches to midscale, wiper centered, and SDO latch cleared. Latches all RDAC latches to 80H. Open circuits all resistor A–terminals, connects W to B, turns off SDO output transistor. RDAC 4 CLK SDI SERIAL REGISTER X X X P H X H H L H H H Figure 39. Equivalent Input Control Logic The target RDAC latch is loaded with the last eight bits of the serial data word completing one DAC update. In the case of the AD8403 four separate 10-bit data words must be clocked in to change all four VR settings. SHDN CS SDI SERIAL REGISTER D Q SDO X X H H P H H L CK RS CLK RS NOTE: P = positive edge, X = don’t care, SR = shift register. The serial data-output (SDO) pin contains an open drain nchannel FET. This output requires a pull-up resistor in order to transfer data to the next package’s SDI pin. The pull-up resistor termination voltage may be larger than the VDD supply (but less than max VDD of +8 V) of the AD8403 SDO output device, e.g., the AD8403 could operate at VDD = 3.3 V and the pull-up for interface to the next device could be set at +5 V. This allows for daisy chaining several RDACs from a single processor serial data line. The clock period needs to be increased when using a pull-up resistor to the SDI pin of the following device in the series. Capacitive loading at the daisy chain node SDO–SDI between devices must be accounted for to successfully transfer data. When daisy chaining is used, the CS should be kept low until all the bits of every package are clocked into their respective serial registers insuring that the address bits and data bits are in the proper decoding location. This would require 20 bits of address and data complying to the word format provided in Table I if two AD8403 four-channel RDACs are daisy chained. Note, only the AD8403 has a SDO pin. During shutdown SHDN the SDO output pin is forced to the off (logic high state) to disable power dissipation in the pull up resistor. See Figure 40 for equivalent SDO output circuit schematic. The data setup and data hold times in the specification table determine the data valid time requirements. The last 10 bits of the data word entered into the serial register are held when CS returns high. At the same time CS goes high it gates the address decoder, which enables one of the two (AD8402) or four (AD8403) positive edge triggered RDAC latches. See Figure 39 detail and Table III Address Decode Table. Table III. Address Decode Table Figure 40. Detail SDO Output Schematic of the AD8403 All digital pins are protected with a series input resistor and parallel Zener ESD structure shown in Figure 41a. This structure applies to digital pins CS, SDI, SDO, RS, SHDN, CLK. The digital input ESD protection allows for mixed power supply applications where +5 V CMOS logic can be used to drive an AD8400/AD8402 or AD8403 operating from a +3 V power supply. The analog pins A, B, W are protected with a 20 Ω series resistor and parallel Zener, see Figure 41b. 1kΩ DIGITAL PINS LOGIC Figure 41a. Equivalent ESD Protection Circuits 20Ω A, B, W Figure 41b. Equivalent ESD Protection Circuit (Analog Pins) RDAC 10kΩ A CA DW ) + 30pF 256 CB DW ) + 30pF 256 B CW 120pF CA = 90.4pF · ( CB = 90.4pF · (1 – A1 0 0 1 1 A0 0 1 0 1 Latch Decoded RDAC#1 RDAC#2 RDAC#3 AD8403 Only RDAC#4 AD8403 Only W Figure 42. RDAC Circuit Simulation Model for RDAC = 10 kΩ –14– REV. B AD8400/AD8402/AD8403 The ac characteristics of the RDACs are dominated by the internal parasitic capacitances and the external capacitive loads. The –3 dB bandwidth of the AD8403AN10 (10 kΩ resistor) measures 600 kHz at half scale as a potentiometer divider. Figure 23 provides the large signal BODE plot characteristics of the three available resistor versions 10 kΩ, 50 kΩ, and 100 kΩ. The gain flatness versus frequency graph, Figure 26, predicts filter applications performance. A parasitic simulation model has been developed, and is shown in Figure 42. Listing I provides a macro model net list for the 10 kΩ RDAC: Listing I. Macro Model Net List for RDAC .PARAM DW=255, RDAC=10E3 * .SUBCKT DPOT (A,W,) * CA A 0 {DW/256*90.4E-12+30E-12} RAW A W {(1-DW/256)*RDAC+50} CW W 0 120E-12 RBW W B {DW/256*RDAC+50} CB B 0 {(1-DW/256)*90.4E-12+30E-12} * .ENDS DPOT The total harmonic distortion plus noise (THD+N) is measured at 0.003% in an inverting op amp circuit using an offset ground and a rail-to-rail OP279 amplifier, Figure 33. Thermal noise is primarily Johnson noise, typically 9 nV/√Hz for the 10 kΩ version at f = 1 kHz. For the 100 kΩ device, thermal noise becomes 29 nV/√Hz. Channel-to-channel crosstalk measures less than –65 dB at f = 100 kHz. To achieve this isolation, the extra ground pins provided on the package to segregate the individual RDACs must be connected to circuit ground. AGND and DGND pins should be at the same voltage potential. Any unused potentiometers in a package should be connected to ground. Power supply rejection is typically –35 dB at 10 kHz (care is needed to minimize power supply ripple in high accuracy applications). APPLICATIONS Certain boundary conditions must be satisfied for proper AD8400/AD8402/AD8403 operation. First, all analog signals must remain within the 0 to VDD range used to operate the single-supply AD8400/AD8402/AD8403 products. For standard potentiometer divider applications, the wiper output can be used directly. For low resistance loads, buffer the wiper with a suitable rail-to-rail op amp such as the OP291 or the OP279. Second, for ac signals and bipolar dc adjustment applications, a virtual ground will generally be needed. Whatever method is used to create the virtual ground, the result must provide the necessary sink and source current for all connected loads, including adequate bypass capacitance. Figure 33 shows one channel of the AD8402 connected in an inverting programmable gain amplifier circuit. The virtual ground is set at +2.5 V which allows the circuit output to span a ± 2.5 volt range with respect to virtual ground. The rail-to-rail amplifier capability is necessary for the widest output swing. As the wiper is adjusted from its midscale reset position (80H) toward the A terminal (code FFH), the voltage gain of the circuit is increased in successfully larger increments. Alternatively, as the wiper is adjusted toward the B terminal (code 00H), the signal becomes attenuated. The plot in Figure 43 shows the wiper settings for a 100:1 range of voltage gain (V/V). Note the ± 10 dB of pseudologarithmic gain around 0 dB (1 V/V). This circuit is mainly useful for gain adjustments in the range of 0.14 V/V to 4 V/V; beyond this range the step sizes become very large and the resistance of the driving circuit can become a significant term in the gain equation. 256 224 DIGITAL CODE – Decimal 192 160 128 96 64 32 0 0.1 1.0 INVERTING GAIN – V/V 10 The digital potentiometer (RDAC) allows many of the applications of trimming potentiometers to be replaced by a solid-state solution offering compact size, freedom from vibration, shock and open contact problems encountered in hostile environments. A major advantage of the digital potentiometer is its programmability. Any settings can be saved for later recall in system memory. The two major configurations of the RDAC include the potentiometer divider (basic 3-terminal application) and the rheostat (2-terminal configuration) connections shown in Figures 29 and 30. Figure 43. Inverting Programmable Gain Plot REV. B –15– AD8400/AD8402/AD8403 ACTIVE FILTER 40 –0.16 20 20.0000 k One of the standard circuits used to generate a low-pass, highpass or bandpass filter is the state variable active filter. The digital potentiometer allows full programmability of the frequency, gain and Q of the filter outputs. Figure 44 shows the filter circuit using a +2.5 V virtual ground, which allows a ± 2.5 VP input and output swing. RDAC2 and 3 set the LP, HP and BP cutoff and center frequencies respectively. These variable resistors should be programmed with the same data (as with ganged potentiometers) to maintain the best circuit Q. Figure 45 shows the measured filter response at the bandpass output as a function of the RDAC2 and RDAC3 settings which produce a range of center frequencies from 2 kHz to 20 kHz. The filter gain response at the bandpass output is shown in Figure 46. At a center frequency of 2 kHz, the gain is adjusted over a –20 dB to +20 dB range determined by RDAC1. Circuit Q is adjusted by RDAC4. For more detailed reading on the state variable active filter, see Analog Devices’ application note, AN-318. 10k RDAC4 B VIN 10k 0.01µF 0.01µF B RDAC1 A1 A2 RDAC2 ± 2.5V OP279 × 2 A3 RDAC3 A4 BANDPASS B B HIGHPASS AMPLITUDE – dB 0 –20 –40 –60 –80 20 100 1k 10k FREQUENCY – Hz 100k 200k Figure 45. Programmed Center Frequency Bandpass Response 40 –19.01 20 2.00000 k ~ AMPLITUDE – dB LOWPASS 0 –20 –40 Figure 44. Programmable State Variable Active Filter –60 –80 20 100 1k 10k FREQUENCY – Hz 100k 200k Figure 46. Programmed Amplitude Bandpass Response –16– REV. B AD8400/AD8402/AD8403 OUTLINE DIMENSIONS Dimensions shown in inches and (mm) 8-Pin Plastic DIP (N-8) 0.430 (10.92) 0.348 (8.84) 8 5 8-Lead SOIC (SO-8) 0.1968 (5.00) 0.1890 (4.80) 8 1 5 4 0.280 (7.11) 0.240 (6.10) 1 4 0.1574 (4.00) 0.1497 (3.80) 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.2440 (6.20) 0.2284 (5.80) PIN 1 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN SEATING PLANE PIN 1 0.0098 (0.25) 0.0040 (0.10) 0.0688 (1.75) 0.0532 (1.35) 0.0196 (0.50) x 45° 0.0099 (0.25) 0.022 (0.558) 0.100 0.070 (1.77) 0.014 (0.356) (2.54) 0.045 (1.15) BSC 0.015 (0.381) 0.008 (0.204) SEATING PLANE 0.0500 0.0192 (0.49) (1.27) 0.0138 (0.35) BSC 0.0098 (0.25) 0.0075 (0.19) 8° 0° 0.0500 (1.27) 0.0160 (0.41) 14-Pin Plastic DIP Package (N-14) 14 PIN 1 1 0.795 (20.19) 0.725 (18.42) 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 7 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 8 0.280 (7.11) 0.240 (6.10) PIN 1 14-Pin Narrow Body SOIC Package (SO-14) 14 8 0.1574 (4.00) 0.1497 (3.80) 1 7 0.2440 (6.20) 0.2284 (5.80) 0.3444 (8.75) 0.3367 (8.55) 0.0688 (1.75) 0.0532 (1.35) 0.0098 (0.25) 0.0040 (0.10) 0.0500 (1.27) BSC 0.0192 (0.49) 0.0138 (0.35) 8° 0° 0.0196 (0.50) x 45 ° 0.0099 (0.25) 0.130 (3.30) MIN SEATING PLANE 0.015 (0.381) 0.008 (0.204) 0.100 (2.54) BSC 0.070 (1.77) 0.045 (1.15) 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 14-Lead TSSOP (RU-14) 0.201 (5.10) 0.193 (4.90) 14 8 0.177 (4.50) 0.169 (4.30) 1 7 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX 0.0256 (0.65) BSC 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) 0.256 (6.50) 0.246 (6.25) SEATING PLANE 8° 0° 0.028 (0.70) 0.020 (0.50) REV. B –17– AD8400/AD8402/AD8403 24-Pin Narrow Body Plastic DIP Package (N-24) 24 PIN 1 1 12 13 0.280 (7.11) 0.240 (6.10) 1.275 (32.30) 1.125 (28.60) 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.92) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.070 (1.77) 0.045 (1.15) 0.015 (0.38) MIN 0.130 (3.30) MIN 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) SEATING PLANE 0.015 (0.381) 0.008 (0.203) 24-Pin SOIC Package (SOL-24) 24 13 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) PIN 1 1 12 0.6141 (15.60) 0.5985 (15.20) 0.1043 (2.65) 0.0926 (2.35) 0.0291 (0.74) x 45 ° 0.0098 (0.25) 0.0118 (0.30) 0.0040 (0.10) 0.0500 (1.27) BSC 0.0192 (0.49) 0.0138 (0.35) 0.0125 (0.32) 0.0091 (0.23) 8° 0° 0.0500 (1.27) 0.0157 (0.40) 24-Lead Thin Surface Mount TSSOP Package (RU-24) 0.311 (7.90) 0.303 (7.70) 24 13 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 1 12 0.006 (0.15) 0.002 (0.05) PIN 1 0.0433 (1.10) MAX 0.0256 (0.65) BSC 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) 8° 0° 0.246 (6.25) 0.028 (0.70) 0.020 (0.50) SEATING PLANE –18– REV. B – 19– –20– C1997b–12–1/97 PRINTED IN U.S.A.