PIN CONFIGURATIONS
Low offset voltage: 1 μV
Input offset drift: 0.005 μV/°C
Rail-to-rail input and output swing
5 V/2.7 V single-supply operation
High gain, CMRR, PSRR: 130 dB
Ultralow input bias current: 20 pA
Low supply current: 700 μA/op amp
Overload recovery time: 50 μs
No external capacitors required
1
NC
–IN A
+IN A
V–
8
NC
V+
OUT A
NC
AD8551
4
5
NC = NO CONNECT
01101-001
FEATURES
Figure 1. 8-Lead MSOP (RM Suffix)
8 NC
+IN A 3
AD8551
V– 4
APPLICATIONS
7 V+
6 OUT A
5 NC
NC = NO CONNECT
Temperature sensors
Pressure sensors
Precision current sensing
Strain gage amplifiers
Medical instrumentation
Thermocouple amplifiers
01101-002
NC 1
–IN A 2
Figure 2. 8-Lead SOIC (R Suffix)
OUT A
–IN A
+IN A
V–
1
8
AD8552
4
5
V+
OUT B
–IN B
+IN B
01101-003
Data Sheet
Zero-Drift, Single-Supply, Rail-to-Rail
Input/Output Operational Amplifiers
AD8551/AD8552/AD8554
Figure 3. 8-Lead TSSOP (RU Suffix)
GENERAL DESCRIPTION
With an offset voltage of only 1 μV and drift of 0.005 μV/°C, the
AD8551/AD8552/AD8554 are perfectly suited for applications
in which error sources cannot be tolerated. Temperature,
position and pressure sensors, medical equipment, and strain
gage amplifiers benefit greatly from nearly zero drift over their
operating temperature range. The rail-to-rail input and output
swings provided by the AD8551/AD8552/AD8554 make both
high-side and low-side sensing easy.
The AD8551/AD8552/AD8554 are specified for the extended
industrial/automotive temperature range (−40°C to +125°C).
The AD8551 single amplifier is available in 8-lead MSOP and
8-lead narrow SOIC packages. The AD8552 dual amplifier is
available in 8-lead narrow SOIC and 8-lead TSSOP surfacemount packages. The AD8554 quad is available in 14-lead
narrow SOIC and 14-lead TSSOP packages.
Rev. F
+IN A 3
8 V+
AD8552
V– 4
7 OUT B
6 –IN B
5 +IN B
01101-004
–IN A 2
Figure 4. 8-Lead SOIC (R Suffix)
OUT A
–IN A
+IN A
V+
+IN B
–IN B
OUT B
1
14
AD8554
7
8
OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C
01101-005
The AD8551/AD8552/AD8554 provide the benefits previously
found only in expensive auto-zeroing or chopper-stabilized
amplifiers. Using Analog Devices, Inc. topology, these new
zero-drift amplifiers combine low cost with high accuracy. No
external capacitors are required.
OUT A 1
Figure 5. 14-Lead TSSOP (RU Suffix)
OUT A 1
14 OUT D
–IN A 2
13 –IN D
+IN A 3
12 +IN D
V+ 4
AD8554
11 V–
+IN B 5
10 +IN C
–IN B 6
9 –IN C
OUT B 7
8 OUT C
01101-006
This family of amplifiers has ultralow offset, drift, and bias
current. The AD8551, AD8552, and AD8554 are single, dual,
and quad amplifiers featuring rail-to-rail input and output swings.
All are guaranteed to operate from 2.7 V to 5 V with a single supply.
Figure 6. 14-Lead SOIC (R Suffix)
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Technical Support
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AD8551/AD8552/AD8554
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
1/f Noise Characteristics ........................................................... 16
Applications ....................................................................................... 1
Intermodulation Distortion ...................................................... 17
General Description ......................................................................... 1
Broadband and External Resistor Noise Considerations ...... 18
Pin Configurations ........................................................................... 1
Output Overdrive Recovery...................................................... 18
Revision History ............................................................................... 2
Input Overvoltage Protection ................................................... 18
Specifications..................................................................................... 3
Output Phase Reversal ............................................................... 18
Electrical Characteristics ............................................................. 3
Capacitive Load Drive ............................................................... 19
Absolute Maximum Ratings............................................................ 5
Power-Up Behavior .................................................................... 19
Thermal Characteristics .............................................................. 5
Applications Information .............................................................. 20
ESD Caution .................................................................................. 5
A 5 V Precision Strain Gage Circuit ........................................ 20
Typical Performance Characteristics ............................................. 6
3 V Instrumentation Amplifier ................................................ 20
Functional Description .................................................................. 14
A High Accuracy Thermocouple Amplifier ........................... 21
Amplifier Architecture .............................................................. 14
Precision Current Meter ............................................................ 21
Basic Auto-Zero Amplifier Theory .......................................... 14
Precision Voltage Comparator.................................................. 21
High Gain, CMRR, PSRR .......................................................... 15
Outline Dimensions ....................................................................... 22
Maximizing Performance Through Proper Layout ............... 16
Ordering Guide .......................................................................... 24
REVISION HISTORY
6/15—Rev. E to Rev. F
Change to Input Voltage Parameter, Table 3 ................................. 5
3/07—Rev. B to Rev. C
Changes to Specifications Section ...................................................3
11/12—Rev.D to Rev. E
Changes to Figure 68 ...................................................................... 21
Updated Outline Dimensions (RM-8) ......................................... 22
Changes to Ordering Guide .......................................................... 24
2/07—Rev. A to Rev. B
Updated Format .................................................................. Universal
Changes to Figure 54...................................................................... 16
Deleted Spice Model Section ........................................................ 19
Deleted Figure 63, Renumbered Sequentially ............................ 19
Changes to Ordering Guide .......................................................... 24
9/08—Rev. C to Rev. D
Changes to Ordering Guide .......................................................... 23
11/02—Rev. 0 to Rev. A
Edits to Figure 60 ............................................................................ 16
Updated Outline Dimensions ....................................................... 20
Rev. F | Page 2 of 24
Data Sheet
AD8551/AD8552/AD8554
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VS = 5 V, VCM = 2.5 V, VO = 2.5 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Symbol
Conditions
Min
VOS
Typ
Max
Unit
1
5
10
50
1.5
300
4
70
200
150
400
5
μV
μV
pA
nA
pA
nA
pA
pA
pA
pA
V
dB
dB
dB
dB
μV/°C
−40°C ≤ TA ≤ +125°C
Input Bias Current
AD8551/AD8554
AD8552
AD8552
Input Offset Current
AD8551/AD8554
AD8552
AD8552
Input Voltage Range
Common-Mode Rejection Ratio
CMRR
Large Signal Voltage Gain1
AVO
Offset Voltage Drift
OUTPUT CHARACTERISTICS
Output Voltage High
IB
10
1.0
160
2.5
20
150
30
150
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
IOS
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
ΔVOS/ΔT
VOH
Output Voltage Low
VOL
Output Short-Circuit Limit Current
ISC
VCM = 0 V to +5 V
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ, VO = 0.3 V to 4.7 V
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
RL = 100 kΩ to GND
RL = 100 kΩ to GND @ −40°C to +125°C
RL = 10 kΩ to GND
RL = 10 kΩ to GND @ −40°C to +125°C
RL = 100 kΩ to V+
RL = 100 kΩ to V+ @ −40°C to +125°C
RL = 10 kΩ to V+
RL = 10 kΩ to V+ @ −40°C to +125°C
0
120
115
125
120
4.99
4.99
4.95
4.95
±25
−40°C to +125°C
Output Current
IO
−40°C to +125°C
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
DYNAMIC PERFORMANCE
Slew Rate
Overload Recovery Time
Gain Bandwidth Product
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
1
PSRR
ISY
SR
VS = 2.7 V to 5.5 V
−40°C ≤ TA ≤ +125°C
VO = 0 V
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ
GBP
en p-p
en p-p
en
in
0 Hz to 10 Hz
0 Hz to 1 Hz
f = 1 kHz
f = 10 Hz
Gain testing is dependent upon test bandwidth.
Rev. F | Page 3 of 24
120
115
140
130
145
135
0.005
4.998
4.997
4.98
4.975
1
2
10
15
±50
±40
±30
±15
130
130
850
1000
0.4
0.05
1.5
1.0
0.32
42
2
0.04
10
10
30
30
975
1075
0.3
V
V
V
V
mV
mV
mV
mV
mA
mA
mA
mA
dB
dB
μA
μA
V/μs
ms
MHz
μV p-p
μV p-p
nV/√Hz
fA/√Hz
AD8551/AD8552/AD8554
Data Sheet
VS = 2.7 V, VCM = 1.35 V, VO = 1.35 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
Symbol
Conditions
Min
VOS
Typ
Max
Unit
1
5
10
50
1.5
300
4
50
200
150
400
2.7
μV
μV
pA
nA
pA
nA
pA
pA
pA
pA
V
dB
dB
dB
dB
μV/°C
−40°C ≤ TA ≤ +125°C
Input Bias Current
AD8551/AD8554
AD8552
AD8552
Input Offset Current
AD8551/AD8554
AD8552
AD8552
Input Voltage Range
Common-Mode Rejection Ratio
IB
Large Signal Voltage Gain1
AVO
Offset Voltage Drift
OUTPUT CHARACTERISTICS
Output Voltage High
10
1.0
160
2.5
10
150
30
150
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
IOS
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +125°C
CMRR
ΔVOS/ΔT
VOH
Output Voltage Low
VOL
Short-Circuit Limit
ISC
VCM = 0 V to 2.7 V
−40°C ≤ TA ≤ +125°C
RL = 10 kΩ, VO = 0.3 V to 2.4 V
−40°C ≤ TA ≤ +125°C
−40°C ≤ TA ≤ +125°C
RL = 100 kΩ to GND
RL = 100 kΩ to GND @ −40°C to +125°C
RL = 10 kΩ to GND
RL = 10 kΩ to GND @ −40°C to +125°C
RL = 100 kΩ to V+
RL = 100 kΩ to V+ @ −40°C to +125°C
RL = 10 kΩ to V+
RL = 10 kΩ to V+ @ −40°C to +125°C
0
115
110
110
105
2.685
2.685
2.67
2.67
±10
−40°C to +125°C
Output Current
IO
−40°C to +125°C
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current/Amplifier
DYNAMIC PERFORMANCE
Slew Rate
Overload Recovery Time
Gain Bandwidth Product
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
1
PSRR
ISY
SR
VS = 2.7 V to 5.5 V
−40°C ≤ TA ≤ +125°C
VO = 0 V
−40°C ≤ TA ≤ +125°C
2.697
2.696
2.68
2.675
1
2
10
15
±15
±10
±10
±5
130
130
750
950
0.04
10
10
20
20
900
1000
V
V
V
V
mV
mV
mV
mV
mA
mA
mA
mA
dB
dB
μA
μA
RL = 10 kΩ
0.5
0.05
1
V/μs
ms
MHz
0 Hz to 10 Hz
f = 1 kHz
f = 10 Hz
1.6
75
2
μV p-p
nV/√Hz
fA/√Hz
GBP
en p-p
en
in
120
115
130
130
140
130
0.005
Gain testing is dependent upon test bandwidth.
Rev. F | Page 4 of 24
Data Sheet
AD8551/AD8552/AD8554
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Table 3.
Parameter
Supply Voltage
Input Voltage
Differential Input Voltage1
ESD (Human Body Model)
Output Short-Circuit Duration to GND
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature Range
(Soldering, 60 sec)
1
Rating
6V
GND −0.3 V to VS + 0.3 V
±5.0 V
2000 V
Indefinite
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
Table 4.
Package Type
8-Lead MSOP (RM)
8-Lead TSSOP (RU)
8-Lead SOIC (R)
14-Lead TSSOP (RU)
14-Lead SOIC (R)
ESD CAUTION
Differential input voltage is limited to ±5.0 V or the supply voltage,
whichever is less.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. F | Page 5 of 24
θJA
190
240
158
180
120
θJC
44
43
43
36
36
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
AD8551/AD8552/AD8554
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
180
180
NUMBER OF AMPLIFIERS
140
120
100
80
60
140
120
100
80
60
40
40
20
20
0
–2.5
–1.5
–0.5
1.5
0.5
OFFSET VOLTAGE (µV)
VSY = 5V
VCM = 2.5V
TA = 25°C
160
0
–2.5
01101-007
NUMBER OF AMPLIFIERS
160
2.5
–1.5
Figure 7. Input Offset Voltage Distribution at 2.7 V
2.5
Figure 10. Input Offset Voltage Distribution at 5 V
12
50
VSY = 5V
TA = –40°C, +25°C, +85°C
40
VSY = 5V
VCM = 2.5V
TA = –40°C TO +125°C
10
+85°C
30
NUMBER OF AMPLIFIERS
INPUT BIAS CURRENT (pA)
0.5
–0.5
1.5
OFFSET VOLTAGE (µV)
01101-010
VSY = 2.7V
VCM = 1.35V
TA = 25°C
20
10
+25°C
0
–40°C
–10
8
6
4
2
0
1
4
2
3
INPUT COMMON-MODE VOLTAGE (V)
0
01101-008
–30
5
Figure 8. Input Bias Current vs. Common-Mode Voltage
1500
1
0
2
3
4
INPUT OFFSET DRIFT (nV/°C)
5
6
01101-011
–20
Figure 11. Input Offset Voltage Drift Distribution at 5 V
10k
VSY = 5V
TA = 125°C
VSY = 5V
TA = 25°C
1000
OUTPUT VOLTAGE (mV)
500
0
–500
–1000
100
SOURCE
10
SINK
1
–2000
0
1
4
2
3
INPUT COMMON-MODE VOLTAGE (V)
5
0.1
0.0001
Figure 9. Input Bias Current vs. Common-Mode Voltage
0.001
0.01
0.1
1
LOAD CURRENT (mA)
10
100
Figure 12. Output Voltage to Supply Rail vs. Load Current at 5 V
Rev. F | Page 6 of 24
01101-012
–1500
01101-009
INPUT BIAS CURRENT (pA)
1k
Data Sheet
AD8551/AD8552/AD8554
800
10k
TA = +25°C
100
SOURCE
10
SINK
1
1
0.01
0.1
LOAD CURRENT (mA)
0.001
100
10
500
400
300
200
100
0
01101-013
0.1
0.0001
600
3
4
2
SUPPLY VOLTAGE (V)
5
6
Figure 16. Supply Current per Amplifier vs. Supply Voltage
Figure 13. Output Voltage to Supply Rail vs. Load Current at 2.7 V
60
0
VCM = 2.5V
VSY = 5V
50
40
OPEN-LOOP GAIN (dB)
–250
–500
–750
VSY = 2.7V
CL = 0pF
RL = ∞
0
30
45
20
90
10
135
0
180
–10
225
–20
270
–25
75
0
25
50
TEMPERATURE (°C)
100
125
150
–40
10k
1M
FREQUENCY (Hz)
10M
100M
Figure 17. Open-Loop Gain and Phase Shift vs. Frequency at 2.7 V
Figure 14. Input Bias Current vs. Temperature
60
1.0
VCM = 2.5V
VSY = 5V
100k
50
5V
40
OPEN-LOOP GAIN (dB)
0.8
2.7V
0.6
0.4
0.2
VSY = 5V
CL = 0pF
RL = ∞
0
30
45
20
90
10
135
0
180
–10
225
–20
270
PHASE SHIFT (Degrees)
–50
01101-014
–1000
–75
01101-017
–30
0
–75
–50
–25
0
75
25
50
TEMPERATURE (°C)
100
125
150
–40
10k
100k
1M
FREQUENCY (Hz)
10M
100M
Figure 18. Open-Loop Gain and Phase Shift vs. Frequency at 5 V
Figure 15. Supply Current vs. Temperature
Rev. F | Page 7 of 24
01101-018
–30
01101-015
SUPPLY CURRENT (mA)
INPUT BIAS CURRENT (pA)
1
0
PHASE SHIFT (Degrees)
OUTPUT VOLTAGE (mV)
1k
700
01101-016
SUPPLY CURRENT PER AMPLIFIER (µA)
VSY = 2.7V
TA = 25°C
AD8551/AD8552/AD8554
Data Sheet
60
300
50
AV = –100
270
240
OUTPUT IMPEDANCE (Ω)
40
CLOSED-LOOP GAIN (dB)
VSY = 5V
VSY = 2.7V
CL = 0pF
RL = 2kΩ
30
20
AV = –10
10
AV = +1
0
–10
210
180
150
120
AV = 100
90
–20
60
–30
30
AV = 10
1k
10k
100k
FREQUENCY (Hz)
1M
10M
0
100
01101-019
–40
100
Figure 19. Closed-Loop Gain vs. Frequency at 2.7 V
1k
1M
10k
100k
FREQUENCY (Hz)
10M
Figure 22. Output Impedance vs. Frequency at 5 V
60
AV = –100
40
CLOSED-LOOP GAIN (dB)
VSY = 2.7V
CL = 300pF
RL = 2kΩ
AV = 1
VSY = 5V
CL = 0pF
RL = 2kΩ
50
30
20
AV = –10
10
AV = +1
0
–10
–30
1k
10k
100k
FREQUENCY (Hz)
1M
10M
500mV
01101-020
2µs
–40
100
Figure 20. Closed-Loop Gain vs. Frequency at 5 V
01101-023
–20
Figure 23. Large Signal Transient Response at 2.7 V
300
270
VSY = 5V
CL = 300pF
RL = 2kΩ
AV = 1
VSY = 2.7V
210
180
150
120
90
AV = 100
60
0
100
AV = 1
1k
10k
100k
FREQUENCY (Hz)
1M
5µs
10M
1V
Figure 21. Output Impedance vs. Frequency at 2.7 V
Figure 24. Large Signal Transient Response at 5 V
Rev. F | Page 8 of 24
01101-024
AV = 10
30
01101-021
OUTPUT IMPEDANCE (Ω)
240
01101-022
AV = 1
Data Sheet
AD8551/AD8552/AD8554
45
VSY = ±1.35V
CL = 50pF
VSY = ±2.5V
RL = 2kΩ
TA = 25°C
40
35
30
25
20
+OS
15
–OS
10
5
0
10
Figure 25. Small Signal Transient Response at 2.7 V
100
1k
CAPACITANCE (pF)
10k
Figure 28. Small Signal Overshoot vs. Load Capacitance at 5 V
VSY = ±2.5V
CL = 50pF
0V
RL = ∞
AV = 1
VIN
VSY = ±2.5V
VIN = –200mV p-p
(RET TO GND)
CL = 0pF
RL = 10kΩ
AV = –100
VOUT
0V
20µs
1V
01101-029
01101-026
50mV
5µs
BOTTOM SCALE: 1V/DIV
TOP SCALE: 200mV/DIV
Figure 29. Positive Overvoltage Recovery
Figure 26. Small Signal Transient Response at 5 V
50
VSY = ±1.35V
RL = 2kΩ
TA = 25°C
VIN
40
0V
35
30
25
+OS
0V
20
15
–OS
10
VOUT
5
20µs
100
1k
CAPACITANCE (pF)
10k
01101-027
0
10
VSY = ±2.5V
VIN = 200mV p-p
(RET TO GND)
CL = 0pF
RL = 10kΩ
AV = –100
1V
BOTTOM SCALE: 1V/DIV
TOP SCALE: 200mV/DIV
Figure 30. Negative Overvoltage Recovery
Figure 27. Small Signal Overshoot vs. Load Capacitance at 2.7 V
Rev. F | Page 9 of 24
01101-030
SMALL SIGNAL OVERSHOOT (%)
45
01101-028
50mV
5µs
01101-025
SMALL SIGNAL OVERSHOOT (%)
RL = ∞
AV = 1
AD8551/AD8552/AD8554
Data Sheet
140
VS = ±2.5V
RL = 2kΩ
AV = –100
VIN = 60mV p-p
VSY = ±1.35V
120
PSRR (dB)
100
80
60
+PSRR
40
0
100
1M
10M
Figure 34. PSRR vs. Frequency at ±1.35 V
Figure 31. No Phase Reversal
140
140
VSY = 2.7V
VSY = ±2.5V
120
120
100
100
PSRR (dB)
CMRR (dB)
100k
10k
FREQUENCY (Hz)
1k
01101-034
20
01101-031
1V
200µs
–PSRR
80
60
80
+PSRR
60
40
40
20
20
1k
10k
100k
FREQUENCY (Hz)
1M
10M
0
100
01101-032
0
100
Figure 32. CMRR vs. Frequency at 2.7 V
10k
100k
FREQUENCY (Hz)
1k
10M
Figure 35. PSRR vs. Frequency at ±2.5 V
140
3.0
VSY = ±1.35V
RL = 2kΩ
AV = 1
THD+N < 1%
TA = 25°C
VSY = 5V
120
OUTPUT SWING (V p-p)
2.5
100
80
60
40
1.5
1.0
1k
10k
100k
FREQUENCY (Hz)
1M
10M
Figure 33. CMRR vs. Frequency at 5 V
0
100
1k
10k
FREQUENCY (Hz)
100k
1M
Figure 36. Maximum Output Swing vs. Frequency at 2.7 V
Rev. F | Page 10 of 24
01101-036
0
100
2.0
0.5
20
01101-033
CMRR (dB)
1M
01101-035
–PSRR
Data Sheet
AD8551/AD8552/AD8554
5.5
VSY = ±2.5V
RL = 2kΩ
AV = 1
THD+N < 1%
TA = 25°C
5.0
156
en (nV/√Hz)
3.5
3.0
2.5
2.0
130
104
78
1.5
52
1.0
1k
10k
FREQUENCY (Hz)
100k
1M
01101-037
0
100
0
0.5
1.0
1.5
FREQUENCY (kHz)
2.0
2.5
01101-040
26
0.5
Figure 40. Voltage Noise Density at 2.7 V from 0 Hz to 2.5 kHz
Figure 37. Maximum Output Swing vs. Frequency at 5 V
VSY = ±1.35V
AV = 10000
VSY = 2.7V
RS = 0Ω
112
en (nV/√Hz)
96
0V
80
64
48
32
2mV
0
Figure 38. 0.1 Hz to 10 Hz Noise at 2.7 V
5
10
15
FREQUENCY (kHz)
20
25
01101-041
16
01101-038
1s
Figure 41. Voltage Noise Density at 2.7 V from 0 Hz to 25 kHz
VSY = ±2.5V
AV = 10000
VSY = 5V
RS = 0Ω
91
en (nV/√Hz)
78
65
52
39
26
2mV
13
0
Figure 39. 0.1 Hz to 10 Hz Noise at 5 V
0.5
1.0
1.5
FREQUENCY (kHz)
2.0
2.5
Figure 42. Voltage Noise Density at 5 V from 0 Hz to 2.5 kHz
Rev. F | Page 11 of 24
01101-042
1s
01101-039
OUTPUT SWING (V p-p)
4.5
4.0
VSY = 2.7V
RS = 0Ω
182
AD8551/AD8552/AD8554
Data Sheet
150
VSY = 5V
RS = 0Ω
VSY = 2.7V TO 5.5V
POWER SUPPLY REJECTION (dB)
112
en (nV/√Hz)
96
80
64
48
32
145
140
135
130
5
10
15
FREQUENCY (kHz)
20
25
125
–75
01101-043
0
Figure 43. Voltage Noise Density at 5 V from 0 Hz to 25 kHz
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
150
01101-045
16
Figure 45. Power Supply Rejection vs. Temperature
50
VSY = 5V
RS = 0Ω
VSY = 2.7V
40
SHORT-CIRCUIT CURRENT (mA)
168
120
96
72
48
24
30
ISC–
20
10
0
ISC+
–10
–20
–30
0
5
FREQUENCY (Hz)
10
–50
–75
Figure 44. Voltage Noise Density at 5 V from 0 Hz to 10 Hz
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
150
Figure 46. Output Short-Circuit Current vs. Temperature
Rev. F | Page 12 of 24
01101-046
–40
01101-044
en (nV/√Hz)
144
Data Sheet
AD8551/AD8552/AD8554
100
250
SHORT-CIRCUIT CURRENT (mA)
ISC–
60
40
20
0
–20
ISC+
–40
–60
–100
–75
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
150
01101-047
–80
VSY = 2.7V
225
200
175
150
RL = 1kΩ
100
75
RL = 100kΩ
25
0
–75
RL = 10kΩ
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
150
01101-048
OUTPUT VOLTAGE TO SUPPLY RAIL (mV)
250
50
200
175
150
RL = 1kΩ
125
100
75
50
RL = 10kΩ
25
0
–75
–50
–25
0
25
50
75
TEMPERATURE (°C)
RL = 100kΩ
100
125
150
Figure 49. Output Voltage to Supply Rail vs. Temperature
Figure 47. Output Short-Circuit Current vs. Temperature
125
VSY = 5.0V
225
Figure 48. Output Voltage to Supply Rail vs. Temperature
Rev. F | Page 13 of 24
01101-049
OUTPUT VOLTAGE TO SUPPLY RAIL (mV)
VSY = 5.0V
80
AD8551/AD8552/AD8554
Data Sheet
FUNCTIONAL DESCRIPTION
The AD8551/AD8552/AD8554 are CMOS amplifiers and
achieve their high degree of precision through auto-zero
stabilization. This autocorrection topology allows the
AD8551/AD8552/AD8554 to maintain its low offset voltage
over a wide temperature range and over its operating lifetime.
AMPLIFIER ARCHITECTURE
Each AD8551/AD8552/AD8554 op amps consist of two
amplifiers, a main amplifier and a secondary amplifier, used
to correct the offset voltage of the main amplifier. Both consist
of a rail-to-rail input stage, allowing the input common-mode
voltage range to reach both supply rails. The input stage consists
of an NMOS differential pair operating concurrently with a
parallel PMOS differential pair. The outputs from the
differential input stages are combined in another gain stage
whose output is used to drive a rail-to-rail output stage.
The wide voltage swing of the amplifier is achieved by using two
output transistors in a common-source configuration. The output
voltage range is limited by the drain-to-source resistance of
these transistors. As the amplifier is required to source or sink
more output current, the rDS of these transistors increases, raising
the voltage drop across these transistors. Simply put, the output
voltage does not swing as close to the rail under heavy output
current conditions as it does with light output current. This is a
characteristic of all rail-to-rail output amplifiers. Figure 12 and
Figure 13 show how close the output voltage can get to the rails
with a given output current. The output of the AD8551/AD8552/
AD8554 is short-circuit protected to approximately 50 mA of
current.
some improvements made over time. The AD8551/AD8552/
AD8554 design offers a number of significant performance
improvements over previous versions while attaining a very
substantial reduction in device cost. This section offers a simplified
explanation of how the AD8551/AD8552/AD8554 are able to
offer extremely low offset voltages and high open-loop gains.
As noted in the Amplifier Architecture section, each AD8551/
AD8552/AD8554 op amp contains two internal amplifiers. One
is used as the primary amplifier, the other as an autocorrection,
or nulling, amplifier. Each amplifier has an associated input
offset voltage that can be modeled as a dc voltage source in
series with the noninverting input. In Figure 50 and Figure 51
these are labeled as VOSX, where x denotes the amplifier
associated with the offset: A for the nulling amplifier and B for
the primary amplifier. The open-loop gain for the +IN and −IN
inputs of each amplifier is given as AX. Both amplifiers also have
a third voltage input with an associated open-loop gain of BX.
There are two modes of operation determined by the action of
two sets of switches in the amplifier: an auto-zero phase and an
amplification phase.
Auto-Zero Phase
In this phase, all φA switches are closed and all φB switches are
opened. Here, the nulling amplifier is taken out of the gain loop
by shorting its two inputs together. Of course, there is a degree
of offset voltage, shown as VOSA, inherent in the nulling amplifier
which maintains a potential difference between the +IN and
−IN inputs. The nulling amplifier feedback loop is closed through
φB2 and VOSA appears at the output of the nulling amp and on
CM1, an internal capacitor in the AD8551/AD8552/AD8554.
Mathematically, this is expressed in the time domain as
VOA[t] = AAVOSA[t] − BAVOA[t]
(1)
which can be expressed as
VOA t
AAVOSA t
1 BA
(2)
This demonstrates that the offset voltage of the nulling amplifier
times a gain factor appears at the output of the nulling amplifier
and, thus, on the CM1 capacitor.
The AD8551/AD8552/AD8554 amplifiers have exceptional gain,
yielding greater than 120 dB of open-loop gain with a load of 2 kΩ.
Because the output transistors are configured in a common-source
configuration, the gain of the output stage, and thus the openloop gain of the amplifier, is dependent on the load resistance.
Open-loop gain decreases with smaller load resistances. This is
another characteristic of rail-to-rail output amplifiers.
BASIC AUTO-ZERO AMPLIFIER THEORY
VIN+
AB
VIN–
ФB
ФA
VOUT
BB
VOA
VOSA
+
ФB
AA
CM2
VNB
–BA
ФA
CM1
VNA
Autocorrection amplifiers are not a new technology. Various IC
implementations have been available for more than 15 years with
Rev. F | Page 14 of 24
Figure 50. Auto-Zero Phase of the AD8551/AD8552/AD8554
01101-050
The AD8551/AD8552/AD8554 are high precision, rail-to-rail
operational amplifiers that can be run from a single-supply voltage.
Their typical offset voltage of less than 1 μV allows these amplifiers
to be easily configured for high gains without risk of excessive
output voltage errors. The extremely small temperature drift of
5 nV/°C ensures a minimum of offset voltage error over its
entire temperature range of −40°C to +125°C, making the
AD8551/AD8552/AD8554 amplifiers ideal for a variety of
sensitive measurement applications in harsh operating
environments, such as underhood and braking/suspension
systems in automobiles.
Data Sheet
AD8551/AD8552/AD8554
Amplification Phase
When the φB switches close and the φA switches open for the
amplification phase, this offset voltage remains on CM1 and,
essentially, corrects any error from the nulling amplifier. The
voltage across CM1 is designated as VNA. Furthermore, VIN is
designated as the potential difference between the two inputs to
the primary amplifier, or VIN = (VIN+ − VIN−). Thus, the nulling
amplifier can be expressed as
VOA [t ] = A A (VIN [t ] − VOSA [t ]) − B AVNA [t ]
(3)
VIN+
VOUT
AB
VIN–
BB
VOA
VOSA
+
ФA
ФB
AA
VOUT [t ] = AB (VIN [t ] + VOSB ) + BBVNB
V
VOUT [t ] = A BVIN [t ] + A BVOSB + B B A A VIN [t ] + OSB
1 + BA
ФA
VOUT [t ] = VIN [t ](AB + AB BB ) +
Because φA is now open and there is no place for CM1 to discharge,
the voltage (VNA), at the present time (t), is equal to the voltage
at the output of the nulling amp (VOA) at the time when φA was
closed. If the period of the autocorrection switching frequency is
labeled tS, then the amplifier switches between phases every 0.5 × tS.
Therefore, in the amplification phase
(4)
(5)
VOUT [t ] ≈ VIN [t ]AA BA + AA (VOSA + VOSB )
time invariant; therefore, Equation 5 can be rearranged and
rewritten as
AA (1 + BA )VOSA − AA BAVOSA
1 + BA
(6)
or
V
VOA [t ] = AA VIN [t ] + OSA
1 + BA
(11)
Most obvious is the gain product of both the primary and nulling
amplifiers. This AABA term is what gives the AD8551/AD8552/
AD8554 its extremely high open-loop gain. To understand how
VOSA and VOSB relate to the overall effective input offset voltage of
the complete amplifier, establish the generic amplifier equation of
VOUT = k × (VIN + VOS , EFF )
(12)
where k is the open-loop gain of an amplifier and VOS, EFF is its
effective offset voltage.
Putting Equation 12 into the form of Equation 11 gives
For the sake of simplification, assume that the autocorrection
frequency is much faster than any potential change in VOSA or
VOSB. This is a valid assumption because changes in offset voltage
are a function of temperature variation or long-term wear time,
both of which are much slower than the auto-zero clock frequency
of the AD8551/AD8552/AD8554. This effectively renders VOS
VOA [t ] = AAVIN [t ] +
(10)
Also, the gain product of AABB is much greater than AB. These
allow Equation 10 to be simplified to
Substituting Equation 4 and Equation 2 into Equation 3 yields
1
AA B AVOSA t − t S
2
VOA [t ] = AAVIN [t ] + AAVOSA [t ] −
1 + BA
AA BAVOSA
+ ABVOSA
1 + BA
AA = AB and BA = BB and BA >> 1
Figure 51. Output Phase of the Amplifier
1
VNA [t ] = VNA t − t S
2
(9)
The AD8551/AD8552/AD8554 architecture is optimized in
such a way that
CM1
VNA
Combining terms,
VNB
–BA
(8)
In the amplification phase, VOA = VNB, so this can be rewritten as
CM2
01101-051
ФB
the nulling amplifier has greatly reduced its own offset voltage
error even before correcting the primary amplifier. This results
in the primary amplifier output voltage becoming the voltage at
the output of the AD8551/AD8552/AD8554 amplifiers. It is
equal to
(7)
From these equations, the auto-zeroing action becomes evident.
Note the VOS term is reduced by a 1 + BA factor. This shows how
VOUT [t ] ≈ VIN [t ]AA BA + VOS , EFF AA BA
(13)
Thus, it is evident that
VOS , EFF ≈
VOSA + VOSB
BA
(14)
The offset voltages of both the primary and nulling amplifiers
are reduced by the Gain Factor BA. This takes a typical input
offset voltage from several millivolts down to an effective input
offset voltage of submicrovolts. This autocorrection scheme is
the outstanding feature of the AD8551/AD8552/AD8554 series
that continues to earn the reputation of being among the most
precise amplifiers available on the market.
HIGH GAIN, CMRR, PSRR
Common-mode and power supply rejection are indications of
the amount of offset voltage an amplifier has as a result of a change
in its input common-mode or power supply voltages. As shown
in the previous section, the autocorrection architecture of the
Rev. F | Page 15 of 24
AD8551/AD8552/AD8554
Data Sheet
PC board at one end of the component (TA1) is different from
the temperature at the other end (TA2), the resulting Seebeck
voltages are not equal, resulting in a thermal voltage error.
MAXIMIZING PERFORMANCE THROUGH
PROPER LAYOUT
To achieve the maximum performance of the extremely high
input impedance and low offset voltage of the AD8551/
AD8552/AD8554, care is needed in laying out the circuit board.
The PC board surface must remain clean and free of moisture to
avoid leakage currents between adjacent traces. Surface coating
of the circuit board reduces surface moisture and provides a
humidity barrier, reducing parasitic resistance on the board.
The use of guard rings around the amplifier inputs further reduces
leakage currents. Figure 52 shows proper guard ring
configuration, and Figure 53 shows the top view of a surfacemount layout. The guard ring does not need to be a specific
width, but it should form a continuous loop around both inputs.
By setting the guard ring voltage equal to the voltage at the
noninverting input, parasitic capacitance is minimized as well.
For further reduction of leakage currents, components can be
mounted to the PC board using Teflon standoff insulators.
This thermocouple error can be reduced by using dummy components to match the thermoelectric error source. Placing the
dummy component as close as possible to its partner ensures both
Seebeck voltages are equal, thus canceling the thermocouple error.
Maintaining a constant ambient temperature on the circuit board
further reduces this error. The use of a ground plane helps distribute heat throughout the board and reduces EMI noise pickup.
COMPONENT
LEAD
VSC1 +
SURFACE-MOUNT
COMPONENT
+
VSC2
VTS1 +
SOLDER
+ VTS2
PC BOARD
TA1
TA2
IF TA1 ≠ TA2, THEN
VTS1 + VSC1 ≠ VTS2 + VSC2
COPPER
TRACE
01101-054
AD8551/AD8552/AD8554 allows it to quite effectively
minimize offset voltages. The technique also corrects for offset
errors caused by common-mode voltage swings and power
supply variations. This results in superb CMRR and PSRR
figures in excess of 130 dB. Because the autocorrection occurs
continuously, these figures can be maintained across the entire
temperature range of the device, from −40°C to +125°C.
Figure 54. Mismatch in Seebeck Voltages Causes
Thermoelectric Voltage Error
RF
R1
VOUT
VIN
AD8551/
AD8552/
AD8554
RS = R1
VOUT
VIN
VIN
AD8552
NOTES
1. RS SHOULD BE PLACED IN CLOSE PROXIMITY AND
ALIGNMENT TO R1 TO BALANCE SEEBECK VOLTAGES.
AD8552
01101-055
AV = 1 + (RF/R1)
VOUT
Figure 55. Using Dummy Components to Cancel
Thermoelectric Voltage Errors
VIN
VOUT
01101-052
AD8552
Figure 52. Guard Ring Layout and Connections to Reduce
PC Board Leakage Currents
V+
R1
R2
AD8552
VIN1
R2
R1
GUARD
RING
VREF
VREF
GUARD
RING
V–
01101-053
VIN2
Figure 53. Top View of AD8552 SOIC Layout with Guard Rings
Other potential sources of offset error are thermoelectric
voltages on the circuit board. This voltage, also called Seebeck
voltage, occurs at the junction of two dissimilar metals and is
proportional to the temperature of the junction. The most common
metallic junctions on a circuit board are solder-to-board trace
and solder-to-component lead. Figure 54 shows a cross-section
of the thermal voltage error sources. If the temperature of the
1/f NOISE CHARACTERISTICS
Another advantage of auto-zero amplifiers is their ability to
cancel flicker noise. Flicker noise, also known as 1/f noise, is
noise inherent in the physics of semiconductor devices, and it
increases 3 dB for every octave decrease in frequency. The 1/f
corner frequency of an amplifier is the frequency at which the
flicker noise is equal to the broadband noise of the amplifier.
At lower frequencies, flicker noise dominates, causing higher
degrees of error for sub-Hertz frequencies or dc precision
applications.
Because the AD8551/AD8552/AD8554 amplifiers are selfcorrecting op amps, they do not have increasing flicker noise at
lower frequencies. In essence, low frequency noise is treated as a
slowly varying offset error and is greatly reduced as a result of
autocorrection. The correction becomes more effective as the
noise frequency approaches dc, offsetting the tendency of the
noise to increase exponentially as frequency decreases. This
allows the AD8551/AD8552/AD8554 to have lower noise near
dc than standard low noise amplifiers that are susceptible to 1/f
noise.
Rev. F | Page 16 of 24
Data Sheet
AD8551/AD8552/AD8554
INTERMODULATION DISTORTION
The AD8551/AD8552/AD8554 can be used as a conventional
op amp for gain/ bandwidth combinations up to 1.5 MHz. The
auto-zero correction frequency of the device is fixed at 4 kHz.
Although a trace amount of this frequency feeds through to the
output, the amplifier can be used at much higher frequencies.
Figure 56 shows the spectral output of the AD8552 with the
amplifier configured for unity gain and the input grounded.
the amplifier. Figure 58 shows the spectral output of an AD8552
configured as a high gain stage (+60 dB) with a 1 mV input signal
applied. The relative levels of all IMD products and harmonic
distortion add up to produce an output error of −60 dB relative
to the input signal. At unity gain, these add up to only −120 dB
relative to the input signal.
0
VSY = 5V
AV = 60dB
OUTPUT SIGNAL
1V rms @ 200Hz
–20
OUTPUT SIGNAL (dB)
The 4 kHz auto-zero clock frequency appears at the output with
less than 2 μV of amplitude. Harmonics are also present, but at
reduced levels from the fundamental auto-zero clock frequency.
The amplitude of the clock frequency feedthrough is proportional
to the closed-loop gain of the amplifier. Like other autocorrection
amplifiers, at higher gains there is more clock frequency
feedthrough. Figure 57 shows the spectral output with the
amplifier configured for a gain of 60 dB.
–60
–80
IMD < 100µV rms
–120
VSY = 5V
AV = 0dB
0
1
2
3
4
5
6
FREQUENCY (kHz)
7
8
9
10
01101-058
–100
0
–20
–40
OUTPUT SIGNAL (dB)
Figure 58. Spectral Analysis of AD8552 in High Gain with a 1 mV Input Signal
–40
For most low frequency applications, the small amount of autozero clock frequency feedthrough does not affect the precision
of the measurement system. If it is desired, the clock frequency
feedthrough can be reduced through the use of a feedback
capacitor around the amplifier. However, this reduces the
bandwidth of the amplifier. Figure 59 and Figure 60 show a
configuration for reducing the clock feedthrough and the
corresponding spectral analysis at the output. The −3 dB
bandwidth of this configuration is 480 Hz.
–60
–80
–100
–140
0
1
2
3
4
5
6
FREQUENCY (kHz)
7
8
9
10
01101-056
–120
Figure 56. Spectral Analysis of AD8552 Output in Unity Gain Configuration
3.3nF
0
–20
100Ω
VIN = 1mV rms
@ 200Hz
–40
–60
01101-059
OUTPUT SIGNAL (dB)
100kΩ
VSY = 5V
AV = 60dB
Figure 59. Reducing Autocorrection Clock Noise Using a Feedback Capacitor
–80
0
VSY = 5V
AV = 60dB
–100
–20
1
2
3
4
5
6
FREQUENCY (kHz)
7
8
9
10
Figure 57. Spectral Analysis of AD8551/AD8552/AD8554 Output
with +60 dB Gain
When an input signal is applied, the output contains some
degree of intermodulation distortion (IMD). This is another
characteristic feature of all autocorrection amplifiers. IMD
appears as sum and difference frequencies between the input
signal and the 4 kHz clock frequency (and its harmonics) and is
at a level similar to, or less than, the clock feedthrough at the
output. The IMD is also proportional to the closed-loop gain of
Rev. F | Page 17 of 24
–40
–60
–80
–100
–120
0
1
2
3
4
5
6
FREQUENCY (kHz)
7
8
9
10
Figure 60. Spectral Analysis Using a Feedback Capacitor
01101-060
0
01101-057
–140
OUTPUT SIGNAL
–120
AD8551/AD8552/AD8554
Data Sheet
BROADBAND AND EXTERNAL RESISTOR NOISE
CONSIDERATIONS
The total broadband noise output from any amplifier is primarily
a function of three types of noise: input voltage noise from the
amplifier, input current noise from the amplifier, and Johnson
noise from the external resistors used around the amplifier.
Input voltage noise, or en, is strictly a function of the amplifier
used. The Johnson noise from a resistor is a function of the resistance and the temperature. Input current noise, or in, creates
an equivalent voltage noise proportional to the resistors used
around the amplifier. These noise sources are not correlated
with each other and their combined noise sums in a rootsquared-sum fashion. The full equation is given as
[
en _ TOTAL = en2 + 4kTrS + (in RS )2
]
1
2
(15)
Where:
en = the input voltage noise density of the amplifier.
in = the input current noise of the amplifier.
RS = source resistance connected to the noninverting terminal.
k = Boltzmann’s constant (1.38 × 10−23 J/K).
T = ambient temperature in Kelvin (K = 273.15 + °C).
The input voltage noise density (en) of the AD8551/AD8552/
AD8554 is 42 nV/√Hz, and the input noise, in, is 2 fA/√Hz. The
en, TOTAL is dominated by the input voltage noise, provided the
source resistance is less than 106 kΩ. With source resistance
greater than 106 kΩ, the overall noise of the system is
dominated by the Johnson noise of the resistor itself.
Because the input current noise of the AD8551/AD8552/
AD8554 is very small, it does not become a dominant term
unless RS is greater than 4 GΩ, which is an impractical value of
source resistance.
The total noise (en, TOTAL) is expressed in volts per square root
Hertz, and the equivalent rms noise over a certain bandwidth
can be found as
en = en,TOTAL × BW
(16)
where BW is the bandwidth of interest in Hertz.
OUTPUT OVERDRIVE RECOVERY
The AD8551/AD8552/AD8554 amplifiers have an excellent
overdrive recovery of only 200 μs from either supply rail. This
characteristic is particularly difficult for autocorrection
amplifiers because the nulling amplifier requires a nontrivial
amount of time to error correct the main amplifier back to a
valid output. Figure 29 and Figure 30 show the positive and
negative overdrive recovery times for the AD8551/AD8552/
AD8554.
The output overdrive recovery for an autocorrection amplifier is
defined as the time it takes for the output to correct to its final
voltage from an overload state. It is measured by placing the
amplifier in a high gain configuration with an input signal that
forces the output voltage to the supply rail. The input voltage is
then stepped down to the linear region of the amplifier, usually
to halfway between the supplies. The time from the input signal
stepdown to the output settling to within 100 μV of its final
value is the overdrive recovery time.
INPUT OVERVOLTAGE PROTECTION
Although the AD8551/AD8552/AD8554 are rail-to-rail input
amplifiers, exercise care to ensure that the potential difference
between the inputs does not exceed 5 V. Under normal
operating conditions, the amplifier corrects its output to ensure
the two inputs are at the same voltage. However, if the device is
configured as a comparator, or is under some unusual operating
condition, the input voltages may be forced to different
potentials. This can cause excessive current to flow through
internal diodes in the AD8551/AD8552/AD8554 used to
protect the input stage against overvoltage.
If either input exceeds either supply rail by more than 0.3 V, large
amounts of current begin to flow through the ESD protection
diodes in the amplifier. These diodes connect between the inputs
and each supply rail to protect the input transistors against an
electrostatic discharge event and are normally reverse-biased.
However, if the input voltage exceeds the supply voltage, these
ESD diodes become forward-biased. Without current limiting,
excessive amounts of current can flow through these diodes,
causing permanent damage to the device. If inputs are subjected
to overvoltage, appropriate series resistors should be inserted to
limit the diode current to less than 2 mA maximum.
OUTPUT PHASE REVERSAL
Output phase reversal occurs in some amplifiers when the input
common-mode voltage range is exceeded. As common-mode
voltage moves outside of the common-mode range, the outputs
of these amplifiers suddenly jump in the opposite direction to
the supply rail. This is the result of the differential input pair
shutting down and causing a radical shifting of internal
voltages, resulting in the erratic output behavior.
The AD8551/AD8552/AD8554 amplifiers have been carefully
designed to prevent any output phase reversal, provided both
inputs are maintained within the supply voltages. If there is the
potential of one or both inputs exceeding either supply voltage,
place a resistor in series with the input to limit the current to
less than 2 mA to ensure the output does not reverse its phase.
Rev. F | Page 18 of 24
Data Sheet
AD8551/AD8552/AD8554
CAPACITIVE LOAD DRIVE
Table 5. Snubber Network Values for Driving Capacitive Loads
The AD8551/AD8552/AD8554 have excellent capacitive load
driving capabilities and can safely drive up to 10 nF from a
single 5 V supply. Although the device is stable, capacitive
loading limits the bandwidth of the amplifier. Capacitive loads
also increase the amount of overshoot and ringing at the output.
An R-C snubber network, shown in Figure 61, can be used to
compensate the amplifier against capacitive load ringing and
overshoot.
CLOAD
1 nF
4.7 nF
10 nF
5V
AD8551/
AD8552/
AD8554
RX
60Ω
CX
0.47µF
CL
4.7nF
CX
1 nF
0.47 μF
10 μF
POWER-UP BEHAVIOR
At power-up, the AD8551/AD8552/AD8554 settle to a valid
output within 5 μs. Figure 63 shows an oscilloscope photo of the
output of the amplifier with the power supply voltage, and
Figure 64 shows the test circuit. With the amplifier configured
for unity gain, the device takes approximately 5 μs to settle to its
final output voltage. This turn-on response time is much faster
than most other autocorrection amplifiers, which can take
hundreds of microseconds or longer for their output to settle.
01101-061
VOUT
VIN
200mV p-p
RX
200 Ω
60 Ω
20 Ω
Figure 61. Snubber Network Configuration for Driving Capacitive Loads
Although the snubber does not recover the loss of amplifier
bandwidth from the load capacitance, it does allow the amplifier to
drive larger values of capacitance while maintaining a minimum of
overshoot and ringing. Figure 62 shows the output of an AD8551/
AD8552/AD8554 driving a 1 nF capacitor with and without a
snubber network.
VOUT
0V
V+
0V
10µs
1V
WITH
SNUBBER
01101-063
5µs
BOTTOM TRACE = 2V/DIV
TOP TRACE = 1V/DIV
Figure 63. AD8551/AD8552/AD8554 Output Behavior on Power-Up
100kΩ
VSY = 0V TO 5V
WITHOUT
SNUBBER
100mV
01101-062
VSY = 5V
CLOAD = 4.7nF
AD8551/
AD8552/
AD8554
01101-064
VOUT
100kΩ
Figure 64. AD8551/AD8552/AD8554 Test Circuit for Turn-On Time
Figure 62. Overshoot and Ringing are Substantially Reduced
Using a Snubber Network
The optimum value for the resistor and capacitor is a function
of the load capacitance and is best determined empirically because
actual CLOAD (CL) includes stray capacitances and may differ
substantially from the nominal capacitive load. Table 5 shows
some snubber network values that can be used as starting points.
Rev. F | Page 19 of 24
AD8551/AD8552/AD8554
Data Sheet
APPLICATIONS INFORMATION
A 5 V PRECISION STRAIN GAGE CIRCUIT
R2
The extremely low offset voltage of the AD8552 makes it an
ideal amplifier for any application requiring accuracy with high
gains, such as a weigh scale or strain gage. Figure 65 shows a
configuration for a single-supply, precision, strain gage
measurement system.
(17)
R3
IF
2
5V
AV =
3
AD8552-A
R4
100Ω
(19)
The high common-mode rejection, high open-loop gain, and
operation down to 3 V of supply voltage makes the AD8551/
AD8552/AD8554 an excellent choice of op amp for discrete
single-supply instrumentation amplifiers. The common-mode
rejection ratio of the AD8551/AD8552/AD8554 is greater than
120 dB, but the CMRR of the system is also a function of the
external resistor tolerances. The gain of the difference amplifier
shown in Figure 66 is given as
R2
− V 2 R
1
(20)
(21)
(18)
1
2δ
(22)
AD8554-A
R
3 V INSTRUMENTATION AMPLIFIER
VOUT
× (V1 – V2)
R1R4 + 2R2 R4 + R2 R3
2R1R4 − 2R2 R3
CMRRMIN =
V2
Figure 65. A 5 V Precision Strain Gage Amplifier
R
1 + 1
R
2
R1
In the three-op amp, instrumentation amplifier configuration
shown in Figure 67, the output difference amplifier is set to
unity gain with all four resistors equal in value. If the tolerance
of the resistors used in the circuit is given as δ, the worst-case
CMRR of the instrumentation amplifier is
VOUT
0V TO 4.0V
A1
NOTES
1. USE 0.1% TOLERANCE RESISTORS.
R4
= V 1
R3 + R 4
R2
R2 R4
=
R1 R3
CMRR =
R2
100Ω
R3
17.4kΩ
, THEN VOUT =
Due to finite component tolerance, the ratio between the four
resistors is not exactly equal, and any mismatch results in a
reduction of common-mode rejection from the system. Referring
to Figure 66, the exact common-mode rejection ratio can be
expressed as
20kΩ
40mV
FULL-SCALE
R1
Which sets the output voltage of the system to
4
AD8552-B
R1
17.4kΩ
350Ω
LOAD
CELL
REF192
6
12.0kΩ
R2
In an ideal difference amplifier, the ratio of the resistors are set
exactly equal to
01101-065
4.0V
2.5V
A2
=
VOUT = AV (V1 − V2)
Using the values given in Figure 65, the output voltage linearly
varies from 0 V with no strain to 4.0 V under full strain.
1kΩ
R3
R4
Figure 66. Using the AD8551/AD8552/AD8554 as a Difference Amplifier
where RB is the resistance of the load cell.
Q1
2N2222
OR
EQUIVALENT
R4
AD8551/
AD8552/
AD8554
R
R
R
R
RG
V1
VOUT
R
AD8554-C
RTRIM
AD8554-B
VOUT = 1 +
2R
(V1 – V2)
RG
01101-067
2 × (R1 + R2 )
RB
VOUT
V1
01101-066
A REF192 provides a 2.5 V precision reference voltage for A2.
The A2 amplifier boosts this voltage to provide a 4.0 V reference
for the top of the strain gage resistor bridge. Q1 provides the
current drive for the 350 Ω bridge network. A1 is used to
amplify the output of the bridge with the full-scale output
voltage equal to
R1
V2
Figure 67. A Discrete Instrumentation Amplifier Configuration
Consequently, using 1% tolerance resistors results in a worst-case
system CMRR of 0.02, or 34 dB. Therefore, either high precision
resistors or an additional trimming resistor, as shown in Figure 67,
must be used to achieve high common-mode rejection. The
value of this trimming resistor must be equal to the value of R
multiplied by its tolerance. For example, using 10 kΩ resistors
with 1% tolerance requires a series trimming resistor equal to
100 Ω.
Rev. F | Page 20 of 24
Data Sheet
AD8551/AD8552/AD8554
A HIGH ACCURACY THERMOCOUPLE AMPLIFIER
R
Monitor Output = R2 × SENSE
R1
Figure 68 shows a K-type thermocouple amplifier configuration
with cold junction compensation. Even from a 5 V supply, the
AD8551 can provide enough accuracy to achieve a resolution of
better than 0.02°C from 0°C to 500°C. D1 is used as a temperature measuring device to correct the cold junction error from
the thermocouple and should be placed as close as possible to
the two terminating junctions. With the thermocouple measuring
tip immersed in a 0°C ice bath, R6 should be adjusted until the
output is at 0 V.
Figure 70 shows the low-side monitor equivalent. In this circuit,
the input common-mode voltage to the AD8552 is at or near
ground. Again, a 0.1 Ω resistor provides a voltage drop proportional to the return current. The output voltage is given as
R
VOUT = (V + ) − 2 × RSENSE × I L
R1
5.000V
R1
10.7kΩ
R5
40.2kΩ
R1
100Ω
5V
10µF
+
D1
3
2
0.1µF
R2
2.74kΩ
R6
200Ω
R4
5.62kΩ
V+
3V
R8
124kΩ
1N4148
K-TYPE
THERMOCOUPLE
40.7µV/°C
IL
R3
53.6Ω
R7
453Ω
2
–
3
+
8
1/2
AD8552
1
4
S
7
AD8551
0.1µF
G
M1
Si9433
1
D
MONITOR
OUTPUT
4
0V TO 5.00V
(0°C TO 500°C)
R2
2.49kΩ
01101-069
4
RSENSE
0.1Ω
3V
Figure 69. A High-Side Load Current Monitor
Figure 68. A Precision K-Type Thermocouple Amplifier with
Cold Junction Compensation
V+
PRECISION CURRENT METER
R2
2.49kΩ
Because of its low input bias current and superb offset voltage at
single supply voltages, the AD8551/AD8552/AD8554 are
excellent amplifiers for precision current monitoring. Its rail-torail input allows the amplifier to be used as either a high-side or
low-side current monitor. Using both amplifiers in the AD8552
provides a simple method to monitor both current supply and
return paths for load or fault detection.
Figure 69 shows a high-side current monitor configuration. In
this configuration, the input common-mode voltage of the
amplifier is at or near the positive supply voltage. The rail-torail input of the amplifier provides a precise measurement even
with the input common-mode voltage at the supply voltage. The
CMOS input structure does not draw any input bias current,
ensuring a minimum of measurement error.
The 0.1 Ω resistor creates a voltage drop to the noninverting
input of the AD8551/AD8552/AD8554. The output of the
amplifier is corrected until this voltage appears at the inverting
input. This creates a current through R1, which in turn flows
through R2. The monitor output is given by
VOUT
Q1
V+
R1
100Ω
RSENSE
0.1Ω
1/2 AD8552
RETURN TO
GROUND
01101-070
REF02EZ 6
(24)
For the component values shown in Figure 70, the output
transfer function decreases from V+ at −2.5 V/A.
01101-068
0.1µF
2
(23)
Using the components shown in Figure 69, the monitor output
transfer function is 2.5 V/A.
Using the values shown in Figure 68, the output voltage tracks
temperature at 10 mV/°C. For a wider range of temperature
measurement, R9 can be decreased to 62 kΩ. This creates a
5 mV/°C change at the output, allowing measurements of up
to 1000°C.
12V
× IL
Figure 70. A Low-Side Load Current Monitor
PRECISION VOLTAGE COMPARATOR
The AD8551/AD8552/AD8554 can be operated open-loop and
used as a precision comparator. The AD8551/AD8552/AD8554
have less than 50 μV of offset voltage when run in this
configuration. The slight increase of offset voltage stems from
the fact that the autocorrection architecture operates with
lowest offset in a closed-loop configuration, that is, one with
negative feedback. With 50 mV of overdrive, the device has a
propagation delay of 15 μs on the rising edge and 8 μs on the
falling edge. Ensure the maximum differential voltage of the
device is not exceeded. For more information, refer to the Input
Overvoltage Protection section.
Rev. F | Page 21 of 24
AD8551/AD8552/AD8554
Data Sheet
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
3.20
3.00
2.80
5.15
4.90
4.65
5
1
4
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.23
0.09
6°
0°
0.40
0.25
10-07-2009-B
0.15
0.05
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 71. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
3.10
3.00
2.90
8
5
4.50
4.40
4.30
1
6.40 BSC
4
PIN 1
0.65 BSC
0.15
0.05
1.20
MAX
COPLANARITY
0.10
0.30
0.19
SEATING 0.20
PLANE
0.09
8°
0°
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AA
Figure 72. 8-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-8)
Dimensions shown in millimeters
Rev. F | Page 22 of 24
Data Sheet
AD8551/AD8552/AD8554
5.00 (0.1968)
4.80 (0.1890)
5
1
6.20 (0.2441)
5.80 (0.2284)
4
1.27 (0.0500)
BSC
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
SEATING
PLANE
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012407-A
8
4.00 (0.1574)
3.80 (0.1497)
Figure 73. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
5.10
5.00
4.90
14
8
4.50
4.40
4.30
6.40
BSC
1
7
PIN 1
0.65 BSC
1.20
MAX
0.15
0.05
COPLANARITY
0.10
0.30
0.19
0.20
0.09
SEATING
PLANE
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 74. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
Rev. F | Page 23 of 24
0.75
0.60
0.45
061908-A
1.05
1.00
0.80
AD8551/AD8552/AD8554
Data Sheet
8.75 (0.3445)
8.55 (0.3366)
8
14
1
7
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
0.10
0.51 (0.0201)
0.31 (0.0122)
6.20 (0.2441)
5.80 (0.2283)
0.50 (0.0197)
0.25 (0.0098)
1.75 (0.0689)
1.35 (0.0531)
SEATING
PLANE
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
060606-A
4.00 (0.1575)
3.80 (0.1496)
Figure 75. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-14)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1
AD8551ARZ
AD8551ARZ-REEL
AD8551ARZ-REEL7
AD8551ARM-REEL
AD8551ARMZ
AD8551ARMZ-REEL
AD8552AR
AD8552AR-REEL
AD8552AR-REEL7
AD8552ARZ
AD8552ARZ-REEL
AD8552ARZ-REEL7
AD8552ARU
AD8552ARU-REEL
AD8552ARUZ
AD8552ARUZ-REEL
AD8554ARZ
AD8554ARZ-REEL
AD8554ARZ-REEL7
AD8554ARUZ
AD8554ARUZ-REEL
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead TSSOP
8-Lead TSSOP
8-Lead TSSOP
8-Lead TSSOP
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead TSSOP
14-Lead TSSOP
Z = RoHS Compliant Part, # denotes RoHS compliant part may be top or bottom marked.
©1999–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01101-0-6/15(F)
Rev. F | Page 24 of 24
Package Option
R-8
R-8
R-8
RM-8
RM-8
RM-8
R-8
R-8
R-8
R-8
R-8
R-8
RU-8
RU-8
RU-8
RU-8
R-14
R-14
R-14
RU-14
RU-14
Branding
AHA
AHA#
AHA#
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