AD8555

Precision, Dual-Channel Instrumentation Amplifier AD8222 FEATURES Two channels in small 4 mm × 4 mm LFCSP Gain set with 1 resistor per amplifier (G = 1 to 10,000) Low noise 8 nV/√Hz @ 1 kHz 0.25 μV p-p (0.1 Hz to 10 Hz) High accuracy dc performance (B grade) 60 μV maximum input offset voltage 0.3 μV/°C maximum input offset drift 1.0 nA maximum input bias current 126 dB minimum CMRR (G = 100) Excellent ac performance 150 kHz bandwidth (G = 100) 13 μs settling time to 0.001% Differential output option (single channel) Fully specified Adjustable common-mode output Supply range: ±2.3 V to ±18 V FUNCTIONAL BLOCK DIAGRAM OUT1 OUT2 14 +VS 16 15 –IN1 RG1 RG1 +IN1 AD8222 1 2 3 4 12 11 10 9 –VS 13 –IN2 RG2 RG2 +IN2 5 6 7 8 05947-001 +VS REF1 Figure 1. 4mm × 4 mm LFCSP Table 1. In Amps and Differential Amplifier by Category High Performance AD8221 AD82201 AD8222 Low Cost AD85531 AD6231 High Voltage AD628 AD629 Mil Grade AD620 AD621 AD524 AD526 AD624 Low Power AD6271 Digital Prog Gain AD85551 AD85561 AD85571 APPLICATIONS Multichannel data acquisition for ECG and medical instrumentation Industrial process controls Wheatstone bridge sensors Differential drives for High resolution input ADCs Remote sensors 1 Rail-to-rail output. GENERAL DESCRIPTION The AD8222 is a dual-channel, high performance instrumentation amplifier that requires only one external resistor per amplifier to set gains of 1 to 10,000. The AD8222 is the first dual-instrumentation amplifier in the small 4 mm × 4mm LFCSP. It requires the same board area as a typical single instrumentation amplifier. The smaller package allows a 2× increase in channel density and a lower cost per channel, all with no compromise in performance. The AD8222 can also be configured as a single-channel, differential output instrumentation amplifier. Differential outputs provide high noise immunity, which can be useful when the output signal must travel through a noisy environment, such as with remote sensors. The configuration can also be used to drive differential input ADCs. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. The AD8222 maintains a minimum CMRR of 80 dB to 4 kHz for all grades at G = 1. High CMRR over frequency allows the AD8222 to reject wideband interference and line harmonics, greatly simplifying filter requirements. The AD8222 also has a typical CMRR drift over temperature of just 0.07 μV/V/°C at G = 1. The AD8222 operates on both single and dual supplies and only requires 2.2 mA maximum supply current for both amplifiers. It is specified over the industrial temperature range of −40°C to +85°C and is fully RoHS compliant. For a single-channel version, see the AD8221. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. REF2 –VS AD8222 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 6 Thermal Resistance ...................................................................... 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 Theory of Operation ...................................................................... 15 Amplifier Architecture .............................................................. 15 Gain Selection ............................................................................. 15 Reference Terminal .................................................................... 16 Layout .......................................................................................... 16 Solder Wash................................................................................. 17 Input Bias Current Return Path ............................................... 17 Input Protection ......................................................................... 17 RF Interference ........................................................................... 18 Common-Mode Input Voltage Range ..................................... 18 Applications..................................................................................... 19 Differential Output .................................................................... 19 Driving a Differential Input ADC............................................ 20 Precision Strain Gauge .............................................................. 20 Driving Cabling .......................................................................... 21 Outline Dimensions ....................................................................... 22 Ordering Guide .......................................................................... 22 REVISION HISTORY 7/06—Revision 0: Initial Version Rev. 0 | Page 2 of 24 AD8222 SPECIFICATIONS VS = ±15 V, VREF = 0 V, TA = 25°C, G = 1, RL = 2 kΩ, unless otherwise noted. Table 2. Single-Ended and Differential 1 Output Configuration Parameter COMMON-MODE REJECTION RATIO (CMRR) CMRR DC to 60 Hz G=1 G = 10 G = 100 G = 1000 CMRR at 4 kHz G=1 G = 10 G = 100 G = 1000 CMRR Drift NOISE Voltage Noise, 1 kHz Input Voltage Noise, eNI Output Voltage Noise, eNO RTI G=1 G = 10 G = 100 to 1000 Current Noise VOLTAGE OFFSET Input Offset, VOSI Overtemperature Average TC Output Offset, VOSO Overtemperature Average TC Offset RTI vs. Supply (PSR) G=1 G = 10 G = 100 G = 1000 INPUT CURRENT (PER CHANNEL) Input Bias Current Over temperature Average TC Input Offset Current Overtemperature Average TC REFERENCE INPUT RIN IIN Voltage Range Gain to Output Conditions VCM = –10 V to +10 V 1 kΩ source imbalance 80 100 120 130 80 90 100 100 T = −40°C to +85°C, G = 1 RTI Noise = √(eNI2 + (eNO/G)2) VIN+, VIN−, VREF = 0 V VIN+, VIN−, VREF = 0 V f = 0.1 Hz to 10 Hz 2 0.5 0.25 40 6 120 150 0.4 500 0.8 9 90 110 124 130 110 120 130 140 0.5 T = −40°C to +85°C 1 0.2 T = −40°C to +85°C 1 20 50 −VS 1 ± 0.0001 Rev. 0 | Page 3 of 24 Min A Grade Typ Max Min B Grade Typ Max Unit 86 106 126 140 80 100 110 110 0.07 0.07 dB dB dB dB dB dB dB dB μV/V/°C 8 75 2 0.5 0.25 40 6 8 75 nV/√Hz nV/√Hz μV p-p μV p-p μV p-p fA/√Hz pA p-p f = 1 kHz f = 0.1 Hz to 10 Hz RTI VOS = ( VOSI) + (VOSO/G) VS = ±5 V to ±15 V T = −40°C to +85°C VS = ±5 V to ±15 V T = −40°C to +85°C VS = ±2.3 V to ±18 V 60 80 0.3 350 0.5 5 94 114 130 140 110 130 140 150 0.2 1 0.1 0.5 20 50 −VS 1 ± 0.0001 1.0 1.5 0.5 0.6 2 μV μV μV/°C μV mV μV/°C dB dB dB dB nA nA pA/°C nA nA pA/°C kΩ μA V V/V 2.0 3.0 1 1.5 VIN+, VIN−, VREF = 0 V 60 +VS 60 +VS AD8222 Parameter GAIN Gain Range Gain Error G=1 G = 10 G = 100 G = 1000 Gain Nonlinearity G=1 G = 10 G = 100 Gain vs. Temperature G=1 G > 12 INPUT Input Impedance Differential Common Mode Input Operating Voltage Range 3 Overtemperature Input Operating Voltage Range3 Overtemperature OUTPUT Output Swing Overtemperature Output Swing Overtemperature Short-Circuit Current POWER SUPPLY Operating Range Quiescent Current (per Amplifier) Overtemperature TEMPERATURE RANGE Specified Performance Operational 4 1 2 3 Conditions G = 1 + (49.4 kΩ/RG) VOUT ± 10 V Min 1 A Grade Typ Max 10000 0.05 0.3 0.3 0.3 Min 1 B Grade Typ Max 10000 0.02 0.15 0.15 0.15 1 7 7 2 5 20 20 5 −50 Unit V/V % % % % ppm ppm ppm ppm/°C ppm/°C VOUT = –10 V to +10 V 3 7 7 3 10 20 20 10 −50 100||2 100||2 VS = ±2.3 V to ±5 V T = −40°C to +85°C VS = ±5 V to ±18 V T = −40°C to +85°C RL = 10 kΩ VS = ±2.3 V to ±5 V T = −40°C to +85°C VS = ±5 V to ±18 V T = −40°C to +85°C −VS + 1.9 −VS + 2.0 −VS + 1.9 −VS + 2.0 −VS + 1.1 −VS + 1.4 −VS + 1.2 −VS + 1.6 18 VS = ±2.3 V to ±18 V T = −40°C to +85°C −40 −40 ±2.3 0.9 1 ±18 1.1 1.2 +85 +125 ±2.3 +VS − 1.1 +VS − 1.2 +VS − 1.2 +VS − 1.2 +VS − 1.2 +VS − 1.3 +VS − 1.4 +VS − 1.5 −VS + 1.9 −VS + 2.0 −VS + 1.9 −VS + 2.0 −VS + 1.1 −VS + 1.4 −VS + 1.2 −VS + 1.6 100||2 100||2 +VS − 1.1 +VS − 1.2 +VS − 1.2 +VS − 1.2 +VS − 1.2 +VS − 1.3 +VS − 1.4 +VS − 1.5 18 ±18 1.1 1.2 +85 +125 GΩ||pF GΩ||pF V V V V V V V V mA V mA mA °C °C 0.9 1 −40 −40 Refers to differential configuration shown in Figure 49. Does not include the effects of external resistor RG. One input grounded. G = 1. 4 See Typical Performance Characteristics for expected operation between 85°C to 125°C. Rev. 0 | Page 4 of 24 AD8222 VS = ±15 V, VREF = 0 V, TA = 25°C, RL = 2 kΩ, unless otherwise noted. Table 3. Single-Ended Output Configuration—Dynamic Performance (Both Amplifiers) Parameter DYNAMIC RESPONSE Small Signal −3 dB Bandwidth G=1 G = 10 G = 100 G =1000 Settling Time 0.01% G = 1 to 100 G = 1000 Settling Time 0.001% G = 1 to 100 G = 1000 Slew Rate Conditions Min A Grade Typ Max Min B Grade Typ Max Unit 1200 750 140 15 10 V step 10 80 10 V step 13 110 G=1 G = 5 to 1000 1.5 2 2 2.5 1.5 2 1200 750 140 15 10 80 13 110 2 2.5 kHz kHz kHz kHz μs μs μs μs V/μs V/μs Table 4. Differential Output Configuration 1 —Dynamic Performance Parameter DYNAMIC RESPONSE Small Signal −3 dB Bandwidth G=1 G = 10 G = 100 G =1000 Settling Time 0.01% G = 1 to 100 G = 1000 Settling Time 0.001% G = 1 to 100 G = 1000 Slew Rate Conditions Min A Grade Typ Max Min B Grade Typ Max Unit 1000 650 140 15 10 V step 15 80 10 V step 18 110 G=1 G = 5 to 1000 1.5 2 2 2.5 1.5 2 1000 650 140 15 15 80 18 110 2 2.5 kHz kHz kHz kHz μs μs μs μs V/μs V/μs 1 Refers to differential configuration shown in Figure 49. Rev. 0 | Page 5 of 24 AD8222 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Supply Voltage Output Short-Circuit Current Input Voltage (Common Mode) Differential Input Voltage Storage Temperature Range Operational Temperature Range Package Glass Transition Temperature (TG) ESD (Human Body Model) ESD (Charge Device Model) Rating ±18 V Indefinite ±VS ±VS −65°C to +130°C −40°C to +125°C 130°C 1 kV 1 kV THERMAL RESISTANCE Table 6. Thermal Pad Soldered to Board Not Soldered to Board θJA 48 86 Unit °C/W °C/W The θJA values in Table 6 assume a 4-layer JEDEC standard board. If the thermal pad is soldered to the board, then it is also assumed it is connected to a plane. θJC at the exposed pad is 4.4°C/W. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Maximum Power Dissipation The maximum safe power dissipation for the AD8222 is limited by the associated rise in junction temperature (TJ) on the die. At approximately 130°C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the amplifiers. Exceeding a temperature of 130°C for an extended period can result in a loss of functionality. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 6 of 24 AD8222 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 15 OUT1 14 OUT2 13 –VS PIN 1 INDICATOR 16 +VS –IN1 1 RG1 2 RG1 3 +IN1 4 12 –IN2 11 RG2 10 RG2 9 +IN2 05947-002 AD8222 TOP VIEW +VS 5 Figure 2. Pin Configuration Table 7. Pin Function Descriptions Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic −IN1 RG1 RG1 +IN1 +VS REF1 REF2 −VS +IN2 RG2 RG2 −IN2 −VS OUT2 OUT1 +VS Description Negative Input In-Amp 1 Gain Resistor In-Amp 1 Gain Resistor In-Amp 1 Positive Input In-Amp 1 Positive Supply Reference Adjust In-Amp 1 Reference Adjust In-Amp 2 Negative Supply Positive Input In-Amp 2 Gain Resistor In-Amp 2 Gain Resistor In-Amp 2 Negative Input In-Amp 2 Negative Supply Output In-Amp 2 Output In-Amp 1 Positive Supply Rev. 0 | Page 7 of 24 REF1 6 REF2 7 –VS 8 AD8222 TYPICAL PERFORMANCE CHARACTERISTICS 500 N = 1713 800 400 NUMBER OF UNITS NUMBER OF UNITS 600 300 400 200 100 200 –40 –30 –20 –10 0 10 20 30 40 50 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 CMRR (µV/V) IOFFSET (nA) Figure 3. Typical Distribution for CMRR (G = 1) 15 INPUT COMMON-MODE VOLTAGE (V) Figure 6. Typical Distribution of Input Offset Current 300 N = 1713 250 NUMBER OF UNITS 10 VS = ±15V 5 200 150 0 VS = ±5V 100 –5 10 –10 VOSI (µV) –10 –5 0 5 10 15 OUTPUT VOLTAGE (V) Figure 4. Typical Distribution of Input Offset Voltage Figure 7. Input Common-Mode Range vs. Output Voltage, G = 1 15 INPUT COMMON-MODE VOLTAGE (V) N = 1713 700 600 NUMBER OF UNITS 10 VS = ±15V 5 500 400 300 200 100 0 –2.0 0 VS = ±5V –5 –10 IBIAS (nA) –10 –5 0 5 10 15 OUTPUT VOLTAGE (V) Figure 5. Typical Distribution of Input Bias Current Figure 8. Input Common-Mode Range vs. Output Voltage, G = 100 Rev. 0 | Page 8 of 24 05947-008 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 05947-005 –15 –15 05947-007 80 60 40 20 0 20 40 60 80 100 05947-004 0 –100 –15 –15 05947-006 05947-003 0 –50 0 –2.0 AD8222 200 150 INPUT BIAS CURRENT (pA) 160 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 0.1 BANDWIDTH LIMITED GAIN = 1000 100 50 0 VS = ±15V +PSRR (dB) VS = ±5V –50 –100 –150 –200 –15 GAIN = 100 GAIN = 10 GAIN = 1 05947-009 –10 –5 0 5 10 15 1 10 100 1k 10k 100k 1M COMMON-MODE VOLTAGE (V) FREQUENCY (Hz) Figure 9. IBIAS vs. Common-Mode Voltage 2.0 CHANGE IN INPUT OFFSET VOLTAGE (µV) Figure 12. Positive PSRR vs. Frequency, RTI (G = 1 to 1000) 160 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 0.1 1.8 1.6 1.4 –PSRR (dB) GAIN = 1000 GAIN = 100 1.2 1.0 0.8 0.6 0.4 0.2 05947-010 GAIN = 10 GAIN = 1 1 10 100 1k 10k 100k 1M 05947-013 05947-014 0 0 2 4 6 8 10 WARM-UP TIME (Minutes) FREQUENCY (Hz) Figure 10. Change in Input Offset Voltage vs. Warm-Up Time 1000 800 600 INPUT BIAS CURRENT (pA) Figure 13. Negative PSRR vs. Frequency, RTI (G = 1 to 1000) 10k NEGATIVE TOTAL DRIFT: 25°C TO 85°C RTI (µV) 1k GAIN = 1 100 GAIN = 10 GAIN = 100 400 200 0 –200 –400 –600 –800 05947-011 POSITIVE OFFSET CURRENT 10 GAIN = 1000 –1000 –55 –35 –15 5 25 45 65 85 105 125 1 1 10 100 1k 10k 100k 1M 10M TEMPERATURE (°C) SOURCE RESISTANCE (Ω) Figure 11. Input Bias Current and Offset Current vs. Temperature Figure 14. Total Drift vs. Source Resistance Rev. 0 | Page 9 of 24 05947-012 AD8222 70 60 50 40 30 GAIN (dB) 20 GAIN = 1000 15 GAIN = 100 10 ΔCMR (µV/V) 5 0 –5 –10 –15 –20 –40 20 10 0 –10 –20 –30 GAIN = 10 EXAMPLE PART 1 GAIN = 1 EXAMPLE PART 2 05947-015 1k 10k 100k 1M 10M –20 0 20 40 60 80 100 120 FREQUENCY (Hz) TEMPERATURE (°C) Figure 15. Gain vs. Frequency 160 150 INPUT VOLTAGE LIMIT (V) REFERRED TO SUPPLY VOLTAGES Figure 18. ΔCMR vs. Temperature, G = 1 +VS–0 –0.4 FROM +V GAIN = 1000 GAIN = 100 140 130 120 CMRR (dB) –0.8 –1.2 –1.6 –2.0 GAIN = 10 BANDWIDTH LIMITED GAIN = 1 110 100 90 80 70 60 50 +2.0 +1.6 +1.2 +0.8 +0.4 FROM –V 05947-016 1 10 100 1k 10k 100k 1M 2 6 10 SUPPLY VOLTAGE (V) 14 18 FREQUENCY (Hz) Figure 16. CMRR vs. Frequency, RTI 160 150 140 130 120 CMRR (dB) Figure 19. Input Voltage Limit vs. Supply Voltage, G = 1 +VS–0 –0.4 GAIN = 1000 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES –0.8 –1.2 –1.6 RL = 10kΩ GAIN = 100 RL = 2kΩ 110 100 90 80 70 60 50 GAIN = 10 BANDWIDTH LIMITED +1.6 +1.2 +0.8 +0.4 RL = 10kΩ RL = 2kΩ GAIN = 1 05947-017 1 10 100 1k 10k 100k 1M 2 6 10 SUPPLY VOLTAGE (V) 14 18 FREQUENCY (Hz) Figure 17. CMRR vs. Frequency, RTI, 1 kΩ Source Imbalance Figure 20. Output Voltage Swing vs. Supply Voltage, G = 1 Rev. 0 | Page 10 of 24 05947-020 40 0.1 –VS+0 05947-019 40 0.1 –VS+0 05947-018 –40 100 AD8222 30 40 30 OUTPUT VOLTAGE SWING (V p-p) NONLINEARITY (10ppm/DIV) 20 10 0 –10 –20 –30 2kΩ LOAD 20 600Ω LOAD 10 10kΩ LOAD 05947-021 1 10 100 LOAD RESISTANCE (Ω) 1k 10k –8 –6 –4 –2 0 VOUT (V) 2 4 6 8 10 Figure 21. Output Voltage Swing vs. Load Resistance +VS–0 –1 –2 –3 SOURCING VOLTAGE NOISE RTI (nV/ Hz) 1k Figure 24. Gain Nonlinearity, G = 100 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES GAIN = 1 100 GAIN = 10 GAIN = 100 GAIN = 1000 +3 +2 SINKING +1 10 05947-022 0 1 2 3 4 5 6 7 8 9 10 11 12 1 10 100 1k 10k 100k OUTPUT CURRENT (mA) FREQUENCY (Hz) Figure 22. Output Voltage Swing vs. Output Current, G = 1 4 3 Figure 25. Voltage Noise Spectral Density vs. Frequency (G = 1 to 1000) NONLINEARITY (1ppm/DIV) 2 1 0 2kΩ LOAD –1 –2 05947-027 10kΩ LOAD 600Ω LOAD –3 –4 –10 05947-023 –8 –6 –4 –2 0 VOUT (V) 2 4 6 8 10 2µV/DIV 1s/DIV Figure 23. Gain Nonlinearity, G = 1 Figure 26. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1) Rev. 0 | Page 11 of 24 05947-026 –VS+0 1 GAIN = 1000 BW LIMIT 05947-024 0 –40 –10 AD8222 30 GAIN = 10, 100, 1000 MAX OUTPUT VOLTAGE (V p-p) 25 GAIN = 1 20 15 10 05947-028 5 10k 100k FREQUENCY (Hz) 1M Figure 27. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000) 1k Figure 30. Large Signal Frequency Response 5V/DIV CURRENT NOISE (fA/ Hz) 100 7.4µs TO 0.01% 8.3µs TO 0.001% 0.002%/DIV 20µs/DIV 05947-032 1 10 100 1k 10k 100k FREQUENCY (Hz) 05947-029 10 Figure 28. Current Noise Spectral Density vs. Frequency Figure 31. Large Signal Pulse Response and Settling Time (G = 1) 5V/DIV 4.8µs TO 0.01% 6.6µs TO 0.001% 0.002%/DIV 05947-030 20µs/DIV 5pA/DIV 1s/DIV Figure 29. 0.1 Hz to 10 Hz Current Noise Figure 32. Large Signal Pulse Response and Settling G = 10) Rev. 0 | Page 12 of 24 05947-033 05947-031 0.1µV/DIV 1s/DIV 0 1k AD8222 5V/DIV 9.2µs TO 0.01% 16.2µs TO 0.001% 0.002%/DIV 05947-034 20µs/DIV 20mV/DIV 4µs/DIV Figure 33. Large Signal Pulse Response and Settling Time (G = 100) Figure 36. Small Signal Response, G = 10, RL = 2 kΩ, CL = 100 pF 5V/DIV 83µs TO 0.01% 112µs TO 0.001% 0.002%/DIV 05947-035 200µs/DIV 20mV/DIV 10µs/DIV Figure 34. Large Signal Pulse Response and Settling Time (G = 1000) Figure 37. Small Signal Response, G = 100, RL = 2 kΩ, CL = 100 pF 05947-036 20mV/DIV 4µs/DIV 20mV/DIV 100µs/DIV Figure 35. Small Signal Response, G = 1, RL = 2 kΩ, CL = 100 pF Figure 38. Small Signal Response, G = 1000, RL = 2 kΩ, CL = 100 pF Rev. 0 | Page 13 of 24 05947-039 05947-038 05947-037 AD8222 15 60 GAIN = 1000 40 GAIN = 100 SETTLING TIME (µs) 10 GAIN (dB) SETTLED TO 0.001% 20 GAIN = 10 5 SETTLED TO 0.01% 0 GAIN = 1 –20 05947-040 0 5 10 15 20 1k 10k 100k 1M 10M OUTPUT VOLTAGE STEP SIZE (V) FREQUENCY (Hz) Figure 39. Settling Time vs. Step Size (G = 1) 1k Figure 42. Differential Output Configuration: Gain vs. Frequency 100 90 80 CMROUT = 20 log VDIFF_OUT VCM_OUT SETTLING TIME (µs) 100 70 CMROUT (dB) 60 50 40 30 LIMITED BY MEASUREMENT SYSTEM SETTLED TO 0.001% 10 SETTLED TO 0.01% 20 10 05947-041 1 10 GAIN 100 1k 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 40. Settling Time vs. Gain for a 10 V Step 200 180 Figure 43. Differential Output Configuration: Common-Mode Output vs. Frequency SOURCE VOUT = 20V p-p GAIN = 1000 SOURCE VOUT SMALLER TO AVOID SLEW RATE LIMIT CHANNEL SEPARATION (dB) 160 140 120 GAIN = 1 100 80 60 THERMAL CROSSTALK VARIES WITH LOAD 1 10 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 41. Channel Separation vs. Frequency, RL = 2 kΩ, Source Channel at G = 1 05947-042 Rev. 0 | Page 14 of 24 05947-056 1 0 05947-043 0 –40 100 AD8222 THEORY OF OPERATION I VB I IB COMPENSATION C1 A1 A2 C2 IB COMPENSATION 10kΩ +VS 10kΩ OUTPUT 10kΩ A3 +VS –VS REF +VS –IN 400Ω Q1 R1 24.7kΩ +VS RG –VS –VS –VS R2 +VS 24.7kΩ Q2 +VS 400Ω +IN 10kΩ –VS 05947-045 –VS Figure 44. Simplified Schematic AMPLIFIER ARCHITECTURE The two instrumentation amplifiers of the AD8222 are based on the classic three op amp topology. Figure 44 shows a simplified schematic of one of the amplifiers. Input Transistors Q1 and Q2 are biased at a fixed current. Any differential input signal forces the output voltages of A1 and A2 to change so that the differential voltage also appears across RG. The current that flows through RG must also flow through R1 and R2, resulting in a precisely amplified version of the differential input signal between the outputs of A1 and A2. Topologically, Q1, A1, and R1 and Q2, A2, and R2 can be viewed as precision current feedback amplifiers. The common-mode signal and the amplified differential signal are applied to a difference amplifier that rejects the common-mode voltage. The difference amplifier employs innovations that result in low output offset voltage as well as low output offset voltage drift. Because the input amplifiers employ a current feedback architecture, the gain-bandwidth product of the AD8222 increases with gain, resulting in a system that does not suffer from the expected bandwidth loss of voltage feedback architectures at higher gains. The transfer function of the AD8222 is VOUT = G(VIN+ − VIN−) + VREF where GAIN SELECTION Placing a resistor across the RG terminals sets the gain of the AD8222, which can be calculated by referring to Table 8 or by using the following gain equation. RG = 49.4 kΩ G −1 Calculated Gain 1.990 4.984 9.998 19.93 50.40 100.0 199.4 495.0 991.0 Table 8. Gains Achieved Using 1% Resistors 1% Standard Table Value of RG (Ω) 49.9 k 12.4 k 5.49 k 2.61 k 1.00 k 499 249 100 49.9 The AD8222 defaults to G = 1 when no gain resistor is used. The tolerance and gain drift of the RG resistor should be added to the AD8222’s specifications to determine the total gain accuracy of the system. When the gain resistor is not used, gain error and gain drift are kept to a minimum. G =1+ 49.4 kΩ RG Rev. 0 | Page 15 of 24 AD8222 REFERENCE TERMINAL The output voltage of the AD8222 is developed with respect to the potential on the reference terminal. This is useful when the output signal needs to be offset to a precise midsupply level. For example, a voltage source can be tied to the REF pin to levelshift the output so that the AD8222 can drive a single-supply ADC. The REF pin is protected with ESD diodes and should not exceed either +VS or −VS by more than 0.3 V. For best performance, source impedance to the REF terminal should be kept below 1 Ω. As shown in Figure 44, the reference terminal, REF, is at one end of a 10 kΩ resistor. Additional impedance at the REF terminal adds to this 10 kΩ resistor and results in amplification of the signal connected to the positive input. The amplification from the additional RREF can be computed by Thermal Pad The AD8222’s 4 mm × 4 mm LFCSP comes with a thermal pad. This pad is connected internally to −VS. The pad can either be left unconnected or connected to the negative supply rail. To preserve maximum pin compatibility with future dual instrumentation amplifiers, leave the pad unconnected. This can be done by not soldering the paddle at all or by soldering the part to a landing that is a not connected to any other net. For high vibration applications, a landing is recommended. Because the AD8222 dissipates little power, heat dissipation is rarely an issue. If improved heat dissipation is desired (for example, when driving heavy loads), connect the thermal pad to the negative supply rail. For the best heat dissipation performance, the negative supply rail should be a plane in the board. See the section for thermal coefficients with and without the pad soldered. 2 (10 kΩ + RREF ) 20 kΩ + RREF Common-Mode Rejection over Frequency The AD8222 has a higher CMRR over frequency than typical in-amps, which gives it greater immunity to disturbances, such as line noise and its associated harmonics. A well-implemented layout is required to maintain this high performance. Input source impedances should be matched closely. Source resistance should be placed close to the inputs so that it interacts with as little parasitic capacitance as possible. Parasitics at the RGx pins can also affect CMRR over frequency. The PCB should be laid out so that the parasitic capacitances at each pin match. Traces from the gain setting resistor to the RGx pins should be kept short to minimize parasitic inductance. 05947-054 Only the positive signal path is amplified; the negative path is unaffected. This uneven amplification degrades the amplifier’s CMRR. INCORRECT CORRECT CORRECT AD8222 VREF VREF + AD8222 VREF AD8222 + OP2177 – AD8222 – Reference Errors introduced at the reference terminal feed directly to the output. Care should be taken to tie REF to the appropriate local ground. Figure 45. Driving the Reference Pin LAYOUT The AD8222 is a high precision device. To ensure optimum performance at the PC board level, care must be taken in the design of the board layout. The AD8222 pinout is arranged in a logical manner to aid in this task. Power Supplies A stable dc voltage should be used to power the instrumentation amplifier. Noise on the supply pins can adversely affect performance. The AD8222 has two positive supply pins (Pin 5 and Pin 16) and two negative supply pins (Pin 8 and Pin 13). While the part functions with only one pin from each supply pair connected, both pins should be connected for specified performance and optimum reliability. Package Considerations The AD8222 comes in a 4 mm × 4 mm LFCSP. Beware of blindly copying the footprint from another 4 mm × 4 mm LFCSP part; it may not have the same thermal pad size and leads. Refer to the Outline Dimensions section to verify that the PCB symbol has the correct dimensions. Space between the leads and thermal pad should be kept as wide as possible for the best bias current performance. Rev. 0 | Page 16 of 24 AD8222 The AD8222 should be decoupled with 0.1 μF bypass capacitors, one for each supply. The positive supply decoupling capacitor should be placed near Pin 16, and the negative supply decoupling capacitor should be placed near Pin 8. Each supply should also be decoupled with a 10 μF tantalum capacitor. The tantalum capacitor can be placed further away from the AD8222 and can generally be shared by other precision integrated circuits. Figure 46 shows an example layout. INCORRECT +VS CORRECT +VS AD8222 REF AD8222 REF –VS TRANSFORMER +VS –VS TRANSFORMER +VS 0.1µF AD8222 REF AD8222 REF 10MΩ 16 15 14 13 –VS THERMOCOUPLE AD8222 1 2 RG 3 4 10 C 12 11 RG –VS THERMOCOUPLE +VS C +VS 9 5 6 7 8 AD8222 C REF fHIGH-PASS = 2π1 RC C R AD8222 REF R 05947-047 –VS –VS CAPACITIVELY COUPLED 0.1µF CAPACITIVELY COUPLED Figure 47. Creating an IBIAS Path 05947-046 INPUT PROTECTION All terminals of the AD8222 are protected against ESD (1 kV— human body model). In addition, the input structure allows for dc overload conditions of about 2½ V beyond the supplies. Figure 46. Example Layout SOLDER WASH The solder process can leave flux and other contaminants on the board. When these contaminants are between the AD8222 leads and thermal pad, they can create leakage paths that are larger than the AD8222’s bias currents. A thorough washing process removes these contaminants and restores the AD8222’s excellent bias current performance. Input Voltages Beyond the Rails For larger input voltages, an external resistor should be used in series with each input to limit current during overload conditions. The AD8222 can safely handle a continuous 6 mA current. The limiting resistor can be computed from RLIMIT ≥ VIN − VSUPPLY − 400 Ω 6 mA INPUT BIAS CURRENT RETURN PATH The input bias current of the AD8222 must have a return path to common. When the source, such as a thermocouple, cannot provide a return current path, one should be created, as shown in Figure 47. For applications where the AD8222 encounters extreme overload voltages, such as cardiac defibrillators, external series resistors and low leakage diode clamps, such as the BAV199L, the FJH1100s, or the SP720, should be used. Rev. 0 | Page 17 of 24 AD8222 Differential Input Voltages at High Gains When operating at high gain, large differential input voltages can cause more than 6 mA of current to flow into the inputs. This condition occurs when the differential voltage exceeds the following critical voltage VCRITICAL = (400 + RG) × (6 mA) This is true for differential voltages of either polarity. The maximum allowed differential voltage can be increased by adding an input protection resistor in series with each input. The value of each protection resistor should be RPROTECT = (VDIFF_MAX − VCRITICAL)/6 mA R 4.02kΩ CC 1nF 0.1µF –15V 10µF 05947-048 +15V 0.1µF CC 1nF R 4.02kΩ CD 10nF R1 499Ω –IN +IN 10µF AD8222 REF VOUT Figure 48. RFI Suppression RF INTERFERENCE RF rectification is often a problem when amplifiers are used in applications where there are strong RF signals. The disturbance can appear as a small dc offset voltage. High frequency signals can be filtered with a low-pass, RC network placed at the input of the instrumentation amplifier, as shown in Figure 48. The filter limits the input signal bandwidth according to the following relationship. Figure 48 shows an example where the differential filter frequency is approximately 2 kHz, and the common-mode filter frequency is approximately 40 kHz. Values of R and CC should be chosen to minimize RFI. Mismatch between the R × CC at the positive input and the R × CC at negative input degrades the CMRR of the AD8222. By using a value of CD 10× larger than the value of CC, the effect of the mismatch is reduced and performance is improved. FilterFreqDiff = FilterFreqCM = where CD ≥ 10CC. 1 2π R(2CD + CC ) 1 2π RCC COMMON-MODE INPUT VOLTAGE RANGE The three op amp architecture of the AD8222 applies gain and then removes the common-mode voltage. Therefore, internal nodes in the AD8222 experience a combination of both the gained signal and the common-mode signal. This combined signal can be limited by the voltage supplies even when the individual input and output signals are not. Figure 7 and Figure 8 show the allowable common-mode input voltage ranges for various output voltages, supply voltages, and gains. Rev. 0 | Page 18 of 24 AD8222 APPLICATIONS DIFFERENTIAL OUTPUT The differential configuration of the AD8222 has the same excellent dc precision specifications as the single-ended output configuration and is recommended for applications in the frequency range of dc to 100 kHz. The circuit configuration is shown in Figure 49. The differential output specification in Table 2 and Table 4 refer to this configuration only. The circuit includes an RC filter that maintains the stability of the loop. The transfer function for the differential output is: VDIFF_OUT = V+OUT − V−OUT = (V+IN − V−IN) × G where Setting the Common-Mode Voltage The output common-mode voltage is set by the average of +IN2 and REF2. The transfer function is VCM_OUT = (V+OUT + V−OUT)/2 = (V+IN2 + VREF2)/2 +IN2 and REF2 have different properties that allow the reference voltage to be easily set for a wide variety of applications. +IN2 has high impedance but cannot swing to the supply rails of the part. REF2 must be driven with a low impedance but can go 300 mV beyond the supply rails. A common application sets the common-mode output voltage to the midscale of a differential ADC. In this case, the ADC reference voltage would be sent to the +IN2 terminal, and ground would be connected to the REF2 terminal. This would produce a common-mode output voltage of half the ADC reference voltage. G =1+ 49.4 kΩ RG + 2-Channel Differential Output Using a Dual Op Amp +IN RG –IN AD8222 – – 10kΩ +OUT AD8222 + REF2 100pF +IN2 Another differential output topology is shown in Figure 50. Instead of a second in-amp, ½ of a dual OP2177 op amp creates the inverted output. Because the OP2177 comes in an MSOP, this configuration allows the creation of a dual channel, precision differential output in-amp with little board area. Errors from the op amp are common to both outputs and are thus common mode. Errors from mismatched resistors also create a common-mode dc offset. Because these errors are common mode, they will likely be rejected by the next device in the signal chain. +IN 05947-049 –OUT Figure 49. Differential Circuit Schematic AD8222 –IN REF 4.99kΩ VREF +OUT 4.99kΩ + – OP2177 –OUT Figure 50. Differential Output Using Op Amp Rev. 0 | Page 19 of 24 05947-053 AD8222 +12V + 10µF 0.1µF +5V 100pF NPO 5% +OUT 1000pF –IN 1kΩ 100pF NPO 5% +IN2 (DIFF OUT) –OUT REF2 1kΩ 1kΩ 2200pF 2200pF 0.1µF VDD +IN 1kΩ AD8222 IN+ IN– AD7688 GND REF +5V REF 10µF + 0.1µF –12V 0.1µF +12V 10µF X5R VIN VOUT 0.1µF +5V REF ADR435 GND Figure 51. Driving a Differential ADC DRIVING A DIFFERENTIAL INPUT ADC The AD8222 can be configured in differential output mode to drive a differential analog-to-digital converter. Figure 51 illustrates several of the concepts. First Antialiasing Filter The 1 kΩ resistor, 1000 pF capacitor, and 100 pF capacitors in front of the in-amp form a 76 kHz filter. This is the first of two antialiasing filters in the circuit and helps to reduce the noise of the system. The 100 pF capacitors protect against commonmode RFI signals. Note that they are 5% COG/NPO types. These capacitors match well over time and temperature, which keeps the system’s CMRR high over frequency. The 1 kΩ resistors can also protect an ADC from overvoltages. Because the AD8222 runs on wider supply voltages than a typical ADC, there is a possibility of overdriving the ADC. This is not an issue with a PulSAR® converter, such as the AD7688. Its input can handle a 130 mA overdrive, which is much higher than the short-circuit limit of the AD8222. However, other converters have less robust inputs and may need the added protection. Reference The ADR435 supplies a reference voltage to both the ADC and the AD8222. Because REF2 on the AD8222 is grounded, the common-mode output voltage is precisely half the reference voltage, exactly where it needs to be for the ADC. Second Antialiasing Filter A 1 kΩ resistor and 2200 pF capacitor are located between each AD8222 output and ADC input. They create a 72 kHz low-pass filter for another stage of antialiasing protection. These four elements also help distortion performance. The 2200 pF capacitor provides charge to the switched capacitor front end of the ADC, while the 1 kΩ resistor shields the AD8222 from driving any sharp current changes. If the application requires a lower frequency antialiasing filter and is distortion sensitive, increase the value of the capacitor rather than the resistor. PRECISION STRAIN GAUGE The low offset and high CMRR over frequency of the AD8222 make it an excellent candidate for both ac and dc bridge measurements. As shown in Figure 52, the bridge can be connected to the inputs of the amplifier directly. 5V 10µF 350Ω 350Ω +IN 350Ω 350Ω RG –IN + 0.1µF 05947-051 AD8222 – 05947-050 2.5V Figure 52. Precision Strain Gauge Rev. 0 | Page 20 of 24 AD8222 DRIVING CABLING All cables have a certain capacitance per unit length, which varies widely with cable type. The capacitive load from the cable may cause peaking in the AD8222’s output response. To reduce the peaking, use a resistor between the AD8222 and the cable. Because cable capacitance and desired output response vary widely, this resistor is best determined empirically. A good starting point is 50 Ω. The AD8222 operates at a low enough frequency that transmission line effects are rarely an issue; therefore, the resistor need not match the characteristic impedance of the cable. AD8222 (DIFF OUT) (SINGLE OUT) AD8222 Figure 53. Driving a Cable Rev. 0 | Page 21 of 24 05947-052 AD8222 OUTLINE DIMENSIONS 4.00 BSC SQ 0.60 MAX 12 13 0.50 0.40 0.30 PIN 1 INDICATOR 16 1 PIN 1 INDICATOR 3.75 BSC SQ 0.65 BSC TOP VIEW 9 EXPOSED PAD 4 8 5 2.65 2.50 SQ 2.35 0.25 MIN 1.95 BCS 0.80 MAX 0.65 TYP BOT TOM VIEW COMPLIANT TO JEDEC STANDARDS MO-220-VGGC. Figure 54. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-16-13) Dimensions are shown in millimeters ORDERING GUIDE Model AD8222ACPZ-R7 1 AD8222ACPZ-RL1 AD8222ACPZ-WP1 AD8222BCPZ-R71 AD8222BCPZ-RL1 AD8222BCPZ-WP1 AD8222-EVAL 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Product Description 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ 16-Lead LFCSP_VQ Evaluation Board 031006-A 12° MAX 1.00 0.85 0.80 SEATING 0.30 PLANE 0.23 0.18 0.05 MAX 0.02 NOM COPLANARITY 0.20 REF 0.08 Package Option CP-16-13 CP-16-13 CP-16-13 CP-16-13 CP-16-13 CP-16-13 Z = Pb-free part. Rev. 0 | Page 22 of 24 AD8222 NOTES Rev. 0 | Page 23 of 24 AD8222 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05947-0-7/06(0) Rev. 0 | Page 24 of 24