AD8569

a FEATURES Single-Supply Operation: 4.5 V to 16 V Input Capability Beyond the Rails Rail-to-Rail Output Swing Continuous Output Current: 35 mA Peak Output Current: 250 mA Offset Voltage: 10 mV Max Slew Rate: 6 V/ s Stable with 1 F Loads Supply Current APPLICATIONS LCD Reference Drivers Portable Electronics Communications Equipment 16 V Rail-to-Rail Buffer Amplifiers AD8568/AD8569/AD8570 PIN CONFIGURATIONS 6-Lead SOT-23 (RT Suffix) OUT A 1 IN A GND 2 3 6 5 4 OUT B V+ IN B AD8568 10-Lead MSOP (RM Suffix) OUT A 1 IN A V+ 2 3 4 10 OUT D 9 IN D GND IN C OUT C AD8569 8 7 6 GENERAL DESCRIPTION These LCD buffers have high slew rates, 35 mA continuous output drive, and high capacitive load drive capability. They have a wide supply range and offset voltages below 10 mV. The AD8568, AD8569, and AD8570 are specified over the –40°C to +85°C temperature range. They are available on tape and reel, with the AD8568 packaged in a 6-lead SOT-23, the AD8569 in a 10-lead MSOP, and the AD8570 in a 32-lead LFCSP and 20-lead TSSOP. V+ 1 NC 2 IN C 3 IN D 4 IN E 5 IN F 6 NC 7 V+ 8 32 NC 31 IN B 30 IN A 29 NC 28 NC 27 OUT A 26 OUT B 25 NC PIN 1 INDICATOR The AD8568, AD8569, and AD8570 are low-cost, single-supply buffer amplifiers with rail-to-rail input and output capability. They are optimized for LCD monitor applications and built on an advanced high voltage CBCMOS process. The AD8568 includes two buffers, the AD8569 includes four buffers, and the AD8570 includes eight buffers. IN B OUT B 5 32-Lead LFCSP (CP Suffix) AD8570 TOP VIEW 24 GND 23 NC 22 OUT C 21 OUT D 20 OUT E 19 OUT F 18 NC 17 GND NC = NO CONNECT NC 9 IN G 10 IN H 11 NC 12 NC 13 OUT H 14 OUT G 15 NC 16 20-Lead TSSOP IN 1 1 20 OUT 1 19 OUT 2 18 V– IN 2 2 V+ 3 IN 3 4 IN 4 5 IN 5 6 IN 6 7 V+ 8 AD8570-ARU TOP VIEW 17 OUT 3 16 OUT 4 15 OUT 5 14 OUT 6 13 V– 12 OUT 7 11 OUT 8 REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. IN 7 9 IN 8 10 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 w ww.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. AD8568/AD8569/AD8570–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (4.5 V ≤ V ≤ 16 V, V S CM = VS/2, TA = 25 C, unless otherwise noted.) Min Typ 2 5 80 –0.5 Max 10 Unit Parameter INPUT CHARACTERISTICS Offset Voltage Offset Voltage Drift Input Bias Current Input Voltage Range Input Impedance Input Capacitance OUTPUT CHARACTERISTICS Output Voltage High Symbol VOS ∆VOS/∆T IB ZIN CIN VOH Conditions –40°C ≤ TA ≤ +85°C –40°C ≤ TA ≤ +85°C 400 1 IL = 100 µA VS = 16 V, IL = 5 mA –40°C ≤ TA ≤ +85°C VS = 4.5 V, IL = 5 mA –40°C ≤ TA ≤ +85°C IL = 100 µA VS = 16 V, IL = 5 mA –40°C ≤ TA ≤ +85°C VS = 4.5 V, IL = 5 mA –40°C ≤ TA ≤ +85°C VS = 1 6 V R L = 2 kΩ –40°C ≤ TA ≤ +85°C RL = 2 kΩ, VO = 0.5 to (VS – 0.5 V) 0.995 0.995 VS – 0.005 15.95 4.38 5 42 95 35 250 0.9985 0.9980 0.01 mV µV/°C 600 nA 800 nA –VS + 0.5 V kΩ pF V V V V V mV mV mV mV mV mA mA V/V V/V % V dB µA mA V/µs MHz Degrees dB nV/√Hz nV/√Hz pA/√Hz 15.85 15.75 4.2 4.1 Output Voltage Low VOL 150 250 300 400 Continuous Output Current Peak Output Current TRANSFER CHARACTERISTICS Gain Gain Linearity POWER SUPPLY Supply Voltage Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Bandwidth Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Density Current Noise Density Specifications subject to change without notice. IOUT IPK AVCL NL VS PSRR ISY 1.005 1.005 4.5 VS = 4 V to 17 V –40°C ≤ TA ≤ +85°C VO = VS/2, No Load –40°C ≤ TA ≤ +85°C RL = 10 kΩ, CL = 200 pF –3 dB, RL = 10 kΩ, CL = 10 pF RL = 10 kΩ, CL = 10 pF 70 90 700 16 850 1 SR BW Øo 4 6 6 65 75 26 25 0.8 en en in f = 1 kHz f = 10 kHz f = 10 kHz – 2– REV. C AD8568/AD8569/AD8570 ABSOLUTE MAXIMUM RATINGS * Supply Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Input Voltage . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VS + 0.5 V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VS Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Operating Temperature Range . . . . . . . . . . . –40°C to +85°C Junction Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300°C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Type 6-Lead SOT-23 (RT) 10-Lead MSOP (RM) 20-Lead TSSOP (RU) 32-Lead LFCSP (CP) 1 JA JC 2 JB Unit °C/W °C/W °C/W °C/W 250 200 72 35 140 44 45 13 NOTES 1 θJA is specified for worst-case conditions, i.e., θJA is specified for a device soldered onto a circuit board for surface-mount packages. 2 JB is applied for calculating the junction temperature by reference to the board temperature. ORDERING GUIDE Model AD8568ART-R2 AD8568ART-REEL AD8568ART-REEL7 AD8569ARM-R2 AD8569ARM-REEL AD8569ARMZ-REEL* AD8570ACP-R2 AD8570ACP-REEL AD8570ACP-REEL7 AD8570ARU AD8570ARU-REEL *Z = Pb-free part. Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description 6-Lead SOT-23 6-Lead SOT-23 6-Lead SOT-23 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 32-Lead LFCSP 32-Lead LFCSP 32-Lead LFCSP 20-Lead TSSOP 20-Lead TSSOP Package Option RT-6 RT-6 RT-6 RM-10 RM-10 RM-10 CP-32-2 CP-32-2 CP-32-2 RU-20 RU-20 Branding Information AWA AWA AWA AXA AXA AXA CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8568/AD8569/AD8570 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. C – 3– AD8568/AD8569/AD8570 –Typical Performance Characteristics 100 90 80 TA = 25 C 4.5V < VS < 16V 0 VCM = VS/2 50 INPUT BIAS CURRENT (nA) VS = 16V 100 150 VS = 4.5V 200 250 300 QUANTITY (Amplifiers) 70 60 50 40 30 20 10 0 12 9 0 3 6 6 3 INPUT OFFSET VOLTAGE (mV) 9 12 350 40 25 TEMPERATURE ( C) 85 TPC 1. Input Offset Voltage Distribution TPC 4. Input Bias Current vs. Temperature 300 4.5V < VS < 16V 250 5 4 INPUT OFFSET CURRENT (nA) 3 2 1 VS = 4.5V 0 1 2 3 4 VS = 16V QUANTITY (Amplifiers) 200 150 100 50 0 0 10 20 30 40 50 60 TCVOS ( V/ C) 70 80 90 100 5 40 25 TEMPERATURE ( C) 85 TPC 2. Input Offset Voltage Drift Distribution TPC 5. Input Offset Current vs. Temperature 0 VCM = VS /2 15.96 ILOAD = 5mA 15.95 VS = 16V OUTPUT VOLTAGE SWING (V) 4.46 4.45 4.44 4.43 4.42 4.41 4.40 VS = 4.5V 4.39 4.38 4.37 4.36 40 25 TEMPERATURE ( C) 85 INPUT OFFSET VOLTAGE (mV) 0.25 15.94 15.93 15.92 15.91 15.90 15.89 15.88 15.87 0.50 VS = 16V 0.75 1.00 VS = 4.5V 1.25 1.50 40 25 TEMPERATURE ( C) 85 15.86 TPC 3. Input Offset Voltage vs. Temperature TPC 6. Output Voltage Swing vs. Temperature – 4– REV. C AD8568/AD8569/AD8570 150 ILOAD = 5mA 135 SUPPLY CURRENT/AMPLIFIER (mA) 0.80 VCM = VS /2 0.75 VS = 16V 0.70 OUTPUT VOLTAGE SWING (mV) 120 105 90 VS = 4.5V 75 60 45 VS = 16V 30 15 0 40 25 TEMPERATURE ( C) 85 0.65 0.60 VS = 4.5V 0.55 0.50 40 25 TEMPERATURE ( C) 85 TPC 7. Output Voltage Swing vs. Temperature TPC 10. Supply Current/Amplifier vs. Temperature 0.9999 4.5V < VS < 16V VOUT = 0.5V TO 15V RL = 2k GAIN ERROR (V/V) 7 6 5 VS = 16V SLEW RATE (V/ s) VS = 4.5V 4 3 2 1 0.9997 RL = 600 0.9995 40 25 TEMPERATURE ( C) 85 0 RL = 10k CL = 200pF 40 25 TEMPERATURE ( C) 85 TPC 8. Voltage Gain vs. Temperature TPC 11. Slew Rate vs. Temperature 1k TA = 25 C 1.0 0.9 TA = 25 C AV = +1 VO = VS /2 SUPPLY CURRENT/AMPLIFIER (mA) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 OUTPUT VOLTAGE (mV) 100 VS = 4.5V 10 VS = 16V 1 0.1 0.001 0 0.01 0.1 1 LOAD CURRENT (mA) 10 100 0 2 4 6 8 10 12 SUPPLY VOLTAGE (V) 14 16 18 TPC 9. Output Voltage to Supply Rail vs. Load Current TPC 12. Supply Current/Amplifier vs. Supply Voltage REV. C – 5– AD8568/AD8569/AD8570 10 5 1k 0 5 GAIN (dB) 10 15 20 150 25 30 35 TA = 25 C VS = 8V VIN = 50mV rms CL = 40pF AV = +1 1M 10M FREQUENCY (Hz) 100M 560 OUTPUT SWING (V p-p) 10k 14 12 10 8 6 4 2 0 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) TA = 25 C VS = 16V AV = +1 RL = 10k DISTORTION < 1% 18 16 40 100k TPC 13. Frequency Response vs. Resistive Loading TPC 16. Closed-Loop Output Swing vs. Frequency 25 POWER SUPPLY REJECTION RATIO (dB) 20 15 10 GAIN (dB) 5 0 50pF 5 1040pF 10 15 20 25 100k 540pF 100pF TA = 25 C VS = 8V VIN = 50mV rms RL = 10k AV = +1 160 140 120 100 80 +PSRR 60 40 PSRR 20 0 20 40 100 1k 10k 100k FREQUENCY (Hz) 1M 10M TA = 25 C VS = 16V 1M 10M FREQUENCY (Hz) 100M TPC 14. Frequency Response vs. Capacitive Loading TPC 17. Power Supply Rejection Ratio vs. Frequency 500 160 POWER SUPPLY REJECTION RATIO (dB) 450 400 350 140 120 100 TA = 25 C VS = 4.5V IMPEDANCE ( ) +PSRR 80 60 40 20 0 20 40 100 1k 10k 100k FREQUENCY (Hz) 1M 10M PSRR 300 250 200 150 100 50 0 100 1k 10k 100k FREQUENCY (Hz) VS = 4.5V VS = 16V 1M 10M TPC 15. Closed-Loop Output Impedance vs. Frequency TPC 18. Power Supply Rejection Ratio vs. Frequency – 6– REV. C AD8568/AD8569/AD8570 1,000 TA = 25 C 4.5V VS VOLTAGE NOISE DENSITY (nV/ Hz) 100 16V 90 80 OVERSHOOT (%) 100 70 60 50 40 30 20 10 TA = 25 C VS = 4.5V VCM = 2.25V VIN = 100mV p-p AV = +1 RL = 10k 10 OS +OS 1 10 1k 100 FREQUENCY (Hz) 10k 0 10 100 LOAD CAPACITANCE (pF) 1k TPC 19. Voltage Noise Density vs. Frequency TPC 22. Small Signal Overshoot vs. Load Capacitance 20 0 TA = 25 C 4.5V < VS < 16V 15 TA = 25 C VS = 8V RL = 10k CHANNEL SEPARATION (dB) 20 40 60 80 100 120 140 160 180 100 OUTPUT SWING FROM 0V TO V 10 5 OVERSHOOT SETTLING TO 0.1% 0 5 UNDERSHOOT SETTLING TO 0.1% 10 15 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 0 0.5 1.0 SETTLING TIME ( s) 1.5 2.0 TPC 20. Channel Separation vs. Frequency TPC 23. Settling Time vs. Step Size 100 90 80 70 TA = 25 C VS = 16V VCM = 8V VIN = 100mV p-p AV = +1 RL = 10k 0 0 0 TA = 25 C VS = 16V AV = +1 RL = 10k CL = 300pF VOLTAGE (3V/DIV) OVERSHOOT (%) 60 50 40 OS 30 20 10 0 10 100 LOAD CAPACITANCE (pF) 1k +OS 0 0 0 0 0 0 0 0 0 0 0 0 TIME (2 s/DIV) 0 0 0 TPC 21. Small Signal Overshoot vs. Load Capacitance TPC 24. Large Signal Transient Response REV. C – 7– AD8568/AD8569/AD8570 0 0 0 TA = 25 C VS = 4.5V AV = +1 RL = 10k CL = 300pF 0 0 0 TA = 25 C VS = 4.5V AV = +1 RL = 10k CL = 100pF VOLTAGE (50mV/DIV) VOLTAGE (1V/DIV) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIME (2 s/DIV) 0 0 0 0 0 0 0 0 TIME (1 s/DIV) 0 0 0 TPC 25. Large Signal Transient Response TPC 27. Small Signal Transient Response 0 0 0 TA = 25 C VS = 16V AV = +1 RL = 10k CL = 100pF 0 0 0 TA = 25 C VS = 16V AV = +1 RL = 10k VOLTAGE (50mV/DIV) VOLTAGE (3V/DIV) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIME (1 s/DIV) 0 0 0 0 0 0 0 0 TIME (40 s/DIV) 0 0 0 TPC 26. Small Signal Transient Response TPC 28. No Phase Reversal – 8– REV. C AD8568/AD8569/AD8570 APPLICATIONS Theory of Operation MAXIMUM POWER DISSIPATION – W This family of buffers is designed to drive large capacitive loads in LCD applications. Each has high output current drive and railto-rail input/output operation and can be powered from a single 16 V supply. They are also intended for other applications where low distortion and high output current drive are needed. Input Overvoltage Protection Figure 1 shows the maximum power dissipation versus temperature. To achieve proper operation, use the previous equation to calculate PDISS for a specific package at any given temperature, or see Figure 1. 1.00 0.75 10-LEAD MSOP 6-LEAD SOT-23 0.50 As with any semiconductor device, whenever the input exceeds either supply voltage, attention needs to be paid to the input overvoltage characteristics. As an overvoltage occurs, the amplifier could be damaged, depending on the voltage level and the magnitude of the fault current. When the input voltage exceeds either supply by more than 0.6 V, the internal pn junctions will allow current to flow from the input to the supplies. This input current is not inherently damaging to the device as long as it is limited to 5 mA or less. If a condition exists using the buffers where the input exceeds the supply by more than 0.6 V, an external series resistor should be added. The size of the resistor can be calculated by using the maximum overvoltage divided by 5 mA. This resistance should be placed in series with the input exposed to an overvoltage. Output Phase Reversal 0.25 0 35 15 5 25 45 AMBIENT TEMPERATURE – C 65 85 Figure 1. Maximum Power Dissipation vs. Temperature for 6- and 10-Lead Packages Total Harmonic Distortion + Noise (THD+N) The buffer family is immune to phase reversal. Although the device’s output will not change phase, large currents due to input overvoltage could damage the device. In applications where the possibility exists of an input voltage exceeding the supply voltage, overvoltage protection should be used as described in the previous section. Power Dissipation The buffer family features low THD+N. The total harmonic distortion plus noise for the buffer over the entire supply range is below 0.08%. When the device is powered from a 16 V supply, the THD+N stays below 0.03%. Figure 2 shows the AD8568 THD+N versus frequency performance. 10 The maximum allowable internal junction temperature of 150°C limits the device’s maximum power dissipation. As the ambient temperature increases, the maximum power dissipated by the device must decrease linearly to maintain the maximum junction temperature. If this maximum junction temperature is exceeded momentarily, the device will still operate properly once the junction temperature is reduced below 150°C. If the maximum junction temperature is exceeded for an extended period of time, overheating could lead to permanent damage of the device. The maximum safe junction temperature, TJMAX, is 150°C. Using the following formula, we can obtain the maximum power that the buffer family can safely dissipate as a function of temperature. 1 THD + N – %  0.1 VS = VS = 2.5V 8V 0.01 PDISS = (TJMAX − TA ) / θ JA where: PDISS = the power dissipation. TJMAX = the maximum allowable junction temperature (150°C). TA = the ambient temperature of the circuit. θJA = the AD856x package thermal resistance, junction-to-ambient. The power dissipated by the device can be calculated as 20 100 1k FREQUENCY – Hz 10k 30k Figure 2. AD8568 THD+N vs. Frequency Short-Circuit Output Conditions The buffer family does not have internal short-circuit protection circuitry. As a precautionary measure, do not short the output directly to the positive power supply or to ground. It is not recommended to operate the AD856x with more than 35 mA of continuous output current. The output current can be limited by placing a series resistor at the output of the amplifier whose value can be derived using the following equation. PDISS = (VS − VOUT ) × I LOAD where: VS = the supply voltage. VOUT = the output voltage. ILOAD = the output load current. REV. C RX ≥ VS 35 mA For a 5 V single-supply operation, RX should have a minimum value of 143 Ω. – 9– AD8568/AD8569/AD8570 OUTLINE DIMENSIONS 6-Lead Small Outline Transistor Package [SOT-23] (RT-6) Dimensions shown in millimeters 10-Lead Micro Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 2.90 BSC 3.00 BSC 6 5 4 10 6 1.60 BSC 1 2 3 2.80 BSC 3.00 BSC 1 5 4.90 BSC PIN 1 0.95 BSC 1.30 1.15 0.90 1.90 BSC PIN 1 0.50 BSC 0.95 0.85 0.75 1.45 MAX 0.22 0.08 10 4 0 0.60 0.45 0.30 0.15 0.00 0.27 0.17 1.10 MAX 8 0 0.80 0.60 0.40 SEATING PLANE 0.23 0.08 0.15 MAX 0.50 0.30 SEATING PLANE COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187BA COMPLIANT TO JEDEC STANDARDS MO-178AB 32-Lead Lead Frame Chip Scale Package [LFCSP] 5 x 5 mm Body (CP-32-2) Dimensions shown in millimeters 5.00 BSC SQ 0.60 MAX 0.60 MAX 25 24 32 1 PIN 1 INDICATOR PIN 1 INDICATOR TOP VIEW 4.75 BSC SQ 0.50 BSC BOTTOM VIEW 3.25 3.10 SQ 2.95 8 0.50 0.40 0.30 12 MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 17 16 9 0.25 MIN 3.50 REF 1.00 0.85 0.80 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 – 10– REV. C AD8568/AD8569/AD8570 OUTLINE DIMENSIONS 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters 6.60 6.50 6.40 20 11 4.50 4.40 4.30 1 10 6.40 BSC PIN 1 0.65 BSC 0.15 0.05 0.30 COPLANARITY 0.19 0.10 1.20 MAX 0.20 0.09 SEATING PLANE 8 0 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153AC Revision History Location 12/03—Data Sheet changed from REV. B to REV. C. Page Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5/02—Data Sheet changed from REV. A to REV. B. Added 20-Lead TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Added Package Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Added TSSOP Package to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 REV. C – 11– – 12– C02612–0–12/03(C)