Zero-Drift, Single-Supply, Rail-to-Rail Input/Output Operational Amplifiers AD8571/AD8572/AD8574
FEATURES
Low offset voltage: 1 μV Input offset drift: 0.005 μV/°C Rail-to-rail input and output swing 5 V/2.7 V single-supply operation High gain: 145 dB typical CMRR: 140 dB typical PSRR: 130 dB typical Ultralow input bias current: 10 pA typical Low supply current: 750 μA/op amp Overload recovery time: 50 μs No external capacitors required
NC –IN A +IN A V–
1 2 3 4
PIN CONFIGURATIONS
8
NC V+ OUT A
01104-001
AD8571
NC 1 –IN A 2 +IN A 3
8
NC V+
7
TOP VIEW 6 (Not to Scale)
5
AD8571
7
NC = NO CONNECT
NC = NO CONNECT
Figure 1. 8-Lead MSOP (RM Suffix)
Figure 2. 8-Lead SOIC (R Suffix)
OUT A 1 –IN A V–
2
8
V+ OUT B
01104-002
OUT A –IN A +IN A V–
1 2 3 4
8
V+ OUT B +IN B
01104-005
AD8572
TOP VIEW (Not to Scale)
7 6 5
AD8572
TOP VIEW (Not to Scale)
7 6 5
+IN A 3
4
–IN B +IN B
–IN B
APPLICATIONS
Temperature sensors Pressure sensors Precision current sensing Strain gage amplifiers Medical instrumentation Thermocouple amplifiers
Figure 3. 8-Lead TSSOP (RU Suffix)
Figure 4. 8-Lead SOIC (R Suffix)
OUT A 1 –IN A 2 +IN A 3 V+ 4 +IN B 5 –IN B 6 OUT B 7
14 13
OUT D –IN D +IN D
OUT A 1 –IN A 2 +IN A 3 V+ 4 +IN B 5 –IN B 6
01104-003
14 13
OUT D –IN D +IN D
AD8574
12
AD8574
12
11 V– TOP VIEW (Not to Scale) 10 +IN C 9 8
11 V– TOP VIEW (Not to Scale) 10 +IN C
01104-006
–IN C OUT C
9 8
–IN C OUT C
OUT B 7
Figure 5. 14-Lead TSSOP (RU Suffix)
Figure 6. 14-Lead SOIC (R Suffix)
GENERAL DESCRIPTION
This family of amplifiers has ultralow offset, drift, and bias current. The AD8571, AD8572, and AD8574 are single, dual, and quad amplifiers, respectively, featuring rail-to-rail input and output swings. All are guaranteed to operate from 2.7 V to 5 V single supply. The AD857x family provides benefits previously found only in expensive auto-zeroing or chopper-stabilized amplifiers. Using Analog Devices, Inc. topology, these zero-drift amplifiers combine low cost with high accuracy. (No external capacitors are required.) Using a patented spread-spectrum, auto-zero technique, the AD857x family eliminates the intermodulation effects from interaction of the chopping function with the signal frequency in ac applications. With an offset voltage of only 1 μV and drift of 0.005 μV/°C, the AD857x family is perfectly suited for applications where error sources cannot be tolerated. Position and pressure sensors, medical equipment, and strain gage amplifiers benefit greatly from nearly zero drift over their operating temperature range. Many more systems require the rail-to-rail input and output swings provided by the AD857x family. The AD857x family is specified for the extended industrial/ automotive (−40°C to +125°C) temperature range. The AD8571 single amplifier is available in 8-lead MSOP and narrow 8-lead SOIC packages. The AD8572 dual amplifier is available in 8-lead narrow SOIC and 8-lead TSSOP surface-mount packages. The AD8574 quad amplifier is available in 14-lead narrow SOIC and 14-lead TSSOP packages.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©1999–2007 Analog Devices, Inc. All rights reserved.
01104-004
NC
6 OUT A TOP VIEW V– 4 (Not to Scale) 5 NC
AD8571/AD8572/AD8574 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Pin Configurations ........................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 5 V Electrical Characteristics...................................................... 3 2.7 V Electrical Characteristics................................................... 4 Absolute Maximum Ratings............................................................ 5 Thermal Characteristics .............................................................. 5 ESD Caution.................................................................................. 5 Typical Performance Characteristics ............................................. 6 Functional Description .................................................................. 14 Amplifier Architecture .............................................................. 14 Basic Auto-Zero Amplifier Theory.......................................... 14 Auto-Zero Phase......................................................................... 14 Amplification Phase ................................................................... 15 High Gain, CMRR, and PSRR .................................................. 16 Maximizing Performance Through Proper Layout ............... 16 1/f Noise Characteristics ........................................................... 17 Random Auto-Zero Correction Eliminates Intermodulation Distortion .................................................................................... 17 Broadband and External Resistor Noise Considerations.......... 18 Output Overdrive Recovery...................................................... 18 Input Overvoltage Protection ................................................... 18 Output Phase Reversal............................................................... 18 Capacitive Load Drive ............................................................... 19 Power-Up Behavior .................................................................... 19 Applications..................................................................................... 20 5 V Precision Strain Gage Circuit ............................................ 20 3 V Instrumentation Amplifier ................................................ 20 High Accuracy Thermocouple Amplifier ............................... 21 Precision Current Meter............................................................ 21 Precision Voltage Comparator.................................................. 21 Outline Dimensions ....................................................................... 22 Ordering Guide .......................................................................... 23
REVISION HISTORY
5/07—Rev. B to Rev. C Changes to Features.......................................................................... 1 Changes to Table 1............................................................................ 3 Changes to Table 2............................................................................ 4 Changes to Basic Auto-Zero Amplifier Theory Section ........... 14 Changes to Figure 50...................................................................... 15 Changes to Figure 55...................................................................... 16 Changes to Figure 66...................................................................... 21 Updated Outline Dimensions ....................................................... 22 9/06—Rev. A to Rev. B Updated Format..................................................................Universal Changes to Table 1.............................................................................3 Changes to Table 2.............................................................................4 Changes to Figure 50...................................................................... 14 Changes to Figure 51...................................................................... 15 Changes to Figure 66...................................................................... 21 Deleted Figure 69 and SPICE Macro-Model Section ................ 17 Deleted SPICE Macro-Model for the AD857x Section ............. 18 Updated Outline Dimensions....................................................... 22 Changes to Ordering Guide .......................................................... 23 7/03—Rev. 0 to Rev. A Renumbered Figures ..........................................................Universal Changes to Ordering Guide .............................................................4 Change to Figure 15. ...................................................................... 16 Updated Outline Dimensions....................................................... 19 10/99—Revision 0: Initial Version
Rev. C | Page 2 of 24
AD8571/AD8572/AD8574 SPECIFICATIONS
5 V ELECTRICAL CHARACTERISTICS
VS = 5 V, VCM = 2.5 V, VO = 2.5 V, TA = 25°C, unless otherwise noted. Table 1.
Parameter INPUT CHARACTERISTICS Offset Voltage Input Bias Current AD8571/AD8574 AD8572 Input Offset Current AD8571/AD8574 AD8572 Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain 1 Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage High Symbol VOS −40°C ≤ TA ≤ +125°C IB −40°C ≤ TA ≤ +125°C −40°C ≤ TA ≤ +85°C −40°C ≤ TA ≤ +125°C IOS −40°C ≤ TA ≤ +125°C −40°C ≤ TA ≤ +85°C −40°C ≤ TA ≤ +125°C CMRR AVO ∆VOS/∆T VOH VCM = 0 V to 5 V −40°C ≤ TA ≤ +125°C RL = 10 kΩ, VO = 0.3 V to 4.7 V −40°C ≤ TA ≤ +125°C −40°C ≤ TA ≤ +125°C RL = 100 kΩ to GND RL = 100 kΩ to GND @ −40°C to +125°C RL = 10 kΩ to GND RL = 10 kΩ to GND @ −40°C to +125°C RL = 100 kΩ to V+ RL = 100 kΩ to V+ @ −40°C to +125°C RL = 10 kΩ to V+ RL = 10 kΩ to V+ @ −40°C to +125°C −40°C to +125°C Output Current POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Overload Recovery Time Gain Bandwidth Product NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density
1
Conditions
Min
Typ 1 10 1.0 160 2.5 20 150 30 150
Max 5 10 50 1.5 300 4 70 200 150 400 5
Unit μV μV pA nA pA nA pA pA pA pA V dB dB dB dB μV/°C V V V V mV mV mV mV mA mA mA mA dB dB μA μA V/μs ms MHz μV p-p μV p-p nV/√Hz fA/√Hz
0 120 115 125 120
140 130 145 135 0.005 4.998 4.997 4.98 4.975 1 2 10 15 ±50 ±40 ±30 ±15 130 130 850 1000 0.4 0.05 1.5 1.3 0.41 51 2
0.04
4.99 4.99 4.95 4.95
Output Voltage Low
VOL
10 10 30 30
Short-Circuit Limit
ISC IO −40°C to +125°C PSRR ISY VS = 2.7 V to 5.5 V −40°C ≤ TA ≤ +125°C VO = 0 V −40°C ≤ TA ≤ +125°C RL = 10 kΩ
±25
120 115
975 1075
SR GBP en p-p en in
0.3
0 Hz to 10 Hz 0 Hz to 1 Hz f = 1 kHz f = 10 Hz
Gain testing is dependent upon test bandwidth.
Rev. C | Page 3 of 24
AD8571/AD8572/AD8574
2.7 V ELECTRICAL CHARACTERISTICS
VS = 2.7 V, VCM = 1.35 V, VO = 1.35 V, TA = 25°C, unless otherwise noted. Table 2.
Parameter INPUT CHARACTERISTICS Offset Voltage Input Bias Current AD8571/AD8574 AD8572 Input Offset Current AD8571/AD8574 AD8572 Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain 1 Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage High Symbol VOS −40°C ≤ TA ≤ +125°C IB −40°C ≤ TA ≤ +125°C −40°C ≤ TA ≤ +85°C −40°C ≤ TA ≤ +125°C IOS −40°C ≤ TA ≤ +125°C −40°C ≤ TA ≤ +85°C −40°C ≤ TA ≤ +125°C CMRR AVO ∆VOS/∆T VOH VCM = 0 V to 2.7 V −40°C ≤ TA ≤ +125°C RL = 10 kΩ, VO = 0.3 V to 2.4 V −40°C ≤ TA ≤ +125°C −40°C ≤ TA ≤ +125°C RL = 100 kΩ to GND RL = 100 kΩ to GND @ −40°C to +125°C RL = 10 kΩ to GND RL = 10 kΩ to GND @ −40°C to +125°C RL = 100 kΩ to V+ RL = 100 kΩ to V+ @ −40°C to +125°C RL = 10 kΩ to V+ RL = 10 kΩ to V+ @ −40°C to +125°C −40°C to +125°C Output Current POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Overload Recovery Time Gain Bandwidth Product NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density
1
Conditions
Min
Typ 1 10 1.0 160 2.5 10 150 30 150
Max 5 10 50 1.5 300 4 50 200 150 400 2.7
Unit μV μV pA nA pA nA pA pA pA pA V dB dB dB dB μV/°C V V V V mV mV mV mV mA mA mA mA dB dB μA μA V/μs ms MHz μV p-p nV/√Hz fA/√Hz
0 115 110 110 105
130 130 140 130 0.005 2.697 2.696 2.68 2.675 1 2 10 15 ±15 ±10 ±10 ±5 130 130 750 950 0.5 0.05 1 2.0 94 2
0.04
2.685 2.685 2.67 2.67
Output Voltage Low
VOL
10 10 20 20
Short-Circuit Limit
ISC IO −40°C to +125°C PSRR ISY VS = 2.7 V to 5.5 V −40°C ≤ TA ≤ +125°C VO = 0 V −40°C ≤ TA ≤ +125°C RL = 10 kΩ
±10
120 115
900 1000
SR GBP en p-p en in
0 Hz to 10 Hz f = 1 kHz f = 10 Hz
Gain testing is dependent upon test bandwidth.
Rev. C | Page 4 of 24
AD8571/AD8572/AD8574 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Supply Voltage Input Voltage Differential Input Voltage 1 ESD (Human Body Model) Output Short-Circuit Duration to GND Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 60 sec)
1
Rating 6V GND to VS + 0.3 V ±5.0 V 2000 V Indefinite −65°C to +150°C −40°C to +125°C −65°C to +150°C 300°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
θJA is specified for the worst-case conditions, that is, θJA is specified for a device soldered in a circuit board for SOIC and TSSOP packages. Table 4. Thermal Resistance
Package Type 8-Lead MSOP (RM) 8-Lead TSSOP (RU) 8-Lead SOIC (R) 14-Lead TSSOP (RU) 14-Lead SOIC (R) θJA 190 240 158 180 120 θJC 44 43 43 36 36 Unit °C/W °C/W °C/W °C/W °C/W
Differential input voltage is limited to ±5.0 V or the supply voltage, whichever is less.
ESD CAUTION
Rev. C | Page 5 of 24
AD8571/AD8572/AD8574 TYPICAL PERFORMANCE CHARACTERISTICS
180 160 VS = 2.7V VCM = 1.35V TA = 25°C
180 160
NUMBER OF AMPLIFIERS
VS = 5V VCM = 2.5V TA = 25°C
NUMBER OF AMPLIFIERS
140 120 100 80 60 40 20
01104-007
140 120 100 80 60 40 20
–1.5
–0.5
0.5
1.5
2.5
–1.5
–0.5
0.5
1.5
2.5
OFFSET VOLTAGE (µV)
OFFSET VOLTAGE (µV)
Figure 7. Input Offset Voltage Distribution at 2.7 V
50 40
INPUT BIAS CURRENT (pA)
Figure 10. Input Offset Voltage Distribution at 5 V
12
VS = 5V TA = –40°C, +25°C, +85°C
NUMBER OF AMPLIFIERS
10
30 +85°C 20 10 +25°C 0 –10 –40°C –20 –30
01104-008
VS = 5V VCM = 2.5V TA = –40°C TO +125°C
8
6
4
2
0
1 2 3 4 INPUT COMMON-MODE VOLTAGE (V)
5
0
1
2
3
4
5
6
INPUT OFFSET DRIFT (nV/°C)
Figure 8. Input Bias Current vs. Input Common-Mode Voltage
1500 1000
Figure 11. Input Offset Voltage Drift Distribution at 5 V
10k VS = 5V TA = 25°C 1k
OUTPUT VOLTAGE (mV)
VS = 5V TA = 125°C
INPUT BIAS CURRENT (pA)
500 0
100 SOURCE 10 SINK
–500 –1000 –1500 –2000
1
01104-009
0
1
2
3
4
5
0.001
0.01
0.1
1
10
100
COMMON-MODE VOLTAGE (V)
LOAD CURRENT (mA)
Figure 9. Input Bias Current vs. Common-Mode Voltage
Figure 12. Output Voltage to Supply Rail vs. Output Current at 5 V
Rev. C | Page 6 of 24
01104-012
0.1 0.0001
01104-011
0
01104-010
0 –2.5
0 –2.5
AD8571/AD8572/AD8574
10k
SUPPLY CURRENT PER AMPLIFIER (µA)
VS = 2.7V TA = 25°C
800 TA = 25°C 700 600 500 400 300 200 100 0
1k
OUTPUT VOLTAGE (mV)
100 SOURCE 10 SINK
1
01104-013
0.001
0.01
0.1
1
10
100
0
1
2
3
4
5
6
LOAD CURRENT (mA)
SUPPLY VOLTAGE (V)
Figure 13. Output Voltage to Supply Rail vs. Output Current at 2.7 V
Figure 16. Supply Current vs. Supply Voltage
1000 VCM = 2.5V VS = 5V
INPUT BIAS CURRENT (pA)
60 50 40 VS = 2.7V CL = 0pF RL = ∞ 0 45 90 135 180 225 270
30 20 10 0 –10 –20 –30
500
250
01104-014
–50
–25
0
25
50
75
100
125
150
100k
1M FREQUENCY (Hz)
10M
100M
TEMPERATURE (°C)
Figure 14. Input Bias Current vs. Temperature
1.0 5V 0.8
SUPPLY CURRENT (mA)
Figure 17. Open-Loop Gain and Phase Shift vs. Frequency at 2.7 V
60 50 40 VS = 5V CL = 0pF RL = ∞ 0 45 90 135 180 225 270
2.7V 0.6
30 20 10 0 –10 –20 –30
0.4
0.2
01104-015
–50
–25
0
25
50
75
100
125
150
100k
1M FREQUENCY (Hz)
10M
100M
TEMPERATURE (°C)
Figure 15. Supply Current vs. Temperature
Figure 18. Open-Loop Gain and Phase Shift vs. Frequency at 5 V
Rev. C | Page 7 of 24
01104-018
0 –75
–40 10k
PHASE SHIFT (Degrees)
OPEN-LOOP GAIN (dB)
01104-017
0 –75
–40 10k
PHASE SHIFT (Degrees)
OPEN-LOOP GAIN (dB)
750
01104-016
0.1 0.0001
AD8571/AD8572/AD8574
60 50 40
CLOSED-LOOP GAIN (dB)
300
VS = 2.7V CL = 0pF RL = 2kΩ
OUTPUT IMPEDANCE (Ω)
270 240 210 180 150 120 90 60 30
01104-019
VS = 5V
30 20 10 0 –10 –20 –30 –40 100
AV = –100
AV = –10
AV = 100
AV = +1
AV = 10
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 19. Closed-Loop Gain vs. Frequency at 2.7 V
Figure 22. Output Impedance vs. Frequency at 5 V
60 50 40 VS = 5V CL = 0pF RL = 2kΩ AV = –100
VS = 2.7V CL = 300pF RL = 2kΩ AV = 1
CLOSED-LOOP GAIN (dB)
30 20 10 0 –10 –20 –30
AV = –10
AV = +1
2µs
1k 10k 100k 1M 10M
01104-020
500mV
–40 100
FREQUENCY (Hz)
Figure 20. Closed-Loop Gain vs. Frequency at 5 V
300 270 240
OUTPUT IMPEDANCE (Ω)
Figure 23. Large Signal Transient Response at 2.7 V
VS = 2.7V
VS = 5V CL = 300pF RL = 2kΩ AV = 1
210 180 150 120 90 60 30 0 100 1k 10k 100k AV = 1 1M 10M
01104-021
AV = 100
AV = 10
5µs
1V
FREQUENCY (Hz)
Figure 21. Output Impedance vs. Frequency at 2.7 V
Figure 24. Large Signal Transient Response at 5 V
Rev. C | Page 8 of 24
01104-024
01104-023
01104-022
0 100
AV = 1
AD8571/AD8572/AD8574
45
SMALL SIGNAL OVERSHOOT (%)
VS = ±1.35V CL = 50pF RL = ∞ AV = 1
40 35
VS = ±2.5V RL = 2kΩ TA = 25°C +OS
30 25 20 –OS 15 10 5 100 1k 10k
01104-028
5µs
50mV
01104-025
0 10
CAPACITANCE (pF)
Figure 25. Small Signal Transient Response at 2.7 V
Figure 28. Small Signal Overshoot vs. Load Capacitance at 5 V
VS = ±2.5V CL = 50pF RL = ∞ AV = 1
0V VIN VS = ±2.5V VIN = –200mV p-p (RET TO GND) CL = 0pF RL = 10kΩ AV = –100
VOUT
01104-026
0V 20µs BOTTOM SCALE: 1V/DIV TOP SCALE: 200mV/DIV 1V
01104-029
5µs
50mV
Figure 26. Small Signal Transient Response at 5 V
50 45 VS = ±1.35V RL = 2kΩ TA = 25°C
VIN 0V
Figure 29. Positive Overvoltage Recovery
SMALL SIGNAL OVERSHOOT (%)
40 35 30 25 20 15 10 5
+OS –OS
0V
VS = ±2.5V VIN = 200mV p-p (RET TO GND) CL = 0pF RL = 10kΩ AV = –100
VOUT 20µs 1V
01104-030
100
1k
10k
CAPACITANCE (pF)
01104-027
0 10
BOTTOM SCALE: 1V/DIV TOP SCALE: 200mV/DIV
Figure 27. Small Signal Overshoot vs. Load Capacitance at 2.7 V
Figure 30. Negative Overvoltage Recovery
Rev. C | Page 9 of 24
AD8571/AD8572/AD8574
140
VS = ±2.5V RL = 2kΩ AV = –100 VIN = 60mV p-p
VS = ±1.35V 120 100
PSRR (dB)
80 60 40 20 0 100 –PSRR +PSRR
200µs
1V
01104-031
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 31. No Phase Reversal
140 VS = 2.7V 120 100
Figure 34. PSRR vs. Frequency at ±1.35 V
140 VS = ±2.5V 120 100
PSRR (dB)
+PSRR
CMRR (dB)
80 60 40 20 0 100
80 60 40 20 0 100 –PSRR
1k
10k
100k
1M
10M
01104-032
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 32. CMRR vs. Frequency at 2.7 V
140 VS = 5V 120 100
CMRR (dB)
2.5 3.0
Figure 35. PSRR vs. Frequency at ±2.5 V
OUTPUT SWING (V p-p)
2.0
VS = ±1.35V RL = 2kΩ AV = 1 THD + N < 1% TA = 25°C
80 60 40 20 0 100
1.5
1.0
0.5
1k
10k FREQUENCY (Hz)
100k
1M
FREQUENCY (Hz)
Figure 33. CMRR vs. Frequency at 5 V
Figure 36. Maximum Output Swing vs. Frequency at 2.7 V
Rev. C | Page 10 of 24
01104-036
1k
10k
100k
1M
10M
01104-033
0 100
01104-035
01104-034
AD8571/AD8572/AD8574
5.5 5.0 4.5 VS = ±2.5V RL = 2kΩ AV = 1 THD + N < 1% TA = 25°C
364 312 260 208 156 104 52
VS = 2.7V RS = 0Ω
OUTPUT SWING (V p-p)
4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 1k 10k FREQUENCY (Hz)
100k
1M
01104-037
0
0.5
1.0
1.5
2.0
2.5
FREQUENCY (kHz)
Figure 37. Maximum Output Swing vs. Frequency at 5 V
Figure 40. Voltage Noise Density at 2.7 V from 0 Hz to 2.5 kHz
VS = ±1.35V AV = 120,000
112 96 80 64 48 32
01104-038
VS = 2.7V RS = 0Ω
0V
en (nV/ Hz)
1s
50mV
16
0
5
10
15
20
25
FREQUENCY (kHz)
Figure 38. 0.1 Hz to 10 Hz Noise at 2.7 V
Figure 41. Voltage Noise Density at 2.7 V from 0 Hz to 25 kHz
VS = ±2.5V AV = 120,000
182 156 130 104 78 52
01104-039
VS = 5V RS = 0Ω
en (nV/ Hz)
1s
50mV
26
0
0.5
1.0
1.5
2.0
2.5
FREQUENCY (kHz)
Figure 39. 0.1 Hz to 10 Hz Noise at 5 V
Figure 42. Voltage Noise Density at 5 V from 0 Hz to 2.5 kHz
Rev. C | Page 11 of 24
01104-042
01104-041
01104-040
0 100
en (nV/ Hz)
AD8571/AD8572/AD8574
150
112 96 80 64 48 32 16
POWER SUPPLY REJECTION (dB)
VS = 5V RS = 0Ω
VS = 2.7V TO 5.5V 145
en (nV/ Hz)
140
135
130
–50
–25
0
25
50
75
100
125
150
FREQUENCY (kHz)
TEMPERATURE (°C)
Figure 43. Voltage Noise Density at 5 V from 0 Hz to 25 kHz
50
Figure 45. Power Supply Rejection vs. Temperature
210 180 150 120 90 60 30
OUTPUT SHORT-CIRCUIT CURRENT (mA)
VS = 5V RS = 0Ω
40 30 20 10 0 –10 –20 –30 –40
VS = 2.7V ISC–
en (nV/ Hz)
ISC+
–50
–25
0
25
50
75
100
125
150
FREQUENCY (kHz)
TEMPERATURE (°C)
Figure 44. Voltage Noise Density at 5 V from 0 Hz to 10 Hz
Figure 46. Output Short-Circuit Current vs. Temperature
Rev. C | Page 12 of 24
01104-046
0
5
10
01104-044
–50 –75
01104-045
0
5
10
15
20
25
01104-043
125 –75
AD8571/AD8572/AD8574
100 80
SHORT-CIRCUIT CURRENT (mA)
250
VS = 5V
OUTPUT VOLTAGE SWING (mV)
225
VS = 5V
60 40 20 0 –20 –40 –60 –80
ISC–
200 175 150 125 100 75 50 25 RL = 10kΩ RL = 1kΩ
ISC+
RL = 100kΩ
01104-047
–50
–25
0
25
50
75
100
125
150
–50
–25
0
25
50
75
100
125
150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 47. Output Short-Circuit Current vs. Temperature
250 225
OUTPUT VOLTAGE SWING (mV)
Figure 49. Output Voltage to Supply Rail vs. Temperature
VS = 5V
200 175 150 125 100 75 50 25 0 –75 –50 –25 0 25 50 75 RL = 10kΩ RL = 100kΩ RL = 1kΩ
100
125
150
TEMPERATURE (°C)
Figure 48. Output Voltage to Supply Rail vs. Temperature
Rev. C | Page 13 of 24
01104-048
01104-049
–100 –75
0 –75
AD8571/AD8572/AD8574 FUNCTIONAL DESCRIPTION
The AD8571/AD8572/AD8574 are CMOS amplifiers that achieve their high degree of precision through random frequency auto-zero stabilization. The autocorrection topology allows the AD857x to maintain its low offset voltage over a wide temperature range, and the randomized auto-zero clock eliminates any intermodulation distortion (IMD) errors at the amplifier output. The AD857x can be run from a single-supply voltage as low as 2.7 V. The extremely low offset voltage of 1 μV and no IMD products allow the amplifier to be easily configured for high gains without risk of excessive output voltage errors, which makes the AD857x an ideal amplifier for applications requiring both dc precision and low distortion for ac signals. The extremely small temperature drift of 5 nV/°C ensures a minimum of offset voltage error over its −40°C to +125°C temperature range. These combined features make the AD857x an excellent choice for a variety of sensitive measurement and automotive applications.
BASIC AUTO-ZERO AMPLIFIER THEORY
Autocorrection amplifiers are not a new technology. Various IC implementations have been available for more than 15 years, and some improvements have been made over time. The AD857x design offers a number of significant performance improvements over older versions while attaining a very substantial reduction in device cost. This section offers a simplified explanation of how the AD857x is able to offer extremely low offset voltages and high open-loop gains. As noted in the Amplifier Architecture section, each AD857x op amp contains two internal amplifiers. One is used as the primary amplifier, the other as an autocorrection, or nulling, amplifier. Each amplifier has an associated input offset voltage that can be modeled as a dc voltage source in series with the noninverting input. In Figure 50 and Figure 51, these are labeled as VOSA and VOSB, where A denotes the nulling amplifier and B denotes the primary amplifier. The open-loop gain for the +IN and −IN inputs of each amplifier is given as AX. Both amplifiers also have a third voltage input with an associated open-loop gain of BX.
B
AMPLIFIER ARCHITECTURE
Each AD857x op amp consists of two amplifiers: a main amplifier and a secondary amplifier that is used to correct the offset voltage of the main amplifier. Both consist of a rail-to-rail input stage, allowing the input common-mode voltage range to reach both supply rails. The input stage consists of an NMOS differential pair operating concurrently with a parallel PMOS differential pair. The outputs from the differential input stages are combined in another gain stage whose output is used to drive a rail-to-rail output stage. The wide voltage swing of the amplifier is achieved by using two output transistors in a common-source configuration. The output voltage range is limited by the drain-to-source resistance of these transistors. As the amplifier is required to source or sink more output current, the voltage drop across these transistors increases due to their on resistance (RDS). Simply put, the output voltage does not swing as close to the rail under heavy output current conditions as it does with light output current. This is a characteristic of all rail-to-rail output amplifiers. Figure 12 and Figure 13 show how close the output voltage can get to the rails with a given output current. The output of the AD857x is shortcircuit protected to approximately 50 mA of current. The AD857x amplifiers have exceptional gain, yielding greater than 120 dB of open-loop gain with a load of 2 kΩ. Because the output transistors are configured in a common-source configuration, the gain of the output stage, and thus the openloop gain of the amplifier, is dependent on the load resistance. Open-loop gain decreases with smaller load resistances, which is another characteristic of rail-to-rail output amplifiers.
There are two modes of operation determined by the action of two sets of switches in the amplifier: an auto-zero phase and an amplification phase.
AUTO-ZERO PHASE
In this phase, all φA switches are closed, and all φB switches are opened. Here, the nulling amplifier is taken out of the gain loop by shorting its two inputs together. Of course, there is a degree of offset voltage, shown as VOSA, inherent in the nulling amplifier that maintains a potential difference between the +IN and −IN inputs. The nulling amplifier feedback loop is closed through φA2, and VOSA appears at the output of the nulling amplifier and on CM1, an internal capacitor in the AD857x. Mathematically, this can be expressed in the time domain as
VOA [t ] = AAVOSA [t ] − B AVOA[t ]
(1)
this can also be expressed as
VOA [t ] =
A AVOSA [t ] 1 + BA
(2)
This shows that the offset voltage of the nulling amplifier times a gain factor appears at the output of the nulling amplifier and thus on the CM1 capacitor.
Rev. C | Page 14 of 24
AD8571/AD8572/AD8574
VIN+ VIN– ΦB ΦA1 VOSA + AA –BA ΦA2 VOA VOSB + AB BB ΦB CM2 VOUT
variation or long-term wear time, both of which are much slower than the auto-zero clock frequency of the AD857x, which effectively makes the VOS time invariant, and Equation 5 can be rewritten as VOA [t ] = AAVIN [t ] + or
01104-050
AA (1 + BA )VOSA − AA BAVOSA 1 + BA
VNB CM1
(6)
VNA
Figure 50. Auto-Zero Phase of the Amplifier
⎛ VOSA ⎞ ⎟ VOA [t ] = A A ⎜ V IN [t ] + ⎜ 1 + BA ⎟ ⎠ ⎝
(7)
AMPLIFICATION PHASE
When the φB switches close and the φA switches open for the amplification phase, the offset voltage remains on CM1 and essentially corrects any error from the nulling amplifier. The voltage across CM1 is designated as VNA. The potential difference between the two inputs to the primary amplifier is designated as VIN, or VIN = (VIN+ − VIN–). The output of the nulling amplifier can then be expressed as
VOA [t ] = A A (V IN [t ] − VOSA [t ] − B AVNA [t ]
VIN+ VIN– ΦB ΦA VOSA + AA –BA ΦA VOA VOSB + AB BB ΦB CM2 VOUT
Here, the auto-zeroing becomes apparent. Note that the VOS term is reduced by a 1 + BA factor, which shows how the nulling amplifier has greatly reduced its own offset voltage error even before correcting the primary amplifier. Therefore, the primary amplifier output voltage is the voltage at the output of the AD857x amplifier. It is equal to VOUT [t ] = A B (VIN [t ] + VOSB ) + B B VNB (8)
(3)
In the amplification phase, VOA = VNB, so this can be rewritten as
VOUT [t ] = ⎡⎛ ⎞⎤ V ABVIN [t ] + ABVOSB + BB ⎢ AA ⎜ VIN [t ] + OSA ⎟⎥ ⎜ 1 + BA ⎟⎥ ⎢⎝ ⎠⎦ ⎣ combining terms yields
VNB CM1
01104-051
(9)
VOUT [t ] = VIN [t ](AB + AA BB ) + AA B BVOSA + ABVOSB 1 + BA (10)
VNA
Figure 51. Output Phase of the Amplifier
Because φA is now open and there is no place for CM1 to discharge, the voltage (VNA) at the present time (t) is equal to the voltage at the output of the nulling amp (VOA) at the time when φA was closed. If the period of the autocorrection switching frequency is designated as TS, the amplifier switches between phases every 0.5 × TS. Therefore, in the amplification phase
1⎤ ⎡ VNA [t ] = VNA ⎢t − TS ⎥ 2⎦ ⎣
The AD857x architecture is optimized in such a way that AA = AB, BA = BB, and BA >> 1. In addition, the gain product to AABB is much greater than AB. Therefore, Equation 10 can be simplified to
B B B B
VOUT [t ] = VIN [t ]AA BA + AA (VOSA + VOSB )
(11)
(4)
Most obvious is the gain product of both the primary and nulling amplifiers. This AABA term is what gives the AD857x its extremely high open-loop gain. To understand how VOSA and VOSB relate to the overall effective input offset voltage of the complete amplifier, set up the generic amplifier equation of
B B
and substituting Equation 4 and Equation 2 into Equation 3 yields
VOUT = k × (V IN + VOS , EFF ) where: k is the open-loop gain of an amplifier. VOS, EFF is its effective offset voltage. Putting Equation 12 into the form of Equation 11 gives VOUT [t ] = V IN [t ]A A B A + VOS , EFF A A B A
(12)
1⎤ ⎡ A A B AVOSA ⎢t − TS ⎥ 2 ⎦ (5) ⎣ VOA [t ] = A AVIN [t ] + A AVOSA [t ] − 1 + BA For the sake of simplification, it can be assumed that the autocorrection frequency is much faster than any potential change in VOSA or VOSB. This is a good assumption because changes in offset voltage are a function of temperature
B
(13)
Rev. C | Page 15 of 24
AD8571/AD8572/AD8574
Therefore,
VOS , EFF ≈ VOSA + VOSB BA
V+ R1 R2
AD8572
R2
R1 VIN2
(14)
VIN1
Thus, the offset voltages of both the primary and nulling amplifiers are reduced by the gain factor BA, which takes a typical input offset voltage from several millivolts down to an effective input offset voltage of submicrovolts. This autocorrection scheme makes the AD857x family of amplifiers extremely precise.
GUARD RING
VREF VREF V–
GUARD RING
01104-053
Figure 53. Top View of AD8572 SOIC Layout with Guard Rings
HIGH GAIN, CMRR, AND PSRR
Common-mode and power supply rejection are indications of the amount of offset voltage an amplifier has as a result of a change in its input common-mode or power supply voltages. As shown in the Amplification Phase section, the autocorrection architecture of the AD857x allows it to effectively minimize offset voltages. The technique also corrects for offset errors caused by common-mode voltage swings and power supply variations, which results in superb CMRR and PSRR figures in excess of 130 dB. Because the autocorrection occurs continuously, these figures can be maintained across the entire temperature range of the device, from −40°C to +125°C.
Other potential sources of offset error are thermoelectric voltages on the circuit board. This voltage, also called Seebeck voltage, occurs at the junction of two dissimilar metals and is proportional to the junction temperature. The most common metallic junctions on a circuit board are solder-to-board trace and solder-to-component lead. Figure 54 shows a cross-section view of the thermal voltage error sources. When the temperature of the PCB at one end of the component (TA1) differs from the temperature at the other end (TA2), the Seebeck voltages are not equal, resulting in a thermal voltage error. This thermocouple error can be reduced by using dummy components to match the thermoelectric error source. Placing the dummy component as close as possible to its partner ensures both Seebeck voltages are equal, thus canceling the thermocouple error. Maintaining a constant ambient temperature on the circuit board further reduces this error. The use of a ground plane helps distribute heat throughout the board and also reduces EMI noise pickup.
COMPONENT LEAD VSC1 VTS1 – – + PC BOARD TA1 COPPER TRACE TA2 IF TA1 ≠ TA2, THEN VTS1 + VSC1 ≠ VTS2 + VSC2 + + VSC2 – + – SOLDER VTS2
MAXIMIZING PERFORMANCE THROUGH PROPER LAYOUT
To achieve the maximum performance of the extremely high input impedance and low offset voltage of the AD857x, care should be taken in the circuit board layout. The PCB surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. Surface coating of the circuit board reduces surface moisture and provides a humidity barrier, reducing parasitic resistance on the board. The use of guard rings around the amplifier inputs further reduces leakage currents. Figure 52 shows how the guard ring should be configured, and Figure 53 shows the top view of how a surface-mount layout can be arranged. The guard ring does not need to be a specific width, but it should form a continuous loop around both inputs. By setting the guard ring voltage equal to the voltage at the noninverting input, parasitic capacitance is minimized as well. For further reduction of leakage currents, components can be mounted to the PCB using Teflon® standoff insulators.
SURFACE MOUNT COMPONENT
Figure 54. Mismatch in Seebeck Voltages Causes a Thermoelectric Voltage Error
RF R1
VIN
VOUT
VOUT V
IN
AD8572
AD8572
VIN RS = R1
VOUT
AD8571/AD8572/ AD8574
AV = 1 + (RF /R1)
01104-055
VIN
VOUT
01104-052
RS SHOULD BE PLACED IN CLOSE PROXIMITY AND ALIGNMENT TO R1 TO BALANCE SEEBECK VOLTAGES
AD8572
Figure 52. Guard Ring Layout and Connections to Reduce PCB Leakage Currents
Figure 55. Using Dummy Components to Cancel Thermoelectric Voltage Errors
Rev. C | Page 16 of 24
01104-054
AD8571/AD8572/AD8574
1/f NOISE CHARACTERISTICS
Another advantage of auto-zero amplifiers is their ability to cancel flicker noise. Flicker noise, also known as 1/f noise, is noise inherent in the physics of semiconductor devices and increases 3 dB for every octave decrease in frequency. The 1/f corner frequency of an amplifier is the frequency at which the flicker noise is equal to the broadband noise of the amplifier. At lower frequencies, flicker noise dominates, causing higher degrees of error for sub-Hertz frequencies or dc precision applications. Because the AD857x amplifiers are self-correcting op amps, they do not have increasing flicker noise at lower frequencies. In essence, low frequency noise is treated as a slowly varying offset error and is greatly reduced as a result of autocorrection. The correction becomes more effective as the noise frequency approaches dc, offsetting the tendency of the noise to increase exponentially as frequency decreases, which allows the AD857x to have lower noise near dc than standard low noise amplifiers that are susceptible to 1/f noise.
0 VS = 5V AV = 60dB –20
OUTPUT SIGNAL
–40
–60
–80
–100
01104-057
–120
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (kHz)
Figure 57. Spectral Analysis of AD857x Output with 60 dB Gain
Figure 58 shows the spectral output of an AD8572 configured in a high gain (60 dB) with a 1 mV input signal applied. Note the absence of any IMD products in the spectrum. The signal-tonoise ratio (SNR) of the output signal is better than 60 dB, or 0.1%.
0 VS = 5V AV = 60dB
RANDOM AUTO-ZERO CORRECTION ELIMINATES INTERMODULATION DISTORTION
The AD857x can be used as a conventional op amp for gains up to 1 MHz. The auto-zero correction frequency of the device continuously varies, based on a pseudorandom generator with a uniform distribution from 2 kHz to 4 kHz. The randomization of the autocorrection clock creates a continuous randomization of intermodulation distortion (IMD) products that show up as simple broadband noise at the output of the amplifier. This broadband noise naturally combines with the amplifier voltage noise in a root-squared-sum fashion, resulting in an output free IMD. Figure 56 shows the spectral output of an AD8572 with the amplifier configured for unity gain and the input grounded. Figure 57 shows the spectral output with the amplifier configured for a gain of 60 dB.
0 –20 –40
OUTPUT SIGNAL
OUTPUT SIGNAL
–20
–40
–60
–80
–100
01104-058
–120
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (kHz)
Figure 58. Spectral Analysis of AD8572 in High Gain with an Input Signal
VS = 5V AV = 0dB
–60 –80 –100 –120
01104-056
–140 –160
1
2
3
4
5
6
7
8
9
10
FREQUENCY (kHz)
Figure 56. Spectral Analysis of AD8572 Output in Unity Gain Configuration
Rev. C | Page 17 of 24
AD8571/AD8572/AD8574 BROADBAND AND EXTERNAL RESISTOR NOISE CONSIDERATIONS
The total broadband noise output from any amplifier is primarily a function of three types of noise: input voltage noise from the amplifier, input current noise from the amplifier, and Johnson noise from the external resistors used around the amplifier. Input voltage noise, or en, is strictly a function of the amplifier used. The Johnson noise from a resistor is a function of the resistance and the temperature. Input current noise, or in, creates an equivalent voltage noise proportional to the resistors used around the amplifier. These noise sources are not correlated with each other and their combined noise sums in a rootsquared-sum fashion. The full equation is given as
en, TOTAL = [en 2 + 4kTrs + (inrs )2 ]1/ 2
(15)
The output overdrive recovery for an autocorrection amplifier is defined as the time it takes for the output to correct to its final voltage from an overload state. It is measured by placing the amplifier in a high gain configuration with an input signal that forces the output voltage to the supply rail. The input voltage is then stepped down to the linear region of the amplifier, usually to halfway between the supplies. The time from the input signal step-down to the output settling to within 100 μV of its final value is the overdrive recovery time. Many autocorrection amplifiers require a number of auto-zero clock cycles to recover from output overdrive, and some can take several milliseconds for the output to settle properly.
INPUT OVERVOLTAGE PROTECTION
where: en is the input voltage noise of the amplifier. in is the input current noise of the amplifier. rs is the source resistance connected to the noninverting terminal. k is Boltzmann’s constant (1.38 × 10−23 J/K). T is the ambient temperature in Kelvin (K = 273.15 + °C). The input voltage noise density, en, of the AD857x is 51 nV/√Hz, and the input noise, in, is 2 fA/√Hz. The en, TOTAL is dominated by the input voltage noise provided that the source resistance is less than 172 kΩ. With source resistance greater than 172 kΩ, the overall noise of the system is dominated by the Johnson noise of the resistor itself. Because the input current noise of the AD857x is very small, in does not become a dominant term unless rs > 4 GΩ, which is an impractical value of source resistance. The total noise, en, TOTAL, is expressed in volts-per-square-root Hertz, and the equivalent rms noise over a certain bandwidth can be found as
en = en, TOTAL × BW
Although the AD857x are rail-to-rail input amplifiers, care should be taken to ensure that the potential difference between the inputs does not exceed 5 V. Under normal operating conditions, the amplifier corrects its output to ensure the two inputs are at the same voltage. However, if the device is configured as a comparator, or is under some unusual operating condition, the input voltages may be forced to different potentials, which could cause excessive current to flow through the internal diodes in the AD857x used to protect the input stage against overvoltage. If either input exceeds either supply rail by more than 0.3 V, large amounts of current begin to flow through the ESD protection diodes in the amplifier. These diodes are connected between the inputs and each supply rail to protect the input transistors against an electrostatic discharge event and are normally reverse-biased. However, if the input voltage exceeds the supply voltage, these ESD diodes become forward-biased. Without current-limiting, excessive amounts of current can flow through these diodes, causing permanent damage to the device. If inputs are subject to overvoltage, appropriate series resistors should be inserted to limit the diode current to less than 2 mA.
(16)
where BW is the bandwidth of interest in Hertz.
OUTPUT PHASE REVERSAL
Output phase reversal occurs in some amplifiers when the input common-mode voltage range is exceeded. As common-mode voltage moves outside the common-mode range, the outputs of these amplifiers suddenly jump in the opposite direction to the supply rail. This is the result of the differential input pair shutting down, causing a radical shifting of internal voltages that results in the erratic output behavior. The AD857x amplifier has been carefully designed to prevent any output phase reversal, provided both inputs are maintained within the supply voltages. If one or both inputs exceed either supply voltage, a resistor should be placed in series with the input to limit the current to less than 2 mA to ensure the output does not reverse its phase.
OUTPUT OVERDRIVE RECOVERY
The AD857x amplifiers have an excellent overdrive recovery of only 200 μs from either supply rail. This characteristic is particularly difficult for autocorrection amplifiers because the nulling amplifier requires a substantial amount of time to error correct the main amplifier back to a valid output. Figure 29 and Figure 30 show the positive and negative overdrive recovery times for the AD857x.
Rev. C | Page 18 of 24
AD8571/AD8572/AD8574
CAPACITIVE LOAD DRIVE
The AD857x have excellent capacitive load driving capabilities and can safely drive up to 10 nF from a single 5 V supply. Although the device is stable, capacitive loading limits the bandwidth of the amplifier. Capacitive loads also increase the amount of overshoot and ringing at the output. An RC snubber network, shown in Figure 59, can be used to compensate the amplifier against capacitive load ringing and overshoot.
5V
The optimum value for the resistor and capacitor is a function of the load capacitance and is best determined empirically since actual CLOAD includes stray capacitances and can differ substantially from the nominal capacitive load. Table 5 shows some snubber network values that can be used as starting points.
Table 5. Snubber Network Values for Driving Capacitive Loads
CLOAD (nF) 1 4.7 10 Rx (Ω) 200 60 20 Cx 1 nF 0.47 μF 10 μF
–
VIN 200mV p-p
AD8571/ AD8572/ AD8574
Rx 60Ω Cx 0.47µF CL 4.7nF
VOUT
+
POWER-UP BEHAVIOR
01104-059
Figure 59. Snubber Network Configuration for Driving Capacitive Loads
Although the snubber does not recover the loss of amplifier bandwidth from the load capacitance, it does allow the amplifier to drive larger values of capacitance while maintaining a minimum of overshoot and ringing. Figure 60 shows the output of an AD857x driving a 1 nF capacitor with and without a snubber network.
10μs WITH SNUBBER
On power-up, the AD857x settle to a valid output within 5 μs. Figure 61 shows an oscilloscope photo of the output of the amplifier along with the power supply voltage. Figure 62 shows the test circuit. With the amplifier configured for unity gain, the device takes approximately 5 μs to settle to its final output voltage, hundreds of microseconds faster than many other autocorrection amplifiers.
VOUT
0V
V+ 0V
WITHOUT SNUBBER
5µs BOTTOM TRACE = 2V/DIV TOP TRACE = 1V/DIV
1V
01104-061
VS = 5V CLOAD = 4.7nF
100mV
01104-060
Figure 61. AD857x Output Behavior on Power-Up
Figure 60. Overshoot and Ringing Are Substantially Reduced Using a Snubber Network
VSY = 0V TO 5V
100kΩ
Figure 62. AD857x Test Circuit for Turn-On Time
Rev. C | Page 19 of 24
01104-062
100kΩ
AD8571/ AD8572/ AD8574
VOUT
AD8571/AD8572/AD8574 APPLICATIONS
5 V PRECISION STRAIN GAGE CIRCUIT
The extremely low offset voltage of the AD8572 makes it an ideal amplifier for any application requiring accuracy with high gains, such as a weigh scale or strain gage. Figure 63 shows a configuration for a single-supply, precision strain gage measurement system. The REF192 provides a 2.5 V precision reference voltage for A2. The A2 amplifier boosts this voltage to provide a 4.0 V reference for the top of the strain gage resistor bridge. Q1 provides the current drive for the 350 Ω bridge network. A1 is used to amplify the output of the bridge with the full-scale output voltage equal to
2 × (R1 + R 2 ) RB where RB is the resistance of the load cell.
B
R2 V2 V1 R1 R3 R4
AD8571/ AD8572/ AD8574
(V1 – V2)
VOUT
IF
R4 R2 R2 = , THEN VOUT = R3 R1 R1
Figure 64. Using the AD857x as a Difference Amplifier
In an ideal difference amplifier, the ratio of the resistors is set equal to
AV = R2 R1 = R4 R3
01104-064
(17)
(19)
Set the output voltage of the system to VOUT = AV (V1 − V2) (20) Using the values given in Figure 63, the output voltage linearly varies from 0 V with no strain to 4 V under full strain.
5V Q1 2N2222 OR EQUIVALENT 4.0V 1kΩ 2.5V A2 4 20kΩ 12kΩ 6 2 3
REF192
AD8572-B
Due to finite component tolerance, the ratio between the four resistors is not exactly equal, and any mismatch results in a reduction of common-mode rejection from the system. Referring to Figure 64, the exact common-mode rejection ratio can be expressed as CMRR = R1R4 + 2R2R4 + R2R3 2R1R4 − 2R2R3 (21)
R1 17.4kΩ
R2 100Ω
350Ω LOAD CELL
40mV FULL-SCALE
A1
AD8572-A
R4 100Ω
VOUT 0V TO 4V
01104-063
R3 17.4kΩ NOTE: USE 0.1% TOLERANCE RESISTORS.
In the 3-op amp instrumentation amplifier configuration shown in Figure 65, the output difference amplifier is set to unity gain with all four resistors equal in value. If the tolerance of the resistors used in the circuit is given as δ, the worst-case CMRR of the instrumentation amplifier is CMRRMIN =
V2
1 2δ
R
(22)
Figure 63. 5 V Precision Strain Gage Amplifier
3 V INSTRUMENTATION AMPLIFIER
The high common-mode rejection, high open-loop gain, and operation down to 3 V of supply voltage make the AD857x family an excellent choice of op amp for discrete single-supply instrumentation amplifiers. The common-mode rejection ratio of the AD857x is greater than 120 dB, but the CMRR of the system is also a function of the external resistor tolerances. The gain of the difference amplifier shown in Figure 64 is given as VOUT ⎛ R4 ⎞ ⎛ ⎛ R2 ⎞ R1 ⎞ = V 1⎜ ⎟ ⎜1 + ⎟ − V 2⎜ ⎟ R2 ⎠ ⎝ R3 + R 4 ⎠ ⎝ ⎝ R1 ⎠ (18)
AD8574-A
R RG R R R R
VOUT
AD8574-C
V1
AD8574-B
VOUT = 1 + 2R (V1 – V2) RG
RTRIM
01104-065
Figure 65. Discrete Instrumentation Amplifier Configuration
Therefore, using 1% tolerance resistors results in a worst-case system CMRR of 0.02, or 34 dB. To achieve high commonmode rejection, either high precision resistors or an additional trimming resistor, as shown in Figure 65, should be used. The value of this trimming resistor should be equal to the value of R multiplied by its tolerance. For example, using 10 kΩ resistors with 1% tolerance would require a series trimming resistor equal to 100 Ω.
Rev. C | Page 20 of 24
AD8571/AD8572/AD8574
HIGH ACCURACY THERMOCOUPLE AMPLIFIER
Figure 66 shows a K-type thermocouple amplifier configuration with cold-junction compensation. Even from a 5 V supply, the AD8571 can provide enough accuracy to achieve a resolution of better than 0.02°C from 0°C to 500°C. D1 is used as a temperature measuring device to correct the cold-junction error from the thermocouple and should be placed as close as possible to the two terminating junctions. With the thermocouple measuring tip immersed in a 0°C ice bath, R6 should be adjusted until the output is at 0 V. Using the values shown in Figure 66, the output voltage tracks temperature at 10 mV/°C. For a wider range of temperature measurement, R9 can be decreased to 62 kΩ. This creates a 5 mV/°C change at the output, allowing measurements of up to 1000°C.
12V 0.1µF
2
Using the components shown in Figure 67, the monitor output transfer function is 2.5 V/A. Figure 68 shows the low-side monitor equivalent. In this circuit, the input common-mode voltage to the AD8572 is at or near ground. Again, a 0.1 Ω resistor provides a voltage drop proportional to the return current. The output voltage is given as R2 × RSENSE × I L ⎞ VOUT = V+ − ⎛ ⎜ ⎟ ⎝ R1 ⎠ For the component values shown in Figure 68, the output transfer function decreases from V at –2.5 V/A.
3V RSENSE 0.1Ω IL V+ 3V R1 100Ω 3 8 0.1µF
(24)
REF02EZ
6 4
5V
2
R5 40.2kΩ
1/2 AD8572
4
1
R1 10.7kΩ 1N4148 D1 R2 2.74kΩ R6 200Ω R4 5.62kΩ R3 53.6Ω
R9 124kΩ 5V
S M1 Si9433 MONITOR OUTPUT D
G
K-TYPE THERMOCOUPLE 40.7µV/°C
– +
– +
R8 453Ω
0.1µF 2 3 4 8 1
Figure 67. High-Side Load Current Monitor
AD8572
01104-066
V+ R2 2.49kΩ VOUT Q1 V+
0V TO 5V (0°C TO 500°C)
Figure 66. Precision K-Type Thermocouple Amplifier with Cold-Junction Compensation
PRECISION CURRENT METER
Because of its low input bias current and superb offset voltage at single-supply voltages, the AD857x family is an excellent amplifier for precision current monitoring. Its rail-to-rail input allows the amplifier to be used as either a high-side or a lowside current monitor. Using both amplifiers in the AD8572 provides a simple method to monitor both current supply and return paths for load or fault detection. Figure 67 shows a high-side current monitor configuration. Here, the input common-mode voltage of the amplifier is at or near the positive supply voltage. The rail-to-rail input of the amplifier provides a precise measurement, even with the input common-mode voltage at the supply voltage. The CMOS input structure does not draw any input bias current, ensuring a minimum of measurement error. The 0.1 Ω resistor creates a voltage drop to the noninverting input of the AD857x. The output of the amplifier is corrected until this voltage appears at the inverting input, which creates a current through R1 that in turn flows through R2. The monitor output is given by Monitor Output = R2 × (RSENSE/R1) × IL (23)
Rev. C | Page 21 of 24
R1 100Ω
1/2 AD8572
RETURN TO GROUND
01104-068
RSENSE 0.1Ω
Figure 68. Low-Side Load Current Monitor
PRECISION VOLTAGE COMPARATOR
The AD857x can be operated open-loop and used as a precision comparator. The AD857x have less than 50 μV of offset voltage when run in this configuration. The slight increase of offset voltage stems from the fact that the autocorrection architecture operates with the lowest offset in a closed-loop configuration, that is, one with negative feedback. With 50 mV of overdrive, the device has a propagation delay of 15 μs on the rising edge and 8 μs on the falling edge. Care should be taken to ensure the maximum differential voltage of the device is not exceeded. For more information, see the Input Overvoltage Protection section.
01104-067
10µF
R2 2.49kΩ
+
AD8571/AD8572/AD8574 OUTLINE DIMENSIONS
3.20 3.00 2.80
3.10 3.00 2.90
3.20 3.00 2.80 PIN 1
8
5
1
5.15 4.90 4.65
8
5
4 1 4
4.50 4.40 4.30
6.40 BSC
0.65 BSC 0.95 0.85 0.75 0.15 0.00 0.38 0.22 SEATING PLANE 1.10 MAX 8° 0° 0.80 0.60 0.40
PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 1.20 MAX SEATING 0.20 PLANE 0.09
0.23 0.08
8° 0°
COPLANARITY 0.10
0.75 0.60 0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AA
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 69. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters
5.00 (0.1968) 4.80 (0.1890)
Figure 71. 8-Lead Thin Shrink Small Outline Package [TSSOP] (RU-8) Dimensions shown in millimeters
5.10 5.00 4.90
4.00 (0.1574) 3.80 (0.1497)
8 1
5 4
6.20 (0.2441) 5.80 (0.2284)
14
8
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE
1.75 (0.0688) 1.35 (0.0532)
0.50 (0.0196) 0.25 (0.0099) 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157)
45°
4.50 4.40 4.30
1 7
6.40 BSC
0.51 (0.0201) 0.31 (0.0122)
PIN 1 1.05 1.00 0.80 0.65 BSC 1.20 MAX 0.15 0.05 0.30 0.19
0.20 0.09
COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012407-A
SEATING COPLANARITY PLANE 0.10
8° 0°
0.75 0.60 0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 70. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and inches
Figure 72. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters
Rev. C | Page 22 of 24
AD8571/AD8572/AD8574
8.75 (0.3445) 8.55 (0.3366)
14 1 8 7
4.00 (0.1575) 3.80 (0.1496)
6.20 (0.2441) 5.80 (0.2283)
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122)
1.75 (0.0689) 1.35 (0.0531) SEATING PLANE
0.50 (0.0197) 0.25 (0.0098) 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157)
45°
COMPLIANT TO JEDEC STANDARDS MS-012-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 73. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model AD8571AR AD8571AR-REEL AD8571AR-REEL7 AD8571ARZ 1 AD8571ARZ-REEL1 AD8571ARZ-REEL71 AD8571ARM-R2 AD8571ARM-REEL AD8571ARMZ-R21 AD8571ARMZ-REEL1 AD8572AR AD8572AR-REEL AD8572AR-REEL7 AD8572ARZ1 AD8572ARZ-REEL1 AD8572ARZ-REEL71 AD8572ARU AD8572ARU-REEL AD8572ARUZ1 AD8572ARUZ-REEL1 AD8574AR AD8574AR-REEL AD8574AR-REEL7 AD8574ARZ1 AD8574ARZ-REEL1 AD8574ARZ-REEL71 AD8574ARU AD8574ARU-REEL AD8574ARUZ1 AD8574ARUZ-REEL1
1
Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C
Package Description 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead TSSOP 8-Lead TSSOP 8-Lead TSSOP 8-Lead TSSOP 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP
Package Option R-8 R-8 R-8 R-8 R-8 R-8 RM-8 RM-8 RM-8 RM-8 R-8 R-8 R-8 R-8 R-8 R-8 RU-8 RU-8 RU-8 RU-8 R-14 R-14 R-14 R-14 R-14 R-14 RU-14 RU-14 RU-14 RU-14
060606-A
Branding
AJA AJA AJA# AJA #
Z = RoHS Compliant Part, # denote RoHS compliant product may be top or bottom marked.
Rev. C | Page 23 of 24
AD8571/AD8572/AD8574 NOTES
©1999-2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C01104-0-5/07(C)
Rev. C | Page 24 of 24
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