AD8599TRZ-EP-R7

PIN CONFIGURATIONS Low noise: 1.1 nV/√Hz at 1 kHz Low distortion: −120 dB THD at 1 kHz Input noise, 0.1 Hz to 10 Hz: 2 kΩ is achieved; the current noise component is larger than the resistor noise. 100 TOTAL NOISE (nV/ Hz) INPUT VOLTAGE RANGE 10 TOTAL NOISE RESISTOR NOISE ONLY 1 Output phase reversal occurs in some amplifiers when the input common-mode voltage range is exceeded. As the common-mode voltage is moved outside the input voltage range, the outputs of these amplifiers can suddenly jump in the opposite direction to the supply rail. This is the result of the differential input pair shutting down that causes a radical shifting of internal voltages that results in the erratic output behavior. Rev. F | Page 15 of 20 0.1 10 06274-076 OUTPUT PHASE REVERSAL 100 1k SOURCE RESISTANCE (Ω) Figure 58. Noise vs. Source Resistance 10k AD8597/AD8599 Data Sheet general noise theory with extensive calculations, see the AN-358 Application Note, Noise and Operational Amplifier Circuits. A good selection table for low noise op amps can be found in AN-940 Application Note, Low Noise Amplifier Selection Guide for Optimal Noise Performance. An interesting note on using one section of a monolithic dual to phase compensate the other section is in the AN-107 Application Note, Active Feedback Improves Amplifier Phase Accuracy. The AD8597/AD8599 are the optimum choice for low noise performance if the source resistance is kept < 1 kΩ. At higher values of source resistance, optimum performance with respect to only noise is obtained with other amplifiers from Analog Devices. Both voltage noise and current noise must be considered. For more information on avoiding noise from grounding problems and inadequate bypassing, see the AN-345 Application Note, Grounding for Low- and High-Frequency Circuits. For V+ 7 R18 Q36 R19 D1 D31 D34 2 INVERTING – INPUT 3 NONINVERTING + INPUT Q18 Q19 D39 D41 D40 D42 C1 VB Q19 R31 D2 6 R1 Q20 R32 OUTPUT D3 Q32 Q27 V– Q28 4 Figure 59. Simplified Schematic Rev. F | Page 16 of 20 06247-079 D2 Data Sheet AD8597/AD8599 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 8 1 5 6.20 (0.2441) 5.80 (0.2284) 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 012407-A COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 60. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) DETAIL A (JEDEC 95) 1.84 1.74 1.64 0.50 BSC 8 5 PIN 1 INDEX AREA 1.55 1.45 1.35 EXPOSED PAD 0.50 0.40 0.30 0.80 0.75 0.70 SIDE VIEW 0.30 0.25 0.20 PKG-003886 SEATING PLANE 1 4 BOTTOM VIEW TOP VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-229-WEED-4 02-10-2017-A 3.10 3.00 SQ 2.90 Figure 61. 8-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-8-13) Dimensions shown in millimeters ORDERING GUIDE Model1 AD8597ACPZ-R2 AD8597ACPZ-REEL AD8597ACPZ-REEL7 AD8597ARZ AD8597ARZ-REEL AD8597ARZ-REEL7 AD8599ARZ AD8599ARZ-REEL AD8599ARZ-REEL7 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 8-Lead Lead Frame Chip Scale Package [LFCSP] 8-Lead Lead Frame Chip Scale Package [LFCSP] 8-Lead Lead Frame Chip Scale Package [LFCSP] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] Z = RoHS Complaint Part. Rev. F | Page 17 of 20 Package Option CP-8-13 CP-8-13 CP-8-13 R-8 R-8 R-8 R-8 R-8 R-8 Branding A22 A22 A22 AD8597/AD8599 Data Sheet NOTES Rev. F | Page 18 of 20 Data Sheet AD8597/AD8599 NOTES Rev. F | Page 19 of 20 AD8597/AD8599 Data Sheet NOTES ©2007–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06274-0-9/17(F) Rev. F | Page 20 of 20