AD8642ARZ-REEL7

FEATURES PIN CONFIGURATIONS Low supply current: 250 μA max Very low input bias current: 1 pA max Low offset voltage: 750 μV max Single-supply operation: 5 V to 26 V Dual-supply operation: ±2.5 V to ±13 V Rail-to-rail output Unity-gain stable No phase reversal SC70 package OUT 1 5 VCC 4 –IN VEE 2 TOP VIEW (Not to Scale) +IN 3 05072-101 AD8641 Figure 1. 5-Lead SC70 (KS-5) 1 –IN 2 +IN 3 VEE APPLICATIONS 8 AD8641 NIC VCC TOP VIEW 6 OUT (Not to Scale) 4 5 NIC 7 NIC = NO INTERNAL CONNECTION. Line-/battery-powered instruments Photodiode amplifiers Precision current sensing Medical instrumentation Industrial controls Precision filters Portable audio ATE 05072-102 NIC Figure 2. 8-Lead SOIC (R-8) –IN A 2 8 AD8642 V+ OUT B TOP VIEW 6 –IN B (Not to Scale) 5 +IN B V– 4 7 +IN A 3 05072-105 OUT A 1 OUT A 1 TOP VIEW (Not to Scale) V– 4 8 V+ 7 OUT B 6 –IN B 5 +IN B Figure 4. 8-Lead MSOP (RM-8) OUT A 1 14 OUT D –IN A 2 13 –IN D 12 +IN D +IN A 3 V+ 4 +IN B 5 AD8643 TOP VIEW 11 V– (Not to Scale) 10 +IN C –IN B 6 9 –IN C OUT B 7 8 OUT C 13 NIC 12 –IN D –IN A 1 +IN A 2 AD8643 11 +IN D V+ 3 TOP VIEW 10 V– 9 +IN C –IN C 8 OUT C 7 +IN B 4 NOTES 1. NIC = NO INTERNAL CONNECTION. 2. EXPOSED PAD SHOULD BE CONNECTED TO V+. 05072-104 PIN 1 INDICATOR 14 OUT D Figure 5. 14-Lead SOIC (R-14) –IN B 5 The AD8641/AD8642/AD8643 are fully specified over the extended industrial temperature range of −40°C to +125°C. The AD8641 is available in 5-lead SC70 and 8-lead SOIC lead-free packages. The AD8642 is available in 8-lead MSOP and 8-lead SOIC lead-free packages. The AD8643 is available in 14-lead SOIC and 16-lead, 3 mm × 3 mm, LFCSP lead-free packages. +IN A 3 16 NIC The AD8641/AD8642/AD8643 are suitable for applications utilizing multichannel boards that require low power to manage heat. Other applications include photodiodes, ATE reference level drivers, battery management, and industrial controls. AD8642 15 OUT A The AD8641/AD8642/AD8643 are low power, precision JFET input amplifiers featuring extremely low input bias current and rail-to-rail output. The ability to swing nearly rail-to-rail at the input and rail-to-rail at the output enables designers to buffer complementary metal-oxide semiconductor digital-to-analog converters (CMOS DACs), ASICs, and other wide output swing devices in single-supply systems. The outputs remain stable with capacitive loads of more than 500 pF. –IN A 2 OUT B 6 GENERAL DESCRIPTION 05072-064 Figure 3. 8-Lead SOIC (R-8) 05072-103 Data Sheet Low Power, Rail-to-Rail Output, Precision JFET Amplifiers AD8641/AD8642/AD8643 Figure 6. 16-Lead LFCSP (CP-16-27) (Not Drawn to Scale) Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2004–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD8641/AD8642/AD8643 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................5 Applications ....................................................................................... 1 Thermal Resistance .......................................................................5 General Description ......................................................................... 1 ESD Caution...................................................................................5 Pin Configurations ........................................................................... 1 Typical Performance Characteristics ..............................................6 Revision History ............................................................................... 2 Outline Dimensions ....................................................................... 13 Specifications..................................................................................... 3 Ordering Guide .......................................................................... 14 Electrical Characteristics ............................................................. 3 REVISION HISTORY 4/16—Rev. E to Rev. F Changed CP-16-3 to CP-16-27 .................................... Throughout Changes to Figure 2 and Figure 6 ................................................... 1 Updated Outline Dimensions ....................................................... 13 Changes to Ordering Guide .......................................................... 14 9/11—Rev. D to Rev. E Changes to Thermal Resistance Section........................................ 5 7/11—Rev. C to Rev. D Changes to Figure 6 .......................................................................... 1 11/10—Rev. B to Rev. C Changes to Figure 6 .......................................................................... 1 Added Thermal Resistance Section and Table 4 .......................... 5 Updated Outline Dimensions ....................................................... 13 Changes to Ordering Guide .......................................................... 15 3/05—Rev. 0 to Rev. A Added AD8642 ................................................................... Universal Changes to General Description .....................................................1 Added Figure 3 and Figure 4............................................................1 Changes to Specifications .................................................................3 Changes to Absolute Maximum Ratings ........................................5 Changes to Figure 22.........................................................................8 Changes to Figure 23.........................................................................9 Changes to Figure 41...................................................................... 12 Updated Outline Dimensions ....................................................... 13 Changes to Ordering Guide .......................................................... 14 10/04—Initial Version: Revision 0 4/05—Rev. A to Rev. B Added AD8643 ................................................................... Universal Added 14-Lead SOIC ......................................................... Universal Added 16-Lead LFCSP....................................................... Universal Updated Outline Dimensions ....................................................... 13 Changes to Ordering Guide .......................................................... 14 Rev. F | Page 2 of 15 Data Sheet AD8641/AD8642/AD8643 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VS = 5.0 V, VCM = 2.5 V, TA = 25°C, unless otherwise noted. Table 1. Parameter INPUT CHARACTERISTICS Offset Voltage Symbol Test Conditions/Comments Min VOS Typ Max Unit 50 750 1 1.5 1.6 1 180 0.5 60 3 93 140 2.5 µV mV mV mV pA pA pA pA V dB V/mV µV/°C 0.01 ±6 V V V V mA AD8643 LFCSP only −40°C < TA < +85°C +85°C < TA < +125°C, VCM = 1.5 V Input Bias Current IB 0.25 −40°C < TA < +125°C Input Offset Current IOS −40°C < TA < +125°C Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage High CMRR AVO ∆VOS/∆T VCM = 0 V to 2.5 V RL = 10 kΩ, VO = 0.5 to 4.5 V −40°C < TA < +125°C VOH IL = 1 mA, −40°C to +125°C Output Voltage Low 0 74 80 4.95 4.94 VOL IL = 1 mA, −40°C to +125°C Output Current POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier IOUT PSRR ISY VS = 5 V to 26 V 90 107 195 −40°C < TA < +125°C DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product Phase Margin NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density SR GBP 250 270 dB µA µA AD8641, AD8642 AD8643 2 3 2.5 50 V/µs MHz MHz Degrees f = 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz 4.0 28.5 0.5 µV p-p nV/√Hz fA/√Hz Øm eN p-p eN iN 0.05 0.05 Rev. F | Page 3 of 15 AD8641/AD8642/AD8643 Data Sheet VS = ±13 V, VCM = 0 V, TA =25°C, unless otherwise noted. Table 2. Parameter INPUT CHARACTERISTICS Offset Voltage Symbol Test Conditions/Comments Min VOS Typ Max Unit 70 750 1 1.5 1 260 0.5 65 +10 107 290 2.5 µV mV mV pA pA pA pA V dB V/mV µV/°C ±12 V V V V mA AD8643 LFCSP only −40°C < TA < +125°C Input Bias Current IB 0.25 −40°C < TA < +125°C Input Offset Current IOS −40°C < TA < +125°C Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage High CMRR AVO ∆VOS/∆T VCM = −13 V to +10 V RL = 10 kΩ, VO = −11 V to +11 V −40°C < TA < +125°C VOH IL = 1 mA, −40°C to +125°C Output Voltage Low −13 90 215 +12.95 +12.94 VOL −12.95 −12.94 IL = 1 mA, −40°C to +125°C Output Current POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier IOUT PSRR ISY VS = ±2.5 V to ±13 V 90 107 200 −40°C < TA < +125°C DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product Phase Margin NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density SR GBP Øm eN p-p eN iN f = 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz Rev. F | Page 4 of 15 290 330 dB µA µA 3 3.5 60 V/µs MHz Degrees 4.2 27.5 0.5 µV p-p nV/√Hz fA/√Hz Data Sheet AD8641/AD8642/AD8643 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings apply at 25°C, unless otherwise noted. Table 3. Parameter Supply Voltage Input Voltage Differential Input Voltage Output Short-Circuit Duration Storage Temperature Range KS-5, R-8, RM-8, R-14, CP-16 Packages Operating Temperature Range Junction Temperature Range KS-5, R-8, RM-8, R-14, CP-16 Packages Lead Temperature (Soldering, 60 sec) Rating 27.3 V VS− to VS+ ±Supply Voltage Indefinite −65°C to +150°C −40°C to +125°C −65°C to +150°C 300°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. This was measured using a standard 4-layer board. For the LFCSP, solder the exposed pad to a copper plane, which should be connected to V+. Table 4. Package Type 5-Lead SC70 (KS) 8-Lead SOIC (R) 8-Lead MSOP (RM) 14-Lead SOIC (R) 16-Lead LFCSP (CP) ESD CAUTION Rev. F | Page 5 of 15 θJA 430 121 142 110 81 θJC 149 43 45 36 16 Unit °C/W °C/W °C/W °C/W °C/W AD8641/AD8642/AD8643 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 20 80 VSY = ±13V VSY = 5V VCM = 1.5V 18 70 16 NUMBER OF AMPLIFIERS FREQUENCY 60 50 40 30 20 14 12 10 8 6 9.5 10.0 9.0 8.5 8.0 7.5 7.0 6.0 6.5 5.5 5.0 4.5 4.0 3.0 3.5 2.0 2.5 1.5 1.0 0 TCVOS (µV/°C) Figure 7. Input Offset Voltage 05072-005 VOS (mV) 05072-002 0 –0.60 –0.55 –0.50 –0.45 –0.40 –0.35 –0.30 –0.25 –0.20 –0.15 –0.10 –0.05 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 2 0 0.5 4 10 Figure 10. Offset Voltage Drift 16 4.5 VSY = ±13V 4.0 14 VSY = ±13V TA = 25°C 3.0 INPUT BIAS (pA) NUMBER OF AMPLIFIERS 3.5 12 10 8 6 2.5 2.0 1.5 1.0 4 0.5 2 OFFSET VOLTAGE (µV/°C) –0.5 05072-003 9.5 10.0 9.0 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0 0.5 0 –15 –13 –11 –9 –7 –5 –3 1 –1 3 5 7 11 9 13 15 VCM (V) 05072-006 0 Figure 11. Input Bias Current vs. VCM Figure 8. Offset Voltage Drift 70 0.5 VSY = ±2.5V 0.4 60 VSY = ±13V TA = 25°C 0.3 INPUT BIAS (pA) 0.2 40 30 0.1 0 –0.1 –0.2 20 –0.3 10 Figure 9. Input Offset Voltage –0.5 –15.0 –12.5 –10.0 –7.5 –5.0 –2.5 0 2.5 5.0 7.5 10.0 VCM (V) Figure 12. Input Bias Current vs. VCM Rev. F | Page 6 of 15 12.5 15.0 05072-007 VOS (mV) 05072-004 –0.4 0 –0.60 –0.55 –0.50 –0.45 –0.40 –0.35 –0.30 –0.25 –0.20 –0.15 –0.10 –0.05 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 FREQUENCY 50 Data Sheet AD8641/AD8642/AD8643 1000 500 VSY = ±13V VSY = 5V 400 200 VOS (µV) INPUT BIAS CURRENT (pA) 300 100 10 100 0 –100 –200 1 –300 –400 50 100 75 150 125 TEMPERATURE (°C) –500 0 0.5 1.0 1.5 2.0 05072-011 25 0 05072-008 0.1 2.5 VCM (V) Figure 16. Input Offset Voltage vs. VCM Figure 13. Input Bias Current vs. Temperature 10M 1.0 VSY = +5V OR ±5V 0.8 OPEN-LOOP GAIN (V/V) 0.6 INPUT BIAS (pA) 0.4 0.2 0 –0.2 –0.4 1M VSY = ±13V VSY = ±2.5V 100k –0.6 –4 –3 –1 –2 0 1 2 3 4 5 VCM (V) 10k 0.1 Figure 14. Input Bias Current vs. VCM 1000 900 1000 A B 800 C 700 100 AVO (V/mV) 600 500 400 300 D E 10 200 A. VSY = ±13V, VO = ±11V, RL = 10kΩ B. VSY = ±13V, VO = ±11V, RL = 2kΩ C. VSY = +5V, VO = +0.5V/+4.5V, RL = 10kΩ D. VSY = +5V, VO = +0.5V/+4.5V, RL = 2kΩ E. VSY = +5V, VO = +0.5V/+4.5V, RL = 600Ω 100 0 –100 –9 –7 –5 –3 –1 0 1 3 5 7 9 VCM (V) 11 13 15 05072-010 VOS (µV) 100 10 Figure 17. Open-Loop Gain vs. Load Resistance VSY = ±13V –15 –13 –11 1 LOAD RESISTANCE (kΩ) 1 –50 –30 –10 10 30 50 70 90 110 130 TEMPERATURE (°C) Figure 18. Open-Loop Gain vs. Temperature Figure 15. Input Offset Voltage vs. VCM Rev. F | Page 7 of 15 150 05072-013 –5 05072-009 –1.0 05072-012 –0.8 AD8641/AD8642/AD8643 Data Sheet 10000 600 VSY = ±13V VSY = ±13V 500 SATURATION VOLTAGE (mV) OFFSET VOLTAGE (µV) 400 300 200 100 0 100kΩ –100 –200 –300 10kΩ 1kΩ VSY – VOH 1000 100 –VSY – VOL 10 –400 –10 –5 0 5 10 15 OUTPUT VOLTAGE (V) 1 0.001 05072-014 –600 –15 0.01 0.1 1 10 05072-017 –500 100 LOAD CURRENT (mA) Figure 22. Output Saturation Voltage vs. Load Current Figure 19. Input Error Voltage vs. Output Voltage for Resistive Loads 10000 250 VSY = ±5V 200 VSY = 5V POS RAIL VSY – VOH RL = 1kΩ 50 RL = 2kΩ 0 RL = 10kΩ RL = 100kΩ –50 –100 –150 –200 1000 RL = 100kΩ RL = 1kΩ RL = 10kΩ NEG RAIL RL = 2kΩ –300 –350 0 50 100 150 200 250 300 350 OUTPUT VOLTAGE FROM SUPPLY RAIL (mV) 100 10 1 0.001 05072-015 –250 VOL 0.01 0.1 1 10 05072-018 100 SATURATION VOLTAGE (mV) INPUT VOLTAGE (µV) 150 100 LOAD CURRENT (mA) Figure 23. Output Saturation Voltage vs. Load Current Figure 20. Input Error Voltage vs. Output Voltage Within 300 mV of Supply Rails 70 800 VSY = ±13V RL = 2kΩ CL = 40pF 60 700 50 315 270 225 40 GAIN (dB) ISY (µA) 180 GAIN 500 400 +25°C 300 +125°C 30 135 20 PHASE 90 10 45 0 0 PHASE (Degrees) 600 –55°C 0 4 8 12 16 VSY (V) 20 24 28 05072-016 100 Figure 21. Quiescent Current vs. Supply Voltage at Different Temperatures Rev. F | Page 8 of 15 –10 –45 –20 –90 –30 10k –135 100k 1M 10M FREQUENCY (Hz) Figure 24. Open-Loop Gain and Phase Margin vs. Frequency 05072-019 200 Data Sheet AD8641/AD8642/AD8643 30 225 100 180 80 135 20 90 PHASE 10 45 0 0 –10 –45 –20 –90 –30 10k –135 100k 1M VSY = ±13V 60 40 20 0 –20 –40 –60 1k 10M 100k 10k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 25. Open-Loop Gain and Phase Margin vs. Frequency Figure 28. CMRR vs. Frequency 50 10M 10M 140 70 60 10M 05072-023 GAIN 120 05072-024 GAIN (dB) 40 270 05072-025 50 140 CMRR (dB) 60 315 PHASE (Degrees) VSY = 5V RL = 2kΩ CL = 40pF 05072-020 70 VSY = ±13V RL = 2kΩ CL = 40pF 120 VSY = 5V 100 80 40 CMRR (dB) GAIN (dB) G = +100 30 20 G = +10 10 60 40 20 0 0 G = +1 –10 –20 –20 –40 10k 100k 1M 10M FREQUENCY (Hz) –60 1k 05072-021 –30 1k 10k Figure 29. CMRR vs. Frequency 140 70 50 1M FREQUENCY (Hz) Figure 26. Closed-Loop Gain vs. Frequency 60 100k VSY = 5V RL = 2kΩ CL = 40pF 120 VSY = ±13V 100 +PSRR 80 40 PSRR (dB) 20 G = +10 10 60 40 –PSRR 20 0 0 G = +1 –10 –20 –20 –40 –30 1k 10k 100k 1M 10M FREQUENCY (Hz) 05072-022 GAIN (dB) G = +100 30 Figure 27. Closed-Loop Gain vs. Frequency –60 1k 10k 100k 1M FREQUENCY (Hz) Figure 30. PSRR vs. Frequency Rev. F | Page 9 of 15 AD8641/AD8642/AD8643 Data Sheet 140 100 1 80 VIN INPUT BIAS (pA) 0.4 60 40 –PSRR 20 0.2 0 –0.2 0 –0.4 –20 –0.6 –40 –0.8 2 100k 1M 10M FREQUENCY (Hz) VOUT –1.0 CH1 –4 10.0V –3CH2 –2 10.0V–1 –5 CH1 4 1.00V5 0M400µs 1 2 A 3 T 0.00000s VCM (V) 05072-009 10k 05072-026 –60 1k Figure 34. No Phase Reversal Figure 31. PSRR vs. Frequency 15 1000 VSY = ±13V VS = ±13V GAIN = +5 G = +100 10 100 TS + (1%) OUTPUT SWING (V) 10 G = +10 1 G = +1 0.1 5 TS + (0.1%) 0 –5 TS – (0.1%) –10 10k 100k 1M 10M 100M FREQUENCY (Hz) –15 05072-027 0.01 1k TS – (1%) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 SETTLING TIME (µs) Figure 32. Output Impedance vs. Frequency 05072-030 ZOUT (Ω) VSY = ±13V 0.6 +PSRR PSRR (dB) T 0.8 05072-029 120 1.0 VSY = 5V Figure 35. Output Swing and Error vs. Settling Time 70 1000 VS = ±13V RL = 10kΩ VIN = 100mV p-p AV = +1 VSY = 5V G = +100 60 100 OVERSHOOT (%) 10 G = +10 1 G = +1 40 OS– 30 OS+ 20 0.1 0.01 1k 10k 100k 1M 10M FREQUENCY (Hz) 100M Figure 33. Output Impedance vs. Frequency 0 1 10 100 1000 CAPACITANCE (pF) Figure 36. Small Signal Overshoot vs. Load Capacitance Rev. F | Page 10 of 15 05072-031 10 05072-028 ZOUT (Ω) 50 Data Sheet AD8641/AD8642/AD8643 70 1k 40 OS– 30 OS+ 20 0 10 1 1000 100 CAPACITANCE (pF) 10 1 10 05072-032 10 100 100 Figure 37. Small Signal Overshoot vs. Load Capacitance 10k Figure 40. Voltage Noise Density 1k 1.0 VS = ±13V G = +1M CH1 p-p = 4.26V VSY = 5V VOLTAGE NOISE DENSITY (nV/ Hz) 0.8 0.6 0.4 INPUT BIAS (pA) 1k FREQUENCY (Hz) 0.2 10 –0.2 –0.4 10 05072-033 –0.6 100 –1.0 CH1 –4 1.00V –3 –5 –2 –1 0M1.00s1 2 A CH1 3 1 10 05072-009 –0.8 4–20.0V5 VCM (V) 100 10k 1k FREQUENCY (Hz) 05072-036 OVERSHOOT (%) 50 VSY = ±13V 05072-035 60 VOLTAGE NOISE DENSITY (nV/ Hz) VS = ±2.5V RL = 10kΩ VIN = 100mV p-p AV = +1 Figure 41. Voltage Noise Density Figure 38. 0.1 Hz to 10 Hz Noise 0.004 1.0 VS = ±2.5V G = +1M CH1 p-p = 4.06V 0.8 VSY = ±13V LOAD = 100kΩ GAIN = +1 0.001 8V p-p INPUT 0.6 THD + NOISE (%) 0.2 10 –0.2 –0.4 1V p-p INPUT 2V p-p INPUT 0.0001 4V p-p INPUT 0.00001 –1.0 CH1 –4 1.00V –3 –5 –2 –1 0M1.00s1 2 A CH1 3 VCM (V) 4–20.0V5 0.000001 05072-009 –0.8 1 100 1k 10k 20k FREQUENCY (Hz) Figure 42. Total Harmonic Distortion + Noise vs. Frequency Figure 39. 0.1 Hz to 10 Hz Noise Rev. F | Page 11 of 15 05072-037 –0.6 05072-034 INPUT BIAS (pA) 0.4 AD8641/AD8642/AD8643 Data Sheet –40 20kΩ –50 2kΩ – –60 + –70 VIN – 2kΩ 2kΩ + –80 VIN = 18V p-p –110 –120 VIN = 4.5V p-p –130 –140 –150 –160 20 VIN = 9V p-p 100 05072-041 (dB) –90 –100 1k 10k 100k FREQUENCY (Hz) Figure 43. Channel Separation Rev. F | Page 12 of 15 Data Sheet AD8641/AD8642/AD8643 OUTLINE DIMENSIONS 2.20 2.00 1.80 1.35 1.25 1.15 5 2.40 2.10 1.80 4 1 3 2 0.65 BSC 0.40 0.10 1.10 0.80 0.10 MAX COPLANARITY 0.10 SEATING PLANE 0.30 0.15 0.46 0.36 0.26 0.22 0.08 072809-A 1.00 0.90 0.70 COMPLIANT TO JEDEC STANDARDS MO-203-AA Figure 44. 5-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-5) Dimensions shown in millimeters 5.00 (0.1968) 4.80 (0.1890) 8 4.00 (0.1574) 3.80 (0.1497) 5 1 6.20 (0.2441) 5.80 (0.2284) 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) COPLANARITY 0.10 SEATING PLANE 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 012407-A COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 45. 8-Lead Standard Small Outline Package [SOIC_N] (R-8) Dimensions shown in millimeters and (inches) 3.20 3.00 2.80 8 3.20 3.00 2.80 1 5.15 4.90 4.65 5 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.40 0.25 6° 0° 0.23 0.09 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 46. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. F | Page 13 of 15 0.80 0.55 0.40 10-07-2009-B 0.15 0.05 COPLANARITY 0.10 AD8641/AD8642/AD8643 Data Sheet 8.75 (0.3445) 8.55 (0.3366) 4.00 (0.1575) 3.80 (0.1496) 8 14 1 7 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 6.20 (0.2441) 5.80 (0.2283) 0.50 (0.0197) 0.25 (0.0098) 1.75 (0.0689) 1.35 (0.0531) SEATING PLANE 45° 8° 0° 1.27 (0.0500) 0.40 (0.0157) 0.25 (0.0098) 0.17 (0.0067) 060606-A COMPLIANT TO JEDEC STANDARDS MS-012-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 47. 14-Lead Standard Small Outline Package [SOIC_N] (R-14) Dimensions shown in millimeters and (inches) 0.30 0.25 0.20 0.50 BSC 13 PIN 1 INDICATOR 16 1 12 EXPOSED PAD 1.65 1.50 SQ 1.45 9 TOP VIEW 0.80 0.75 0.70 SEATING PLANE 0.50 0.40 0.30 4 8 5 0.20 MIN BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6. 01-26-2012-A PIN 1 INDICATOR 3.10 3.00 SQ 2.90 Figure 48. 16-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-16-27) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD8641AKSZ-R2 AD8641AKSZ-REEL7 AD8641ARZ AD8641ARZ-REEL7 AD8642ARMZ AD8642ARMZ-REEL AD8642ARZ AD8642ARZ-REEL7 AD8642ARZ-REEL AD8643ARZ AD8643ARZ-REEL7 AD8643ACPZ-R2 AD8643ACPZ-REEL7 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 5-Lead Thin Shrink Small Outline Transistor Package [SC70] 5-Lead Thin Shrink Small Outline Transistor Package [SC70] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 14-Lead Standard Small Outline Package [SOIC_N] 14-Lead Standard Small Outline Package [SOIC_N] 16-Lead Lead Frame Chip Scale Package [LFCSP] 16-Lead Lead Frame Chip Scale Package [LFCSP] Z = RoHS Compliant Part. Rev. F | Page 14 of 15 Package Option KS-5 KS-5 R-8 R-8 RM-8 RM-8 R-8 R-8 R-8 R-14 R-14 CP-16-27 CP-16-27 Branding A07 A07 A0A A0A AUA AUA Data Sheet AD8641/AD8642/AD8643 NOTES ©2004–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05072-0-4/16(F) Rev. F | Page 15 of 15