a
FEATURES
150 MSPS ENCODE Rate
Low Input Capacitance: 17 pF
Low Power: 750 mW
–5.2 V Single Supply
MIL-STD-883 Compliant Versions Available
APPLICATIONS
Radar Systems
Digital Oscilloscopes/ATE Equipment
Laser/Radar Warning Receivers
Digital Radio
Electronic Warfare (ECM, ECCM, ESM)
Communication/Signal Intelligence
High Speed 8-Bit
Monolithic A/D Converter
AD9002
FUNCTIONAL BLOCK DIAGRAM
OVERFLOW
INH
AD9002
ANALOG IN
R
256
R
BIT 8 (MSB)
255
R
128
R/2
REFMID
R/2
127
GENERAL DESCRIPTION
The AD9002 is an 8-bit, high speed, analog-to-digital converter.
The AD9002 is fabricated in an advanced bipolar process that
allows operation at sampling rates in excess of 150 MSPS. Functionally, the AD9002 is comprised of 256 parallel comparator
stages whose outputs are decoded to drive the ECL compatible
output latches.
An exceptionally wide, large signal, analog input bandwidth of
160 MHz is due to an innovative comparator design and very
close attention to device layout considerations. The wide input
bandwidth of the AD9002 allows very accurate acquisition of
high speed pulse inputs without an external track-and-hold. The
comparator output decoding scheme minimizes false codes,
which is critical to high speed linearity.
The AD9002 provides an external hysteresis control pin that
can be used to optimize comparator sensitivity to further improve
performance. Additionally, the AD9002’s low power dissipation
of 750 mW makes it usable over the full extended temperature
range. The AD9002 also incorporates an overflow bit to indicate
overrange inputs. This overflow output can be disabled with the
overflow inhibit pin.
OVERFLOW
+VREF
R
D
E
C
O
D
I
N
G
L
O
G
I
C
BIT 7
L
A
T
C
H
BIT 6
BIT 5
BIT 4
BIT 3
2
BIT 2
R
BIT 1 (LSB)
1
–VREF
ENCODE
ENCODE
GND
HYSTERESIS
–VS
The AD9002 is available in two grades, one with 0.5 LSB linearity
and one with 0.75 LSB linearity. Both versions are offered in an
industrial grade, –25°C to +85°C, packaged in a 28-lead DIP
and a 28-leaded JLCC. The military temperature range devices,
–55°C to +125°C, are available in a ceramic DIP package and
complies with MIL-STD-883 Class B.
REV. G
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
AD9002–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (–V = –5.2 V, Differential Reference Voltage = 2.0 V, unless otherwise noted.)
S
Parameter
Temp
RESOLUTION
DC ACCURACY
Differential Linearity
Integral Linearity
No Missing Codes
INITIAL OFFSET ERROR
Top of Reference Ladder
Bottom of Reference Ladder
Offset Drift Coefficient
ANALOG INPUT
Input Bias Current1
Input Resistance
Input Capacitance
Large Signal Bandwidth2
Input Slew Rate3
REFERENCE INPUT
Reference Ladder Resistance
Ladder Temperature Coefficient
Reference Input Bandwidth
25°C
Full
25°C
Full
Full
AD9002AD/AJ
Min
Typ
Max
AD9002BD/BJ
Min
Typ
Max
Min
8
8
8
0.6
0.6
Guaranteed
25°C
Full
25°C
Full
Full
25°C
Full
25°C
25°C
25°C
25°C
25°C
8
4
60
25
200
17
160
440
40
80
0.25
10
125
150
1.3
15
3.7
6
6
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
ENCODE INPUT
Logic “1” Voltage4
Logic “0” Voltage4
Logic “1” Current
Logic “0” Current
Input Capacitance
ENCODE Pulsewidth (Low)9
ENCODE Pulsewidth (High)9
Full
Full
Full
Full
25°C
25°C
25°C
OVERFLOW INHIBIT INPUT
0 V Input Current
Full
144
25°C
7.6
2.5
14
17
10
12
8
4
200
200
60
25
200
17
160
440
22
110
5.5
40
80
0.25
10
125
150
1.3
15
3.7
6
6
2.5
Full
Full
–1.1
25
110
5.5
200
17
160
440
40
80
0.25
10
125
150
1.3
15
3.7
6
6
2.5
48
300
46
1.5
200
200
750
50
0.8
NOTES
1
Measured with AIN = 0 V.
2
Measured by FFT analysis where fundamental is –3 dBc.
3
Input slew rate derived from rise time (10% to 90%) of full-scale input.
4
Outputs terminated through 100 Ω to –2 V.
5
Measured from ENCODE in to data out for LSB only.
6
For full-scale step input, 8-bit accuracy is attained in specified time.
7
Recovers to 8-bit accuracy in specified time after 150% full-scale input overvoltage.
8
Output time skew includes high-to-low and low-to-high transitions as well as
60
25
22
110
5.5
1.5
200
200
µA
µA
kΩ
pF
MHz
V/µs
200
17
160
440
40
80
0.25
10
125
150
1.3
15
3.7
6
6
2.5
22
110
5.5
3.0
2.5
0.6
–1.5
150
120
3
300
55
50
44
47.6
60
144
48
46
–1.1
175
200
mV
mV
mV
mV
µV/°C
1.5
1.5
300
750
50
0.8
175
200
1.5
MSPS
ns
ps
ns
ns
ns
ns
ns
ns
V
V
µA
µA
pF
ns
ns
µA
Bits
55
50
44
47.6
60
dB
dB
dB
dB
dB
–1.5
145
Ω
Ω/°C
MHz
7.6
–1.1
–1.5
145
14
17
10
12
–1.1
144
48
LSB
LSB
LSB
LSB
20
7.6
–1.1
–1.5
4
3
55
50
44
47.6
60
46
8
–1.5
150
120
7.6
175
200
14
17
10
12
–1.1
144
0.5
0.75
0.5
1.2
Guaranteed
1.5
1.5
300
0.4
0.6
–1.5
150
120
Unit
Bits
3.0
2.5
3
55
50
44
47.6
60
750
50
0.8
60
22
1.5
1.5
145
4
200
200
AD9002TD
Typ
Max
0.4
20
–1.1
3
DIGITAL OUTPUTS4
Logic “1” Voltage
Logic “0” Voltage
8
0.6
1.5
1.5
0.75
1.0
1.0
1.2
Guaranteed
3.0
2.5
–1.5
150
120
46
0.6
14
17
10
12
Min
8
0.6
20
–1.1
48
0.5
0.75
0.5
1.2
Guaranteed
0.6
25°C
25°C
25°C
25°C
25°C
Nominal Power Dissipation
Reference Ladder Dissipation
Power Supply Rejection Ratio15
0.4
3.0
2.5
AC LINEARITY10
Effective Bits11
In-Band Harmonics
DC to 1.23 MHz
DC to 9.3 MHz
DC to 19.3 MHz
Signal-to-Noise Ratio12
Two Tone Intermod Rejection13
25°C
Full
25°C
25°C
25°C
0.4
20
DYNAMIC PERFORMANCE
Conversion Rate
Aperture Delay
Aperture Uncertainty (Jitter)
Output Delay (tPD)4, 5
Transient Response6
Overvoltage Recovery Time7
Output Rise Time4
Output Fall Time4
Output Time Skew4, 8
POWER SUPPLY14
Supply Current (–5.2 V)
0.75
1.0
1.0
1.2
AD9002SD
Typ
Max
–1.5
145
750
50
0.8
175
200
1.5
V
V
mA
mA
mW
mW
mV/V
bit-to-bit time skew differences.
9
ENCODE signal rise/fall times should be less than 10 ns for normal operation.
10
Measured at 125 MSPS ENCODE rate.
11
Analog input frequency = 1.23 MHz.
12
RMS signal to rms noise, with 1.23 MHz analog input signal.
13
Input signals 1 V p-p @ 1.23 MHz and 1 V p-p @ 2.30 MHz.
14
Supplies should remain stable within ± 5% for normal operation.
15
Measured at –5.2 V ± 5%.
Specifications subject to change without notice.
–2–
REV. G
AD9002
ABSOLUTE MAXIMUM RATINGS 1
Supply Voltage (–VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . –6 V
Analog-to-Digital Supply Voltage Differential . . . . . . . . 0.5 V
Analog Input Voltage . . . . . . . . . . . . . . . . . . . . –VS to +0.5 V
Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . . –VS to 0 V
Reference Input Voltage (+VREF, – VREF)2 . . . –3.5 V to +0.1 V
Differential Reference Voltage . . . . . . . . . . . . . . . . . . . . 2.1 V
Reference Midpoint Current . . . . . . . . . . . . . . . . . . . . ± 4 mA
ENCODE to ENCODE Differential Voltage . . . . . . . . . . . 4 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature Range
AD9002AD/BD/AJ/BJ . . . . . . . . . . . . . . . –25°C to +85°C
AD9002SD/TD . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature3 . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead Soldering Temperature (10 sec) . . . . . . . . . . . . . 300°C
NOTES
1
Absolute Maximum Ratings are limiting values, to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect device
reliability.
2
+VREF ≥ –VREF under all circumstances.
3
Maximum junction temperature (T J max) should not exceed 175°C for ceramic
packages, and 150°C for plastic packages:
TJ = PD (θJA) + TA
= PD (θJC) + TC
where
PD = power dissipation
θJA = thermal impedance from junction to ambient (°C/W)
θJC = thermal impedance from junction to case (°C/W)
TA = ambient temperature (°C)
TC = case temperature (°C)
Typical thermal impedances are:
Ceramic DIP θJA = 56°C/W; θJC = 20°C/W
PLCC θJA = 60°C/W; θJC = 19°C/W
Recommended Operating Conditions
Input Voltage (V)
Parameter
Min
Nominal
Max
–VS
+VREF
–VREF
Analog Input
–5.46
–VREF
–2.1
–VREF
–5.20
0.0
–2.0
–4.94
+0.1
+VREF
+VREF
EXPLANATION OF TEST LEVELS
Test Level I
Test Level II
– 100% production tested.
– 100% production tested at 25°C and sample
tested at specified temperatures.
Test Level III – Sample tested only.
Test Level IV – Parameter is guaranteed by design and
characterization testing.
Test Level V – Parameter is a typical value only.
Test Level VI – All devices are 100% production tested at
25°C. 100% production tested at temperature
extremes for extended temperature devices;
sample tested at temperature extremes for
commercial/industrial devices.
ORDERING GUIDE
Model
Package
Linearity Temperature Range Option*
AD9002AD
AD9002BD
AD9002AJ
AD9002BJ
AD9002SD/883B
AD9002TD/883B
0.75 LSB
0.50 LSB
0.75 LSB
0.50 LSB
0.75 LSB
0.50 LSB
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–55°C to +125°C
–55°C to +125°C
*D = Ceramic DIP; J = Ceramic Chip Carrier, J-Formed Leads.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9002 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. G
–3–
D-28
D-28
J-28
J-28
D-28
D-28
AD9002
FUNCTIONAL DESCRIPTION
Pin No.
Mnemonic
Description
1
2
DIGITAL GROUND
OVERFLOW INH
One of Four Digital Ground Pins. All digital ground pins should be connected together.
OVERFLOW INHIBIT controls the data output polarity for overvoltage inputs.
3
HYSTERESIS
4
5
6
7
+VREF
ANALOG INPUT
ANALOG GROUND
ENCODE
8
9
10
11
12
13
14
ENCODE
ANALOG GROUND
ANALOG INPUT
–VREF
REFMID
DIGITAL GROUND
DIGITAL –VS
15
16–19
20
21, 22
D1 (LSB)
D2–D5
DIGITAL GROUND
ANALOG –VS
23
24, 25
26
27
DIGITAL GROUND
D6, D7
D8 (MSB)
OVERFLOW
28
DIGITAL –VS
Analog Input
Overflow Enabled
(Floating or –5.2 V)
of D1–D8
Overflow Inhibited (GND)
of D1–D8
VIN > +VREF
1 0 0 0 0 0 0 0 0
0 1 1 1 1 1 1
VIN ≤ +VREF
0 X X X X X X X X
0 X X X X X X X X
1 1
The hysteresis control voltage varies the comparator hysteresis from 0 mV to 10 mV, for a change
from –5.2 V to –2.2 V at the hysteresis control pin. Normally converted to –5.2 V.
The Most Positive Reference Voltage for the Internal Resistor Ladder
One of Two Analog Input Pins. Both analog input pins should be connected together.
One of Two Analog Ground Pins. Both analog ground pins should be connected together.
Noninverted Input of the Differential ENCODE Input. This pin is driven in conjunction with
ENCODE. Data is latched on the rising edge of the ENCODE signal.
Inverted Input of the Differential ENCODE Input. This pin is driven in conjunction with ENCODE.
One of Two Analog Ground Pins. Both analog ground pins should be connected together.
One of Two Analog Input Pins. Both analog inputs should be connected together.
The Most Negative Reference Voltage for the Internal Resistor Ladder
The Midpoint Tap on the Internal Resistor Ladder
One of Four Digital Ground Pins. All digital ground pins should be connected together.
One of Two Negative Digital Supply Pins (Nominally –5.2 V). Both digital supply pins should be
connected together.
Digital Data Output
Digital Data Output
One of Four Digital Ground Pins. All digital ground pins should be connected together.
One of Two Negative Analog Supply Pins (Nominally –5.2 V). Both analog supply pins should be
connected together.
One of Four Digital Ground Pins. All digital ground pins should be connected together.
Digital Data Output
Digital Data Output
Overflow Data Output. Logic high indicates an input overvoltage (V IN > +VREF) if OVERFLOW
INH is enabled (overflow enabled, –5.2 V). See OVERFLOW INH.
One of Two Negative Digital Supply Pins (Nominally –5.2 V). Both digital supply pins should
be connected together.
PIN DESIGNATIONS
D7
ANALOG INPUT 5
ANALOG 6
GROUND
24
D6
ENCODE 7
25 24 23 22 21 20 19
DIGITAL
GROUND
22 ANALOG –VS
23
AD9002
TOP VIEW
ENCODE 8 (Not to Scale) 21 ANALOG –VS
ANALOG 9
20 DIGITAL
GROUND
GROUND
19 D5
ANALOG INPUT 10
–VREF 11
18
D4
REFMID 12
17
D3
16
D2
15
D1(LSB)
DIGITAL 13
GROUND
DIGITAL –VS 14
D5
25
ANALOG –VS
DIGITAL GROUND
D8(MSB)
+VREF 4
DIGITAL GROUND
26
–4–
D8(MSB)
26
18
D4
OVERFLOW
DIGITAL –VS
DIGITAL
GROUND
OVERFLOW INH
HYSTERESIS
27
17
3
13
+VREF
4
12
D3
D2
D1(LSB)
DIGITAL –VS
DIGITAL
GROUND
REFMID
28
1
AD9002
16
TOP VIEW
15
(Not to Scale)
2
9
10
14
5
6
7
8
ENCODE
ANALOG GROUND
ANALOG INPUT
–VREF
OVERFLOW
HYSTERESIS 3
ENCODE
DIGITAL –VS
27
ANALOG INPUT
28
OVERFLOW INH 2
ANALOG GROUND
DIGITAL 1
GROUND
ANALOG –VS
JLCC
D7
D6
DIP
11
REV. G
AD9002
N+1
ANALOG
INPUT
N
N+2
APERTURE
DELAY
ENCODE
t PD
OUTPUT
DATA
N–1
N+1
N
Figure 1. Timing Diagram
AD9002
+VREF
AD9002
R
AD9002
R/2
REFMID
ENCODE
ANALOG
INPUT
ENCODE
R/2
–5.2V
–5.2V
DIGITAL
OUTPUT
R
–VREF
–5.2V
–5.2V
–5.2V
COMPARATOR CELLS
Figure 2. Input/Output Circuits
OVERFLOW
INH
HYSTERESIS
DIGITAL
GROUND
DIGITAL –VS
OVERFLOW
0.1F
–5.2V
–VS
HYSTERESIS
OVERFLOW INH
100
AD1
AD2
1k
OVERFLOW
ANALOG IN
1k
1k
1k
ANALOG
GROUND
1k
ENCODE
1k
ANALOG –VS
DIGITAL
GROUND
1k
AD9002
+VREF
GROUND
STATIC BURN IN
AD1 = 0V
AD2 = ECL HIGH
DYNAMIC BURN IN
D3
ANALOG
GROUND
1k
D2
1k
D1
D5
ANALOG
INPUT
D4
AD3 = ECL LOW
AD1
0V
D1 (LSB)
DIGITAL
GROUND DIGITAL
REFMID
–VS
–VREF
–2V
ECL HIGH
AD2
D2
D3
ECL LOW
Figure 4. Die Layout and Mechanical Information
ECL HIGH
AD3
ECL LOW
ALL RESISTORS 5%
ALL CAPACITORS 20%
ALL SUPPLIES 5%
Figure 3. Burn-In Diagram
REV. G
DIGITAL
GROUND
ENCODE
D4
–VREF
0.1F
D6
1k
D5
ENCODE
–2V
D7
D7
ANALOG
INPUT
1k
D6
ENCODE
AD3
D8
D8 (MSB)
+VREF
Die Dimensions . . . . . 106 mils × 114 mils × 15 mils (± 2 mils)
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . 4 mils × 4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –VS
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride
Die Attach . . . . . . . . . . . . . . . . . . . . . Gold Eutectic (Ceramic)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Epoxy (Plastic)
Bond Wire . . . . . . . . . . 1 mil–1.3 mil Gold; Gold Ball Bonding
–5–
AD9002
APPLICATION INFORMATION
LAYOUT SUGGESTIONS
The AD9002 is compatible with all standard ECL logic families,
including 10K and 10KH. 100K ECL logic levels are temperature
compensated and are therefore compatible with the AD9002 (and
most other ECL device families) only over a limited temperature
range. To operate at the highest ENCODE rates, the supporting logic
around the AD9002 will need to be equally fast. Whichever
ECL logic family is used, special care must be exercised to keep
digital switching noise away from the analog circuits round
the AD9002. The two most critical items are digital supply
lines and digital ground return.
Designs using the AD9002, such as all high speed devices,
must follow a few basic layout rules to ensure optimum performance. Essentially, these guidelines are meant to avoid many
of the problems associated with high speed designs. The first
requirement is for a substantial ground plane around and
under the AD9002. Separate ground plane areas for the digital and
analog components may be useful, but these separate grounds
should be connected together at the AD9002 to avoid the
effects of ground loop currents.
The input capacitance of the AD9002 is an exceptionally low
17 pF. This allows the use of a wide range of input amplifiers,
both hybrid and monolithic. To take full advantage of the wide
input bandwidth of the AD9002, a hybrid amplifier such as the
AD9610 will be required. For those applications that do not
require the full input bandwidth of the AD9002, more traditional monolithic amplifiers, such as the AD846, will work very
well. Overall performance with any amplifier can be improved
by inserting a 10 Ω resistor in series with the amplifier output.
The output data is buffered through the ECL compatible output
latches. All data is delayed by one clock cycle, in addition to the
latch propagation delay (tPD), before becoming available at the
outputs. Both the analog-to-digital conversion cycle and the
data transfer to the output latches are triggered on the rising
edge of the differential, ECL compatible ENCODE signal (see
Figure 1). In applications where only a single-ended signal is available, the AD96685, a high speed, ECL voltage comparator, can
be employed to generate the differential signals. All ECL signals (including the overflow bit) should be terminated properly to
avoid ringing and reflection.
The AD9002 also incorporates a HYSTERESIS control pin
that provides from 0 mV to 10 mV of additional hysteresis in the
comparator input stages. Adjustments in the HYSTERESIS
control voltage may help improve noise immunity and overall
performance in harsh environments.
The OVERFLOW INH pin of the AD9002 determines how
the converter handles overrange inputs (AIN ≥ +VREF). In the
“enabled” state (floating at –5.2 V), the OVERFLOW INH output will be at logic HIGH and all other outputs will be at logic
LOW for overrange inputs (return-to-zero operation). In the
“inhibited” state (tied to ground), the OVERFLOW INH
output will be at logic LOW, and all other outputs will be at
logic HIGH for overrange inputs (nonreturn-to-zero operation).
The second area that requires an extra degree of attention involves
the three reference inputs, +VREF, REFMID, and –VREF. The
+VREF input and the –VREF input should both be driven from a
low impedance source (note that the +VREF input is typically
tied to analog ground). A low drift amplifier should provide
satisfactory results, even over an extended temperature range.
Adjustments at the REFMID input may be useful in improving the
integral linearity by correcting any reference ladder skews. The
application circuit shown below demonstrates a simple and
effective means of driving the reference circuit.
The reference inputs should be adequately decoupled to ground
through 0.1 µF chip capacitors to limit the effects of system noise
on conversion accuracy. The power supply pins must also be
decoupled to ground to improve noise immunity; 0.1 µF and
0.01 µF chip capacitors are recommended.
The analog input signal is brought into the AD9002 through
two separate input pins. It is very important that the two input
pins be driven symmetrically with equal length electrical connections. Otherwise, aperture delay errors may degrade converter
performance at high frequencies.
–15V
1k
4k
100
0.1F
ANALOG
INPUT
(0V TO 2V)
2N3906
10
AD741
0.1F
NYQUIST
FILTER
–VREF +VREF
1.5k
1.5k
40
50
AIN
AD9611
The AD9002 provides outstanding error rate performance. This
is due to tight control of comparator offset matching and a fault
tolerant decoding stage. Additional improvements in error rate
are possible through the addition of hysteresis (see HYSTERESIS
control pin). This level of performance is extremely important in
fault sensitive applications, such as digital radio (QAM).
ENCODE
INPUT
(GROUND
THRESHOLD)
AIN
AD9002
ENCODE
50
ENCODE
AD96685
0.01F
Dramatic improvements in comparator design and construction
give the AD9002 excellent dynamic characteristics, especially
SNR (signal-to-noise ratio). The 160 MHz input bandwidth
and low error rate performance give the AD9002 an SNR of
48 dB with a 1.23 MHz input. High SNR performance is particularly important in wide bandwidth applications, such as
pulse signature analysis, commonly performed in advanced
radar receivers.
OVERFLOW
D8 (MSB)
D7
D6
D5
D4
D3
D2
D1 (LSB)
EQUAL
DISTANCE
–5.2A –5.2D
0.1F
0.1F
0.01F
Figure 5. Typical Application
–6–
REV. G
AD9002
LINEARITY OUTPUT
(ERROR WAVEFORM)
HOS100
RECONSTRUCTED
OUTPUT
HOS100
50
1k
4.3k
1k
–15V
3.75
150
AD741
0.1F
2N3906
90 20 90
0.01F
AD9768
DAC
0.1F
50
HOS200
75
ANALOG
INPUT
–VREF
AIN
10F
REFMID
+VREF
OVERFLOW
EQUAL
DISTANCE
50
2k
D8(MSB)
D7
AIN
D6
AD96687
ENCODE
1k
0.1F
D2
D1(LSB)
0.1F
1k
37-PIN
D
CONNECTOR
D3
HYSTERESIS
–15V
LINE
DRIVER
100114
D4
OVERFLOW
INH
3.9k
REGISTER
100151
D5
AD9002*
ENCODE
–5.2A
–5.2D
625
–5.2V
ENCODE INPUT
(GROUND
THRESHOLD)
0.1F
0.1F
0.01F
AD96687
0.01F
AD96687
AD96687
510
50
*CONTACT FACTORY ABOUT
EVALUATION BOARD AVAILABILITY
510
0.1F
–5.2V
–5.2V
DELAY
13k
1k
880
DELAY
13k
–15V
1k
880
–15V
Figure 6. AD9002 Evaluation Circuit
RMS SIGNAL-TO-NOISE RATIO (dB)
AND HARMONIC LEVELS (–dBc)
65
60
55
SECOND HARMONIC
THIRD HARMONIC
50
SNR
45
40
35
30
10MHz
100MHz
1MHz
ANALOG INPUT FREQUENCY (0.1dB BELOW FULL SCALE)
125 MSPS ENCODE RATE
Figure 7. Dynamic Performance
REV. G
–7–
100114 LINE DRIVER OUTPUTS
REQUIRE 510 PULL-DOWN
RESISTORS TO –5.2V. ALL OTHER
ECL OUTPUTS SHOULD BE
TERMINATED TO –2V WITH
100 RESISTORS, UNLESS
OTHERWISE SPECIFIED.
AD9002
OUTLINE DIMENSIONS
28-Lead Ceramic Chip Carrier - J-Formed Leads [ JLCC]
(J-28A)
Dimensions shown in inches and (millimeters)
0.040 (1.02)
REF
x 45
3 PLACES
0.460 (11.68)
SQ
0.440 (11.18)
4
26
5
0.035 (0.89)
0.025 (0.64)
25
0.020 (0.51)
REF
x 45
26
4
25
5
PIN 1 INDEX
0.055 (1.40)
PIN 1
0.450 (11.43)
0.410 (10.41)
0.050
(1.27)
C00545–0–5/03(G)
0.125 (3.18)
MAX
0.310 (7.87)
0.290 (7.37)
TOP VIEW
BOTTOM VIEW
0.022 (0.56)
0.012 (0.30)
11
19
12
19
18
11
18
12
0.500 (12.70)
SQ
0.480 (12.19)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
28-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]
(D-28)
Dimensions shown in inches and (millimeters)
0.005 (0.13)
MIN
0.100 (2.54)
MAX
28
15
0.610 (15.49)
0.580 (12.73)
PIN 1
1
1.490 (37.85) MAX
0.085 (2.16)
MAX
0.200 (5.08)
0.125 (3.18)
14
0.026 (0.66)
0.014 (0.36)
0.100 (2.54)
0.060 (1.52)
0.015 (0.38)
0.070 (1.78)
0.030 (0.76)
0.620 (15.75)
0.590 (14.99)
0.150
(3.81)
MIN
SEATING
PLANE
0.018 (0.46)
0.008 (0.20)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Revision History
Location
Page
5/03—Data Sheet changed from REV. F to REV. G.
Deleted the E-28A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Changes to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Data Sheet changed from REV. E to REV. F.
Edit to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
–8–
REV. G
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