a
FEATURES
100 MSPS ENCODE Rate
Very Low Input Capacitance—16 pF
Low Power—1 W
TTL Compatible Outputs
MIL-STD-883 Compliant Versions Available
APPLICATIONS
Radar Guidance
Digital Oscilloscopes/ATE Equipment
Laser/Radar Warning Receivers
Digital Radio
Electronic Warfare (ECM, ECCM, ESM)
Communication/Signal Intelligence
High Speed 8-Bit
TTL A/D Converter
AD9012
FUNCTIONAL BLOCK DIAGRAM
OVERFLOW
INH
AD9012
ANALOG IN
ⴙVREF
R
256
R
128
R/2
REFMID
127
R
GENERAL DESCRIPTION
The exceptionally wide large-signal analog input bandwidth of
160 MHz is due to an innovative comparator design and very
close attention to device layout considerations. The wide input
bandwidth of the AD9012 allows very accurate acquisition of
high speed pulse inputs without an external track-and-hold.
The comparator output decoding scheme minimizes false codes,
which is critical to high speed linearity.
The AD9012 is available in two grades: one with 0.5 LSB
linearity and one with 0.75 LSB linearity. Both versions are
D8 (MSB)
255
R/2
The AD9012 is an 8-bit, ultrahigh speed, analog-to-digital
converter. The AD9012 is fabricated in an advanced bipolar
process that allows operation at sampling rates up to 100
megasamples/second. Functionally, the AD9012 is comprised
of 256 parallel comparator stages whose outputs are decoded
to drive the TTL compatible output latches.
OVERFLOW
R
D
E
C
O
D
I
N
G
L
O
G
I
C
D7
L
A
T
C
H
D5
D4
D3
2
D2
R
D1 (LSB)
1
ⴚVREF
D6
ENCODE
GND
HYSTERESIS
ⴚVS ⴙVS
offered in an industrial grade, –25°C to +85°C, packaged in a
28-lead DIP and a 28-lead JLCC. The military temperature
range devices, –55°C to +125°C, are available in ceramic DIP
and LCC packages and are compliant to MIL-STD-883 Class B.
The AD9012 is available in versions compliant with MIL-STD-883.
Refer to the Analog Devices Military Products Databook or
current AD9012/883B data sheet for detailed specifications.
REV. F
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
AD9012–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (+V = +5.0 V; –V = –5.2 V; Differential Reference Voltage = 2.0 V; unless otherwise noted.)
S
Parameter
Temp
Test
AD9012AQ/AJ
Level Min Typ
Max
RESOLUTION
DC ACCURACY
Differential Linearity
Integral Linearity
No Missing Codes
INITIAL OFFSET ERROR
Top of Reference Ladder
Bottom of Reference Ladder
Offset Drift Coefficient
ANALOG INPUT
Input Bias Current1
Input Resistance
Input Capacitance
Large Signal Bandwidth2
Analog Input Slew Rate3
REFERENCE INPUT
Reference Ladder Resistance
Ladder Temperature Coefficient
Reference Input Bandwidth
S
8
25°C
Full
25°C
Full
Full
I
VI
I
VI
VI
0.6
25°C
Full
25°C
Full
Full
I
VI
I
VI
V
25°C
Full
25°C
25°C
25°C
25°C
I
VI
I
III
V
V
25°C
40
80
0.25
10
100
3.8
15
4.9
8
8
6.6
3.3
3.0
0.6
6
60
25
200
16
160
440
25°C
DYNAMIC PERFORMANCE
Conversion Rate
Aperture Delay
Aperture Uncertainty (Jitter)
Output Delay (tPD)4, 5
Transient Response6
Overvoltage Recovery Time7
Output Rise Time4
Output Fall Time4
Output Time Skew4, 8
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
I
V
V
I
V
V
I
I
V
75
ENCODE INPUT
Logic “1” Voltage4
Logic “0” Voltage4
Logic “1” Current
Logic “0” Current
Input Capacitance
ENCODE Pulsewidth (Low)9
ENCODE Pulsewidth (High)9
Full
Full
Full
Full
25°C
25°C
25°C
VI
VI
VI
VI
V
I
I
2.0
OVERFLOW INHIBIT INPUT
0 V Input Current
Full
VI
200
7.5
25°C
V
25°C
25°C
25°C
25°C
25°C
I
V
V
I
V
DIGITAL OUTPUT
Logic “1” Voltage
Logic “0” Voltage
Full
Full
VI
VI
POWER SUPPLY14
Positive Supply Current (+5.0 V) 25°C
Full
Supply Current (–5.2 V)
25°C
Full
Nominal Power Dissipation
25°C
Reference Ladder Dissipation
25°C
15
Power Supply Rejection Ratio
25°C
I
VI
I
VI
V
V
I
AD9012TQ/TE
Min Typ Max
Unit
8
8
8
Bits
0.4
0.4
4
15
18
10
13
7
6
200
200
60
25
18
110
11
200
16
160
440
40
80
0.25
10
75
100
3.8
15
4.9
8
8
6.6
3.3
3.0
4
8.0
4.3
15
18
10
13
200
200
60
25
18
110
11
250
80
0.25
10
75
100
3.8
15
4.9
8
8
6.6
3.3
3.0
4
8.0
4.3
48
46
955
44
0.85
2.5
–2–
200
200
60
25
18
110
11
2.5
200
16
160
440
40
80
0.25
10
75
100
3.8
15
4.9
8
8
6.6
3.3
3.0
4
8.0
4.3
200
200
µA
µA
kΩ
pF
MHz
V/µs
18
110
11
8.0
4.3
0.8
250
400
2.5
250
55
50
44
47.6
37
200
48
46
2.4
45
48
179
191
mV
mV
mV
mV
µV/°C
25
7.5
46
15
18
10
13
2.5
2.5
200
48
LSB
LSB
LSB
LSB
2.0
250
152
955
44
0.8
45
48
179
191
2.5
MSPS
ns
ps
ns
ns
ns
ns
ns
ns
V
V
µA
µA
pF
ns
ns
µA
Bits
55
50
44
47.6
37
dBc
dBc
dBc
dBc
dBc
0.4
33
Ω
Ω/°C
MHz
7.5
2.4
0.4
152
6
0.8
250
400
250
2.4
33
7
2.5
55
50
44
47.6
37
0.4
45
48
179
191
15
18
10
13
2.5
2.5
200
0.4
0.5
0.75
0.5
1.2
Guaranteed
2.0
7.5
2.4
200
16
160
440
40
2.5
55
50
44
47.6
37
955
44
0.85
6
0.4
25
2.5
2.5
152
7
0.8
250
400
2.5
33
0.6
0.75
1.0
1.0
1.2
Guaranteed
2.0
2.5
2.5
46
0.6
25
0.8
250
400
48
0.5
0.75
0.5
1.2
Guaranteed
25
VI
V
V
AC LINEARITY10
Effective Bits11
In-Band Harmonics
DC to 1.23 MHz
DC to 9.3 MHz
DC to 19.3 MHz
Signal-to-Noise Ratio12
Noise Power Ratio13
AD9012SQ/SE
Min
Typ Max
0.75
1.0
1.0
1.2
Guaranteed
7
AD9012BQ/BJ
Min
Typ
Max
0.4
33
152
955
44
0.8
45
48
179
191
2.5
V
V
mA
mA
mA
mA
mW
mW
mV/V
REV. F
AD9012
NOTES
1
Measured with analog input = 0 V.
2
Measured by FFT analysis where fundamental is –3 dBc.
3
Input slew rate derived from rise time (10% to 90%) of full-scale step input.
4
Outputs terminated with two equivalent ’LS00 type loads. (See load circuit.)
5
Measured from ENCODE into data out for LSB only.
6
For full-scale step input, 8-bit accuracy is attained in specified time.
7
Recovers to 8-bit accuracy in specified time, after 150% full-scale input overvoltage.
8
Output time skew includes high-to-low and low-to-high transitions as well a s
bit-to-bit time skew differences.
9
ENCODE signal rise/fall times should be less than 30 ns for normal operation.
Measured at 75 MSPS ENCODE rate. Harmonic data based on worst-case harmonics.
11
Analog input frequency = 1.23 MHz.
12
RMS signal to rms noise, including harmonics with 1.23 MHz. Analog input
signal.
13
NPR measured @ 0.5 MHz. Noise source is 250 mW (rms) from 0.5 MHz
to 8 MHz.
14
Supplies should remain stable within ± 5% for normal operation.
15
Measured at –5.2 V ± 5% and +5.0 V ± 5%.
Specifications subject to change without notice.
10
ABSOLUTE MAXIMUM RATINGS 1
VS
Positive Supply Voltage (+VS) . . . . . . . . . . . . . . . . . . . . . . 6 V
Analog to Digital Supply Voltage Differential (–VS) . . . 0.5 V
Negative Supply Voltage (–VS) . . . . . . . . . . . . . . . . . . . . –6 V
Analog Input Voltage . . . . . . . . . . . . . . . . . . . . –VS to +0.5 V
ENCODE Input Voltage . . . . . . . . . . . . . . . . . –0.5 V to +5 V
OVERFLOW INH Input Voltage . . . . . . . . . . . –5.2 V to 0 V
Reference Input Voltage (+VREF, –VREF)2 . . –3.5 V to +0.1 V
Differential Reference Voltage . . . . . . . . . . . . . . . . . . . . 2.1 V
Reference Midpoint Current . . . . . . . . . . . . . . . . . . . . ± 4 mA
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Operating Temperature Range
AD9012AQ/BQ/AJ/BJ . . . . . . . . . . . . . . . –25°C to +85°C
AD9012SE/SQ/TE/TQ . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature3 . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead Soldering Temperature (10 sec) . . . . . . . . . . . . . 300°C
NOTES
1
Absolute Maximum Ratings are limiting values, to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
2
+VREF ≥ –VREF under all circumstances.
3
Maximum junction temperature (T J max) should not exceed 150°C for ceramic
and plastic packages:
TJ = PD (θJA) + TA
PD (θJC) + Tc
where:
PD = power dissipation
θJA = thermal impedance from junction to ambient (°C/W)
θJC = thermal impedance from junction to case (°C/W)
TA = ambient temperature (°C)
TC = case temperature (°C)
Typical thermal impedances are:
Ceramic DIP θJA = 42°C/W; θJC = 10°C/W
Ceramic LCC θJA = 50°C/W; θJC = 15°C/W
JLCC θJA = 59°C/W; θJC = 15°C/W
Recommended Operating Conditions
Parameter
Min
–VS
+VS
+VREF
–VREF
Analog Input
–5.46
+4.75
–VREF
–2.1
–VREF
Input Voltage (V)
Nominal
–5.20
+5.00
0.0
–2.0
Max
–4.94
+5.25
+0.1
+VREF
+VREF
1k⍀
TTL
OUTPUT
15pF
Figure 1. Load Circuit
EXPLANATION OF TEST LEVELS
Test Level
I
– 100% production tested.
II – 100% production tested at 25°C, and sample tested at
specified temperatures. AC testing done on sample basis.
III – Sample tested only.
IV – Parameter is guaranteed by design and characterization
testing.
V – Parameter is a typical value only.
VI – All devices are 100% production tested at 25°C. 100%
production tested at temperature extremes for extended
temperature devices; guaranteed by design and
characterization testing for industrial devices.
ORDERING GUIDE
Device
Linearity
Temperature
Ranges
Package
Options*
AD9012AQ
AD9012BQ
AD9012AJ
AD9012BJ
AD9012SQ
AD9012SE
AD9012TQ
AD9012TE
0.75 LSB
0.50 LSB
0.75 LSB
0.50 LSB
0.75 LSB
0.75 LSB
0.50 LSB
0.50 LSB
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
Q-28
Q-28
J-28A
J-28A
Q-28
E-28A
Q-28
E-28A
*E = Leadless Ceramic Chip Carrier; J = Ceramic Leaded Chip Carrier;
Q = Cerdip.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9012 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. F
–3–
AD9012
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic
Description
11
12
One of Three Positive Digital Supply Pins (Nominally 5.0 V)
OVERFLOW INH BIT controls the data output coding for overvoltage inputs (AIN ≥ + VREF).
HYSTERESIS
14
15
16
17
18
19
10
11
12
13
14
+VREF
ANALOG INPUT
ANALOG GROUND
ENCODE
DIGITAL +VS
ANALOG GROUND
ANALOG INPUT
–VREF
REFMID
DIGITAL +VS
DIGITAL –VS
15
16–19
20
21, 22
D1 (LSB)
D2–D5
DIGITAL GROUND
ANALOG –VS
23
24, 25
26
27
DIGITAL GROUND
D 6 , D7
D8 (MSB)
OVERFLOW
28
DIGITAL –VS
Analog Input
Overflow Enabled (Floating)
of D1 D2 D3 D4 D5 D6 D7 D8
Overflow Inhibited (GND)
of D1 D2 D3 D4 D5 D6 D7 D8
VIN +VREF
1 0 0 0 0 0 0 0 0
0 1 1 1 1 1 1
VIN < +VREF
0 X X X X X X X X
0 X X X X X X X X
1 1
The hysteresis control voltage varies the comparator hysteresis from 0 mV to 10 mV, for a
change from –5.2 V to –2.2 V at the hysteresis control pin.
The Most Positive Reference Voltage for the Internal Resistor Ladder
One of Two Analog Input Pins. Both analog input pins should be connected together.
One of Two Analog Ground Pins. Both analog ground pins should be connected together.
TTL Level ENCODE Command Input. ENCODE is rising edge sensitive.
One of Three Positive Digital Supply Pins (Nominally +5.0 V)
One of Two Analog Ground Pins. Both analog ground pins should be connected together.
One of Two Analog Input Pins. Both analog inputs should be connected together.
The Most Negative Reference Voltage for the Internal Resistor Ladder
The Midpoint Tap on the Internal Resistor Ladder
One of Three Positive Digital Supply Pins (Nominally +5.0 V)
One of Two Negative Digital Supply Pins (Nominally –5.2 V). Both digital supply pins should be
connected together.
Digital Data Output. D1 (LSB) is the least significant bit of the digital output word.
Digital Data Output
One of Two Digital Ground Pins. Both digital grounds pins should be connected together.
One of Two Negative Analog Supply Pins (Nominally –5.2 V). Both analog supply pins should be
connected together.
One of Two Digital Ground Pins. Both digital ground pins should be connected together.
Digital Data Output
Digital data output D8 (MSB) is the most significant bit of the digital output word.
Overflow Data Output. Logic HIGH indicates an input overvoltage (VIN > + VREF) if
OVERFLOW INH is enabled (overflow enabled, floating). See OVERFLOW INH.
One of Two Negative Digital Supply Pins (Nominally –5.2 V). Both digital supply pins should be
connected together.
ANALOG GROUND
6
ENCODE
7
DIGITAL +VS
ANALOG GROUND
AD9012
19 D5
–VREF 11
18 D4
REFMID 12
17 D3
DIGITAL +VS 13
16 D2
DIGITAL –VS 14
15 D (LSB)
1
2
1
28 27 26
25 D 7
24 D6
ENCODE 7
DIGITAL +VS 8
ANALOG GROUND 9
20 DIGITAL GROUND
ANALOG INPUT 10
3
ANALOG INPUT 5
ANALOG GROUND 6
23 DIGITAL GROUND
TOP VIEW 22 ANALOG –VS
8 (Not to Scale) 21 ANALOG –VS
9
4
OVERFLOW
24 D6
D8 (MSB)
5
23 DIGITAL GROUND
AD9012
22 ANALOG –VS
TOP VIEW
(Not to Scale)
21 ANALOG –VS
20 DIGITAL GROUND
ANALOG INPUT 10
19 D5
–VREF 11
12 13 14 15 16 17 18
–4–
D4
25 D
7
ANALOG INPUT
DIGITAL –VS
4
D3
26 D (MSB)
8
+VREF
DIGITAL +VS
3
OVERFLOW INH
27 OVERFLOW
HYSTERESIS
D1 (LSB)
D2
28 DIGITAL –VS
2
DIGITAL –VS
1
+VREF
DIGITAL +VS
OVERFLOW INH
HYSTERESIS
PIN CONFIGURATIONS
REFMID
DIGITAL +VS
3
DIGITAL +VS
OVERFLOW INH
REV. F
AD9012
N+1
ANALOG
INPUT
N
N+2
APERTURE
DELAY
ENCODE
t PD
OUTPUT
DATA
N–1
N+1
N
Figure 2. Timing Diagram
ⴙVREF
R
ⴙ5.0V
ENCODE
ⴙ5.0V
ANALOG
INPUT
R/2
REFMID
R/2
DIGITAL
OUTPUTS
R
ⴚ5.2V
ⴚVREF
256 COMPARATOR
CELLS
Figure 3. Input Output Circuits
DIE LAYOUT AND MECHANICAL INFORMATION
–5.2V
+5.0V
0.1F
0.1F
ONE JUMPER
PER BOARD
–VS
+VS
100⍀
D8 (MSB)
AIN
AD1
AD9012
510⍀
AD2
ENCODE
–VREF
–2.0V
1k⍀
OVERFLOW
D7
D6
D5
D4
D3
VH
D2
+VREF
D11(LSB)
(LSB)
D
DIGITAL
GROUND
ANALOG
GROUND
1k⍀
1k⍀
1k⍀
1k⍀
1k⍀
1k⍀
1k⍀
1k⍀
LOAD
RESISTORS
ALL RESISTORS ⴞ5%
ALL CAPACITORS ⴞ20%
ALL SUPPLY VOLTAGES ⴞ5%
OPTION #1 (STATIC) AD1 = –2.0V; AD2 = +2.4V
OPTION #2 (DYNAMIC) SEE WAVEFORMS
0V
–2V
AD1
640s
Die Dimensions . . . . . 111 mils × 123 mils × 15 mils (± 2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 4 mils × 4 mils
Metallization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –VS
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride
Die Attach . . . . . . . . . . . . . . . . . . . . Gold Eutectic (Ceramic)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Epoxy (Plastic)
Bond Wire . . . . . . . . 1 mil to 1.3 mil Gold; Gold Ball Bonding
REV. F
+2.4V
+0.4V
AD2
5s
Figure 4. Burn-In Diagram
–5–
AD9012
APPLICATION INFORMATION
LAYOUT SUGGESTIONS
The AD9012 is compatible with all standard TTL logic families.
However, to operate at the highest ENCODE rates, the supporting logic around the AD9012 will need to be equally fast.
Two possible choices are the AS and the ALS families. Whichever of the TTL logic families is used, special care must be
exercised to keep digital switching noise away from the analog
circuits around the AD9012. The two most critical items are the
digital supply lines and the digital ground return.
Designs using the AD9012, such as all high speed devices, must
follow a few basic layout rules to ensure optimum performance.
Essentially, these guidelines are meant to avoid many of the
problems associated with high speed designs. The first requirement is for a substantial ground plane around and under the
AD9012. Separate ground plane areas for the digital and analog
components may be useful, but the separate grounds should
be connected together at the AD9012 to avoid the effects of
“ground loop” currents.
The input capacitance of the AD9012 is an exceptionally low
16 pF. This allows the use of a wide range of input amplifiers,
both hybrid and monolithic. To take full advantage of the
160 MHz input bandwidth of the AD9012, a hybrid amplifier such
as the AD9610 will be required. For those applications that do
not require the full input bandwidth of the AD9012, some of the
more traditional monolithic amplifiers, such as the AD846,
should work very well. Overall performance with monolithic
amplifiers can be improved by inserting a 40 Ω resistor in series
with the amplifier output.
The second area that requires an extra degree of attention
involves the three reference inputs, +VREF, REFMID, and –VREF.
The +VREF input and the –VREF input should both be driven
from a low impedance source (note that the +VREF input is
typically tied to analog ground). A low drift amplifier should
provide satisfactory results, even over an extended temperature
range. Adjustments at the REFMID input may be useful in improving the integral linearity by correcting any reference ladder skews.
The reference inputs should be adequately decoupled to ground
through 0.1 µF chip capacitors to limit the effects of system
noise on conversion accuracy. The power supply pins must also
be decoupled to ground to improve noise immunity; 0.1 µF and
0.01 µF chip capacitors should be very effective.
The output data is buffered through the TTL compatible output latches. In addition to the latch propagation delay (tPD), all
data is delayed by one clock cycle before becoming available at
the outputs. Both the analog-to-digital conversion cycle and the
data transfer to the output latches are triggered on the rising edge
of the TTL compatible ENCODE signal (see Figure 2).
The AD9012 also incorporates a HYSTERESIS control pin
that provides from 0 mV to 10 mV of additional hysteresis in the
comparator input stages. Adjustments in the HYSTERESIS
control voltage may help to improve noise immunity and overall
performance in harsh environments.
The OVERFLOW INH pin of the AD9012 determines how the
converter handles overrange inputs (AIN ≥ + VREF). In the
“enabled” state (floating at –5.2 V), the OVERFLOW INH
output will be at logic HIGH and all other outputs will be at
logic LOW for overrange inputs (return-to-zero operation). In
the “inhibited” state (tied to ground), the OVERFLOW INH
output will be at logic LOW for overrange inputs, and all other
digital outputs will be at logic HIGH (nonreturn-to-zero operation).
The AD9012 provides outstanding error rate performance. This
is due to tight control of comparator offset matching and a fault
tolerant decoding stage. Additional improvements in error rate
are possible through the addition of hysteresis (see HYSTERESIS
control pin). This level of performance is extremely important in
fault sensitive applications, such as digital radio (QAM).
The analog input signal is brought into the AD9012 through
two separate input pins. It is very important that the two input
pins be driven symmetrically with equal length electrical
connections. Otherwise, aperture delay errors may degrade
converter performance at high frequencies.
–15V
1k⍀
4k⍀
100⍀
2N3906
0.1F
AD741
ANALOG
INPUT
(0 TO +2V)
10⍀
0.1F
NYQUIST
FILTER
–VREF
1.5k⍀
40⍀
50⍀
AD9611
EQUAL
DISTANCE
AIN
+VREF
OVERFLOW
D8 (MSB)
D7
D6
AIN
AD9012
TTL
ENCODE
INPUT
Dramatic improvements in comparator design and construction
give the AD9012 excellent dynamic characteristics, namely SNR
(signal-to-noise ratio). The 160 MHz input bandwidth and low
error rate performance give the AD9012 an SNR of 47 dB with
a 1.23 MHz input. High SNR performance is particularly important in broadcast video applications where signals may pass
through the converter several times before the processing is
complete. Pulse signature analysis, commonly performed in
advanced radar receivers, is another area that is especially
dependent on high quality dynamic performance.
D5
D4
D3
ENCODE
D2
D1 (LSB)
50⍀
+5.0V
0.01F 0.1F
–5.2V
0.1F
0.01F
Figure 5. Typical Application
–6–
REV. F
AD9012
LINEARITY OUTPUT
(ERROR WAVEFORM)
430⍀
430⍀
50⍀
50⍀
100⍀
AD642
RECONSTRUCTED
OUTPUT
NOTE:
10124, ECL OUTPUTS,
SHOULD BE TERMINATED
TO –2V WITH
100⍀ REGISTERS.
AD642
–5.2V
160⍀
82⍀
2N3906
37.5⍀
2N3906
AD741 10⍀
240⍀ 100⍀ 240⍀
1N747
0.01F
500⍀
AD9768
0.1F
0.1F
–VREF
50⍀
ANALOG
INPUT
(2V p-p MAX)
EQUAL
DISTANCE
100⍀
AD9012
0.1F
D5
LATCH
74AS843
D2
D1 (LSB)
+5.0V –5.2V
CLK
560⍀
–5.2V
0.01F
0.1F
0.1F
0.01F
1k⍀
TTL
ENCODE
INPUT
1k⍀
74AS04
Figure 6. Evaluation Circuit
70
65
SECOND HARMONIC
60
dBc
55
THIRD HARMONIC
50
45
SNR*
40
*WITH HARMONICS
INPUT = 0.1dB BELOW FULL SCALE
ENCODE RATE = 75MSPS
35
30
1
10
ANALOG INPUT FREQUENCY – MHz
Figure 7. Dynamic Performance
REV. F
10124
25 PIN
D
CONNECTOR
D3
OVERFLOW
INH
HYSTERESIS
D6
D4
ENCODE
1k⍀
10124
+VREF
OVERFLOW
D8 (MSB)
D7
AIN
AIN
HOS200
0.1F
REFMID
–7–
100
AD9012
OUTLINE DIMENSIONS
28-Terminal Ceramic Leadless Chip Carrier [LCC]
(E-28A)
Dimensions shown in inches and (millimeters)
0.300 (7.62)
REF
0.075
(1.91)
REF
0.020 (0.51)
MIN
19
26
0.05 (1.27)
0.458
(11.63)
MAX
SQ
0.458 (11.63)
SQ
0.442 (11.23)
0.028 (0.71)
0.022 (0.56)
25
18
BOTTOM
VIEW
0.075 (1.91)
REF
28
1
12
0.15 (3.81)
REF
4
11
5
0.095 (2.41)
0.075 (1.90)
0.055 (1.40)
0.045 (1.14)
0.088 (2.24)
0.054 (1.37)
C00547–0–5/03(F)
0.100 (2.54)
0.064 (1.63)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
28-Lead Ceramic Leaded Chip Carrier – J-Formed Lead [JLCC]
(J-28A)
Dimensions shown in inches and (millimeters)
0.125 (3.18)
MAX
0.040 (1.02)
REF
x 45
3 PLACES
0.460 (11.68)
SQ
0.440 (11.18)
4
26
5
0.035 (0.89)
0.025 (0.64)
0.020 (0.51)
REF
x 45
26
5
PIN 1 INDEX
0.055 (1.40)
PIN 1
0.450 (11.43)
0.410 (10.41)
0.050
(1.27)
4
25
25
0.310 (7.87)
0.290 (7.37)
TOP VIEW
BOTTOM VIEW
0.022 (0.56)
0.012 (0.30)
11
19
19
12
11
18
18
12
0.500 (12.70)
SQ
0.480 (12.19)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
28-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-28)
Dimensions shown in inches and (millimeters)
0.100 (2.54)
MAX
0.005 (0.13)
MIN
28
15
0.610 (15.49)
0.500 (12.70)
PIN 1
1
0.225(5.72)
MAX
14
0.620 (15.75)
0.590 (14.99)
0.015 (0.38)
MIN
1.490 (37.85) MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.026 (0.66)
0.014 (0.36)
0.100
(2.54)
BSC
0.070 (1.78) SEATING
0.030 (0.76) PLANE
15
0
0.018 (0.46)
0.008 (0.20)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Revision History
Location
Page
5/03—Data Sheet changed from REV. E to REV. F.
Changes to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
–8–
REV. F
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