AD9022BZ

a FEATURES Monolithic 12-Bit 20 MSPS A/D Converter Low Power Dissipation: 1.4 Watts On-Chip T/H and Reference High Spurious-Free Dynamic Range TTL Logic APPLICATIONS Radar Receivers Digital Communications Digital Instrumentation Electro-Optics FUNCTIONAL BLOCK DIAGRAM ANALOG INPUT T/H 5-BIT ADC DIGITAL 12 ERROR CORRECTION TTL 5-BIT ADC DAC ENCODE T/H OBS PRODUCT DESCRIPTION 12-Bit 20 MSPS Monolithic A/D Converter AD9022 +2V REF 16 DAC 8 4-BIT ADC +5V –5.2V GND OLE The AD9022 is a high speed, high performance, monolithic 12bit analog-to-digital converter. All necessary functions, including track-and-hold (T/H) and reference, are included on chip to provide a complete conversion solution. It is a companion unit to the AD9023; the primary difference between the two is that all logic for the AD9022 is TTL compatible, while the AD9023 utilizes ECL logic for digital inputs and outputs. Pinouts for the two parts are nearly identical. Operating from +5 V and –5.2 V supplies, the AD9022 provides excellent dynamic performance. Sampling at 20 Msps with AIN = 1 MHz, the spurious-free dynamic range (SFDR) is typically 76 dB; with AIN = 9.6 MHz, SFDR is 74 dB. SNR is typically 65 dB. The on-board T/H has a 110 MHz bandwidth and, more importantly, is designed to provide excellent dynamic performance for analog input frequencies above Nyquist. This feature is necessary in many under-sampling signal processing applications, such as in direct IF-to-digital conversion. With DNL typically less than 0.5 LSB and 20 ns transient response settling time, the AD9022 provides excellent results when low-frequency analog inputs must be oversampled (such as CCD digitization). The full scale analog input is ± 1 V with a 300 Ω input impedance. The analog input can be driven directly from the signal source, or can be buffered by the AD96xx series of low noise, low distortion buffer amplifiers. TE All timing is internal to the AD9022; the clock signal initiates the conversion cycle. For best results, the encode command should contain as little jitter as possible. High speed layout practices must be followed to ensure optimum A/D performance. The AD9022 is built on a trench isolated bipolar process and utilizes an innovative multipass architecture (see the block diagram). The unit is packaged in 28-pin ceramic DIPs and gullwing surface mount packages. The AD9022 is specified to operate over the industrial (–25°C to +85°C) and military (–55°C to +125°C) temperature ranges. To maintain dynamic performance at higher IFs, monolithic RF track-and-holds (such as the AD9100 and AD9101 Samplifier™) can be used with the AD9022 to process signals up to and beyond 70 MHz. Samplifier is a trademark of Analog Devices, Inc. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD9022–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (+V = +5 V; –V = –5.2 V; Encode = 20 MSPS, unless otherwise noted) S Parameter (Conditions) Temp Test Level RESOLUTION DC ACCURACY Differential Nonlinearity S AD9022AQ/AZ Min Typ Max AD9022BQ/BZ Min Typ Max AD9022SQ/SZ Min Typ Max Units 12 12 12 Bits +25°C Full +25°C Full Full +25°C Full +25°C Full +25°C I VI I VI VI I VI I VI V ANALOG INPUT Input Voltage Range Input Resistance Input Capacitance Analog Bandwidth Full +25°C +25°C IV V V 240 SWITCHING PERFORMANCE 1 Minimum Conversion Rate Maximum Conversion Rate Aperture Delay (tA) Aperture Uncertainty (Jitter) Output Delay (tOD) +25°C Full +25°C +25°C Full IV VI IV V VI 4 20 0.55 0.71 0.85 6 15 27.5 ENCODE INPUT Logic Compatibility Logic “1” Voltage Logic “0” Voltage Logic “1” Current Logic “0” Current Input Capacitance Pulse Width (High) Pulse Width (Low) Full Full Full Full +25°C +25°C +25°C VI VI VI VI V IV IV 2.0 +25°C +25°C V V +25°C Full +25°C +25°C Full I V V I V 65 +25°C Full +25°C +25°C Full I V V I V 62 +25°C Full +25°C +25°C Full I V V I V 63 Integral Nonlinearity No Missing Codes Offset Error Gain Error Thermal Noise OBS DYNAMIC PERFORMANCE Transient Response Overvoltage Recovery Time Harmonic Distortion Analog Input @ 1.2 MHz @ 1.2 MHz @ 4.3 MHz @ 9.6 MHz @ 9.6 MHz Signal-to-Noise Ratio2 Analog Input @ 1.2 MHz @ 1.2 MHz @ 4.3 MHz @ 9.6 MHz @ 9.6 MHz Signal-to-Noise Ratio2 (Without Harmonics) Analog Input @ 1.2 MHz @ 1.2 MHz @ 4.3 MHz @ 9.6 MHz @ 9.6 MHz 0.6 0.75 1.0 1.3 2.5 1.6 3.0 Guaranteed 5 25 15 35 0.5 2.5 0.6 3.5 0.57 ± 1.024 300 360 5 110 0.4 0.5 1.0 1.3 2.0 1.6 3.0 Guaranteed 5 25 15 35 0.5 2.5 0.6 3.5 0.57 240 ± 1.024 300 360 5 110 OLE 4 20 0.55 0.71 0.85 6 15 27.5 TTL TTL 2.0 8 8 6 22.5 20 0.8 20 20 125 125 8 8 6 22.5 20 20 20 63 61 62 0.75 1.0 1.3 2.5 1.6 3.0 Guaranteed 5 25 15 35 0.5 2.5 0.6 3.5 0.57 240 70 64 63 64 63 62 64 66 64 66 65 63 65 69 63 64 ± 1.024 300 360 5 110 4 20 0.55 0.71 0.85 6 15 27.5 LSB LSB LSB LSB mV mV % FS % FS LSB, rms V Ω pF MHz Msps Msps ns ps, rms ns TE TTL 2.0 0.8 20 20 125 125 8 8 6 22.5 20 20 20 73 70 73 72 68 –2– 0.6 75 72 75 74 72 65 66 65 66 65 63 62 67 66 66 66 65 63 63 61 62 0.8 20 20 125 125 V V µA µA pF ns ns 20 20 ns ns 73 70 73 72 68 dBc dBc dBc dBc dBc 64 63 64 63 62 dB dB dB dB dB 66 64 66 65 63 dB dB dB dB dB REV. A AD9022 Parameter (Conditions) Two-Tone Intermodulation Distortion Rejection3 DIGITAL OUTPUTS1 Logic Compatibility Logic “1” Voltage Logic “0” Voltage Output Coding Temp Test Level AD9022AQ/AZ Min Typ Max +25°C V Full Full VI VI 2.4 Full Full Full Full Full VI VI VI VI VI 4.75 5.0 100 –5.45 –5.2 180 1.4 AD9022BQ/BZ Min Typ Max 74 74 TTL POWER SUPPLY +VS Supply Voltage +VS Supply Current –VS Supply Voltage –VS Supply Current Power Dissipation Power Supply Rejection Ratio (PSRR)4 OBS Full 74 TTL 0.5 Offset Binary 0.5 Offset Binary 32 dBc 2.4 5.25 4.75 5.0 120 100 –4.95 –5.45 –5.2 220 180 1.9 1.4 Units TTL 2.4 V AD9022SQ/SZ Min Typ Max 5.25 120 –4.95 220 1.9 0.5 Offset Binary 4.75 5.0 100 –5.45 –5.2 180 1.4 32 5.25 120 –4.95 220 1.9 32 V V mA mA mA mA W mV/V NOTES 1 AD9022 load is a single LS latch. 2 RMS signal-to-rms noise with analog input signal 1 dB below full scale at specified frequency. Tested at 55% duty cycle. 3 Intermodulation measured with analog input frequencies of 8.9 MHz and 9.8 MHz at 7 dB below full scale. 4 PSRR is sensitivity of offset error to power supply variations within the 5% limits shown. Specifications subject to change without notice. ANALOG IN ENCODE OLE N ta N+1 ta = 0.7 TYPICAL tOD tOD = 15–27.5 TYPICAL DATA OUTPUT N–3 N–2 N–1 TE N+2 N AD9022 Timing Diagram ORDERING GUIDE ABSOLUTE MAXIMUM RATINGS 1 +VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V –VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–6 V Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–VS to +VS Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +VS to 0 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature Range AD9022AQ/AZ/BQ/BZ . . . . . . . . . . . . . . . –25°C to +85°C AD9022SQ/SZ . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C Maximum Junction Temperature2 . . . . . . . . . . . . . . . . +175°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Model NOTES 1 Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Typical thermal impedances: “Q” Package (Ceramic DIP): θJC = 10°C/W; θJA = 35°C/W. “Z” Package (Gullwing Surface Mount): θJC = 13°C/W; θJA = 45°C/W. REV.A –3– Temperature Range Package Description 28-Pin Ceramic DIP 28-Pin Ceramic Leaded Chip Carrier –55°C to +125°C 28-Pin Ceramic DIP –55°C to +125°C 28-Pin Ceramic Leaded Chip Carrier Package Option AD9022AQ/BQ –25°C to +85°C AD9022AZ/BZ –25°C to +85°C Q-28 Z-28 AD9022SQ AD9022SZ Q-28 Z-28 AD9022 PIN DESCRIPTIONS EXPLANATION OF TEST LEVELS Test Level I – 100% production tested. II – 100% production tested at +25°C, and sample tested at specified temperatures. AC testing done on sample basis. III – Sample tested only. IV – Parameter is guaranteed by design and characterization testing. V – Parameter is a typical value only. VI – All devices are 100% production tested at +25°C. 100% production tested at temperature extremes for extended temperature devices; guaranteed by design and characterization testing for industrial devices. OBS DIE LAYOUT AND MECHANICAL INFORMATION Name Function 1–3 D3–D1 Digital output bits of ADC; TTL compatible. 4 D0 (LSB) Least significant bit of ADC output; TTL compatible. 5 NC No Connection Internally 6 +VS +5 V Power Supply 7 GND Ground 8 ENCODE Encode clock input to ADC. Internal T/H is placed in hold mode (ADC is encoding) on rising edge of encode signal. 9 GND Ground 10 +VS +5 V Power Supply 11 GND Ground 12 AIN Noninverting input to T/H amplifier. 13 –VS –5.2 V Power Supply 14 +VS +5 V Power Supply 15 –VS –5.2 V Power Supply 16 GND Ground 17 COMP 18 D11 (MSB) Most significant bit of ADC output; TTL compatible. 19–25 D10–D4 Digital output bits of ADC; TTL compatible. 26 +VS +5 V Power Supply 27 –VS TE 28 GND ANALOG INPUT –V S +VS –VS OLE GND COMPENSATION Die Dimensions . . . . . . . . . . . . . . . . 205 × 228 × 21 (± 1) mils Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 × 4 mils Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –VS Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4,080 Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oxynitride Bond Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum Pin No. Should be connected to –V S through 0.1 µF capacitor. –5.2 V Power Supply Ground GND D11 (MSB) +VS D10 PIN DESIGNATIONS GND D9 ENCODE D8 D7 GND ENCODE D6 D5 D0 (LSB) D1 D2 D3 GND –VS +VS D4 D3 1 28 GND D2 2 27 –V S D1 3 26 +VS D0 (LSB) 4 25 D4 NC 5 24 D5 +V S 6 23 D6 GND 7 22 D7 ENCODE 8 TOP VIEW (Not to Scale) 21 D8 GND 9 20 D9 AD9022 +VS 10 19 D10 GND 11 18 D11 (MSB) AIN 12 17 COMP –V S 13 16 GND +V S 14 15 –V S NC = NO CONNECT COMPENSATION (PIN 17) SHOULD BE CONNECTED TO –VS THROUGH 0.01µF –4– REV. A AD9022 DEFINITIONS OF SPECIFICATIONS +VS Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB. +VS Aperture Delay The delay between the rising edge of the ENCODE command and the instant at which the analog input is sampled. 180 ANALOG INPUT 10pF Aperture Uncertainty (Jitter) 120 The sample-to-sample variation in aperture delay. Differential Nonlinearity –V S The deviation of any code from an ideal 1 LSB step. Harmonic Distortion The rms value of the fundamental divided by the rms value of the worst harmonic component. Analog Input OBS Integral Nonlinearity +VS The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a “best straight line” determined by a least square curve fit. Minimum Conversion Rate 100 ENCODE OLE 900 The encode rate at which the SNR of the lowest analog signal frequency tested drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate TE The encode rate at which parametric testing is performed. Output Propagation Delay COMPENSATION The delay between the 50% point of the rising edge of the ENCODE command and the time when all output data bits are within valid logic levels. Overvoltage Recovery Time –VS Encode Input The amount of time required for the converter to recover to 12-bit accuracy after an analog input signal 150% of full scale is reduced to the full-scale range of the converter. 50 –VS 20pF Power Supply Rejection Ratio (PSRR) The ratio of a change in input offset voltage to a change in power supply voltage. –V S Compensation Signal-to-Noise Ratio (SNR) The ratio of the rms signal amplitude to the rms value of “noise,” which is defined as the sum of all other spectral components, including harmonics but excluding dc, with an analog input signal 1 dB below full scale. +V S 12k 11k Signal-to-Noise Ratio (Without Harmonics) The ratio of the rms signal amplitude to the rms value of “noise,” which is defined as the sum of all other spectral components, excluding the first five harmonics and dc, with an analog input signal 1 dB below full scale. DIGITAL OUTPUT Transient Response The time required for the converter to achieve 12-bit accuracy when a step function is applied to the analog input. –VS Two-Tone Intermodulation Distortion (IMD) Rejection Output Stage The ratio of the power of either of two input signals to the power of the strongest third-order IMD signal. Figure 1. Equivalent Circuits REV. A –5– AD9022–Typical Characteristics 70 WORST CASE HARMONIC DISTORTION – dBc –76 –75 +25°C 65 +25°C ROOM –74 60 –55°C SNR – dB –73 –55°C –72 55 50 +125°C –71 45 –70 +125°C 40 –69 35 1.24 2.3 –68 0 1 2 3 4 5 6 7 8 9 10 ANALOG INPUT FREQUENCY – MHz 7.3 OBS 80 80 SNR 65 50 40 30 10 55 5 7.5 10 12.5 15 17.5 19.3 20 22.5 0 –50 25 SFDR 60 20 60 17.3 70 SFDR AND SNR – dB 70 15.3 AIN = 1.2MHz ENCODE = 20MHz WORST HARMONICS 75 13.3 90 OLE AIN = 1.2MHz 11.3 Figure 5. Signal-to-Noise Ratio vs. Analog Input Frequency 85 –45 –40 ENCODE RATE – MSPS TE –35 SNR –30 –25 –20 –15 –10 –5 –1 INPUT LEVEL – dB Figure 3. SNR and Harmonics vs. Encode Rate Figure 6. SFDR and SNR vs. Analog Input Level 80 2.0 AIN = 1.2MHz FS = 20MSPS 1.5 70 SFDR AIN = 9.6MHz ENCODE = 20MHz 60 1.0 SFDR AND SNR – dB DIFFERENTIAL NONLINEARITY – LSBs 9.6 ANALOG INPUT FREQUENCY – MHz Figure 2. Harmonic Distortion vs. Analog Input Frequency HARMONICS AND SNR – dB 5.3 0.5 0 –0.5 50 SNR 40 30 –1.0 20 –1.5 10 0 –2.0 1024 2048 3072 4096 –50 OUTPUT CODE –45 –40 –35 –30 –25 –20 –15 –10 –5 –1 INPUT LEVEL – dB Figure 4. Differential Nonlinearity vs. Output Code Figure 7. SFDR and SNR vs. Analog Input Level –6– REV. A AD9022 0 –10 –20 –30 FULL SCALE – dB track-and-hold (T/H). The T/H holds whatever analog value is present when the unit is strobed with an ENCODE command. The conversion process begins on the rising edge of this pulse, which should conform to the minimum and maximum pulse width requirements shown in the specifications. Operation below the recommended encode rate (4 Msps) may result in excessive droop in the internal T/H devices–leading to large dc and ac errors. AIN = 1.2MHz AIN = –1.0dBFS SNR = 66.7dB THD = 77.51dB SFDR = 79.49dBFS –40 –50 –60 The held analog value of the first track-and-hold is applied to a 5-bit flash converter and a second T/H. The 5-bit flash converter resolves the most significant bits (MSBs) of the held analog voltage. These 5 bits are reconstructed via a 5-bit DAC and subtracted from the original T/H output signal to form a residue signal. –70 –80 –90 –100 0 10 FREQUENCY – MHz A second T/H holds the amplified residue signal while it is encoded with a second 5-bit flash ADC. Again the 5 bits are reconstructed and subtracted from the second T/H output to form a residue signal. This residue is amplified and encoded with a 4bit flash ADC to provide the 3 least significant bits (LSBs) of the digital output and one bit of error correction. Figure 8. FFT Plot OBS 0 AIN = 9.6MHz AIN = –1.0dBFS SNR = 66.05dB THD = 74.28dB SFDR = 75.32dBFS –10 –20 FULL SCALE – dB –30 –40 –50 –60 –70 –80 –90 –100 0 Digital Error Correction logic aligns the data from the three flash converters and presents the result as a 12-bit parallel digital word. The output stage of the AD9022 is TTL. Output data may be strobed on the rising edge of the ENCODE command. OLE AD9022 IN RECEIVER APPLICATIONS TE Advances in semiconductor processes have resulted in low cost digital signal processing (DSP) and analog signal processing which can help create cost effective alternative receiver designs. Today, an all-digital receiver allows tuning, demodulation, and detection of receiver signals in the digital domain. By digitizing IF signals directly and utilizing digital techniques, it becomes possible to make significant improvements in receiver design. For high frequency IFs, the ADC is the key to the receiver’s performance. Unfortunately, the specifications frequently used by receiver designers and analog-to-digital (ADC) manufacturers are often very different. Noise Figure and Intercept Point are common measures of noise and linearity in analog RF system design. ADCs are more frequently specified in terms of SNR and harmonic distortion. 10 FREQUENCY – MHz Figure 9. FFT Plot 0 FULL SCALE – dB 20 AIN1 = 8.9MHz AIN2 = 9.8MHz AIN1 = 7.0dBFS AIN2 = 7.0dBFS SFDR = 80.62dBFS 40 Noise Noise figure (NF) is a measure of receiver sensitivity and is defined as the degradation of signal-to-noise ratio (SNR) as a signal passes through a device. In equation form: 60 80 NF = SNR (in) – SNR (out) 100 Noise figure is a bandwidth invariant parameter for reasonably narrow bandwidths in most devices. The system noise figure for a combination of amplifiers and mixers, for instance, can be analyzed without regard to the information bandwidth. 120 0.0 2.0 4.0 6.0 FREQUENCY – MHz 8.0 10.0 Thermal noise contribution from the ADC behaves in a similar fashion; however, the spectral density of quantization noise is a function of the sample rate. In addition, the spectral density of the quantization noise is flat only in an ADC with perfect linearity, i.e., perfect 1 LSB step sizes. Figure 10. Two Tone FFT THEORY OF OPERATION Refer to the block diagram. The AD9022 employs a three-pass subranging architecture and digital error correction. This combination of design techniques ensures 12-bit accuracy at relatively low power. Analog input signals are immediately attenuated through a resistor divider and applied directly to the sampling bridge of the REV. A To analyze the system noise performance, ADC noise figure is calculated by normalizing the SNR of the ADC output to a 1 Hz bandwidth. This result is given by: SNR (/Hz) = SNR + 10 log10 (Fs/2) where Fs is the sample rate. –7– AD9022 This will be true only for converters in which perfect quantization noise dominates. There may be an upper sample rate, above which the thermal noise of the converter is the dominant source of noise. In this case, normalization would be based on the noise bandwidth of the ADC. For an AD9022 with a typical SNR of 64 dB and a sample rate of 20 Msps, the normalized SNR is equal to 134 dB (64 + 70). Both thermal and quantization noise contribute to this number. AD9022 NOISE PERFORMANCE High speed, wide bandwidth ADCs such as the AD9022 are optimized for dynamic performance over a wide range of analog input frequencies. However, there are many applications (Imaging, Instrumentation, etc.) where dc precision is also important. Due to the wide input bandwidth of the AD9022 for a given input voltage, there will be a range of output codes which may occur. This is caused by unavoidable circuit noise within the wideband circuits in the ADC. If a dc signal is applied to the ADC and several thousand outputs are recorded, a distribution of codes such as that shown in the histogram below may result. The SNR of the input is assumed to be limited by the thermal noise of the input resistance, or –174 dBm/Hz. The input signal level is +10 dBm (2 V p-p into 50 Ω). Noise figure of the ADC can be calculated by: WORST CASE HARMONIC DISTORTION – dBc –76 NF = SNR (in) – SNR (out) = [+10 – (174)] – 134 = 50 dB Most ADCs detect input voltage levels, not power. Consequently, the input SNR can be determined more accurately by determining the ratio of the signal voltage to the noise voltage of the terminating resistor. However, both the input signal and noise voltage delivered to the ADC are also a function of the source impedance. The dependence of NF on sample rate, linearity, source and terminating impedances, and the number of assumptions that are required highlight the weakness of using NF as a figure of merit for an ADC. The rather large number that results bolsters this belief by indicating the ADC is often the weakest link in the signal processing path. OBS Linearity –75 +25°C ROOM –74 –73 –55°C –72 –71 –70 OLE +125°C –69 –68 0 1 2 3 4 5 6 7 8 9 10 ANALOG INPUT FREQUENCY – MHz TE The Third Order intercept point for a linear device (with some nonlinearity) is a good way to predict 3rd order spurious signals as a function of input signal level. For an ADC, however, this in an invalid concept except with signals near full scale. As the input signal is reduced, the performance burden shifts from the input track-and-hold (T/H) to the encoder. This creates a nonlinear function, as contrasted with the third order intercept behavior, which predicts an improvement in dynamic range as the signal level is decreased. Figure 11. ADC Equivalent Input Noise The correct code appears most of the time, but adjacent codes also appear with reduced probability. If a normal probability density curve is fitted to this Gaussian distribution of codes, the standard deviation will be equal to the equivalent input rms noise of the ADC. The rms noise may also be approximated by converting the SNR, as measured by a low frequency FFT, to an equivalent input noise. This method is accurate only if the SNR performance is dominated by random thermal noise (the low frequency SNR without harmonics is the best measure). Sixty-three dB equates to 1 LSB rms for a 2 V p-p (0.707 V rms) input signal. The AD9022 has approximately 0.5 LSB of rms noise or a noise limited SNR of 69 dB, indicating that noise alone does not limit the SNR performance of the device (quantization noise and linearity are also major contributors). For signals near full scale, the intercept point is calculated the same as any device: Intercept Point = [Harmonic Suppression/(N –1)] + Input Power where N = the order of the IMD (3 in this case) AD9022 Intercept Point = 80/2 + 3 dBm (7 dBm below full scale) = 43 dBm For signals below this level, the spurious free dynamic range (SFDR) curves shown in the data sheet are a more accurate predictor of dynamic range. The SFDR curve is generated by measuring the ratio of the signal (either tone in the two-tone measurement) to the worst spurious signal which is observed as the analog input signal amplitude is swept. This thermal noise may come from several sources. The drive source impedance should be kept low to minimize resistor thermal noise. Some of the internal ADC noise is generated in the wideband T/H. Sampling ADCs generally have input bandwidths which exceed the Nyquist frequency of one-half the sampling rate. (The AD9022 has an input bandwidth of over 100 MHz, even though the sampling rate is limited to 20 Msps.) The worst spurious signal is usually the second harmonic or 3rd order IMD. Actual results are shown on several plots. The straightline with a slope of one is constructed at the point where the worst SFDR touches the line. This line, extrapolated to full scale, gives the SFDR of the ADC. This value can then be used to predict the dynamic range by simply subtracting the input level from the SFDR. Wide bandwidth is required to minimize gain and phase distortion and to permit adequate settling times in the internal amplifiers and T/Hs. But a certain amount of unavoidable noise is generated in the T/H and other wideband circuits within the ADC; this causes variation in output codes for dc inputs. Good layout, grounding, and decoupling techniques are essential to prevent external noise from coupling into the ADC and further corrupting performance. It should be noted that all SFDR lines are constructed to be valid only below a certain level below full scale. Above these points, the linearity of the device is dominated by the nonlinearities of the front end and best predicted by the intercept point. –8– REV. A AD9022 The duty cycle of the encode clock for the AD9022 is critical for obtaining rated performance of the ADC. Internal pulse widths within the track-and-hold are established by the encode command pulse width; to ensure rated performance, minimum and maximum pulse width restrictions should be observed. Operation at 20 Msps is optimized when the duty cycle is held at 55%. USING THE AD9022 Layout Information Preserving the accuracy and dynamic performance of the AD9022 requires that designers pay special attention to the layout of the printed circuit board. Analog paths should be kept as short as possible and be properly terminated to avoid reflections. The analog input connection should be kept away from digital signals paths; this reduces the amount of digital switching noise which is capacitively coupled into the analog section. Digital signal paths should also be kept short, and run lengths should be matched to avoid propagation delay mismatch. The AD9022 digital outputs should be buffered or latched close to the device (