AD9122

Dual, 16-Bit, 1200 MSPS, TxDAC+® Digital-to-Analog Converter AD9122 FEATURES Flexible LVDS interface allows word, byte, or nibble load Single-carrier W-CDMA ACLR = 82 dBc @ 122.88 MHz IF Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 Ω to 50 Ω Novel 2×/4×/8× interpolator/complex modulator allows carrier placement anywhere in the DAC bandwidth Digital gain and phase adjustment for sideband suppression Multiple chip synchronization interfaces High performance, low noise PLL clock multiplier Digital inverse sinc filter Flexible LVDS interface allows word, byte, or nibble load Low power: 1.5 W @ 1.2 GSPS, 800 mW @ 500 MSPS, full operating conditions 72-lead, exposed paddle LFCSP GENERAL DESCRIPTION The AD9122 is a dual 16-bit, high dynamic range, digital-toanalog converter (DAC) that provides a sample rate of 1200 MSPS, permitting a multicarrier generation up to the Nyquist frequency. It includes features optimized for direct conversion transmit applications, including complex digital modulation, and gain and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x F-MOD series from Analog Devices, Inc. A 4-wire serial port interface provides for programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 8.7 mA to 31.7 mA. The AD9122 comes in a 72-lead LFCSP. PRODUCT HIGHLIGHTS 1. Ultralow noise and intermodulation distortion (IMD) enable high quality synthesis of wideband signals from baseband to high intermediate frequencies. A proprietary DAC output switching technique enhances dynamic performance. The current outputs are easily configured for various single-ended or differential circuit topologies. Flexible LVDS digital interface allows the standard 32-wire bus to be reduced to ½ or ¼ of the width. APPLICATIONS Wireless infrastructure W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTE Digital high or low IF synthesis Transmit diversity Wideband communications: LMDS/MMDS, point-to-point 2. 3. 4. TYPICAL SIGNAL CHAIN COMPLEX BASEBAND COMPLEX IF RF DC fIF LO – fIF 2 2/4 I DAC ANTIALIASING FILTER AQM PA DIGITAL BASEBAND PROCESSOR 2 SIN COS 2/4 Q DAC LO 08281-001 NOTES 1. AQM = ANALOG QUADRATURE MODULATOR. Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. AD9122 TABLE OF CONTENTS Features .............................................................................................. 1  Applications ....................................................................................... 1  General Description ......................................................................... 1  Product Highlights ........................................................................... 1  Typical Signal Chain......................................................................... 1  Revision History ............................................................................... 2  Functional Block Diagram .............................................................. 3  Specifications..................................................................................... 4  DC Specifications ......................................................................... 4  Digital Specifications ................................................................... 5  Digital Input Data Timing Specifications ................................. 5  AC Specifications.......................................................................... 6  Absolute Maximum Ratings............................................................ 7  Thermal Resistance ...................................................................... 7  ESD Caution .................................................................................. 7  Pin Configuration and Function Descriptions ............................. 8  Typical Performance Characteristics ........................................... 10  Terminology .................................................................................... 16  Theory of Operation ...................................................................... 17  Serial Port Operation ................................................................. 17  Data Format ................................................................................ 17  Serial Port Pin Descriptions ...................................................... 17  Serial Port Options ..................................................................... 18  Device Configuration Register Map and Descriptions ......... 19  LVDS Input Data Ports .................................................................. 31  Word Interface Mode ................................................................. 31  Byte Interface Mode ................................................................... 31  Nibble Interface Mode ............................................................... 31  FIFO Operation .......................................................................... 31  Interface Timing ......................................................................... 33  Digital Datapath.............................................................................. 34  Premodulation ............................................................................ 34  Interpolation Filters ................................................................... 34  NCO Modulation ....................................................................... 37  Datapath Configuration ............................................................ 37  Determining Interpolation Filter Modes ................................ 38  Datapath Configuration Example ............................................ 39  Data Rates vs. Interpolation Modes ......................................... 40  Coarse Modulation Mixing Sequences.................................... 40  Quadrature Phase Correction................................................... 41  DC Offset Correction ................................................................ 41  Inverse Sinc Filter ....................................................................... 41  DAC Input Clock Configurations ................................................ 42  DAC Input Clock Configurations ............................................ 42  Analog Outputs............................................................................... 44  Transmit DAC Operation.......................................................... 44  Auxiliary DAC Operation ......................................................... 45  Baseband Filter Implementation .............................................. 46  Driving the ADL5375-15 .......................................................... 46  Reducing LO Leakage and Unwanted Sidebands .................. 47  Device Power Dissipation.............................................................. 48  Temperature Sensor ................................................................... 49  Multichip Synchronization............................................................ 50  Synchronization with Clock Multiplication ............................... 50  Synchronization with Direct Clocking .................................... 51  Data Rate Mode Synchronization ............................................ 51  FIFO Rate Mode Synchronization ........................................... 52  Additional Synchronization Features ...................................... 52  Interrupt Request Operation ........................................................ 54  Interrupt Service Routine .......................................................... 54  Interface Timing Validation .......................................................... 55  SED Operation............................................................................ 55  SED Example .............................................................................. 55  Outline Dimensions ....................................................................... 56  Ordering Guide .......................................................................... 56  REVISION HISTORY 9/09—Revision 0: Initial Version Rev. 0 | Page 2 of 56 AD9122 FUNCTIONAL BLOCK DIAGRAM 16 1.2G DAC 1 AUX 16-BIT IOUT1P IOUT1N DATA RECEIVER D15P—D15N 16 FIFO fDATA /2 PRE MOD HB1 NCO AND MOD HB2 HB3 10 I OFFSET Q OFFSET 16 16 PHASE CORRECTION INVSINC_CLK 1.2G DAC 1 AUX 16-BIT INV SINC DAC CLK D0P—D0N DCI FRAME IOUT2P IOUT2N GAIN 1 HB1_CLK HB2_CLK HB3_CLK INTP FACTOR MODE GAIN 2 10 10 REF AND BIAS REFIO FSADJ INTERNAL CLOCK TIMING AND CONTROL LOGIC DAC CLK_SEL PLL CONTROL PROGRAMMING REGISTERS SERIAL INPUT/OUTPUT PORT POWER-ON RESET MULTICHIP SYNCHRONIZATION SYNC DAC_CLK 0 1 PLL_LOCK CLOCK MULTIPLIER (2× TO 16×) CLK RCVR CLK RCVR DACCLKP DACCLKN REFCLKP REFCLKN SDIO IRQ CS RESET SDO SCLK Figure 2. AD9122 Functional Block Diagram Rev. 0 | Page 3 of 56 08281-002 AD9122 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 =1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY Differential Nonlinearity (DNL) Integral Nonlinearity (INL) MAIN DAC OUTPUTS Offset Error Gain Error (with Internal Reference) Full-Scale Output Current 1 Output Compliance Range Output Resistance Gain DAC Monotonicity Settling Time to Within ±0.5 LSB MAIN DAC TEMPERATURE DRIFT Offset Gain Reference Voltage REFERENCE Internal Reference Voltage Output Resistance ANALOG SUPPLY VOLTAGES AVDD33 CVDD18 DIGITAL SUPPLY VOLTAGES DVDD18 IOVDD POWER CONSUMPTION 2× Mode, fDAC = 491.22 MSPS, IF = 10 MHz, PLL Off 2× Mode, fDAC = 491.22 MSPS, IF = 10 MHz, PLL On 8× Mode, fDAC = 800 MSPS, IF = 10 MHz, PLL Off AVDD33 CVDD18 DVDD18 Power-Down Mode Power Supply Rejection Ratio, AVDD33 OPERATING RANGE 1 Min Typ 16 ±2.1 ±3.7 Max Unit Bits LSB LSB −0.001 −3.6 8.66 −1.0 0 ±2 19.6 10 Guaranteed 20 0.04 100 30 1.2 5 +0.001 +3.6 31.66 +1.0 % FSR % FSR mA V MΩ ns ppm/°C ppm/°C ppm/°C V kΩ 3.13 1.71 1.71 1.71 3.3 1.8 1.8 1.8/2.5 834 913 1135 55 85 444 2.5 3.47 1.89 1.89 2.94 V V V V mW mW mW mA mA mA mW % FSR/V °C −0.3 −40 +25 1241 57 90 495 9.8 +0.3 +85 Based on a 10 kΩ external resistor. Rev. 0 | Page 4 of 56 AD9122 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD33 = 1.8 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 2. Parameter CMOS INPUT LOGIC LEVEL Input VIN Logic High (IOVDD = 1.8 V) Input VIN Logic High (IOVDD = 2.5 V) Input VIN Logic Low (IOVDD = 1.8 V) Input VIN Logic Low (IOVDD = 2.5 V) CMOS OUTPUT LOGIC LEVEL Output VOUT Logic High Output VOUT Logic High Output VOUT Logic Low Output VOUT Logic Low LVDS RECEIVER INPUTS 1 Input Voltage Range, VIA or VIB Input Differential Threshold, VIDTH Input Differential Hysteresis, VIDTHH to VIDTHL Receiver Differential Input Impedance, RIN LVDS Input Rate DAC CLOCK INPUT (DACCLKP, DACCLKN) Differential Peak-to-Peak Voltage Common-Mode Voltage Maximum Clock Rate REFCLK INPUT (REFCLKP, REFCLKN) Differential Peak-to-Peak Voltage Common-Mode Voltage REFCLK Frequency (PLL Mode) REFCLK Frequency (SYNC Mode) SERIAL PERIPHERAL INTERFACE Maximum Clock Rate (SCLK) Minimum Pulse Width High (tPWH) Minimum Pulse Width Low (tPWOL) Setup Time, SDI to SCLK (tDS) Hold Time, SDI to SCLK (tDH) Data Valid, SDO to SCLK (tDV) Setup Time, CS to SCLK (tDCSB) 1 Conditions Min 1.2 1.6 Typ Max Unit V V V V V V V V mV mV mV Ω 0.6 0.8 IOVDD = 1.8 V IOVDD = 2.5 V IOVDD = 1.8 V IOVDD = 2.5 V 1.4 1.8 0.4 0.4 825 −100 20 80 See Table 5 100 Self biased input, ac couple 1200 100 1 GHz ≤ fVCO ≤ 26 Hz See Multichip Synchronization section for conditions 15.625 0 40 12.5 12.5 1.9 0.2 23 1.4 500 1.25 2000 600 600 500 1.25 2000 120 1575 +100 mV V MSPS mV V MHz MHz MHz ns ns ns ns ns ns LVDS receiver is compliant to the IEEE 1596 reduced range link, unless otherwise noted. DIGITAL INPUT DATA TIMING SPECIFICATIONS Table 3. Parameter LATENCY (DACCLK Cycles) 1× Interpolation (With or Without Modulation) 2× Interpolation (With or Without Modulation) 4× Interpolation (With or Without Modulation) 8× Interpolation (With or Without Modulation) Inverse Sinc Fine Modulation Power-Up Time Rev. 0 | Page 5 of 56 Min Typ 64 135 292 608 20 8 260 Max Unit Cycles Cycles Cycles Cycles Cycles Cycles ms AD9122 AC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 4. Parameter SPURIOUS-FREE DYNAMIC RANGE (SFDR) fDAC = 100 MSPS, fOUT = 20 MHz fDAC = 200 MSPS, fOUT = 50 MHz fDAC = 400 MSPS, fOUT = 70 MHz fDAC = 800 MSPS, fOUT = 70 MHz T WO-TONE INTERMODULATION DISTORTION (IMD) fDAC = 200 MSPS, fOUT = 50 MHz fDAC = 400 MSPS, fOUT = 60 MHz fDAC = 400 MSPS, fOUT = 80 MHz fDAC = 800 MSPS, fOUT = 100 MHz NOISE SPECTRAL DENSITY (NSD) EIGHT-TONE, 500 kHz TONE SPACING fDAC = 200 MSPS, fOUT = 80 MHz fDAC = 400 MSPS, fOUT = 80 MHz fDAC = 800 MSPS, fOUT = 80 MHz W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER fDAC = 491.52 MSPS, fOUT = 10 MHz fDAC = 491.52 MSPS, fOUT = 122.88 MHz fDAC = 983.04 MSPS, fOUT = 122.88 MHz W-CDMA SECOND ACLR, SINGLE CARRIER fDAC = 491.52 MSPS, fOUT = 10 MHz fDAC = 491.52 MSPS, fOUT = 122.88 MHz fDAC = 983.04 MSPS, fOUT = 122.88 MHz Min Typ 78 80 69 72 84 86 84 81 −162 −163 −164 84 82 83 88 86 88 Max Unit dBc dBc dBc dBc dBc dBc dBc dBc dBm/Hz dBm/Hz dBm/Hz dBc dBc dBc dBc dBc dBc Table 5. Interface Speeds Bus Width Nibble (4 Bits) Interpolation Factor 1× 2× (HB1) 2× (HB2) 4× 8× 1× 2× (HB1) 2× (HB2) 4× 8× 1× 2× (HB1) 2× (HB2) 4× 8× 1.8 V ± 5% 1100 1100 1100 1100 1100 1100 1100 1100 1100 550 1100 900 1100 550 275 fBUS (Mbps) 1.8 V ± 2% 1200 1200 1200 1200 1200 1200 1200 1200 1200 600 1200 1000 1200 600 300 1.9 V ± 5% 1200 1200 1200 1200 1200 1200 1200 1200 1200 600 1200 1000 1200 600 300 Byte (8 Bits) Word (16 Bits) Rev. 0 | Page 6 of 56 AD9122 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter AVDD33 IOVDD DVDD18, CVDD18 AVSS EPAD CVSS DVSS FSADJ, REFIO, IOUT1P/IOUT1N, IOUT2P/IOUT2N D[15:0]P/D[15:0]N, FRAMEP/FRAMEN, DCIP/DCIN DACCLKP/DACCLKN, REFCLKP/REFCLKN RESET, IRQ, CS, SCLK, SDIO, SDO Junction Temperature Storage Temperature Range With Respect To AVSS, EPAD, CVSS, DVSS AVSS, EPAD, CVSS, DVSS AVSS, EPAD, CVSS, DVSS EPAD, CVSS, DVSS AVSS, CVSS, DVSS AVSS, EPAD, DVSS AVSS, EPAD, CVSS AVSS Rating −0.3 V to +3.6 V −0.3 V to +3.3 V −0.3 V to +2.1 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to AVDD33 + 0.3 V THERMAL RESISTANCE The exposed paddle (EPAD) must be soldered to the ground plane for the 72-lead, LFCSP. The EPAD performs as an electrical and thermal connection to the board. Typical θJA, θJB, and θJC are specified for a 4-layer board in still air. Airflow increases heat dissipation effectively reducing θJA and θJB. Table 7. Thermal Resistance Package 72-Lead LFCSP_VQ θJA 20.7 θJB 10.9 θJC 1.1 Unit °C/W Conditions EPAD soldered ESD CAUTION EPAD, DVSS −0.3 V to DVDD18 + 0.3 V DVSS EPAD, DVSS −0.3 V to CVDD18 + 0.3 V −0.3 V to IOVDD + 0.3 V 125°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 7 of 56 AD9122 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CVDD18 CVDD18 REFCLKP REFCLKN AVDD33 IOUT1P IOUT1N AVDD33 AVSS FSADJ REFIO AVSS AVDD33 IOUT2N IOUT2P AVDD33 AVSS NC CVDD18 DACCLKP DACCLKN CVSS FRAMEP FRAMEN IRQ D15P D15N NC IOVDD DVDD18 D14P D14N D13P D13N D12P D12N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 PIN 1 INDICATOR AD9122 TOP VIEW (Not to Scale) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 RESET CS SCLK SDIO SDO DVDD18 D0N D0P D1N D1P DVSS DVDD18 D2N D2P D3N D3P D4N D4P D11P D11N D10P D10N D9P D9N D8P D8N DCIP DCIN DVDD18 DVSS D7P D7N D6P D6N D5P D5N 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 NOTES 1. NC = NO CONNECT. 2. EXPOSED PAD MUST BE CONNECTED TO AVSS. Figure 3. Pin Configuration Table 8. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Mnemonic CVDD18 DACCLKP DACCLKN CVSS FRAMEP FRAMEN IRQ D15P D15N NC IOVDD DVDD18 D14P D14N D13P D13N D12P D12N D11P D11N D10P D10N D9P D9N D8P D8N Description 1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry. DAC Clock Input, Positive. DAC Clock Input, Negative. Clock Supply Common. Frame Input, Positive. Frame Input, Negative. Interrupt Request. Open-drain, active low output. Data Bit 15 (MSB), Positive. Data Bit 15 (MSB), Negative. No connection to device. Supply Pin for Serial Ports, RESET and IRQ. 1.8 V to 2.8 V can be supplied to this pin. 1.8 V Digital Supply. Supplies power to digital core and digital data ports. Data Bit 14, Positive. Data Bit 14, Negative. Data Bit 13, Positive. Data Bit 13, Negative. Data Bit 12, Positive. Data Bit 12, Negative. Data Bit 11, Positive. Data Bit 11, Negative. Data Bit 10, Positive. Data Bit 10, Negative. Data Bit 9, Positive. Data Bit 9, Negative. Data Bit 8, Positive. Data Bit 8, Negative. Rev. 0 | Page 8 of 56 08281-003 AD9122 Pin No. 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Mnemonic DCIP DCIN DVDD18 DVSS D7P D7N D6P D6N D5P D5N D4P D4N D3P D3N D2P D2N DVDD18 DVSS D1P D1N D0P D0N DVDD18 SDO SDIO SCLK CS RESET NC AVSS AVDD33 IOUT2P IOUT2N AVDD33 AVSS REFIO FSADJ AVSS AVDD33 IOUT1N IOUT1P AVDD33 REFCLKN REFCLKP CVDD18 CVDD18 EPAD Description Data Clock Input, Positive. Data Clock Input, Negative. 1.8 V Digital Supply. Digital Common. Data Bit 7, Positive. Data Bit 7, Negative. Data Bit 6, Positive. Data Bit 6, Negative. Data Bit 5, Positive. Data Bit 5, Negative. Data Bit 4, Positive. Data Bit 4, Negative. Data Bit 3, Positive. Data Bit 3, Negative. Data Bit 2, Positive. Data Bit 2, Negative. 1.8 V Digital Supply. Digital Common. Data Bit 1, Positive. Data Bit 1, Negative. Data Bit 0, Positive. Data Bit 0, Negative. 1.8 V Digital Supply. Serial Port Data Output (CMOS Levels with Respect to IOVDD). Serial Port Data Input/Output (CMOS Levels with Respect to IOVDD). Serial Port Clock Input (CMOS Levels With Respect to IOVDD). Serial Port Chip Select. Active Low (CMOS Levels With Respect to IOVDD). Reset. Active Low (CMOS Levels With Respect to IOVDD). No connection to device. Analog Supply Common. 3.3 V Analog Supply. Q DAC Positive Current Output. Q DAC Negative Current Output. 3.3 V Analog Supply. Analog Supply Common. Voltage Reference. Nominally 1.2 V output. Should be decoupled to analog common. Full-Scale Current Output Adjust. Place a 10 kΩ resistor on the analog common. Analog Common. 3.3 V Analog Supply. I DAC Positive Current Output. I DAC Negative Current Output. 3.3 V Analog Supply. PLL Reference Clock Input, Negative. This pin has secondary function as SYNC input. PLL Reference Clock Input, Positive. This pin has secondary function as SYNC input. 1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry. 1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry. Exposed pad must be connected to AVSS. This provides an electrical, thermal, and mechanical connection to the PCB. Rev. 0 | Page 9 of 56 AD9122 TYPICAL PERFORMANCE CHARACTERISTICS 0 –10 –20 0 –10 –20 0dBFS –6dBFS –12dBFS –18dBFS fDATA = 250MSPS, SECOND HARMONIC fDATA = 250MSPS, THIRD HARMONIC fDATA = 400MSPS, SECOND HARMONIC fDATA = 400MSPS, THIRD HARMONIC HARMONICS (dBc) 08281-101 HARMONICS (dBc) –30 –40 –50 –60 –70 –80 –90 –100 0 50 100 150 200 250 300 350 400 450 –30 –40 –50 –60 –70 –80 –90 –100 0 50 100 150 200 250 300 350 400 450 08281-104 08281-106 08281-105 fOUT (MHz) fOUT (MHz) Figure 4. Harmonics vs. fOUT over fDATA, 2× Interpolation, Digital Scale = 0 dBFS, fSC = 20 mA 0 –10 –20 Figure 7. Second Harmonic vs. fOUT over Digital Scale, 2× Interpolation, fDATA = 400 MSPS, fSC = 20 mA 0 –10 –20 0dBFS –6dBFS –12dBFS –18dBFS fDATA = 100MSPS, SECOND HARMONIC fDATA = 100MSPS, THIRD HARMONIC fDATA = 200MSPS, SECOND HARMONIC fDATA = 200MSPS, THIRD HARMONIC HARMONICS (dBc) 0 50 100 150 200 250 300 350 400 450 08281-102 HARMONICS (dBc) –30 –40 –50 –60 –70 –80 –90 –100 –30 –40 –50 –60 –70 –80 –90 –100 0 50 100 150 200 250 300 350 400 450 fOUT (MHz) fOUT (MHz) Figure 5. Harmonics vs. fOUT over fDATA, 4× Interpolation, Digital Scale = 0 dBFS, fSC = 20 mA 0 –10 –20 Figure 8. Third Harmonic vs. fOUT over Digital Scale, 2× Interpolation, fDATA = 400 MSPS, fSC = 20 mA 0 –10 –20 10mA, 20mA, 30mA, 10mA, 20mA, 30mA, SECOND HARMONIC SECOND HARMONIC SECOND HARMONIC THIRD HARMONIC THIRD HARMONIC THIRD HARMONIC fDATA = 100MSPS, SECOND HARMONIC fDATA = 100MSPS, THIRD HARMONIC fDATA = 150MSPS, SECOND HARMONIC fDATA = 150MSPS, THIRD HARMONIC HARMONICS (dBc) 0 100 200 300 400 500 600 700 08281-103 HARMONICS (dBc) –30 –40 –50 –60 –70 –80 –90 –100 –30 –40 –50 –60 –70 –80 –90 –100 0 50 100 150 200 250 300 350 400 450 fOUT (MHz) fOUT (MHz) Figure 6. Harmonics vs. fOUT over fDATA, 8× Interpolation, Digital Scale = 0 dBFS, fSC = 20 mA Figure 9. Second Harmonic vs. fOUT over fSC, 2× Interpolation, fDATA = 400 MSPS, Digital Scale = 0 dBFS Rev. 0 | Page 10 of 56 AD9122 0 –10 fDATA = 250MSPS fDATA = 400MSPS HIGHEST DIGITAL SPUR (dBc) –20 –30 –40 –50 –60 –70 –80 –90 0 50 100 150 200 250 300 350 400 450 08281-107 2× INTERPOLATION, SINGLE-TONE SPECTRUM, fDATA = 250MSPS, fOUT = 101MHz START 1.0MHz #RES BW 10kHz VBW 10kHz STOP 500.0MHz SWEEP 6.017s (601 PTS) 08281-110 08281-112 08281-111 fOUT (MHz) Figure 10. Highest Digital Spur vs. fOUT over fDATA, 2× Interpolation, Digital Scale = 0 dBFS, fSC = 20 mA –64 –66 Figure 13. 2× Interpolation, Single-Tone Spectrum fDATA = 100MSPS fDATA = 200MSPS HIGHEST DIGITAL SPUR (dBc) –68 –70 –72 –74 –76 –78 0 50 100 150 200 250 300 350 400 450 4× INTERPOLATION, SINGLE-TONE SPECTRUM, fDATA = 200MSPS, fOUT = 151MHz START 1.0MHz #RES BW 10kHz VBW 10kHz STOP 800.0MHz SWEEP 9.634s (601 PTS) fOUT (MHz) 08281-108 Figure 14. 4× Interpolation, Single-Tone Spectrum Figure 11. Highest Digital Spur vs. fOUT over fDATA, 4× Interpolation, Digital Scale = 0 dBFS, fSC = 20 mA –64 fDATA = 100MSPS fDATA = 150MSPS –66 HIGHEST DIGITAL SPUR (dBc) –68 –70 –72 8× INTERPOLATION, SINGLE-TONE SPECTRUM, fDATA = 100MSPS, fOUT = 131MHz START 1.0MHz #RES BW 10kHz VBW 10kHz STOP 800.0MHz SWEEP 9.634s (601 PTS) –74 –76 0 100 200 300 400 500 600 700 08281-109 fOUT (MHz) Figure 15. 8× Interpolation, Single-Tone Spectrum Figure 12. Highest Digital Spur vs. fOUT over fDATA, 8× Interpolation, Digital Scale = 0 dBFS, fSC = 20 mA Rev. 0 | Page 11 of 56 AD9122 0 –10 –20 –30 fDATA = 250MSPS fDATA = 400MSPS 0 –10 –20 –30 0dBFS –6dBFS –12dBFS –18dBFS IMD (dBc) –40 –50 –60 –70 –80 –90 08281-113 IMD (dBc) –40 –50 –60 –70 –80 –90 0 50 100 150 200 250 300 350 400 450 0 50 100 150 200 250 300 350 400 450 fOUT (MHz) fOUT (MHz) Figure 16. IMD vs. fOUT over fDATA, 2× Interpolation, Digital Scale = 0 dBFS, fSC = 20 mA 0 –10 –20 Figure 19. IMD vs. fOUT over Digital Scale, 2× Interpolation, fDATA = 400 MSPS, fSC = 20 mA –50 –55 –60 IFS = 20mA IFS = 30mA IFS = 10mA fDATA = 100MSPS fDATA = 200MSPS –30 IMD (dBc) IMD (dBc) –40 –50 –60 –65 –70 –75 –70 –80 –90 08281-114 –80 –85 0 50 100 150 200 250 300 350 400 450 0 50 100 150 200 250 300 350 400 450 fOUT (MHz) fOUT (MHz) Figure 17. IMD vs. fOUT over fDATA, 4× Interpolation, Digital Scale = 0 dBFS, fSC = 20 mA 0 –10 –20 –30 Figure 20. IMD vs. fOUT over fSC, 2× Interpolation, fDATA = 400 MSPS, Digital Scale = 0 dBFS –40 –45 –50 –55 PLL ON fDATA = 100MSPS IMD (dBc) –50 –60 –70 –80 –90 –100 08281-115 IMD (dBc) –40 –60 –65 PLL OFF –70 –75 –80 –85 –90 08281-118 0 50 100 150 200 250 300 350 400 450 0 50 100 150 200 250 300 350 400 450 fOUT (MHz) fOUT (MHz) Figure 18. IMD vs. fOUT over fDATA, 8× Interpolation, Digital Scale = 0 dBFS, fSC = 20 mA Figure 21. IMD vs. fOUT, PLL On vs. PLL Off Rev. 0 | Page 12 of 56 08281-117 08281-116 AD9122 –152 –154 –156 –162.5 1×, fDATA 2×, fDATA 4×, fDATA 8×, fDATA = 200MSPS = 200MSPS = 200MSPS = 100MSPS –161.0 –161.5 –162.0 1×, fDATA 2×, fDATA 4×, fDATA 8×, fDATA = 200MSPS = 200MSPS = 200MSPS = 100MSPS NSD (dBm/Hz) –158 –160 –162 NSD (dBm/Hz) 08281-119 –163.0 –163.5 –164.0 –164.5 –164 –166 0 50 100 150 200 250 300 350 400 450 –165.0 –165.5 0 50 100 150 200 250 300 350 400 450 fOUT (MHz) fOUT (MHz) Figure 22. 1-Tone NSD vs. fOUT over Interpolation Rate, Digital Scale = 0 dBFS, fSC = 20 mA, PLL Off –154 –156 –158 0dBFS –6dBFS –12dBFS –18dBFS Figure 25. 8-Tone NSD vs. fOUT over Interpolation Rate, Digital Scale = 0 dBFS, fSC = 20 mA, PLL Off –161.0 –161.5 –162.0 –162.5 0dBFS –6dBFS –12dBFS –18dBFS NSD (dBm/Hz) –160 –162 –164 –166 NSD (dBm/Hz) –163.0 –163.5 –164.0 –164.5 –165.0 –165.5 –166.0 –168 08281-120 –166.5 0 50 100 150 200 250 300 350 400 450 0 50 100 150 200 250 300 350 400 450 fOUT (MHz) fOUT (MHz) Figure 23. 1-Tone NSD vs. fOUT over Digital Scale, fDATA = 200 MSPS, 4× Interpolation, fSC = 20 mA, PLL Off –158 –159 –160 2×, fDATA = 200MSPS 4×, fDATA = 200MSPS 8×, fDATA = 100MSPS Figure 26. 8-Tone NSD vs. fOUT over Digital Scale, fDATA = 200 MSPS, 4× Interpolation, fSC = 20 mA, PLL Off –160 2×, fDATA = 200MSPS 4×, fDATA = 200MSPS 8×, fDATA = 100MSPS –161 –162 NSD (dBm/Hz) –162 –163 –164 NSD (dBm/Hz) –161 –163 –164 –165 –165 –166 08281-121 –166 0 50 100 150 200 250 300 350 400 450 0 50 100 150 200 250 300 350 400 450 fOUT (MHz) fOUT (MHz) Figure 24. 1-Tone NSD vs. fOUT over Interpolation Rate, Digital Scale = 0 dBFS, fSC = 20 mA, PLL On Figure 27. 8-Tone NSD vs. fOUT over Interpolation Rate, Digital Scale = 0 dBFS, fSC = 20 mA, PLL On Rev. 0 | Page 13 of 56 08281-124 08281-123 08281-122 AD9122 –77 –78 –79 0dBFS –3dBFS –6dBFS –50 –55 –60 –65 –70 –75 –80 –85 –90 08281-125 INTERPOLATION FACTOR = 2×, INTERPOLATION FACTOR = 4×, INTERPOLATION FACTOR = 2×, INTERPOLATION FACTOR = 4×, PLL OFF PLL OFF PLL ON PLL ON ACLR (dBc) –80 –81 –82 –83 –84 0 50 100 150 200 250 ACLR (dBc) 0 100 200 300 400 500 fOUT (MHz) fOUT (MHz) Figure 28. 1-Carrier W-CDMA ACLR vs. fOUT over fDAC, Adjacent Channel, PLL Off –78 0dBFS –3dBFS –6dBFS Figure 31. 1-Carrier W-CDMA ACLR vs. fOUT, Adjacent Channel, PLL On vs. PLL Off –70 –72 –74 –76 INTERPOLATION FACTOR = 2×, INTERPOLATION FACTOR = 4×, INTERPOLATION FACTOR = 2×, INTERPOLATION FACTOR = 4×, PLL OFF PLL OFF PLL ON PLL ON –80 –82 ACLR (dBc) ACLR (dBc) –78 –80 –82 –84 –86 –88 –84 –86 –88 –90 08281-126 –90 0 50 100 150 200 250 0 100 200 300 400 500 fOUT (MHz) fOUT (MHz) Figure 29. 1-Carrier W-CDMA ACLR vs. fOUT over fDAC, Alternate Channel, PLL Off –70 0dBFS –3dBFS –6dBFS –75 Figure 32. 1-Carrier W-CDMA ACLR vs. fOUT, Alternate Channel, PLL On vs. PLL Off –70 INTERPOLATION FACTOR = 2×, INTERPOLATION FACTOR = 4×, INTERPOLATION FACTOR = 2×, INTERPOLATION FACTOR = 4×, PLL OFF PLL OFF PLL ON PLL ON –75 ACLR (dBc) –80 ACLR (dBc) –80 –85 –85 –90 –90 –95 08281-127 –95 0 50 100 150 200 250 0 100 200 300 400 500 fOUT (MHz) fOUT (MHz) Figure 30. 1-Carrier W-CDMA ACLR vs. fOUT over fDAC, Second Alternate Channel, PLL Off Figure 33. 1-Carrier W-CDMA ACLR vs. fOUT, Second Alternate Channel, PLL On vs. PLL Off Rev. 0 | Page 14 of 56 08281-130 08281-129 08281-128 AD9122 START 133.06MHz #RES BW 30kHz RMS RESULTS CARRIER POWER –10.00dBm/ 3.840MHz FREQ OFFSET 5.00MHz 10.00MHz 15.00MHz VBW 30kHz STOP 166.94MHz SWEEP 143.6ms (601 PTS) REF BW 3.840MHz 3.840MHz 2.888MHz LOWER dBc dBm –75.96 –85.96 –85.33 –95.33 –95.81 –95.81 UPPER dBc dBm –77.13 –87.13 –85.24 –95.25 –85.43 –95.43 START 125.88MHz #RES BW 30kHz VBW 30kHz STOP 174.42MHz SWEEP 206.9ms (601 PTS) 08281-131 TOTAL CARRIER POWER –11.19dBm/15.3600MHz RRC FILTER: OFF FILTER ALPHA 0.22 REF CARRIER POWER –16.89dBm/3.84000MHz OFFSET FREQ 5.000MHz 10.00MHz 15.00MHz INTEG BW 3.840MHz 3.840MHz 3.840MHz LOWER dBc dBm –65.88 –82.76 –68.17 –85.05 –70.42 –87.31 UPPER dBc dBm –67.52 –84.40 –69.91 –86.79 –71.40 –88.28 1 2 3 4 –16.92dBm –16.89dBm –17.43dBm –17.64dBm Figure 34. 4-Carrier W-CDMA ACLR Performance, IF = ~150 MHz Figure 35. 1-Carrier W-CDMA ACLR Performance, IF = ~150 MHz Rev. 0 | Page 15 of 56 08281-132 AD9122 TERMINOLOGY Integral Nonlinearity (INL) INL is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Offset Error The deviation of the output current from the ideal of zero is called offset error. For IOUT1P, 0 mA output is expected when the inputs are all 0s. For IOUT1N, 0 mA output is expected when all inputs are set to 1. Gain Error The difference between the actual and ideal output span. The actual span is determined by the difference between the output when all inputs are set to 1 and the output when all inputs are set to 0. Output Compliance Range The range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. Temperature Drift Temperature drift is specified as the maximum change from the ambient (25°C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of fullscale range (FSR) per degree Celsius. For reference drift, the drift is reported in ppm per degree Celsius. Power Supply Rejection (PSR) The maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. Settling Time The time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. Spurious Free Dynamic Range (SFDR) The difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal within the dc to the Nyquist frequency of the DAC. Typically, energy in this band is rejected by the interpolation filters. This specification, therefore, defines how well the interpolation filters work and the effect of other parasitic coupling paths to the DAC output. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Interpolation Filter If the digital inputs to the DAC are sampled at a multiple rate of fDATA (interpolation rate), a digital filter can be constructed that has a sharp transition band near fDATA/2. Images that typically appear around fDAC (output data rate) can be greatly suppressed. Adjacent Channel Leakage Ratio (ACLR) The ratio in decibels relative to the carrier (dBc) between the measured power within a channel relative to its adjacent channel. Complex Image Rejection In a traditional two-part upconversion, two images are created around the second IF frequency. These images have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected. Rev. 0 | Page 16 of 56 AD9122 THEORY OF OPERATION The AD9122 combines many features that make it a very attractive DAC for wired and wireless communications systems. The dual digital signal path and dual DAC structure allow an easy interface to common quadrature modulators when designing single sideband transmitters. The speed and performance of the AD9122 allows wider bandwidths and more carriers to be synthesized than in previously available DACs. In addition, these devices include an innovative low power, 32-bit complex NCO that greatly increases the ease of frequency placement. The AD9122 offers features that allow simplified synchronization with incoming data and between multiple devices. Auxiliary DACs are also provided on chip for output dc offset compensation (for LO compensation in SSB transmitters) and for gain matching (for image rejection optimization in SSB transmitters). The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the device and the system controller. Phase 2 of the communication cycle is a transfer of one or more data bytes. Registers change immediately upon writing to the last bit of each transfer byte, except for the frequency tuning word and NCO phase offsets that only change when the frequency update bit (Register 0x36, Bit 0) is set. DATA FORMAT The instruction byte contains the information shown in Table 9. Table 9. Serial Port Instruction Byte I7 (MSB) R/W I6 A6 I5 A5 I4 A4 I3 A3 I2 A2 I1 A1 I0 (LSB) A0 SERIAL PORT OPERATION The serial port is a flexible, synchronous serial communications port allowing easy interface to many industry-standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola SPI® and Intel® SSR protocols. The interface allows read/write access to all registers that configure the AD9122. Single or multiple byte transfers are supported, as well as MSBfirst or LSB-first transfer formats. The serial interface ports can be configured as a single pin I/O (SDIO) or two unidirectional pins for input/output (SDIO/SDO). SDO 50 SDIO 51 SCLK 52 CS 53 SPI PORT 08281-010 R/W, Bit 7 of the instruction byte, determines whether a read or a write data transfer occurs after the instruction byte write. Logic 1 indicates a read operation, and Logic 0 indicates a write operation. A6 to A0, Bit 6 to Bit 0 of the instruction byte, determine the register that is accessed during the data transfer portion of the communication cycle. For multibyte transfers, A6 is the starting byte address. The remaining register addresses are generated by the device based on the LSB_FIRST bit (Register 0x00, Bit 6). SERIAL PORT PIN DESCRIPTIONS Serial Clock (SCLK) The serial clock pin synchronizes data to and from the device and runs the internal state machines. The maximum frequency of SCLK is 40 MHz. All data input is registered on the rising edge of SCLK. All data is driven out on the falling edge of SCLK. Chip Select (CS) An active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communications lines. The SDO and SDIO pins go to a high impedance state when this input is high. During the communication cycle, chip select should stay low. Serial Data I/O (SDIO) Data is always written into the device on this pin. However, this pin can be used as a bidirectional data line. The configuration of this pin is controlled by Register 0x00, Bit 7. The default is Logic 0, configuring the SDIO pin as unidirectional. Serial Data Out (SDO) Data is read from this pin for protocols that use separate lines for transmitting and receiving data. In the case where the device operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state. Figure 36. Serial Port Interface Pins There are two phases to a communication cycle with the AD9122. Phase 1 is the instruction cycle (the writing of an instruction byte into the device), coincident with the first eight SCLK rising edges. The instruction byte provides the serial port controller with information regarding the data transfer cycle, Phase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is a read or write and the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the device. A logic high on the CS pin followed by a logic low resets the serial port timing to the initial state of the instruction cycle. From this state, the next eight rising SCLK edges represent the instruction bits of the current I/O operation. Rev. 0 | Page 17 of 56 AD9122 SERIAL PORT OPTIONS The serial port can support both MSB-first and LSB-first data formats. This functionality is controlled by LSB_FIRST (Register 0x00, Bit 6). The default is MSB-first (LSB_FIRST = 0). When LSB_FIRST = 0 (MSB-first), the instruction and data bit must be written from MSB to LSB. Multibyte data transfers in MSB-first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent data bytes should follow from the high address to low address. In MSB-first mode, the serial port internal byte address generator decrements for each data byte of the multibyte communication cycle. When LSB_FIRST = 1 (LSB-first), the instruction and data bit must be written from LSB to MSB. Multibyte data transfers in LSB-first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes. The serial port internal byte address generator increments for each byte of the multibyte communication cycle. The serial port controller data address decrements from the data address written toward 0x00 for multibyte I/O operations if the MSB-first mode is active. The serial port controller address increments from the data address written toward 0x7F for multibyte I/O operations if the LSB-first mode is active. INSTRUCTION CYCLE CS SCLK DATA TRANSFER CYCLE INSTRUCTION CYCLE CS SCLK DATA TRANSFER CYCLE SDIO A0 A1 A2 A3 A4 N0 N1 R/W D00 D10 D20 D4N D5N D6N D7N 08281-012 SDO D00 D10 D20 D4N D5N D6N D7 N Figure 38. Serial Register Interface Timing LSB-First tDS CS tSCLK tPWH SCLK tPWL tDS SDIO INSTRUCTION BIT 7 INSTRUCTION BIT 6 Figure 39. Timing Diagram for Serial Port Register Write CS SCLK 08281-014 tDV SDIO, SDO DATA BIT n DATA BIT n – 1 Figure 40. Timing Diagram for Serial Port Register Read SDIO R/W A6 A5 A4 A3 A2 A1 A0 D7 D6N D5N D30 D20 D10 D00 08281-011 SDO D7 D6N D5N D30 D20 D10 D00 Figure 37. Serial Register Interface Timing MSB-First Rev. 0 | Page 18 of 56 08281-013 tDH AD9122 DEVICE CONFIGURATION REGISTER MAP AND DESCRIPTIONS Table 10. Device Configuration Register Map Reg Name Comm Power Control Addr (Hex) 0x00 0x01 Bit 7 SDIO Powerdown DAC I Binary data format Enable PLL lock lost 0 Bit 6 LSB_FIRST Powerdown DAC Q Q data first Enable PLL locked 0 Bit 5 Reset Powerdown data receiver MSB swap Bit 4 Powerdown aux ADC Bit 3 Bit 2 Bit 1 Bit 0 PLL lock status Data bus width[1:0] Default 0x00 0x10 Data Format 0x03 0x00 Interrupt Enable 0x04 Interrupt Enable 0x05 Enable sync signal lost 0 Event Flag 0x06 PLL lock lost PLL locked Sync signal lost Event Flag 0x07 Clock Receiver Control PLL Control 0x08 0x0A DACCLK duty correction PLL enable REFCLK duty correction PLL manual enable DACCLK crosscorrection Enable sync signal locked Enable AED compar pass Sync signal locked AED compar pass REFCLK crosscorrection Enable sync phase locked Enable AED compar fail Sync phase locked AED compar fail 0 Enable soft FIFO sync Enable SED compar fail Soft FIFO sync SED compar fail 0 Enable FIFO Warning 1 0 Enable FIFO Warning 2 0 0x00 0x00 FIFO Warning 1 FIFO Warning 2 N/A N/A 0 0 0x3F Manual VCO Band[5:0] 0x40 PLL Control PLL Control PLL Control 0x0B 0x0C 0x0D PLL Loop Bandwidth[1:0] N2[1:0] PLL VCO enable PLL Charge Pump Current[4:0] PLL cross control enable N0[1:0] N1[1:0] 0x00 0xD1 0xD9 PLL Status PLL Status Sync Control Sync Control Sync Status Sync Status Data Receiver Status 0x0E 0x0F 0x10 0x11 0x12 0x13 0x15 PLL lock VCO Control Voltage[3:0] VCO Band Readback[5:0] Data/FIFO rate toggle Sync locked Sync Phase Readback[7:0] (6.2 format) LVDS FRAME level high LVDS FRAME level low LVDS DCI level high LVDS DCI level low LVDS data level high LVDS data level low Sync Averaging[2:0] Rising edge sync Sync Phase Request[5:0] 0x00 0x00 0x48 0x00 N/A N/A N/A Sync enable Sync lost FIFO Control FIFO Status 0x17 0x18 FIFO Warning 1 FIFO Warning 2 FIFO Phase Offset[2:0] FIFO FIFO soft FIFO reset soft align aligned align request ack FIFO Level[7:0] Rev. 0 | Page 19 of 56 0x04 N/A FIFO Status 0x19 N/A AD9122 Reg Name Datapath Control Addr (Hex) 0x1B Bit 7 Bypass premod Bit 6 Bypass Sinc−1 Bit 5 Bypass NCO Bit 4 Bit 3 NCO gain Bit 2 Bit 1 Bypass Select phase sideband comp and dc offset HB1[1:0] Bit 0 Send I data to Q data Default 0xE4 HB1 Control HB2 Control HB3 Control Chip ID FTW LSB FTW FTW FTW MSB NCO Phase Offset LSB NCO Phase Offset MSB NCO FTW Update I Phase Adj LSB I Phase Adj MSB Q Phase Adj LSB Q Phase Adj MSB I DAC Offset LSB I DAC Offset MSB Q DAC Offset LSB Q DAC Offset MSB I DAC FS Adj. I DAC Control Aux DAC I Data I Aux DAC Control Q DAC FS Adj. Q DAC Control Aux DAC Q Data Q Aux DAC Control Die Temp Range Control Die Temp LSB Die Temp MSB SED Control 0x1C 0x1D 0x1E 0x1F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 Frame FTW ack HB2[5:0] HB3[5:0] Chip ID[7:0] FTW[7:0] FTW[15:8] FTW[23:16] FTW[31:24] NCO Phase Offset[7:0] NCO Phase Offset[15:8] Frame FTW request I Phase Adj[7:0] Bypass HB1 Bypass HB2 Bypass HB3 0x00 0x00 0x00 0x08 0x00 0x00 0x00 0x08 0x00 0x00 Update FTW ack Update FTW request 0x00 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 I Phase Adj[9:8] Q Phase Adj[7:0] Q Phase Adj[9:8] I DAC Offset[7:0] I DAC Offset[15:8] Q DAC Offset[7:0] Q DAC Offset[15:8] I DAC FS Adj[7:0] I DAC sleep I Aux DAC[7:0] I Aux DAC sign I Aux DAC current direction I Aux DAC Sleep Q DAC FS Adj[7:0] Q DAC sleep Q Aux DAC[7:0] Q Aux DAC sign Q Aux DAC current direction Q Aux DAC Sleep FS Current[2:0] Die Temp[7:0] Die Temp[15:8] SED compare enable Sample error detected Autoclear enable Compare fail Compare pass Q Aux DAC[9:8] Q DAC FS Adj[9:8] I Aux DAC[9:8] I DAC FS Adj[9:8] 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xF9 0x01 0x00 0x00 0x44 0x45 0x46 0x47 0xF9 0x01 0x00 0x00 0x48 0x49 0x4A 0x67 Ref Current[2:0] Capacitor value 0x02 N/A N/A 0x00 Rev. 0 | Page 20 of 56 AD9122 Reg Name Compare I0 LSBs Compare I0 MSBs Compare Q0 LSBs Compare Q0 MSBs Compare I1 LSBs Compare I1 MSBs Compare Q1 LSBs Compare Q1 MSBs SED I LSBs SED I MSBs SED Q LSBs SED Q MSBs Addr (Hex) 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Compare Value I0[7:0] Compare Value I0[15:8] Compare Value Q0[7:0] Compare Value Q0[15:8] Compare Value I1[7:0] Compare Value I1[15:8] Compare Value Q1[7:0] Compare Value Q1[15:8] Errors Detected I_BITS[7:0] Errors Detected I_BITS[15:8] Errors Detected Q_BITS[7:0] Errors Detected Q_BITS[15:8] Bit 2 Bit 1 Bit 0 Default 0xB6 0x7A 0x45 0xEA 0x16 0x1A 0xC6 0xAA 0x00 0x00 0x00 0x00 Table 11. Device Configuration Register Descriptions Reg Name Comm Addr (Hex) 00 Bit 7 Name SDIO Description SDIO Operation. 0 = SDIO operates as an input only. 1 = SDIO operates as bidirectional input/output. Serial port communication LSB or MSB first. 0 = MSB first. 1 = LSB first. Reset is asserted when this bit transitions from 0 to 1. 1 = power down DAC I. 1 = power down DAC Q. 1 = power down the input data receiver. 1 = power down auxiliary ADC for temperature sensor. 1 = PLL is locked. Default 0 6 LSB_FIRST 0 Power Control 01 5 7 6 5 4 0 Reset Power-down DAC I Power-down DAC Q Power-down data receiver Power-down auxiliary ADC PLL lock status 0 0 0 0 0 0 Rev. 0 | Page 21 of 56 AD9122 Reg Name Data Format Addr (Hex) 03 Bit 7 6 Name Binary data format Q data first Description 0 = input data is in twos complement format. 1 = input data is in binary format. Indicates I/Q data pairing on data input. 0 = I data sent to data receiver first. 1 = Q data sent to data receiver first. Swaps the bit order of the data input port. 0 = order of the data bits corresponds to the pin descriptions 1 = bit designations are swapped; most significant bits become the least significant bits Data receiver interface mode. 00 = word mode; 16-bit interface bus width. 01 = byte mode; 8-bit interface bus width. 10 = nibble mode; 4-bit interface bus width. 11 = invalid. See the LVDS Input Data Ports section for details on the operation of the different interface modes. 1 = enable interrupt for PLL lock lost. 1 = enable interrupt for PLL locked. 1 = enable interrupt for sync signal lock lost. 1 = enable interrupt for sync signal locked. 1 = enable interrupt for clock generation ready. 1 = enable interrupt for soft FIFO reset. 1 = enable interrupt for FIFO Warning 1. 1 = enable interrupt for FIFO Warning 2. Set this bit to 0. Set this bit to 0. Set this bit to 0. 1 = enable interrupt for AED comparison pass. 1 = enable interrupt for AED comparison fail. 1 = enable interrupt for SED comparison fail. Set this bit to 0. Set this bit to 0. Default 0 0 5 MSB swap 0 1:0 Data bus width 0 Interrupt Enable 04 7 6 5 4 3 2 1 0 Enable PLL lock lost Enable PLL locked Enable sync signal lost Enable sync signal locked Enable sync phase locked Enable soft FIFO sync Enable FIFO Warning 1 Enable FIFO Warning 2 Set to 0 Set to 0 Set to 0 Enable AED comparison pass Enable AED comparison fail Enable SED comparison fail Set to 0 Set to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Interrupt Enable 05 7 6 5 4 3 2 1 0 Rev. 0 | Page 22 of 56 AD9122 Reg Name Event Flag Addr (Hex) 06 Bit 7 Name PLL lock lost Description 1 = indicates that the PLL, which had been previously locked, has unlocked from the reference signal. This is a latched signal. 1 = indicates that the PLL has locked to the reference clock input. 1 = indicates that the sync logic, which had been previously locked, has lost alignment. This is a latched signal. 1 = indicates that the sync logic did achieve sync alignment. This is indicated when no phase changes were requested for at least a few full averaging cycles. 1 = indicates that the internal digital clock generation logic is ready. This occurs when internal clocks are present and stable. Default 0 6 5 4 PLL locked Sync signal lost Sync signal locked 0 0 0 3 2 Sync phase locked Soft FIFO sync 0 0 1 0 Event Flag 07 4 3 2 Clock Receiver Control 08 7 6 5 4 1 = indicates that a FIFO reset originating from a serial port-based request has successfully completed. This is a latched signal. FIFO Warning 1 1 = indicates that the difference between the FIFO read and write pointers is 1. FIFO Warning 2 1 = indicates that the difference between the FIFO read and write pointers is 2. Note that all bit event flags are cleared by writing the respective bit high. AED comparison pass 1 = indicates that the SED logic detected a valid input data pattern compared against the preprogrammed expected values. This is a latched signal. AED comparison fail 1 = indicates that the SED logic detected an invalid input data pattern comparison against the preprogrammed expected values. This is a latched signal that automatically clears when eight valid I/Q data pairs are received. SED comparison fail 1 = indicates that the SED logic detected an invalid input data pattern comparison against the preprogrammed expected values. This is a latched signal. Note that all bit event flags are cleared by writing the respective bit high. DACCLK duty correction 1 = enables duty-cycle correction on DACCLK input. REFCLK duty correction DACCLK crosscorrection REFCLK crosscorrection PLL enable PLL manual enable 1 = enables duty-cycle correction on REFCLK input. 1 = enables differential crossing correction on the CLK input. 1 = enables differential crossing correction on the REFCLK input. 1 = enables the PLL clock multiplier. REFCLK input is used as the PLL reference clock signal. Enables the manual selection of the VCO band. 1 = manual mode; the correct VCO band must be determined by the user. Selects the VCO band to be used. 0 = disables the PLL VCO. 1 = enables the PLL VCO. Set this bit high prior to enabling PLL. 0 0 0 0 0 0 0 0 0 1 PLL Control 0A 7 6 5:0 PLL Control 0B 5 Manual VCO band PLL VCO enable 0 Rev. 0 | Page 23 of 56 AD9122 Reg Name PLL Control Addr (Hex) 0C Bit 7:6 Name PLL Loop Bandwidth[1:0] Description Selects the PLL loop filter bandwidth. 00 = narrowest bandwidth. 01 = narrow/medium bandwidth. 10 = medium/wide bandwidth. 11 = widest bandwidth. Sets the nominal PLL charge pump current. 00000 = lowest current setting. 11111 = highest current setting. PLL control clock divider. It determines the ratio of the DACCLK rate to the PLL controller clock rate. 00 = fDACCLK/fPC_CLK = 2. 01 = fDACCLK/fPC_CLK = 4. 10 = fDACCLK/fPC_CLK = 8. 11 = fDACCLK/fPC_CLK = 16. fPC_CLK must always be less than 50 MHz. Enable PLL cross point controller. PLL VCO divider. It determines the ratio of the VCO output to the DACCLK frequencies. 00 = fVCO/fDACCLK = 1. 01 = fVCO/fDACCLK = 2. 10 = fVCO/fDACCLK = 4. 11 = fVCO/fDACCLK = 4. PLL Loop divider. It determines the ratio of the DACCLK to the REFCLK frequencies. 00 = fDACCLK/fREFCLK = 2. 01 = fDACCLK/fREFCLK = 4. 10 = fDACCLK/fREFCLK = 8. 11 = fDACCLK/fREFCLK = 16. The PLL generated clock is tracking the REFCLK input signal. VCO Control Voltage readback. See Table 24. Indicates the VCO band currently selected. 1 = enables the synchronization logic. 0 = operates the synchronization at the FIFO reset rate. 1 = operates the synchronization at the data rate. 0 = sync is initiated on the falling edge of the sync input. 1 = sync is initiated on the rising edge of the sync input. Sets the number of input samples that are averaged in determining the sync phase. 000 = 1. 001 = 2. 010 = 4. 011 = 8. 100 = 16. 101 = 32. 110 = 64. 111 = 128. Default 3 4:0 PLL Charge Pump Current[4:0] 001 PLL Control 0D 7:6 N2[1:0] 3 4 3:2 PLL cross control enable N0[1:0] 0 01 1:0 N1[1:0] 01 PLL Status PLL Status Sync Control 0E 7 3:0 5:0 7 6 3 2:0 0F 10 PLL lock VCO Control Voltage[3:0] VCO Band Readback[5:0] Sync enable Data/FIFO rate toggle Rising edge sync Sync Averaging[2:0] R R R 0 0 1 0 Rev. 0 | Page 24 of 56 AD9122 Reg Name Sync Control Addr (Hex) 11 Bit 5:0 Name Sync Phase Request[5:0] Description This sets the requested clock phase offset after sync. The offset unit is in DACCLK cycles. 000000 = 0 DACCLK cycles. 000001 = 1 DACCLK cycle. … 111111 = 63 DACCLK cycles. This enables repositioning of the DAC output with respect to the sync input. The offset can also be used to skew the DAC outputs between the synchronized DACs. 1 = indicates that synchronization had been attained but has been lost. 1 = indicates that synchronization has been attained. Indicates the averaged sync phase offset (6.2 format). 00000000 = 0.0. 00000001 = 0.25. … 11111110 = 63.50. 11111111 = 63.75. If this value differs from the requested sync phase value, this indicates sync timing errors. One or both of the LVDS FRAME input signals have exceeded 1.7 V. One or both of the LVDS FRAME input signals have crossed below 0.7 V. One or both of the LVDS DCI input signals have exceeded 1.7 V. One or both of the LVDS DCI input signals have crossed below 0.7 V. One or more of the LVDS Dx input signals have exceeded 1.7 V. One or both of the LVDS Dx input signals have crossed below 0.7 V. FIFO write pointer phase offset following FIFO reset. 000 = 0. 001 = 1. … 111 = 7. This is the difference between the read pointer and the write pointer values upon FIFO reset. The optimal value is nominally 4. FIFO read and write pointers within ±1. FIFO read and write pointers within ±2. FIFO read and write pointers are aligned after serial port initiated FIFO reset. Request FIFO read and write pointers alignment via serial port. FIFO read and write pointers aligned after hardware reset. Thermometer encoded measure of the FIFO level. Default 0 Sync Status Sync Status 12 7 6 7:0 Sync lost Sync locked Sync Phase Readback[7:0] R R R 13 Data Receiver Status 15 5 4 3 2 1 0 LVDS FRAME level high LVDS FRAME level low LVDS DCI level high LVDS DCI level low LVDS data level high LVDS data level low FIFO Phase Offset[2:0] R R R R R R 0 FIFO Control 17 2:0 FIFO Status 18 7 6 2 1 0 7:0 FIFO Warning 1 FIFO Warning 2 FIFO soft align acknowledge FIFO soft align request FIFO reset aligned FIFO Level[7:0] 0 0 0 0 0 FIFO Status 19 Rev. 0 | Page 25 of 56 AD9122 Reg Name Datapath Control Addr (Hex) 1B Bit 7 6 5 3 Name Bypass Premod Bypass Sinc−1 Bypass NCO NCO gain Description 1 = bypasses fS/2 premodulator. 1 = bypasses inverse sinc filter. 1 = bypasses NCO. 0 = default. No gain scaling is applied to the NCO input to the internal digital modulator. 1 = gain scaling of 0.5 is applied to the NCO input to the internal digital modulator. This can eliminate saturation of the modulator output for some combinations of data inputs and NCO signals. 1 = bypasses phase compensation. Default 1 1 1 0 2 1 Bypass phase compensation and dc offset Select sideband 1 0 HB1 Control 1C 2:1 Send I data to Q data HB1[1:0] 0 HB2 Control 1D 6:1 Bypass HB1 HB2[5:0] 0 = the modulator outputs high-side image. 1 = the modulator outputs low-side image. The image is spectrally inverted compared to the input data. 1 = ignores Q data from interface and disables the clocks to Q datapath. Sends I data to both I and Q DACs. 00 = input signal not modulated, filter pass band is from −0.4 to +0.4 of fIN1. 01 = input signal not modulated, filter pass band is from 0.1 to 0.9 of fIN1. 10 = input signal modulated by fIN1, filter pass band is from 0.6 to 1.4 of fIN1. 11 = input signal modulated by fIN1, filter pass band is from 1.1 to 1.9 of fIN1. 1 = bypasses first stage interpolation filter. Modulation mode for I Side Half-Band Filter 2. 000000 = input signal not modulated, filter pass band is from −0.25 to +0.25 of fIN2. 001001 = input signal not modulated, filter pass band is from 0.0 to 0.5 of fIN2. 010010 = input signal not modulated, filter pass band is from 0.25 to 0.75 of fIN2. 011011 = input signal not modulated, filter pass band is from 0.5 to 1.0 of fIN2. 100100 = input signal modulated by fIN2, filter pass band is from 0.75 to 1.25 of fIN2. 101101 = input signal modulated by fIN2, filter pass band is from 1.0 to 1.5 of fIN2. 110110 = input signal modulated by fIN2, filter pass band is from 1.25 to 1.75 of fIN2. 111111 = input signal modulated by fIN2, filter pass band is from 1.5 to 2.0 of fIN2. 1 = bypasses second stage interpolation filter. 0 0 0 0 0 0 Bypass HB2 0 Rev. 0 | Page 26 of 56 AD9122 Reg Name HB3 Control Addr (Hex) 1E Bit 6:1 Name HB3[5:0] Description Modulation mode for I Side Half-Band Filter 3. 000000 = input signal not modulated, filter pass band is from −0.2 to +0.2 of fIN3. 001001 = input signal not modulated, filter pass band is from 0.05 to 0.45 of fIN3. 010010 = input signal not modulated, filter pass band is from 0.3 to 0.7 of fIN3. 011011 = input signal not modulated, filter pass band is from 0.55 to 0.95 of fIN3. 100100 = input signal modulated by fIN3, filter pass band is from 0.8 to 1.2 of fIN3. 101101 = input signal modulated by fIN3, filter pass band is from 1.05 to 1.45 of fIN3. 110110 = input signal modulated by fIN3, filter pass band is from 1.3 to 1.7 of fIN3. 111111 = input signal modulated by fIN3, filter pass band is from 1.55 to 1.95 of fIN3. 1 = bypasses third stage interpolation filter. Chip ID. See Register 0x33. See Register 0x33. See Register 0x33. FTW[31:0] is the 32-bit frequency tuning word that determines the frequency of the complex carrier generated by the on-chip NCO. The frequency is not updated when the FTW registers are written. The values are only updated when Bit 0 of Register 0x36 transitions from 0 to 1. See Register 0x35. Default 0 Chip ID FTW LSB FTW FTW FTW MSB 1F 30 31 32 33 0 7:0 7:0 7:0 7:0 7:0 Bypass HB3 Chip ID[7:0] FTW[7:0] FTW[15:8] FTW[23:16] FTW[31:24] 0 8 0 0 0 0 NCO Phase Offset LSB NCO Phase Offset MSB NCO FTW Update 34 7:0 NCO Phase Offset[7:0] 0 35 7:0 NCO Phase Offset[15:8] 36 5 4 1 0 7:0 1:0 FRAME FTW acknowledge FRAME FTW request Update FTW acknowledge Update FTW request I Phase Adj[7:0] I Phase Adj[9:8] The NCO sets the phase of the complex carrier signal when the NCO is reset. The phase offset spans between 0° and 360°. Each bit represents an offset of 0.0055°. Value is in twos complement format. 1 = indicates that the NCO has been reset due to an extended FRAME pulse signal. 0 → 1 = the NCO is reset on the first extended FRAME pulse after this bit transitions from 0 to 1. 1 = indicates that the FTW has been updated. 0 → 1 = the FTW is updated on 0-to-1 transition of this bit. See Register 0x39. I Phase Adj[9:0] is used to insert a phase offset between the I and Q datapaths. This can be used to correct for phase imbalance in a quadrature modulator. See the Quadrature Phase Correction section for details. See Register 0x3B. Q Phase Adj[9:0] is used to insert a phase offset between the I and Q datapaths. This can be used to correct for phase imbalance in a quadrature modulator. See the Quadrature Phase Correction section for details. 0 0 0 0 0 0 0 I Phase Adj LSB I Phase Adj MSB 38 39 Q Phase Adj LSB Q Phase Adj MSB 3A 3B 7:0 1:0 Q Phase Adj[7:0] Q Phase Adj[9:8] 0 0 Rev. 0 | Page 27 of 56 AD9122 Reg Name I DAC Offset LSB I DAC Offset MSB Q DAC Offset LSB Q DAC Offset MSB I DAC FS Adjust Addr (Hex) 3C Bit 7:0 Name I DAC Offset[7:0] Description I DAC Offset[15:0] is a value added directly to the samples written to the I DAC. See Register 0x3C. Default 0 3D 7:0 I DAC Offset[15:8] 0 3E 7:0 Q DAC Offset[7:0] Q DAC Offset[15:0] is a value added directly to the samples written to the Q DAC. See Register 0x3E. 0 3F 7:0 Q DAC Offset[15:8] 0 40 7:0 I DAC FS Adj[7:0] I DAC Control Aux DAC I Data 41 7 1:0 I DAC sleep I DAC FS Adj[9:8] I Aux DAC[7:0] I DAC FS Adj[9:0] sets the full-scale current of the I DAC. The full-scale current can be adjusted from 8.64 mA to 31.6 mA in step sizes of approximately 22.5 μA. 0x000 = 8.64 mA. … 0x200 = 20.14 mA. … 0x3FF = 31.66 mA. 1 = puts the I-channel DAC into sleep mode (fast wake-up mode). See Register 0x40. I Aux DAC[9:0] sets the magnitude of the auxiliary DAC current. The range is 0 mA to 2 mA and the step size is 2 μA. 0x000 = 0.000 mA. 0x001 = 0.002 mA. … 0x3FF = 2.046 mA. 0 = the auxiliary DAC I sign is positive, and the current is directed to the IOUT1P pin (Pin 67). 1 = the auxiliary DAC I sign is negative, and the current is directed to the IOUT1N pin (Pin 66). 0 = the auxiliary DAC I sources current. 1 = the auxiliary DAC I sinks current. I channel auxiliary DAC sleep. See Register 0x42. Q DAC FS Adj[9:0] sets the full-scale current of the I DAC. The full-scale current can be adjusted from 8.64 mA to 31.6 mA in step sizes of approximately 22.5 μA. 0x000 = 8.64 mA. … 0x200 = 20.14 mA. … 0x3FF = 31.66 mA. 1 = puts the Q-channel DAC into sleep mode (fast wake-up mode). See Register 0x44. F9 0 1 0 42 7:0 I Aux DAC Control 43 7 I aux DAC sign 0 6 I aux DAC current direction I aux DAC sleep I Aux DAC[9:8] Q DAC FS Adj[7:0] 0 Q DAC FS Adj. 44 5 1:0 7:0 0 0 F9 Q DAC Control 45 7 1:0 Q DAC sleep Q DAC FS Adj[9:8] 0 1 Rev. 0 | Page 28 of 56 AD9122 Reg Name Aux DAC Q Data Addr (Hex) 46 Bit 7:0 Name Q Aux DAC[7:0] Description Q Aux DAC[9:0] sets the magnitude of the aux DAC current. The range is 0 mA to 2 mA and the step size is 2 μA. 0x000 = 0.000 mA. 0x001 = 0.002 mA. … 0x3FF = 2.046 mA. 0 = the auxiliary DAC Q sign is positive, and the current is directed to the IOUT2P pin (Pin 58). 1 = the auxiliary DAC Q sign is negative, and the current is directed to the IOUT2N pin (Pin 59). 0 = the auxiliary DAC Q sources current. 1 = the auxiliary DAC Q sinks current. Q-channel auxiliary DAC sleep See Register 0x46. Auxiliary ADC full-scale current. 000 = lowest current. … 111 = highest current. Auxiliary ADC reference current. 000 = lowest current. 111 = highest current. Auxiliary ADC internal capacitor value. 0 = 5 pF. 1 = 10 pF. See Register 0x4A. Default 0 Q Aux DAC Control 47 7 Q aux DAC sign 0 6 Q aux DAC current direction Q aux DAC sleep Q Aux DAC[9:8] FS Current[2:0] 0 5 Die Temp Range Control 0x48 1:0 6:4 0 0 0 3:1 Reference Current[2:0] 1 0 Capacitor value 0 Die Temp LSB Die Temp MSB 49 7:0 Die Temp[7:0] R 4A 7:0 Die Temp[15:8] SED Control 67 7 SED compare enable 5 3 Sample error detected Autoclear enable 1 Compare fail Compare I0 LSBs Compare I0 MSBs Compare Q0 LSBs 68 69 6A 0 7:0 7:0 7:0 Compare pass Compare Value I0[7:0] Compare Value I0[15:8] Compare Value Q0[7:0] Die Temp[15:0] indicates the approximate die temperature. 0xADCC = −39.9°C 0xC422 = 25.1°C … 0xD8A8 = 84.8°C (see Temperature Sensor section for details) 1 = enables the SED circuitry. None of the flags in this register or the values in Register 0x70 through Register 0x73 are significant if the SED is not enabled. 1 = indicates an error is detected. The bit remains set until cleared. Any write to this register clears this bit to 0. 1 = enables autoclear mode. This activates Bit 1 and Bit 0 of this register and causes Register 0x70 through Register 0x73 to be autocleared whenever eight consecutive sample data sets are received error free. 1 = indicates an error has been detected. This bit remains high until it is autocleared by the reception of eight consecutive error free comparisons or is cleared by writing to this register. 1 = indicates that the last sample comparison was error free. Compare Value I0[15:0] is the word that is compared with the I0 input sample captured at the input interface. See Register 0x68. Compare Value Q0[15:0] is the word that is compared with the Q0 input sample captured at the input interface. Rev. 0 | Page 29 of 56 R 0 0 0 0 0 B6 7A 45 AD9122 Reg Name Compare Q0 MSBs Compare I1 LSBs Compare I1 MSBs Compare Q1 LSBs Compare Q1 MSBs SED I LSBs SED I MSBs SED Q LSBs SED Q MSBs Addr (Hex) 6B 6C 6D 6E 6F 70 71 72 73 Bit 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 7:0 Name Compare Value Q0[15:8] Compare Value I1[7:0] Compare Value I1[15:8] Compare Value Q1[7:0] Compare Value Q1[15:8] Errors Detected I_BITS[7:0] Errors Detected I_BITS[15:8] Errors Detected Q_BITS[7:0] Errors Detected Q_BITS[15:8] Description See Register 0x6A Compare Value I1[15:0] is the word that is compared with the I1 input sample captured at the input interface. See Register 0x6C. Compare Value Q1[15:0] is the word that is compared with the Q1 input sample captured at the input interface. See Register 0x6E. Errors Detected I_BITS[15:0] indicates which bits were received in error. See Register 0x70. Errors Detected Q_BITS[15:0] indicates which bits were received in error. See Register 0x72. Default EA 16 1A C6 AA 0 0 0 0 Rev. 0 | Page 30 of 56 AD9122 LVDS INPUT DATA PORTS The AD9122 has one LVDS data port that receives data for both the I and Q transmit paths. The device can accept data in word, byte, and nibble formats. In word, byte, and nibble modes, the data is sent over 16-bit, 8-bit, and 4-bit LVDS data busses, respectively. The pin assignment of the bus in each mode is shown in Table 12. Table 12. Data Bit Pair Assignments for Data Input Modes Mode Word Byte1 Nibble1 1 with DCI being high, and the least significant byte of the data should correspond with DCI being low. The FRAME signal indicates to which DAC the data is sent. When FRAME is high, data is sent to the I DAC, and when FRAME is low, data is sent to the Q DAC. The complete timing diagram is shown in Figure 42. NIBBLE INTERFACE MODE In nibble mode, the DCI signal is a reference bit used for generating the data sampling clock and should be time aligned with the data. The FRAME signal indicates to which DAC the data is sent. When FRAME is high, data is sent to the I DAC. When FRAME is low, data is sent to the Q DAC. All four nibbles must be written to the device for proper operation. For 12-bit resolution devices, the data in the fourth nibble acts as a place holder for the data framing structure. The complete timing diagram is shown in Figure 43. MSB, …, LSB D15, D14, …, D0 D14, D12, D10, D8, D7, D5, D3, D1 D10, D8, D7, D5 In byte and nibble modes, the unused pins can be left floating. The data is accompanied by a reference bit (DCI) that is used to generate a double data rate (DDR) clock. In byte and nibble modes, a FRAME signal is required for controlling to which DAC the data is sent. All of the interface signals are time aligned. While there is a maximum skew requirement on the bus, there are no setup and hold times to be met. FIFO OPERATION The AD9122 contains a 2-channel, 16-bit wide, eight-word deep FIFO designed to relax the timing relationship between the data arriving at the DAC input ports and the internal DAC data rate clock. The FIFO acts as a buffer that absorbs timing variations between the data source and DAC, such as the clock-to-data variation of an FPGA or ASIC, which significantly increases the timing budget of the interface. Figure 44 shows the block diagram of the datapath through the FIFO. The data is latched into the device, is formatted, and is then written into the FIFO register determined by the FIFO write pointer. The value of the write pointer is incremented every time a new word is loaded into the FIFO. Meanwhile, data is read from the FIFO register determined by the read pointer and fed into the digital datapath. The value of the read pointer is updated every time data is read into the datapath from the FIFO. This happens at the data rate, that is, the DACCLK rate divided by the interpolation ratio. WORD INTERFACE MODE In word mode, the DCI signal is a reference bit used for generating the data sampling clock. Time align the DCI signal with the data. The I DAC data should correspond with DCI being high and the Q DAC data with DCI being low, as illustrated in Figure 41. DCI 08281-015 DATA[15:0] Q0 I1 Q1 I2 Q2 I3 Q3 Figure 41. Timing Diagram for Word Mode BYTE INTERFACE MODE In byte mode, the DCI signal is a reference bit used for generating the data sampling clock and should be time aligned with the data. The most significant byte of the data should correspond DCI DATA[15:0] QLSB I1MSB I1LSB Q1MSB Q1LSB I2MSB I2LSB Q2MSB Q2LSB FRAME Figure 42. Timing Diagram for Byte Mode DCI DATA[15:0] Q0N0 I1N3 I1N2 I1N1 I1N0 Q1N3 Q1N2 Q1N1 Q1N0 Q2N3 FRAME Figure 43. Timing Diagram for Nibble Mode Rev. 0 | Page 31 of 56 08281-017 08281-016 AD9122 32 BITS REG 0 REG 1 REG 2 DATA INPUT LATCH DATA ASSEMBLER REG 3 REG 4 REG 5 REG 6 REG 7 DCI WRITE POINTER 32 BITS READ POINTER ÷ INT DACCLK 08281-018 16 DATA PATHS 16 DACS Figure 44. Block Diagram of FIFO Valid data is transmitted through the FIFO as long as the FIFO does not overflow or become empty. Note that an overflow or empty condition of the FIFO is the same as the write pointer and read pointer being equal. When both pointers are equal, an attempt is made to read and write a single FIFO register simultaneously. This simultaneous register access leads to unreliable data transfer through the FIFO and must be avoided. Nominally, data is written to the FIFO at the same rate that data is read from the FIFO, which keeps the data level in the FIFO constant. If data is written to the FIFO faster than data is read, the data level in the FIFO increases. If the data is written to the device slower than data is read, the data level in the FIFO decreases. For optimum timing margin, the FIFO level should be maintained near half full, which is the same as maintaining a difference of four between the write pointer and read pointer values. To initialize the FIFO data level through the serial port, Bit 1 of Register 0x18 should be toggled from 0 to 1 and back. When the write to the register is complete, the FIFO data level is initialized. This method operates similar to the method previously described. When the initialization is triggered, the next time the read pointer becomes 0, the write pointer is set to the value of the FIFO start level (Register 0x17, Bits[2:0]) variable upon initialization. By default, this is 4 but can be programmed to a value of 0 to 7. The recommended procedure for a serial port FIFO data level initialization is as follows: • Request FIFO level reset by setting Register 0x18, Bit 1 to 1. • Verify the part acknowledges the request by ensuring Register 0x18, Bit 2 is 1. • Remove the request by setting Register 0x18, Bit 1 to 0. • Verify the part drops the acknowledge signal by ensuring Register 0x18, Bit 2 is 0. Resetting the FIFO Data Level To maximize the timing margin between the DCI input and the internal DAC data rate clock, the FIFO data level should be initialized prior to beginning data transmission. The value of the FIFO data level can be initialized in three ways; by resetting the device, by strobing the FRAME input, and via a write sequence to the serial port. The two preferred methods are by using of the FRAME signal and by issuing a command. As discussed in the Byte Interface Mode and Nibble Interface Mode sections, the FRAME input is used as a data select signal that indicates to which DACs the input data is written. The second function of the FRAME input is initializing the FIFO data level value. This is done by asserting the FRAME signal high for at least the time interval needed to load complete data to the I and Q DACs. This corresponds to one DCI period in word mode, two DCI periods in byte mode, and four DCI periods in nibble mode. When FRAME is asserted in this manner, the write pointer is set to 4 (by default or to the FIFO start level) the next time the read pointer becomes 0 (see Figure 45). READ POINTER 0 1 2 3 4 5 6 7 0 1 2 3 Monitoring the FIFO Status The FIFO initialization and status can be read from Register 0x18. This register provides information on the FIFO initialization method, and whether the initialization was successful. The MSB of Register 0x18 is a FIFO warning flag that can optionally trigger a device IRQ. This flag is an indication that the FIFO is close to emptying (FIFO level is 1) or overflowing (FIFO level is 7). This is an indication that data may soon be corrupted, and action should be taken. The FIFO data level can be read from Register 0x19 at any time. The serial port reported FIFO data level is denoted as a 7-bit thermometer code of the write counter state relative to the absolute read counter being at 0. The optimum FIFO data level of 4 is therefore reported as a value of 00001111 in the status register. It should be noted that, depending on the timing relationship between DCI and the main DACCLK, the FIFO level value can be off by ±1 count. Therefore, it is important to keep the difference between the read and write pointers to at least 2. FRAME FIFO WRITE RESETS WRITE POINTER 3 4 5 6 7 0 1 2 4 5 6 7 Figure 45. Timing of the FRAME Input vs. Write Pointer Value Rev. 0 | Page 32 of 56 08281-019 AD9122 INTERFACE TIMING The timing diagram for the digital interface port is shown in Figure 46. The sampling point of the data bus occurs about 350 ps after each edge of the DCI signal and has an uncertainty of ±300 ps, as illustrated by the sampling interval shown in Figure 46. The DATA and FRAME signals must be valid throughout this sampling interval. The DATA and FRAME signals may change at any time between sampling intervals. The setup (tS) and hold (tH) times with respect to the edges are shown in Figure 46. The minimum setup and hold times are shown in Table 13. tDATA tDATA In data rate mode, a second timing constraint between DCI and DACCLK must be met in addition to the DCI-to-DATA timing shown in Table 14. In data rate mode, only one FIFO slot is being used. The DCI to DACCLK timing restriction is required to prevent data being written to and read from the FIFO slot at the same time. The required timing between DCI and DACCLK is shown in Figure 47. tDATA DACCLK/ REFCLK SAMPLING INTERVAL DCI DCI SAMPLING INTERVAL SAMPLING INTERVAL tSDCI 08281-147 tHDCI DATA Figure 47. Timing Diagram for Input Data Port (Data Rate Mode) Table 14. Data Port Setup and Hold Times tH tH 08281-146 tS tS Figure 46. Timing Diagram for Input Data Ports Parameter tSDCI (MIN) tHDCI (MIN) Time (ps) −120 820 Table 13. Data Port Setup and Hold Times Parameter tS (MIN) tH (MIN) Time (ps) −50 650 The data interface timing can be verified by using the sample error detection (SED) circuitry. See the Interface Timing Validation section for details. Rev. 0 | Page 33 of 56 AD9122 DIGITAL DATAPATH The block diagram in Figure 48 shows the functionality of the digital datapath. The digital processing includes a premodulation block, three half-band interpolation filters, a quadrature modulator with a fine resolution NCO, phase and offset adjustment blocks, and an inverse sinc filter. PHASE AND OFFSET ADJUST Half-Band Filter 1 (HB1) HB1 has four modes of operation, as shown in Figure 49. The shape of the filter response is identical in each of the four modes. The four modes are distinguished by two factors, the filter center frequency and whether or not the input signal is modulated by the filter. MODE 0 MODE 1 MODE 2 MODE 3 0 PREMOD HB1 HB2 HB3 SINC–1 Figure 48. Block Diagram of Digital Datapath 08281-020 –20 The digital datapath accepts I and Q data streams and processes them as a quadrature data stream. The signal processing blocks can be used when the input data stream is represented as complex data. The datapath can be used to process an input data stream representing two independent real data streams as well, but the functionality is somewhat restricted. The premodulation block can be used. As well as, any of the nonshifted interpolation filter modes. See the Premodulation section for more details. (dB) –40 –60 –80 –100 0 0.2 0.4 0.6 0.8 1.0 (× fIN1) 1.2 1.4 1.6 1.8 2.0 08281-021 PREMODULATION The half-band interpolation filters have selectable pass bands that allow the center frequencies to be moved in increments of ½ of their input data rate. The premodulation block provides a digital upconversion of the incoming waveform by ½ of the incoming data rate, fDATA. This can be used to frequency shift baseband input data to the center of the interpolation filters pass band. Figure 49. HB1 Filter Modes INTERPOLATION FILTERS The transmit path contains three interpolation filters. Each of the three interpolation filters provides a 2× increase in output data rate. The half-band (HB) filters can be individually bypassed or cascaded to provide 1×, 2×, 4×, or 8× interpolation ratios. Each of the half-band filter stages offers a different combination of bandwidths and operating modes. The bandwidth of the three half-band filters with respect to the data rate at the filter input is as follows: • • • Bandwidth of HB1 = 0.8 × fIN1 Bandwidth of HB2 = 0.5 × fIN2 Bandwidth of HB3 = 0.4 × fIN3 As is shown in Figure 49, the center frequency in each mode is offset by ½ of the input data rate (fIN1) of the filter. Mode 0 and Mode 1 do not modulate the input signal. Mode 2 and Mode 3 modulate the input signal by fIN1. When operating in Mode 0 and Mode 2, the I and Q paths operate independently and no mixing of the data between channels occurs. When operating in Mode 1 and Mode 3, mixing of the data between the I and Q paths occurs; therefore, the data input into the filter is assumed complex. Table 15 summarizes the HB1 modes. Table 15. HB1 Filter Mode Summary Mode 0 1 2 3 fCENTER DC fIN/2 fIN 3fIN/2 fMOD None None fIN fIN Input Data Real or complex Complex Real or complex Complex The usable bandwidth is defined as the frequency over which the filters have a pass-band ripple of less than ±0.001 dB and an image rejection of greater than +85 dB. As is discussed in the Half-Band Filter 1 (HB1) section, the image rejection usually sets the usable bandwidth of the filter, not the pass-band flatness. The half-band filters operate in several modes, providing programmable pass-band center frequencies as well as signal modulation. The HB1 filter has four modes of operation and the HB2 and HB3 filters each have eight modes of operation. Rev. 0 | Page 34 of 56 AD9122 Figure 50 shows the pass-band filter response for HB1. In most applications, the usable bandwidth of the filter is limited by the image suppression provided by the stop-band rejection and not by the pass-band flatness. Table 16 shows the pass-band flatness and stop-band rejection the HB1 filter supports at different bandwidths. 0.02 MODE 0 0 0 –20 –0.02 (dB) Half-Band Filter 2 (HB2) HB2 has eight modes of operation, as shown in Figure 51 and Figure 52. The shape of the filter response is identical in each of the eight modes. The eight modes are distinguished by two factors, the filter center frequency and whether the input signal is modulated by the filter. MODE 2 MODE 4 MODE 6 –0.04 (dB) 08281-022 –40 –0.06 –60 –0.08 –80 –0.10 0 0.04 0.08 0.12 0.16 0.20 0.24 0.28 0.32 0.36 0.40 (× fIN1) –100 0 0.2 0.4 0.6 0.8 1.0 (× fIN2) 1.2 1.4 1.6 1.8 2.0 08281-023 08281-024 Figure 50. Pass-Band Detail of HB1 Figure 51. HB2, Even Filter Modes MODE 1 0 MODE 3 MODE 5 MODE 7 Table 16. HB1 Pass-Band and Stop-Band Performance by Bandwidth Bandwidth (% of fIN1) 80 80.4 81.2 82.0 83.6 85.6 Pass-Band Flatness (dB) 0.001 0.0012 0.0033 0.0076 0.0271 0.1096 Stop-Band Rejection (dB) 85 80 70 60 50 40 –20 (dB) –40 –60 –80 –100 0 0.2 0.4 0.6 0.8 1.0 (× fIN2) 1.2 1.4 1.6 1.8 2.0 Figure 52. HB2, Odd Filter Modes As shown in Figure 51 and Figure 52, the center frequency in each mode is offset by ¼ of the input data rate (fIN2) of the filter. Mode 0 through Mode 3 do not modulate the input signal. Mode 4 through Mode 7 modulate the input signal by fIN2. When operating in Mode 0 and Mode 4, the I and Q paths operate independently and no mixing of the data between channels occurs. When operating in the other six modes, mixing of the data between the I and Q paths occurs; therefore, the data input to the filter is assumed complex. Rev. 0 | Page 35 of 56 AD9122 Table 17 summarizes the HB2 and HB3 modes. Table 17. HB2 and HB3 Filter Mode Summary Mode 0 1 2 3 4 5 6 7 fCENTER DC fIN/8 fIN/4 3fIN/8 fIN/2 5fIN/8 3fIN/4 7fIN/8 fMOD None None None None fIN fIN fIN fIN Input Data Real or complex Complex Complex Complex Real or complex Complex Complex Complex Half-Band Filter 3 (HB3) HB3 has eight modes of operation that function the same as HB2. The primary difference between HB2 and HB3 are the filter bandwidths. 0.02 0 –0.02 (dB) –0.04 –0.06 Figure 53 shows the pass-band filter response for HB2. In most applications, the usable bandwidth of the filter is limited by the image suppression provided by the stop-band rejection and not by the pass-band flatness. Table 18 shows the pass-band flatness and stop-band rejection the HB2 filter supports at different bandwidths. 0.02 –0.08 –0.10 0 0.04 0.08 0.12 0.16 0.20 0.24 0.28 0.32 0.36 0.40 (× fIN3) 08281-026 Figure 54. Pass-Band Detail of HB3 0 –0.02 (dB) –0.04 Figure 54 shows the pass-band filter response for HB3. In most applications, the usable bandwidth of the filter is limited by the image suppression provided by the stop-band rejection and not by the pass-band flatness. Table 19 shows the pass-band flatness and stop-band rejection the HB3 filter supports at different bandwidths. Table 19. HB3 Pass-Band and Stop-Band Performance by Bandwidth Bandwidth (% of fIN3) 40 40.8 42.4 45.6 49.8 55.6 Pass-Band Flatness (dB) 0.001 0.0014 0.002 0.0093 0.03 0.1 Stop-Band Rejection (dB) 85 80 70 60 50 40 –0.06 –0.08 –0.10 0 0.04 0.08 0.12 0.16 (× fIN2) 0.20 0.24 0.28 0.32 08281-025 Figure 53. Pass-Band Detail of HB2 Table 18. HB2 Pass-Band and Stop-Band Performance by Bandwidth Bandwidth (% of fIN2) 50 50.8 52.8 56.0 60 64.8 Pass-Band Flatness (dB) 0.001 0.0012 0.0028 0.0089 0.0287 0.1877 Stop-Band Rejection (dB) 85 80 70 60 50 40 Rev. 0 | Page 36 of 56 AD9122 I DATA INTERPOLATION COSINE FTW[31:0] NCO PHASE OFFSET [15:0] NCO SINE – + –1 OUT_I OUT_Q SPECTRAL INVERSION 0 1 Q DATA INTERPOLATION Figure 55. Digital Quadrature Modulator Block Diagram NCO MODULATION The digital quadrature modulator makes use of a numerically controlled oscillator, a phase shifter, and a complex modulator to provide a means for modulating the signal by a programmable carrier signal. A block diagram of the digital modulator is shown in Figure 55. The fine modulation provided by the digital modulator, in conjunction with the coarse modulation of the interpolation filters and premodulation block, allows the signal to be placed anywhere in the output spectrum with very fine frequency resolution. The quadrature modulator is used to mix the carrier signal generated by the NCO with the I and Q signal. The NCO produces a quadrature carrier signal to translate the input signal to a new center frequency. A complex carrier signal is a pair of sinusoidal waveforms of the same frequency, offset 90° from each other. The frequency of the complex carrier signal is set via FTW[31:0] in Register 0x30 through Register 0x33. The NCO operating frequency, fNCO, is at either fDATA (HB1 bypassed) or twice fDATA (HB1 enabled). The frequency of the complex carrier signal can be set from dc up to fNCO. The frequency tuning word (FTW) is calculated as Given these four parameters, the first step in configuring the datapath is to verify that the device supports the bandwidth requirements. The modes of the interpolation filters are then chosen. Finally, any additional frequency offset requirements are determined and applied with premodulation and NCO modulation. Determining Datapath Signal Bandwidth The available signal bandwidth of the datapath is dependent on the center frequency of the output signal in relation to the center frequency of the interpolation filters used. Signal center frequencies offset from the center frequencies of the half-band filters lower the available signal bandwidth. When correctly configured, the available complex signal bandwidth for 2× interpolation is always 80% of the input data rate. The available signal bandwidth for 4× interpolation vs. output frequency varies between 50% and 80% of the input data rate, as shown in Figure 56. Note that in 4× interpolation mode, fDAC = 4 × fDATA; therefore, the data shown in Figure 56 repeats four times from dc to fDAC. HB1 AND HB2 0.8 BANDWIDTH/ fDATA FTW = f CARRIER × 2 32 f NCO The generated quadrature carrier signal is mixed with the I and Q data. The quadrature products are then summed into the I and Q data paths, as shown in Figure 55. 0.5 HB2 AND HB3 0.3 Updating the Frequency Tuning Word The frequency tuning word registers are not updated immediately upon writing as other configuration registers do. After loading the FTW registers with the desired values, Bit 0 of Register 0x36 must transition from 0 to 1 for the new FTW to take effect. 0.2 0.4 0.6 0.8 1.0 08281-028 08281-027 fOUT/fDATA Figure 56. Signal Bandwidth vs. Center Frequency of the Output Signal, 4× Interpolation DATAPATH CONFIGURATION Configuring the AD9122 datapath starts with the application requirements of the input data rate, the interpolation ratio, the output signal bandwidth, and the output signal center frequency. Configuring 4× interpolation using the HB2 and HB3 filters can lower the power consumption of the device at the expense of bandwidth. The lower curve in Figure 56 shows that the supported bandwidth in this mode varies from 30% to 50% of fDATA. Rev. 0 | Page 37 of 56 AD9122 The available signal bandwidth for 8× interpolation vs. output frequency varies between 50% and 80% of the input data rate, as shown in Figure 57. Note that in 8× interpolation mode, fDAC = 8 × fDATA; therefore, the data shown in Figure 57 repeats eight times from dc to fDAC. HB1, HB2, AND HB3 0.8 DETERMINING INTERPOLATION FILTER MODES Table 20 shows the recommended interpolation filter settings for a variety of filter interpolation factors, filter center frequencies, and signal modulation. The interpolation modes were chosen based on the final center frequency of the signal and by determining the frequency shift of the signal required. When these are known, and put in terms of the input data rate (fDATA), the filter configuration that comes closest to matching is chosen from Table 20. BANDWIDTH/ fDATA 0.6 0.5 0.25 0.50 0.75 1.00 fOUT/fDATA Figure 57. Signal Bandwidth vs. Center Frequency of the Output Signal, 8× Interpolation Table 20. Recommended Interpolation Filter Modes (Register 0x1C through Register 0x1E) Interpolation Factor 8 8 82 8 8 8 8 8 8 8 8 8 8 8 8 8 4 43 4 4 4 4 4 4 2 2 2 2 1 HB1[1:0] 00 (0) 01 (1) 10 (2) 11 (3) 00 (0) 01 (1) 10 (2) 11 (3) 00 (0) 01 (1) 10 (2) 11 (3) 00 (0) 01 (1) 10 (2) 11 (3) 00 (0) 01 (1) 10 (2) 11 (3) 00 (0) 01 (1) 10 (2) 11 (3) 00 (0) 01 (1) 10 (2) 11 (3) Filter Modes HB2[5:0] 000000 001001 010010 011011 100100 101101 110110 111111 000000 001001 010010 011011 100100 101101 110110 111111 000000 001001 010010 011011 100100 101101 110110 111111 Bypass Bypass Bypass Bypass 08281-029 0.1 0.4 0.6 0.9 HB3[5:0] 000000 000000 001001 001001 010010 010010 011011 011011 100100 100100 101101 101101 110110 110110 111111 111111 Bypass Bypass Bypass Bypass Bypass Bypass Bypass Bypass Bypass Bypass Bypass Bypass fSIGNAL Modulation DC DC1 fDATA fDATA1 2fDATA 2fDATA1 3fDATA 3 fDATA1 4fDATA 4fDATA1 5fDATA 5fDATA1 6fDATA 6fDATA1 7fDATA 7fDATA1 DC DC1 fDATA fDATA1 2fDATA 2fDATA1 3fDATA 3fDATA1 DC DC1 fDATA fDATA1 fCENTER Shift 0 fDATA/2 fDATA 3fDATA/2 2fDATA 5fDATA/2 3fDATA 7fDATA/2 4fDATA 9fDATA/2 5fDATA 11fDATA/2 6fDATA 13fDATA/2 7fDATA 15fDATA/2 0 fDATA/2 fDATA 3fDATA/2 2fDATA 5fDATA/2 3fDATA 7fDATA/2 0 fDATA/2 fDATA 3fDATA/2 When HB1 Mode 1 or Mode 3 is used, enabling premodulation provides an addition frequency translation of the input signal by fDATA/2, which centers a baseband input signal in the filter pass band. This configuration was used in the 8× interpolation without NCO example. Also, see the 8× Interpolation Without NCO section. 3 This configuration was used in the 4× interpolation with NCO example. Also, see the 4× Interpolation With NCO section. 2 Rev. 0 | Page 38 of 56 AD9122 DATAPATH CONFIGURATION EXAMPLE 8× Interpolation Without NCO Given the following: fDATA = 100 MSPS 8× interpolation fBW = 75 MHz fCENTER = 100 MHz The desired 75 MHz of bandwidth is 75% of fDATA. In this case, the ratio of fOUT/fDATA = 100/100 = 1.0. From Figure 57, the bandwidth supported at fDATA is 0.8, which verifies that the AD9122 supports the bandwidth required in this configuration. The signal center frequency is fDATA, and assuming the input signal is at baseband, the frequency shift required is also fDATA. Choosing the third row (highlighted by the superscripted number two) of the IF column from Table 20 selects filter modes that give a center frequency of fDATA and a frequency translation of fDATA. The selected modes for the three half-band filters are: HB1, Mode 2; HB2, Mode 2; and HB3, Mode 1. Figure 58 shows how the signal propagates through the interpolation filters. Because 2 × fIN1 = fIN2 and 2 × fIN2 = fIN3, the signal appears frequency scaled by ½ into each consecutive stage. The output signal band spans 0.15 to 0.35 of fIN3 (400 MHz). Therefore, the output frequency supported is 60 MHz to 140 MHz, which covers the 75 MHz bandwidth centered at 100 MHz, as desired. 4× Interpolation With NCO Given the following: fDATA = 250 MSPS 4× interpolation fBW = 140 MHz fCENTER = 175 MHz The desired 140 MHz of bandwidth is 56% of fDATA. As shown in Figure 56, the value at 0.7 × fDATA is 0.6. This is calculated as 0.8 − 2(0.7 − 0.6) = 0.6. This verifies that the AD9122 supports a bandwidth of 60% of fDATA, which exceeds the required 56%. The signal center frequency is 0.7 × fDATA, and assuming the input signal is at baseband, the frequency shift required is also 0.7 × fDATA. Choosing the second row in the IF column in the 4× interpolation section in Table 20 selects the filter modes that give a center frequency of fDATA/2 and no frequency translation. The selected modes for the three half-band filters are HB1, Mode 1; HB2, Mode 1; and HB3, bypassed. Because Mode 1 of HB1 was selected, the premodulation block should be enabled. This provides fDATA/2 modulation, which centers the baseband input data at the center frequency of HB1. The digital modulator can be used to provide the final frequency translation of 0.2 × fDATA to place the output signal at 0.7 × fDATA, as desired. The formula for calculating the FTW of the NCO is: FTW = f CARRIER f NCO × 2 32 where: fCARRIER = 0.2 × fDATA. fNCO = 2 × fDATA. Therefore, FTW = 232/10. 0 2 0 1 3 HB1 0.1 0.4 0.6 –0.5 0 0.5 1.0 1.5 2.0 × fIN1 HB2 0 1 2 3 4 5 6 7 0.25 0.75 1.25 1.75 –0.5 0 0.3 0.5 0.7 1.0 1.5 2.0 × fIN2 0 1 2 3 HB3 4 5 6 7 –0.2 0.2 0.3 0.7 0.15 0.35 Figure 58. Signal Propagation for 8× Interpolation (fDATA Modulation) Rev. 0 | Page 39 of 56 08281-030 –0.5 0 0.5 1.0 1.5 2.0 × fIN3 AD9122 DATA RATES vs. INTERPOLATION MODES Table 22 summarizes the maximum bus speed (fBUS), supported input data rates, and signal bandwidths with the various combinations of bus width modes and interpolation rates. The maximum bus speed in any mode is 1200 MHz. The maximum DAC update rate (fDAC) in any mode is 1200 MHz. The real signal bandwidth supported is a fraction of the input data rate, which depends on the interpolation filters (HB1, HB2, or HB3) selected. The complex signal bandwidth supported is twice the real signal bandwidth. In general, 2× interpolation is best supported by enabling HB1, and 4× interpolation is best supported enabling HB1 and HB2. In some cases, power dissipation can be lowered by avoiding HB1. If the bandwidth required is low enough, 2× interpolation can be supported by using HB2, and 4× interpolation can be supported by using HB2 and HB3. In practice, this modulation results in mixing functions as shown in Table 21. Table 21. Modulation Mixing Sequences Modulation fS/2 fS/4 3 fS/4 fS/8 Mixing Sequence I = I, −I, I, −I, … Q = Q, −Q, Q, −Q, … I = I, Q, −I, −Q, … Q = Q, −I, −Q, I, … I = I, −Q, −I, Q, … Q = Q, I, −Q, −I, … I = I, r(I + Q), Q, r(−I + Q), −I, −r(I + Q), −Q, r(I − Q), … Q = Q, r(Q − I), −I, −r(Q + I), −Q, r(−Q + I),I, r(Q + I), … Note that r = 2 2 COARSE MODULATION MIXING SEQUENCES The coarse digital quadrature modulation occurs within the interpolation filters. The modulation shifts the frequency spectrum of the incoming data by the frequency offset selected. The frequency offsets available are multiples of the input data rate. The modulation is equivalent to multiplying the quadrature input signal by a complex carrier signal, C(t), of the form C(t) = cos(ωct) + j sin(ωct) As shown in Table 21, the mixing functions of most of the modes crosscouple samples between the I and Q channels. The I and Q channels only operate independently in fS/2 mode. This means that real modulation using both the I and Q DAC outputs can only be done in fS/2 mode. All other modulation modes require complex input data and produce complex output signals. Table 22. Summary of Data Rates and Bandwidths vs. Interpolation Modes Bus Width Nibble (4 Bits) HB3 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 1 Filter Modes HB2 HB1 0 0 0 1 1 0 1 1 1 0 1 1 0 0 0 1 1 0 1 1 1 0 1 1 0 0 0 1 1 0 1 1 1 0 1 1 fBUS (Mbps) 1200 1200 1200 1200 1200 1200 1200 1200 1200 1200 1200 600 1200 800 1200 600 600 300 fDATA (Mbps) 150 150 150 150 150 150 300 300 300 300 300 150 600 400 600 300 300 150 Real Signal Bandwidth (MHz) 75 60 37.5 60 37.5 60 150 120 75 120 75 60 300 160 150 120 75 60 fDAC (MHz) 150 300 300 600 600 1200 300 600 600 1200 1200 1200 600 800 1200 1200 1200 1200 Byte (8 Bits) Word (16 Bits) Rev. 0 | Page 40 of 56 AD9122 QUADRATURE PHASE CORRECTION The purpose of the quadrature phase correction block is to enable compensation of the phase imbalance of the analog quadrature modulator following the DAC. If the quadrature modulator has a phase imbalance, the unwanted sideband appears with significant energy. Tuning the quadrature phase adjust value can optimize image rejection in single sideband radios. Ordinarily, the I and Q channels have an angle of precisely 90° between them. The quadrature phase adjustment is used to change the angle between the I and Q channels. When the I Phase Adj[9:0] is set to 1000000000b, the I DAC output moves approximately 1.75° away from the Q DAC output, creating an angle of 91.75° between the channels. When the I Phase Adj[9:0] is set to 0111111111b, the I DAC output moves approximately 1.75° toward the Q DAC output, creating an angle of 88.25° between the channels. The Q Phase Adj[9:0] works in a similar fashion. When the Q Phase Adj[9:0] is set to 1000000000b, the Q DAC output moves approximately 1.75° away from the I DAC output, creating an angle of 91.75° between the channels. When the Q Phase Adj[9:0] is set to 0111111111b, the Q DAC output moves approximately 1.75° toward the I DAC output, creating an angle of 88.25° between the channels. Based on these two endpoints, the combined resolution of the phase compensation register is approximately 3.5°/1024 or 0.00342° per code. 20 0 15 IOUTxP (mA) 5 IOUTxN (mA) 08281-032 08281-031 10 10 5 15 0 0x0000 0x4000 0x8000 DAC OFFSET VALUE 0xC000 20 0xFFFF Figure 59. DAC Output Currents vs. DAC Offset Value INVERSE SINC FILTER The inverse sinc (sinc−1) filter is a nine-tap FIR filter. The composite response of the sinc−1 and the sin(x)/x response of the DAC is shown in Figure 59. The composite response has less than ±0.05 dB pass-band ripple up to a frequency of 0.4 × fDACCLK. To provide the necessary peaking at the upper end of the pass band, the inverse sinc filters shown have an intrinsic insertion loss of about 3.2 dB. Figure 60 shows the composite frequency response. –3.0 –3.2 DC OFFSET CORRECTION The dc value of the I datapath and the Q datapath can be independently controlled by adjusting the I DAC Offset[15:0] and Q DAC Offset[15:0] values in Register 0x3C through Register 0x3F. These values are added directly to the datapath values. Care should be taken not to overrange the transmitted values. Figure 59 shows how the DAC offset current varies as a function of the I DAC Offset[15:0] and the Q DAC Offset[15:0] values. With the digital inputs fixed at midscale (0x0000, twos complement data format), Figure 59 shows the nominal IOUTP and IOUTN currents as the DAC offset value is swept from 0 to 65535. Because IOUTP and IOUTN are complementary current outputs, the sum of IOUTP and IOUTN is always 20 mA. MAGNITUDE (dB) –3.4 –3.6 –3.8 –4.0 0 0.1 0.2 0.3 0.4 0.5 fOUT/fDAC Figure 60. Sample Composite Responses of the Sinc−1 Filter with Sin(x)/x Roll-Off The sinc−1 filter is enabled by default. It can be bypassed by setting the bypass sinc−1 bit (Register 0x1B, Bit 6). Rev. 0 | Page 41 of 56 AD9122 DAC INPUT CLOCK CONFIGURATIONS DAC INPUT CLOCK CONFIGURATIONS The AD9122 DAC sample clock (DACCLK) can be sourced directly or by clock multiplying. Clock multiplying employs the on-chip phased-locked loop (PLL) that accepts a reference clock operating at a submultiple of the desired DACCLK rate, most commonly the data input frequency. The PLL then multiplies the reference clock up to the desired DACCLK frequency, which can then be used to generate all the internal clocks required by the DAC. The clock multiplier provides a high quality clock that meets the performance requirements of most applications. Using the on-chip clock multiplier removes the burden of generating and distributing the high speed DACCLK. The second mode bypasses the clock multiplier circuitry and allows DACCLK to be sourced directly to the DAC core. This mode enables the user to source a very high quality clock directly to the DAC core. Sourcing the DACCLK directly through the REFCLKP, REFCLKN, DACCLKP, and DACCLKN pins may be necessary in demanding applications that require the lowest possible DAC output noise, particularly when directly synthesizing signals above 150 MHz. when the clock input signal is between 800 mV p-p differential and 1.6 V p-p differential. Whether using the on-chip clock multiplier or sourcing the DACCLK, directly, it is necessary that the input clock signal to the device has low jitter and fast edge rates to optimize the DAC noise performance. Direct Clocking Direct clocking with a low noise clock produces the lowest noise spectral density at the DAC outputs. To select the differential CLK inputs as the source for the DAC sampling clock, set the PLL enable bit (Register 0x0A, Bit[7]) to 0. This powers down the internal PLL clock multiplier and selects the input from the DACCLKP and DACCLKN pins as the source for the internal DAC sample clock. The device also has duty-cycle correction circuitry and differential input level correction circuitry. Enabling these circuits can provide improved performance in some cases. The control bits for these functions can be found in Register 0x08. See Table 11 for complete details. Clock Multiplication The on-chip PLL clock multiplier circuit can be used to generate the DAC sample rate clock from a lower frequency reference clock. When the PLL enable bit (Register 0x0A, Bit[7]) is set to 1, the clock multiplication circuit generates the DAC sample clock from the lower rate REFCLK input. The functional diagram of the clock multiplier is shown in Figure 62. The clock multiplication circuit operates such that the VCO outputs a frequency, fVCO, equal to the REFCLK input signal frequency multiplied by N1 × N0. fVCO = fREFCLK × (N1 × N0) The DAC sample clock frequency, fDACCLK, is equal to fDACCLK = fREFCLK × N1 Driving the DACCLK and REFCLK Inputs The REFCLK and DACCLK differential inputs share similar clock receiver input circuitry. Figure 61 shows a simplified circuit diagram of the input. The on-chip clock receiver has a differential input impedance of about 10 kΩ. It is self biased to a commonmode voltage of about 1.25 V. The inputs can be driven by direct coupling differential PECL or LVDS drivers. The inputs can also be ac-coupled if the driving source cannot meet the input compliance voltage of the receiver. DACCLKP, REFCLKP 5kΩ 5kΩ DACCLKN, REFCLKN 1.25V 08281-033 Figure 61. Clock Receiver Input Equivalent Circuit The minimum input drive level to either of the clock inputs is 200 mV p-p differential. The optimal performance is achieved 0x06[7:6] PLL LOCKED PLL LOCKED LOST REFCLKP/REFCLKN (PIN 69 AND PIN 70) The output frequency of the VCO must be chosen to keep fVCO in the optimal operating range of 1.0 GHz to 2.1 GHz. The frequency of the reference clock and the values of N1 and N0 must be chosen so that the desired DACCLK frequency can be synthesized and the VCO output frequency is in the correct range. ADC 0x0E[3:0] VCO CONTROL VOLTAGE PHASE DETECTION LOOP FILTER VCO ÷N1 0x0D[1:0] N1 ÷N0 0x0D[3:2] N0 DACCLK 0x0D[7:6] ÷N2 N2 08281-034 DACCLKP/DACCLKN (PIN 2 AND PIN 3) 0x0A[7] PLL ENABLE PC_CLK Figure 62. PLL Clock Multiplication Circuit Rev. 0 | Page 42 of 56 AD9122 PLL Settings There are three settings for the PLL circuitry that should be programmed to their nominal values. The PLL values shown in Table 23 are the recommended settings for these parameters. Table 23. PLL Settings PLL SPI Control PLL Loop Bandwidth[1:0] PLL Charge Pump Current[4:0] PLL Cross Control Enable Address Register 0x0C 0x0C 0x0D Bit [7:6] [4:0] [4] Optimal Setting 11 00001 1 Manual VCO Band Select The device also has a manual band select mode (PLL manual enable, Register 0x0A, Bit[6] = 1) that allows the user to select the VCO tuning band. When in manual mode, the VCO band is set directly with the value written to the manual VCO band, (Register 0x0A, Bit[5:0]). To properly select the VCO band, follow these steps: 1. 2. 3. 4. Put the device in manual band select mode. Sweep the VCO band over a range of bands that result in the PLL being locked. For each band, verify that the PLL is locked and read the PLL using the VCO control voltage (Register 0x0E[3:0]). Select the band that results in the control voltage being closest to the center of the range (that is, 0000 or 1000). See Table 24 for more details. The resulting VCO band should be the optimal setting for the device. Write this band to the manual VCO band (Register 0x0A[5:0]) value. If desired, an indication of where the VCO is within the operating frequency band can be determined by querying the VCO control voltage. Table 24 shows how to interpret the PLL VCO control voltage (Register 0x0E, Bits[2:0]) value. Configuring the VCO Tuning Band The PLL VCO has a valid operating range from approximately 1.0 GHz to 2.1 GHz covered in 63 overlapping frequency bands. For any desired VCO output frequency, there may be several valid PLL band select values. The frequency bands of a typical device are shown in Figure 63. Device-to-device variations and operating temperature affect the actual band frequency range. Therefore, it is required that the optimal PLL band select value be determined for each individual device. 5. Automatic VCO Band Select The device has an automatic VCO band select feature on chip. Using the automatic VCO band select feature is a simple and reliable method of configuring the VCO frequency band. This feature is enabled by writing 0x80 to Register 0x0A. When this value is written, the device executes an automated routine that determines the optimal VCO band setting for the device. The setting selected by the device ensures that the PLL remains locked over the full −40°C to +85°C operating temperature range of the device without further adjustment. (The PLL remains locked over the full temperature range even if the temperature during initialization is at one of the temperature extremes.) 0 4 8 12 16 20 PLL BAND Table 24. VCO Control Voltage Range Indications VCO Control Voltage 0111 0110 0101 0100 0011 0010 0001 0000 1000 1001 1010 1011 1100 1101 1110 1111 Indication Move to higher VCO Band VCO is operating in the higher end of frequency band VCO is operating within an optimal region of the frequency band VCO is operating in the lower end of frequency band Move to lower VCO Band 24 28 32 36 40 44 48 52 56 60 1000 1200 1400 1600 1800 2000 2200 08281-035 VCO FREQUENCY (MHz) Figure 63. PLL Lock Range Over Temperature for a Typical Device Rev. 0 | Page 43 of 56 AD9122 ANALOG OUTPUTS TRANSMIT DAC OPERATION Figure 64 shows a simplified block diagram of the transmit path DACs. The DAC core consists of a current source array, a switch core, digital control logic, and full-scale output current control. The DAC full-scale output current (IOUTFS) is nominally 20 mA. The output currents from the IOUT1P/IOUT2P and IOUT1N/ IOUT2N pins are complementary, meaning that the sum of the two currents always equals the full-scale current of the DAC. The digital input code to the DAC determines the effective differential current delivered to the load. 1.2V 5kΩ REFIO 0.1µF FSADJ 10kΩ Q DAC FS ADJUST REGISTER 0x44 CURRENT SCALING IOUT2N Q DAC 08281-037 For nominal values of VREF (1.2 V), RSET (10 kΩ), and DAC gain (512), the full-scale current of the DAC is typically 20.16 mA. The DAC full-scale current can be adjusted from 8.66 mA to 31.66 mA by setting the DAC gain parameter setting as shown in Figure 65. 35 30 25 20 I DAC FS ADJUST REGISTER 0x40 I DAC IFS (mA) IOUT1P IOUT1N 15 10 5 0 0 200 400 600 800 1000 DAC GAIN CODE IOUT2P Figure 64. Simplified Block Diagram of DAC Core Figure 65. DAC Full-Scale Current vs. DAC Gain Code The DAC has a 1.2 V band gap reference with an output impedance of 5 kΩ. The reference output voltage appears on the REFIO pin. When using the internal reference, the REFIO pin should be decoupled to AVSS with a 0.1 μF capacitor. Only use the internal reference for external circuits that draw dc currents of 2 μA or less. For dynamic loads or static loads greater than 2 μA, buffer the REFIO pin. If desired, an external reference (between 1.10 V and 1.30 V) can be applied to the REFIO pin. The internal reference can either be overdriven or powered down by setting Register 0x43, Bit [5]. A 10 kΩ external resistor, RSET, must be connected from the RESET pin to AVSS. This resistor, along with the reference control amplifier, sets up the correct internal bias currents for the DAC. Because the full-scale current is inversely proportional to this resistor, the tolerance of RSET is reflected in the full-scale output amplitude. The full-scale current equation, where the DAC gain is set individually for the I and Q DACs in Register 040 and Register 044, respectively, follows: I FS = VREF ⎛ 3 ⎞ × ⎜ 72 + ⎛ × DAC gain ⎞ ⎟ ⎜ ⎟ R SET ⎝ ⎠⎠ ⎝ 16 Transmit DAC Transfer Function The output currents from the IOUT1P/IOUT2P and IOUT1N/ IOUT2N pins are complementary, meaning that the sum of the two currents always equals the full-scale current of the DAC. The digital input code to the DAC determines the effective differential current delivered to the load. IOUT1P/IOUT2P provide maximum output current when all bits are high. The output currents vs. DACCODE for the DAC outputs are expressed as DACCODE ⎤ I OUTP = ⎡ ⎢ ⎥ × I OUTFS 2N ⎣ ⎦ I OUTN = I OUTFS − I OUTP 08281-036 (1) (2) where DACCODE = 0 to 2N − 1. Transmit DAC Output Configurations The optimum noise and distortion performance of the AD9122 is realized when it is configured for differential operation. The common-mode error sources of the DAC outputs are significantly reduced by the common-mode rejection of a transformer or differential amplifier. These common-mode error sources include even-order distortion products and noise. The enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases and/or its amplitude increases. This is due to the first-order cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough, and noise. Rev. 0 | Page 44 of 56 AD9122 Figure 66 shows the most basic DAC output circuitry. A pair of resistors, RO, is used to convert each of the complementary output currents to a differential voltage output, VOUT. Because the current outputs of the DAC are high impedance, the differential driving point impedance of the DAC outputs, ROUT, is equal to 2 × RO. Figure 67 illustrates the output voltage waveforms. IOUT1P RO VOUTI RO IOUT1N –90 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 –60 –65 10mA 20mA 30mA –70 IMD (dBc) VIP + –75 –80 VIN – –85 IOUT2P RO VQP + VCMD (V) VOUTQ 08281-038 Figure 68. IMD vs. Output Common-Mode Voltage (fOUT = 61 MHz, RLOAD = 50 Ω differential, IFS = 10 mA, 20 mA, and 30 mA) –50 –55 –60 10mA 20mA 30mA RO IOUT2N VQN – Figure 66. Basic Transmit DAC Output Circuit VPEAK VCM IMD (dBc) –65 –70 –75 –80 –85 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VCMD (V) 08281-169 0 VN VP VOUT –VPEAK Figure 67. Voltage Output Waveforms The common-mode signal voltage, VCM, is calculated as VCM I = FS × RO 2 08281-039 Figure 69. IMD vs. Output Common-Mode Voltage (fOUT = 161 MHz, RLOAD = 50 Ω differential, IFS = 10 mA, 20 mA, and 30 mA) The peak output voltage, VPEAK, is calculated as VPEAK = IFS × RO With this circuit configuration, the single-ended peak voltage is the same as the peak differential output voltage. AUXILIARY DAC OPERATION The AD9122 have two auxiliary DACs, one associated with the I path and one associated with the Q path. These auxiliary DACs can be used to compensate for dc offsets in the transmitted signal. Each auxiliary DAC has a single-ended current that can sink or source current into either the P or N output of the associated transmit DAC. The auxiliary DAC structure is shown in Figure 70. VB Transmit DAC Linear Output Signal Swing To achieve optimum performance, the DAC outputs have a linear output compliance voltage range that must be adhered to. The linear output signal swing is dependent on the full-scale output current, IOUTFS, and the common-mode level of the output. Figure 68 and Figure 69 show the IMD performance vs. the common-mode voltage at the different full-scale currents and output frequencies. AUXDAC[4:0] AUXDAC DIRECTION AUXDAC SIGN I DAC IOUTN Figure 70. Auxiliary DAC Structure Rev. 0 | Page 45 of 56 08281-040 IOUTP 08281-168 AD9122 The control registers for controlling the I and Q auxiliary DACs are in Register 0x42, Register 0x43, and Register 0x46. Interfacing to Modulators The AD9122 interfaces to the ADL537x family of modulators with a minimal number of components. An example of the recommended interface circuitry is shown in Figure 71. The baseband inputs of the ADL537x family require a dc bias of 500 mV. The nominal midscale output current on each output of the DAC is 10 mA (½ the full-scale current). Therefore, a single 50 Ω resistor to ground from each of the DAC outputs results in the desired 500 mV dc common-mode bias for the inputs to the ADL537x. The signal level can be reduced through the addition of the load resistor in parallel with the modulator inputs. The peak-to-peak voltage swing of the transmitted signal is Figure 73 shows a fifth-order, low-pass filter. A common-mode choke is used between the I-V resistors and the remainder of the filter. This removes the common-mode signal produced by the DAC and prevents the common-mode signal from being converted to a differential signal, which can appear as unwanted spurious signals in the output spectrum. Splitting the first filter capacitor into two and grounding the center point creates a common-mode low-pass filter, providing additional commonmode rejection of high frequency signals. A purely differential filter can pass common-mode signals. DRIVING THE ADL5375-15 The ADL5375-15 requires a 1500 mV dc bias and, therefore, requires a slightly more complex interface than most other Analog Devices, Inc, modulators. It is necessary to level shift the DAC output from a 500 mV dc bias to the 1500 mV dc bias that the ADL5375-15 requires. Level shifting can be achieved with a purely passive network, as shown in Figure 72. In this network, the dc bias of the DAC remains at 500 mV while the input to the ADL5375-15 is 1500 mV. This passive, level shifting network introduces approximately 2 dB of loss in the ac signal. AD9122 67 IOUT1P RBIP 45.3Ω RLIP 3480Ω RLIN RSIP 1kΩ 3480Ω RSQN 1kΩ RBQN 45.3Ω RBQP 58 45.3Ω IOUT2P RLQN 3480Ω 08281-043 VSIGNAL = I FS × AD9122 [2 × R B × R L ] [2 × R B + R L ] ADL537x IBBP RBIP 50Ω RLI 100Ω IBBN 67 IOUT1P 66 IOUT1N 59 IOUT2N RBIN 50Ω RSIN 1kΩ ADL5375-15 21 IBBP 5V 22 IBBN QBBN RBQN 50Ω RBQP 50Ω 58 RLQ 100Ω QBBP 08281-041 RBIN 66 45.3Ω IOUT1N 59 IOUT2N IOUT2P 9 QBBN 5V 10 QBBP Figure 71. Typical Interface Circuitry Between the AD9122 and the ADL537x Family of Modulators RSQP RLQP 1kΩ 3480Ω BASEBAND FILTER IMPLEMENTATION Most applications require a baseband anti-imaging filter between the DAC and the modulator to filter out Nyquist images and broadband DAC noise. The filter can be inserted between the I-V resistors at the DAC output and the signal-level setting resistor across the modulator input. Doing this establishes the input and output impedances for the filter. Figure 72. Passive, Level Shifting Network for Biasing ADL5375-15 50Ω 33nH 22pF 56nH 3pF 6pF 140Ω ADL537x 08281-042 AD9122 50Ω 2pF 33nH 22pF 56nH 3pF Figure 73. DAC Modulator Interface with Fifth-Order, Low Pass Filter Rev. 0 | Page 46 of 56 AD9122 REDUCING LO LEAKAGE AND UNWANTED SIDEBANDS Analog quadrature modulators can introduce unwanted signals at the LO frequency due to dc offset voltages in the I and Q baseband inputs, as well as feedthrough paths from the LO input to the output. The LO feedthrough can be nulled by applying the correct dc offset voltages at the DAC output. This can be done using the auxiliary DACs (Register 0x42, Register 0x43, Register 0x46, and Register 0x47) or by using the digital dc offset adjustments (Register 0x3C through Register 0x3F). The advantage of using the auxiliary DACs is that none of the main DAC dynamic range is used to perform the dc offset adjustment. The disadvantage is that the common-mode level of the output signal changes as a function of the auxiliary DAC current. The opposite is true when the digital offset adjustment is used. Good sideband suppression requires both gain and phase matching of the I and Q signals. The I/Q phase adjust (Register 0x38 through Register 0x3B) and DAC FS adjust (Register 0x40 and Register 0x44) registers can be used to calibrate I and Q transmit paths to optimize the sideband suppression. Rev. 0 | Page 47 of 56 AD9122 DEVICE POWER DISSIPATION The AD9122 has four supply rails: AVDD33, IOVDD, DVDD18, and CVDD18. The AVDD33 supply powers the DAC core circuitry. The power dissipation of the AVDD33 supply rail is independent of the digital operating mode and sample rate. The current drawn from the AVDD33 supply rail is typically 57 mA (188 mW) when the full-scale current of the I and Q DACs is set to the nominal value of 20 mA. Changing the full-scale current directly impacts the supply current drawn from the AVDD33 rail. For example, if the full-scale current of the I DAC and the Q DAC is changed to 10 mA, the AVDD33 supply current drops by 20 mA to 37 mA. The IOVDD voltage supplies the serial port I/O pins, the RESET pin, and the IRQ pin. The voltage applied to the IOVDD pin can range from 1.8 V to 2.8 V. The current drawn by the IOVDD supply pin is typically 3 mA. The DVDD18 supply powers all of the digital signal processing blocks of the device. The power consumption from this supply is a function of which digital blocks are enabled and the frequency at which the device is operating. The CVDD18 supply powers the clock receiver and clock distribution circuitry. The power consumption from this supply varies directly with the operating frequency of the device. CVDD18 also powers the PLL. The power dissipation of the PLL is typically 80 mA when enabled. Figure 74 through Figure 78 detail the power dissipation of the AD9122 under a variety of operating conditions. All of the graphs are taken with data being supplied to both the I and Q channels. The power consumption of the device does not vary significantly with changes in the coarse modulation mode selected or analog output frequency. Graphs of the total power dissipation are shown along with the power dissipation of the DVDD18 and CVDD18 supplies. Maximum power dissipation can be estimated to be 20% higher than the typical power dissipation. POWER (mW) 1700 1500 1300 1× 2× 4× 8× POWER (mW) 1100 900 700 500 300 100 fDATA (MHz) Figure 74. Total Power Dissipation vs. fDATA Without PLL, Fine NCO, and Inverse Sinc 1200 1× 2× 4× 8× 1000 800 POWER (mW) 600 400 200 0 fDATA (MHz) Figure 75. DVDD18 Power Dissipation vs. fDATA Without Fine NCO and Inverse Sinc 250 1× 2× 4× 8× 200 150 100 50 0 fDATA (MHz) Figure 76. CVDD18 Power Dissipation vs. fDATA with PLL Disabled Rev. 0 | Page 48 of 56 08281-046 0 50 100 150 200 250 300 08281-045 0 50 100 150 200 250 300 08281-044 0 50 100 150 200 250 300 AD9122 300 TEMPERATURE SENSOR The AD9122 has a diode-based temperature sensor for measuring the temperature of the die. The temperature reading is accessed through Register 0x49 and Register 0x4A. The temperature of the die can be calculated by 250 200 POWER (mW) 150 TDIE = (DieTemp[15 : 0] − 47,925) 88 100 50 where TDIE is the die temperature in oC. The temperature accuracy is ±5oC typical. Estimates of the ambient temperature can be made if the power dissipation of the device is known. For example, if the device power dissipation is 800 mW, and the measured die temperature is 50oC, then the ambient temperature can be calculated as TA = TDIE – PD × TJA = 50 – 0.8 × 20.7 = 33.4°C where: TA is the ambient temperature in oC. TJA is the thermal resistance from junction to ambient of the AD9122, as shown in Table 7. To use the temperature sensor, it must be enabled by setting Register 0x01, Bit 4 to 0. In addition, to obtain accurate readings, the range control register (Register 0x48) should be set to 0x02. 0 fDAC (MHz) Figure 77. DVDD18 Power Dissipation vs. fDAC Due to Inverse Sinc Filter 300 1× 2×, 4×, 8× 250 200 POWER (mW) 150 100 50 fDATA (MHz) Figure 78. DVDD18 Power Dissipation vs. fDATA Due to Fine NCO 08281-048 0 50 100 150 200 250 300 08281-047 0 200 400 600 800 100 1200 Rev. 0 | Page 49 of 56 AD9122 MULTICHIP SYNCHRONIZATION System demands may require that the outputs of multiple DACs be synchronized with each other or with a system clock. Systems that support transmit diversity or beam forming, where multiple antennas are used to transmit a correlated signal, require multiple DAC outputs to be phase aligned with each other. Systems with a time division multiplexing transmit chain may require one or more DACs to be synchronized with a system-level reference clock. Multiple devices are considered synchronized to each other when the state of the clock generation state machines is identical for all parts, and when time aligned data is being read from the FIFOs of all parts simultaneously. Devices are considered synchronized to a system clock when there is a fixed and known relationship between the clock generation state machine and the data being read from the FIFO and a particular clock edge of the system clock. The AD9122 has provisions for enabling multiple devices to be synchronized to each other or to a system clock. The AD9122 supports synchronization in two different modes, data rate mode and FIFO rate mode. The lowest rate clock that the synchronization logic attempts to synchronize to distinguishes these two modes. In data rate mode, the input data rate represents the lowest synchronized clock. In FIFO rate mode, the FIFO rate, which is the data rate divided by the FIFO depth of 8, represents the lowest rate clock. The advantage of FIFO rate synchronization is increased time between keep-out windows for DCI changes relative to the DACCLK or REFCLK input. When in data rate mode, the elasticity of the FIFO is not used to absorb timing variations between the data source and the DAC, resulting in keep-out widows repeating at the input data rate. The method chosen for providing the DAC sampling clock directly impacts the synchronization methods available. When the device clock multiplier is used, only data rate mode is available. When the DAC sampling clock is sourced directly, both data rate mode and FIFO rate mode synchronization is available. The following sections detail the synchronization methods for enabling both clocking modes and querying the status of the synchronization logic. SYNCHRONIZATION WITH CLOCK MULTIPLICATION When using the clock multiplier to generate the DAC sample rate clock, the REFCLK input signal acts as both the reference clock for the PLL-based clock multiplier and as the synchronization signal. To synchronize devices, distribute the REFCLK signal with low skew to all of the devices that need to be synchronized. Skew between the REFCLK signals of the different devices shows up directly as a timing mismatch at the DAC outputs. The frequency of the REFCLK signal is typically equal to the input data rate. The FRAME and DCI signals can be created in the FPGA along with the data. A circuit diagram of a typical configuration is shown in Figure 79. MATCHED LENGTH TRACES REFCLKP/ REFCLKN FRAMEP/ FRAMEN DCIP/ DCIN LOW SKEW CLOCK DRIVER REFCLKP/ REFCLKN FPGA FRAMEP/ FRAMEN DCIP/ DCIN IOUT2P/ IOUT2N 08281-049 IOUT1P/ IOUT1N SYSTEM CLOCK Figure 79. Typical Circuit Diagram for Synchronizing Devices The Procedure for Synchronization when Using the PLL section outlines the steps required to synchronize multiple devices. The procedure assumes that the REFCLK signal is applied to all of the devices, and that the PLL of each device is phase locked to it. The following procedure must be carried out on each individual device. Procedure for Synchronization when Using the PLL Configure for data rate, periodic synchronization by writing 0xC0 to the sync control register (Register 0x10). Additional synchronization options are available. Read the sync status register (Register 0x12) and verify that the sync locked bit (Bit 6) is set high, indicating that the device achieved back-end synchronization and that the sync lost bit (Bit 7) is low. These levels indicate that the clocks are running with a constant and known phase relative to the sync signal. Reset the FIFO by strobing the FRAME signal high for the time required to write two complete input data words. Resetting the FIFO ensures that the correct data is being read from the FIFO. This completes the synchronization procedure, and at this stage, all devices should be synchronized. Rev. 0 | Page 50 of 56 AD9122 tSKEW REFCLKP(1)/ REFCLKN(1) REFCLKP(2)/ REFCLKN(2) tSU_DCI DCIP(2)/ DCIN(2) tH_DCI FRAMEP(2)/ FRAMEN(2) Figure 80. Timing Diagram Required for Synchronizing Devices DACCLKP/ DACCLKN REFCLKP/ REFCLKN FRAMEP/ FREMEN DCIP/ DCIN MATCHED LENGTH TRACES IOUT1P/ IOUT1N SAMPLE RATE CLOCK LOW SKEW CLOCK DRIVER SYNC CLOCK LOW SKEW CLOCK DRIVER DACCLKP/ DACCLKN REFCLKP/ REFCLKN FRAMEP/ FREMEN DCIP/ DCIN IOUT2P/ IOUT2N Figure 81. Typical Circuit Diagram for Synchronizing Devices to a System Clock To maintain synchronization, the skew between the REFCLK signals of the devices must be less than tSKEW nanoseconds. There is also a setup-and-hold time to be observed between the DCI and data of each device and the REFCLK signal. When resetting the FIFO, the FRAME signal must be held high for the time interval required to write two complete input data words. A timing diagram of the input signals is shown in Figure 80. The preceding example shows a REFCLK frequency equal to the data rate. While this is the most common situation, it is not strictly required for proper synchronization. Any REFCLK frequency that satisfies the following equation is acceptable. fSYNC_I = fDACCLK/2N and fSYNC_I ≤ fDATA where N = 0, 1, 2, or 3. As an example, a configuration with 4× interpolation and clock frequencies of fVCO = 1600 MHz, fDACCLK = 800 MHz, fDATA = 200 MHz, and fSYNC_I = 100 MHz is a viable solution. to a master clock, then use the master clock directly for generating the REFCLK input (see Figure 81). DATA RATE MODE SYNCHRONIZATION The Procedure for Data Rate Synchronization when Directly Sourcing the DAC Sampling Clock section outlines the steps required to synchronize multiple devices in data rate mode. The procedure assumes that the DACCLK and REFCLK signals are applied to all of the devices. The procedure must be carried out on each individual device. Procedure for Data Rate Synchronization when Directly Sourcing the DAC Sampling Clock Configure for data rate, periodic synchronization by writing 0xC0 to the sync control register (Register 0x10). Additional synchronization options are available and are described in the Additional Synchronization Features section. Poll the sync locked bit (Register 0x12, Bit 6) to verify that the device is back-end synchronized. A high level on this bit indicates that the clocks are running with a constant and known phase relative to the sync signal. Reset the FIFO by strobing the FRAME signal high for the time interval required to input two complete data input words. Resetting the FIFO ensures that the correct data is being read from the FIFO of each of the devices simultaneously. SYNCHRONIZATION WITH DIRECT CLOCKING When directly sourcing the DAC sample rate clock, a separate REFCLK input signal is required for synchronization. To synchronize devices, the DACCLK signal and the REFCLK signal must be distributed with low skew to all of the devices being synchronized. If the devices need to be synchronized Rev. 0 | Page 51 of 56 08281-051 FPGA 08281-050 AD9122 This completes the synchronization procedure, and at this stage, all devices should be synchronized. To ensure that each of the DACs are updated with the correct data on the same CLK edge, two timing relationships must be met on each DAC. DCIP/DCIN and D[15:0]P/D[15:0]N must meet the setup-and-hold times with respect to the rising edge of DACCLK, and REFCLK must also meet the setup-and-hold time with respect to the rising edge of DACCLK. When resetting the FIFO, the FRAME signal must be held high the time required to input two complete data input words. When these conditions are met, the outputs of the DACs are updated within tSKEW + tOUTDLY nanoseconds of each other. A timing diagram that illustrates the timing requirements of the input signals is shown in Figure 82. tSKEW DACCLKP(1)/ DACCLKN(1) Poll the sync locked bit (Register 0x12, Bit[6]) to verify that the device is back-end synchronized. A high level on this bit indicates that the clocks are running with a constant and known phase relative to the sync signal. Reset the FIFO by strobing the FRAME signal high for the time required to input to complete input words. Resetting the FIFO ensures that the correct data is being read from the FIFO of each of the devices simultaneously. This completes the synchronization procedure, and at this stage, all devices should be synchronized. To ensure that each of the DACs are updated with the correct data on the same CLK edge, two timing relationships must be met on each DAC. DCIP/DCIN and D[15:0]P/D[15:0]N must meet the setup-and-hold times with respect to the rising edge of DACCLK, and REFCLK must also meet the setup-and-hold time with respect to the rising edge of DACCLK. When resetting the FIFO, the FRAME signal must be held high for at least three data periods (that is, 1.5 cycles of DCI). When these conditions are met, the outputs of the DACs are updated within tSKEW + tOUTDLY nanoseconds of each other. A timing diagram that illustrates the timing requirements of the input signals is shown in Figure 83. tSKEW DACCLKP(2)/ DACCLKN(2) tSU_SYNC tH_SYNC REFCLKP(2)/ REFCLKN(2) tSU_DCI tH_DCI DCIP(2)/ DCIN(2) FRAMEP(2)/ FRAMEN(3) 08281-052 DACCLKP(1)/ DACCLKN(1) Figure 82. Data Rate Synchronization Signal Timing Requirements, 2x Interpolation DACCLKP(2)/ DACCLKN(2) Figure 82 shows the synchronization signal timing with 2× interpolation; therefore, fDCI = ½ × fCLK. The REFCLK input is shown to be equal to the data rate. The maximum frequency at which the device can be resynchronized in data rate mode can be expressed as fSYNC_I = fDATA/2N where N is any nonnegative integer. Generally, for values of N equal to or greater than 3, select the FIFO rate synchronization mode. tSU_SYNC tH_SYNC REFCLKP(2)/ REFCLKN(2) DCIP(2)/ DCIN(2) FRAMEP(2)/ FRAMEN(2) 08281-053 Figure 83. FIFO Rate Synchronization Signal Timing Requirements, 2× Interpolation FIFO RATE MODE SYNCHRONIZATION The Procedure for FIFO Rate Synchronization when Directly Sourcing the DAC Sampling Clock section outlines the steps required to synchronize multiple devices in FIFO rate mode. The procedure assumes that the REFCLK and DACCLK signals are applied to all of the devices. The procedure must be carried out on each individual device. Figure 83 shows the synchronization signal timing with 2× interpolation; therefore, fDCI = ½ × fCLK. The REFCLK input is shown to be equal to the FIFO rate. More generally, the maximum frequency at which the device can be resynchronized in FIFO rate mode can be expressed as fSYNC_I = (fDATA/8 × 2N) where N is any nonnegative integer. ADDITIONAL SYNCHRONIZATION FEATURES The synchronization logic incorporates additional features that provide means for querying the status of the synchronization, improving the robustness of the synchronization, and a one shot synchronization mode. These features are detailed in the Sync Status Bits and Timing Optimization sections that follow. Procedure for FIFO Rate Synchronization when Directly Sourcing the DAC Sampling Clock Configure for FIFO rate, periodic synchronization by writing 0x80 to the sync control register (Register 0x10). Additional synchronization options are available and are described in the Additional Synchronization Features section. Rev. 0 | Page 52 of 56 AD9122 Sync Status Bits When the sync locked bit (Register 0x12, Bit 6) is set, it indicates that the synchronization logic has reached alignment. This alignment is determined when the clock generation state machine phase is constant. It takes between (11 + averaging) × 64 and (11 + averaging) × 128 DACCLK cycles. This bit may optionally trigger an IRQ as described in the Interrupt Request Operation section. When the sync lost bit (Register 0x12, Bit 7) is set, it indicates a previously synchronized device has lost alignment. This bit is latched and remains set until cleared by overwriting the register. This bit may optionally trigger an IRQ as described in the Interrupt Request Operation section. The sync phase readback bits (Register 0x13, Bits[7:0]) report the current clock phase in a 6.2 format. Bits[7:2] report which of the 64 states (0 to 63) the clock is currently in. When averaging is enabled, Bits[1:0] provide ¼ state accuracy (for 0, ¼, ½, ¾). The lower two bits give an indication of the timing margin issues that may exist. If the sync sampling is error free, the fractional clock state should be 00. The synchronization logic resynchronizes when a phase change between the REFCLK signal and the state of the clock generation state machine exceeds a threshold. To mitigate the effects of jitter and prevent erroneous resynchronizations, the relative phase can be averaged. The amount of averaging is set by the sync averaging bits (Register 0x10, Bits[2:0]) and can be set from 1 to 128. The higher the number of averages, the more slowly the device recognizes and resynchronizes to a legitimate phase correction. Generally, the averaging should be made as large as possible while still meeting the allotted resynchronization time interval. The sync phase request bits value (Register 0x11, Bits[5:0]) is the state to which the clock generation state machine resets upon initialization. By varying this value, the timing of the internal clocks, with respect to the REFCLK signal, can be adjusted. Every increment of the Sync Phase Request[5:0] (Register 0x11, Bits[5:0]) value advances the internal clocks by one DACCLK period. This offset can be used for two purposes: to skew the outputs of two synchronized DAC outputs in increments of the DACCLK period and to change the relative timing between the DCI input and REFCLK. This may allow for a more optimal placement of the DCI sampling point in data rate synchronization mode. Table 25. Synchronization Setup and Hold Times Parameter tSKEW tSV_SYNC TH_SYNC Min −tDACCLK/2 100 330 Max +tDACCLK/2 Unit ps ps ps Timing Optimization The REFCLK signal is sampled by a version of the DACCLK. If sampling errors are being detected, the opposite sampling edge can be selected to improve the sampling point. The sampling edge can be selected by setting Register 0x10, Bit 3 (1 = rising and 0 = falling). Rev. 0 | Page 53 of 56 AD9122 INTERRUPT REQUEST OPERATION The AD9122 provides an interrupt request output signal (on Pin 7, IRQ) that can be used to notify an external host processor of significant device events. Upon assertion of the interrupt, the device should be queried to determine the precise event that occurred. The IRQ pin is an open-drain, active low output. Pull the IRQ pin high external to the device. This pin can be tied to the interrupt pins of other devices with open-drain outputs to wired-OR these pins together. Sixteen different event flags provide visibility into the device. These 16 flags are located in the two event flag registers (Register 0x06 and Register 0x07). The behavior of each of the event flags is independently selected in the interrupt enable registers (Register 0x04 and Register 0x05). When the flag interrupt enable is active, the event flag latches and triggers an external interrupt. When the flag interrupt is disabled, the event flag simply monitors the source signal and the external IRQ remains inactive. Figure 84 shows the IRQ-related circuitry. This diagram shows how the event flag signals propagate to the IRQ output. The interupt_enable signal represents one bit from the interrupt enable register. The event_flag_source signal represents one bit from the event flag register. The event_flag_source signal represents one of the device signals that can be monitored such as the PLL_locked signal from the PLL phase detector or the FIFO Warning 1 signal from the FIFO controller. When an interrupt enable bit is set high, the corresponding event flag bit reflects a positively tripped (that is, latched on the rising edge of the event_flag_source version of the event_flag_source signal. This signal also asserts the external IRQ. When an interrupt enable bit is set low, the event flag bit reflects the current status of the event_flag_source signal, and the event flag has no effect on the external IRQ. The latched version of an event flag (the interupt_source signal) can be cleared in two ways. The recommended way is by writing 1 to the corresponding event flag bit. A hardware or software reset also clears the interupt_source. INTERRUPT SERVICE ROUTINE Interrupt request management starts by selecting the set of event flags that require host intervention or monitoring. Those events that require host action should be enabled so that the host is notified when they occur. For events requiring host intervention, upon IRQ activation, run the following routine to clear an interrupt request: 1. 2. 3. Read the status of the event flag bits that are being monitored. Set the interupt enable bit low so that the unlatched event_flag_source can be monitored directly. Perform any actions that may be required to clear the event_source_flag. In many cases, no specific actions may be required. Read the event flag to verify the actions taken have cleared the event_flag_source. Clear the interrupt by writing 1 to the event flag bit. Set the interupt enable bits of the events to be monitored. 4. 5. 6. Note that some of the event_flag_source signals are latched signals. These are cleared by writing to the corresponding event flag bit. Details of each of the event flags can be found in Table 11. 0 1 EVENT_FLAG IRQ INTERRUPT_ENABLE EVENT_FLAG_SOURCE INTERRUPT SOURCE OTHER INTERRUPT SOURCES DEVICE_RESET Figure 84. Simplified Schematic of IRQ Circuitry Rev. 0 | Page 54 of 56 08281-054 WRITE_1_TO_EVENT_FLAG AD9122 INTERFACE TIMING VALIDATION The AD9122 provides on-chip sample error detection (SED) circuitry that simplifies verification of the input data interface. The SED compares the input data samples captured at the digital input pins with a set of comparison values. The comparison values are loaded into registers through the SPI port. Differences between the captured values and the comparison values are detected and stored. Options are available for customizing SED test sequencing and error handling. The sample error, compare pass, and compare fail flags can be configured to trigger an IRQ when active, if desired. This is done by enabling the appropriate bits in the event flag register (Register 0x07). Table 26 shows a progression of the input sample comparison results and the corresponding states of the error flags. SED EXAMPLE Normal Operation The following example illustrates the SED configuration for continuously monitoring the input data and assertion of an IRQ when a single error is detected. 1. Write to the following registers to enable the SED and load the comparison values. Register 0x67 → 0x80 Register 0x68 → I0[7:0] Register 0x69 → I0[15:8] Register 0x6A → Q0[7:0] Register 0x6B → Q0[15:8] Register 0x6C → I1[7:0] Register 0x6D → I1[15:8] Register 0x6E → Q1[7:0] Register 0x6F → Q1[15:8] Comparison values can be chosen arbitrarily; however, choosing values that require frequent bit toggling provides the most robust test. Enable the SED error detect flag to assert the IRQ pin. Register 0x05 → 0x04 Begin transmitting the input data pattern. SED OPERATION The SED circuitry operates on a data set made up of four 16-bit input words, denoted as I0, Q0, I1, and Q1. To properly align the input samples, the first I and Q data-words (that is, I0 and Q0) are indicated by asserting the FRAME signal for a minimum of two complete input samples. Figure 85 shows the input timing of the interface in word mode. The FRAME signal can be issued once at the start of the data transmission, or it can be asserted repeatedly at intervals coinciding with the I0 and Q0 data-words. FRAME 08281-056 DATA[15:0] I0 Q0 I1 Q1 I0 Q0 Figure 85. Timing Diagram of Extended FRAME Signal Required to Align Input Data for SED The SED has three flag bits (Register 0x67, Bit 0, Bit 1, and Bit 5) that indicate the results of the input sample comparisons. The sample error detected bit (Register 0x67, Bit 5) is set when an error is detected and remains set until cleared. The SED also provides registers that indicate which input data bits experienced errors (Register 0x70 through Register 0x73). These bits are latched and indicate the accumulated errors detected until cleared. The autoclear mode has two effects: it activates the compare fail bit and the compare pass bit (Register 0x67, Bit 1 and Bit 0) and changes the behavior of Register 0x70 through Register 0x73. The compare pass bit sets if the last comparison indicated the sample was error free. The compare fail bit sets if an error is detected. The compare fail bit is automatically cleared by the reception of eight consecutive error-free comparisons. When autoclear mode is enabled, Register 0x70 through Register 0x73 accumulate errors as previously described but reset to all 0s after eight consecutive error-free sample comparisons are made. Compare Results (Pass/Fail) Register 0x67, Bit 5 (Sample Error Detected) Register 0x67, Bit 1 (Compare Fail) Register 0x67, Bit 0 (Compare Pass) Register 0x70 to Register 0x73 (Errors Detected x_BITS[15:0]) 1 2 2. 3. If IRQ is asserted, read Register 0x67 and Register 0x70 through Register 0x73 to verify that a SED error was detected and determine which input bits were in error. The bits in Register 0x70 through Register 0x73 are latched; therefore, the bits indicate any errors that occurred on those bits throughout the test and not just the errors that caused the error detected flag to be set. Table 26. Progression of Comparison Outcomes and the Resulting SED Register Values P 0 0 1 Z1 F 1 1 0 N2 F 1 1 0 N2 F 1 1 0 N2 P 1 1 1 N2 P 1 1 1 N2 P 1 1 1 N2 P 1 1 1 N2 P 1 1 1 N2 P 1 1 1 N2 P 1 1 1 N2 P 1 1 1 N2 P 1 0 1 Z1 F 1 1 0 N2 P 1 1 1 N2 F 1 1 0 N2 Z = all 0s. N = nonzero. Rev. 0 | Page 55 of 56 AD9122 OUTLINE DIMENSIONS 10.00 BSC SQ 0.60 0.42 0.24 0.60 0.42 0.24 55 54 72 1 PIN 1 INDICATOR PIN 1 INDICATOR 9.75 BSC SQ 0.50 BSC EXPOSED PAD (BOTTOM VIEW) TOP VIEW 6.15 6.00 SQ 5.85 0.50 0.40 0.30 1.00 0.85 0.80 SEATING PLANE 12° MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 37 36 18 19 8.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 052809-A 0.30 0.23 0.18 COMPLIANT TO JEDEC STANDARDS MO-220-VNND-4 Figure 86. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 10 mm × 10 mm Body, Very Thin Quad (CP-72-7) Dimensions shown in millimeters ORDERING GUIDE Model AD9122BCPZ1 AD9122BCPZRL1 AD9122-M5372-EBZ1 AD9122-M5375-EBZ1 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 72-lead LFCSP_VQ 72-lead LFCSP_VQ Evaluation Board Connected to ADL5372 Modulator Evaluation Board Connected to ADL5375 Modulator Package Option CP-72-7 CP-72-7 Z = RoHS Compliant Part. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08281-0-9/09(0) Rev. 0 | Page 56 of 56