FEATURES
TYPICAL APPLICATION CIRCUIT
Support input data rate >2 GSPS
Proprietary low spurious and distortion design
SFDR = 82 dBc at dc IF, −9 dBFS
Flexible 8-lane JESD204B interface
Multiple chip synchronization
Fixed latency
Data generator latency compensation
Selectable 1×, 2×, 4×, or 8× interpolation filter
Low power architecture
Transmit enable function allows extra power saving and
instant control of the output status
High performance, low noise phase-locked loop (PLL) clock
multiplier
Digital inverse sinc filter
Low power: 1.42 W at 1.6 GSPS full operating conditions
88-lead LFCSP with exposed pad
QUAD MOD
LPF
ADRF6720
SYSREF±
DAC
RF OUTPUT
0°/90° PHASE
SHIFTER
JESD204B
DAC
SYNCOUT0±
SYNCOUT1±
AD9135/
AD9136
LO_IN
MOD_SPI
CLK±
DAC
SPI
12578-001
Data Sheet
Dual, 11-/16-Bit, 2.8 GSPS, TxDAC+®
Digital-to-Analog Converters
AD9135/AD9136
Figure 1.
APPLICATIONS
Wireless communications
3G/4G W-CDMA base stations
Wideband repeaters
Software defined radios
Wideband communications
Point to point
Local multipoint distribution service (LMDS) and
multichannel multipoint distribution service (MMDS)
Transmit diversity, multiple input/multiple output (MIMO)
Instrumentation
Automated test equipment
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD9135/AD9136 are dual, 11-/16-bit, high dynamic range
digital-to-analog converters (DACs) that provide a maximum
sample rate of 2800 MSPS, permitting a multicarrier generation
over a very wide bandwidth. The DAC outputs are optimized to
interface seamlessly with the ADRF6720, as well as other analog
quadrature modulators (AQMs) from Analog Devices, Inc. An
optional 3-wire or 4-wire serial port interface (SPI) provides for
programming/readback of many internal parameters. The fullscale output current can be programmed over a typical range of
13.9 mA to 27.0 mA. The AD9135/AD9136 are available in an
88-lead LFCSP.
1.
2.
3.
4.
5.
6.
Rev. D
Greater than 2 GHz, ultrawide complex signal bandwidth
enables emerging wideband and multiband wireless
applications.
Advanced low spurious and distortion design techniques
provide high quality synthesis of wideband signals from
baseband to high intermediate frequencies.
JESD204B Subclass 1 support simplifies multichip
synchronization in software and hardware design.
Fewer pins for data interface width with a serializer/
deserializer (SERDES) JESD204B eight-lane interface.
Programmable transmit enable function allows easy design
balance between power consumption and wake-up time.
Small package size with 12 mm × 12 mm footprint.
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AD9135/AD9136
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
JESD204B Setup ......................................................................... 30
Applications ....................................................................................... 1
SERDES Clocks Setup ................................................................ 32
Typical Application Circuit ............................................................. 1
Equalization Mode Setup .......................................................... 32
General Description ......................................................................... 1
Link Latency Setup ..................................................................... 32
Product Highlights ........................................................................... 1
Crossbar Setup ............................................................................ 34
Revision History ............................................................................... 3
JESD204B Serial Data Interface .................................................... 35
Functional Block Diagram .............................................................. 4
JESD204B Overview .................................................................. 35
Specifications..................................................................................... 5
Physical Layer ............................................................................. 36
DC Specifications ......................................................................... 5
Data Link Layer .......................................................................... 39
Digital Specifications ................................................................... 6
Transport Layer .......................................................................... 48
Maximum DAC Update Rate Speed Specifications by Supply 7
JESD204B Test Modes ............................................................... 58
JESD204B Serial Interface Speed Specifications ...................... 7
JESD204B Error Monitoring..................................................... 59
SYSREF Signal to DAC Clock Timing Specifications.............. 8
Hardware Considerations ......................................................... 61
Digital Input Data Timing Specifications ................................. 8
Digital Datapath ............................................................................. 65
Latency Variation Specifications ................................................ 9
DAC Paging ................................................................................. 65
JESD204B Interface Electrical Specifications ........................... 9
Data Format ................................................................................ 65
AC Specifications........................................................................ 10
Interpolation Filters ................................................................... 65
Absolute Maximum Ratings.......................................................... 11
Inverse Sinc ................................................................................. 66
Thermal Resistance .................................................................... 11
Digital Gain, DC Offset, and Group Delay ............................. 66
ESD Caution ................................................................................ 11
Downstream Protection ............................................................ 68
Pin Configuration and Function Descriptions ........................... 12
Datapath PRBS ........................................................................... 69
Terminology .................................................................................... 15
DC Test Mode ............................................................................. 70
Typical Performance Characteristics ........................................... 16
Interrupt Request Operation ........................................................ 71
Theory of Operation ...................................................................... 22
Interrupt Service Routine .......................................................... 71
Serial Port Operation ..................................................................... 23
DAC Input Clock Configurations ................................................ 72
Data Format ................................................................................ 23
Driving the CLK± Inputs .......................................................... 72
Serial Port Pin Descriptions ...................................................... 23
DAC PLL Fixed Register Writes ............................................... 72
Serial Port Options ..................................................................... 23
Clock Multiplication .................................................................. 72
Chip Information ............................................................................ 25
Starting the PLL .......................................................................... 74
Device Setup Guide ........................................................................ 26
Analog Outputs............................................................................... 75
Overview...................................................................................... 26
Transmit DAC Operation.......................................................... 75
Step 1: Start Up the DAC ........................................................... 26
Device Power Dissipation.............................................................. 78
Step 2: Digital Datapath ............................................................. 27
Temperature Sensor ................................................................... 78
Step 3: Transport Layer .............................................................. 27
Start-Up Sequence .......................................................................... 79
Step 4: Physical Layer ................................................................. 28
Step 1: Start Up the DAC ........................................................... 79
Step 5: Data Link Layer .............................................................. 28
Step 2: Digital Datapath............................................................. 79
Step 6: Optional Error Monitoring .......................................... 29
Step 3: Transport Layer .............................................................. 80
Step 7: Optional Features ........................................................... 29
Step 4: Physical Layer ................................................................. 80
DAC PLL Setup ........................................................................... 30
Step 5: Data Link Layer.............................................................. 81
Interpolation ............................................................................... 30
Step 6: Error Monitoring ........................................................... 81
Rev. D | Page 2 of 117
Data Sheet
AD9135/AD9136
Register Maps and Descriptions ....................................................82
Outline Dimensions ......................................................................116
Device Configuration Register Map .........................................82
Ordering Guide .........................................................................117
Device Configuration Register Descriptions ..........................88
REVISION HISTORY
4/2019—Rev. C to Rev. D
Updated Outline Dimensions ......................................................116
Changes to Ordering Guide .........................................................117
5/2017—Rev. B to Rev. C
Changes to Table 25 ........................................................................30
Changes to Table 73 ........................................................................74
3/2017—Rev. A to Rev. B
Changed 10.64 Gbps to 12.4 Gbps, 2.76 Gbps to 3.1 Gbps, and
5.52 Gbps to 6.2 Gbps ................................................... Throughout
Changes to Table 4 ............................................................................ 7
Change to Device Revision Parameter; Table 14 ............................... 25
Changes to Functional Overview of the SERDES PLL Section......37
Changes to Figure 46 ......................................................................38
Change to Register 0x006, Table 84 ..............................................82
Change to Address 0x006, Table 85 ..............................................88
7/2015—Rev. 0 to Rev. A
Changed Functional Block Diagram Section to Typical
Application Circuit Section.............................................................. 1
Changes to General Description Section ....................................... 1
Changed Detailed Functional Block Diagram Section to
Functional Block Diagram Section ................................................. 4
Changes to Offset Drift Parameter, Table 1 ................................... 5
Deleted Reference Voltage Parameter, Table 1 .............................. 5
Changed 1× Interpolation Mode Parameter to 1× Interpolation
Mode, JESD Mode 8, 8 SERDES Lanes Parameter, Table 1 ......... 5
Changes to Output Voltage (VOUT) Logic High Parameter,
Output Voltage (VOUT) Logic Low Parameter, JESD204B Serial
Interface Speed Minimum Parameter, and SYSREF± Frequency
Parameter, Table 2 ............................................................................. 6
Changes to Table 4 ............................................................................ 7
Changes to Interpolation Parameter, Table 6 ................................ 8
Changed Junction Temperature Parameter to Operating
Junction Temperature, Table 10 ....................................................11
Changes to Terminology Section ..................................................17
Changes to Figure 34 Caption and Figure 37 Caption ...............21
Changes to Device Revision Parameter, Table 14 .......................25
Changes to Overview Section, Table 15, Table 16, and
Table 17 .............................................................................................26
Changes to Step 3: Transport Layer Section and Table 19 .........27
Changes to Table 20 and Table 21 .................................................28
Changes to Step 7: Optional Features Section .............................29
Added Table 25; Renumbered Sequentially .................................30
Changes to DAC PLL Setup Section, Table 26, and Table 27 ......30
Changes to Table 28 and CurrentLink Section............................31
Added DAC Power-Down Setup Section .................................... 31
Changes to Table 30 ........................................................................ 32
Changes to Table 32 ........................................................................ 33
Changes to Table 36 and Figure 44 ............................................... 36
Changes to Table 37 ........................................................................ 37
Added SERDES PLL Fixed Register Writes Section and
Table 38 ............................................................................................. 37
Changes to Table 39 ........................................................................ 38
Changes to Figure 47 and Data Link Layer Section ................... 39
Added Figure 50; Renumbered Sequentially ............................... 40
Changes to Table 45 and Table 46 ................................................. 49
Changes to Figure 61 ...................................................................... 51
Changes to Figure 62 ...................................................................... 52
Changes to Figure 63 ...................................................................... 53
Changes to Figure 64 ...................................................................... 54
Changes to Figure 65 ...................................................................... 56
Changes to Figure 66 ...................................................................... 57
Changes to Power Supply Recommendations Section ............... 61
Added Figure 68 .............................................................................. 62
Changes to Figure 72 ...................................................................... 64
Changes to Data Format Section and Table 61 ........................... 65
Changes to Figure 76 ...................................................................... 66
Changed 0x13D[7:0] to 0x13D[3:0], Table 62............................. 67
Changes to Group Delay Section .................................................. 67
Changes to DC Test Mode Section ............................................... 95
Deleted Table 70; Renumbered Sequentially ............................... 71
Moved Figure 78 and Table 68 ...................................................... 71
Added DAC PLL Fixed Register Writes Section and
Table 69 ............................................................................................. 72
Changes to Clock Multiplication Section .................................... 73
Added Loop Filter Section and Charge Pump Filter Section ...... 73
Added Temperature Tracking Section and Table 73 .................. 74
Changes to Starting the PLL Section and Figure 82 ................... 74
Changes to Transmit DAC Operation Section ............................ 75
Changes to Start-Up Sequence Section, Table 77, and
Table 78 ............................................................................................. 79
Changes to Table 80 and Table 81 ................................................. 80
Changes to Table 82 and Table 83 ................................................. 81
Changes to Table 84 ........................................................................ 82
Changes to Table 85 ........................................................................ 88
Deleted Lookup Tables for Three Different DAC PLL Reference
Frequencies Section and Table 83 to 85 ..................................... 112
Added Figure 92 ............................................................................ 116
Updated Outline Dimensions...................................................... 116
Changes to Ordering Guide ......................................................... 117
9/2014—Revision 0: Initial Version
Rev. D | Page 3 of 117
AD9135/AD9136
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
DACCLK
HB2
HB3
OUT1+
FSC
Q-GAIN
DACCLK
MODE CONTROL
I-GAIN
HB1
HB2
I-OFFSET
HB3
OUT0+
FSC
SERDIN0±
CLOCK DISTRIBUTION
AND
CONTROL LOGIC
PLL_CTRL
SERIAL
I/O PORT
POWER-ON
RESET
DAC
ALIGN
DETECT
CLK_SEL
CONFIG
REGISTERS
OUT0–
REF
AND
BIAS
I120
SYSREF+
SYSREF–
CLK+
CLK–
DAC PLL
12578-002
TXEN1
IRQ
TXEN0
SYSREF
Rx
CLK
Rx
DACCLK
PLL_LOCK
RESET
SYNCOUT1+
SYNCOUT1–
SYNCHRONIZATION
LOGIC
SDO
SDIO
SCLK
CS
SYNCOUT0+
SYNCOUT0–
OUT1–
Q-OFFSET
INV SINC
SERDIN7±
HB1
CLOCK DATA RECOVERY
AND CLOCK FORMATTER
VTT
INV SINC
SERDES
PLL
Figure 2.
Rev. D | Page 4 of 117
Data Sheet
AD9135/AD9136
SPECIFICATIONS
DC SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,
TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted.
Table 1.
AD9135
Parameter
RESOLUTION
ACCURACY
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
MAIN DAC OUTPUTS
Gain Error
I/Q Gain Mismatch
Full-Scale Output Current
(IOUTFS)
Maximum Setting
Minimum Setting
Output Compliance Range
Output Resistance
Output Capacitance
Gain DAC Monotonicity
Settling Time
MAIN DAC TEMPERATURE DRIFT
Offset
Gain
REFERENCE
Internal Reference Voltage
ANALOG SUPPLY VOLTAGES
AVDD33
PVDD12
CVDD12
DIGITAL SUPPLY VOLTAGES
SIOVDD33
VTT
DVDD12
SVDD12
IOVDD
POWER CONSUMPTION
1× Interpolation Mode,
JESD Mode 8, 8 SERDES Lanes
AVDD33
PVDD12
CVDD12
SVDD12
DVDD12
SIOVDD33
IOVDD
Test Conditions/Comments
Min
Typ
11
AD9136
Max
Min
Typ
16
Max
Unit
Bits
With calibration
±0.175
±0.35
With internal reference
±1.0
±2.0
LSB
LSB
−2.5
−0.6
+2
+5.5
+0.6
−2.5
−0.6
+2
+5.5
+0.6
% FSR
% FSR
25.5
13.1
−250
27.0
13.9
28.6
14.8
+750
25.5
13.1
−250
27.0
13.9
28.6
14.8
+750
mA
mA
mV
MΩ
pF
Based on a 4 kΩ external resistor
between I120 and GND
To within ±0.5 LSB
1.2 V nominal supply voltage
1.3 V nominal supply voltage
1.2 V nominal supply voltage
1.3 V nominal supply voltage
0.2
3.0
Guaranteed
20
0.2
3.0
Guaranteed
20
0.04
32
0.04
32
ppm
ppm/°C
1.2
1.2
V
ns
3.13
1.14
1.14
3.3
1.2
1.2
3.47
1.26
1.26
3.13
1.14
1.14
3.3
1.2
1.2
3.47
1.26
1.26
V
V
V
3.13
1.1
1.14
1.274
1.14
1.274
1.71
3.3
1.2
1.2
1.3
1.2
1.3
1.8
3.47
1.37
1.26
1.326
1.26
1.326
3.47
3.13
1.1
1.14
1.274
1.14
1.274
1.71
3.3
1.2
1.2
1.3
1.2
1.3
1.8
3.47
1.37
1.26
1.326
1.26
1.326
3.47
V
V
V
V
V
V
V
1.42
1.74
1.42
1.74
W
68
100
101
554
196
11
36
73
113.4
112
665
224
12
50
68
100
101
554
196
11
36
73
113.4
112
665
224
12
50
mA
mA
mA
mA
mA
mA
μA
fDAC = 1.6 GSPS, IF = 40 MHz, PLL on,
digital gain on, inverse sinc on, DAC
full-scale current (IOUTFS) = 20 mA
Includes VTT
Rev. D | Page 5 of 117
AD9135/AD9136
Data Sheet
DIGITAL SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,
TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted.
Table 2.
Parameter
CMOS INPUT LOGIC LEVEL
Input Voltage (VIN) Logic
High
Low
Symbol
CMOS OUTPUT LOGIC LEVEL
Output Voltage (VOUT) Logic
High
Low
Test Conditions/Comments
Min
Typ
Max
Unit
1.8 V IOVDD 3.3 V
1.8 V IOVDD 3.3 V
0.7 × IOVDD
0.3 × IOVDD
V
V
1.8 V IOVDD 3.3 V
1.8 V IOVDD 3.3 V
0.75 × IOVDD
0.25 × IOVDD
V
V
1× interpolation2 (see Table 4)
2× interpolation2
4× interpolation3
8× interpolation3
2120
2120
2800
2800
MSPS
MSPS
MSPS
MSPS
1× interpolation
2× interpolation
4× interpolation
8× interpolation
2120
1060
700
350
MSPS
MSPS
MSPS
MSPS
MAXIMUM DAC UPDATE RATE1
ADJUSTED DAC UPDATE RATE
INTERFACE4
Number of JESD204B Lanes
JESD204B Serial Interface Speed
Minimum
Maximum
DAC CLOCK INPUT (CLK+, CLK−)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
Maximum Clock Rate
REFCLK5 Frequency (PLL Mode)
SYSTEM REFERENCE INPUT
(SYSREF+, SYSREF−)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
SYSREF± Frequency6
SYSREF SIGNAL TO DAC CLOCK7
Setup Time
Hold Time
Keep Out Window
SPI
Maximum Clock Rate
Minimum SCLK Pulse Width
High
Low
SDIO to SCLK
Setup Time
Hold Time
8
Per lane
Per lane, SVDD12 = 1.3 V ± 2%
1.44
Gbps
Gbps
2000
1000
mV
mV
MHz
MHz
2000
2000
fDATA/(K × S)
mV
mV
Hz
12.4
400
Self biased input, ac-coupled
6.0 GHz ≤ fVCO ≤ 12.0 GHz
Lanes
1000
600
2800
35
400
0
1000
SYSREF differential swing = 0.4 V, slew
rate = 1.3 V/ns, common modes tested:
ac-coupled, 0 V, 0.6 V, 1.25 V, 2.0 V
tSSD
tHSD
KOW
SCLK
131
119
ps
ps
ps
20
IOVDD = 1.8 V
10
tPWH
tPWL
MHz
8
12
tDS
tDH
5
2
Rev. D | Page 6 of 117
ns
ns
ns
ns
Data Sheet
Parameter
SDO to SCLK
Data Valid Window
CS to SCLK
Setup Time
Hold Time
AD9135/AD9136
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
tDV
25
ns
tSCS
5
ns
tHCS
2
ns
1
See Table 3 for detailed specifications for DAC update rate conditions.
The maximum speed for 1× and 2× interpolation is limited by the JESD204B interface with increased supply levels. See Table 4 for details.
The maximum speed for 4× and 8× interpolation is limited by the DAC core. See Table 4 for details.
4
See Table 4 for detailed specifications for JESD204B speed conditions.
5
REFCLK is the reference clock.
6
K, F, and S are JESD204B transport layer parameters. See Table 43 for the full definitions.
7
See Table 5 for detailed specifications for SYSREF signal to DAC clock timing conditions.
2
3
MAXIMUM DAC UPDATE RATE SPEED SPECIFICATIONS BY SUPPLY
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,
TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted.
Table 3.
Parameter
MAXIMUM DAC UPDATE RATE
2×, 4×, and 8× Interpolation
Test Conditions/Comments
Min
Typ
Max
Unit
DVDD12, CVDD12 = 1.2 V ± 5%
DVDD12, CVDD12 = 1.2 V ± 2%
DVDD12, CVDD12 = 1.3 V ± 2%
2.23
2.41
2.80
GSPS
GSPS
GSPS
DVDD12, CVDD12 = 1.2 V ± 5%
DVDD12, CVDD12 = 1.2 V ± 2%
DVDD12, CVDD12 = 1.3 V ± 2%
1.81
1.93
2.21
GSPS
GSPS
GSPS
1× Interpolation
JESD204B SERIAL INTERFACE SPEED SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,
TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted.
Table 4.
Parameter
HALF RATE
FULL RATE
OVERSAMPLING
Test Conditions/Comments
SVDD12 = 1.2 V ± 5%
SVDD12 = 1.2 V ± 2%
SVDD12 = 1.3 V ± 2%
SVDD12 = 1.2 V ± 5%
SVDD12 = 1.2 V ± 2%
SVDD12 = 1.3 V ± 2%
SVDD12 = 1.2 V ± 5%
SVDD12 = 1.2 V ± 2%
SVDD12 = 1.3 V ± 2%
Rev. D | Page 7 of 117
Min
5.75
5.75
5.75
2.88
2.88
2.88
1.44
1.44
1.44
Typ
Max
11.4
12.0
12.4
5.98
6.06
6.2
3.0
3.04
3.1
Unit
Gbps
Gbps
Gbps
Gbps
Gbps
Gbps
Gbps
Gbps
Gbps
AD9135/AD9136
Data Sheet
SYSREF SIGNAL TO DAC CLOCK TIMING SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,
TA = −40°C to +85°C, IOUTFS = 20 mA, SYSREF± common-mode voltages = 0.0 V, 0.6 V, 1.25 V, and 2.0 V, unless otherwise noted.
Table 5.
Parameter
SYSREF DIFFERENTIAL SWING = 0.4 V, SLEW RATE = 1.3 V/ns
Setup Time
Hold Time
SYSREF DIFFERENTIAL SWING = 0.7 V, SLEW RATE = 2.28 V/ns
Setup Time
Hold Time
SYSREF SWING = 1.0 V, SLEW RATE = 3.26 V/ns
Setup Time
Hold Time
Test Conditions/Comments
Min
Typ
Max
Unit
AC-coupled
DC-coupled
AC-coupled
DC-coupled
126
131
92
119
ps
ps
ps
ps
AC-coupled
DC-coupled
AC-coupled
DC-coupled
96
104
77
95
ps
ps
ps
ps
AC-coupled
DC-coupled
AC-coupled
DC-coupled
83
90
68
84
ps
ps
ps
ps
DIGITAL INPUT DATA TIMING SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,
TA = 25°C, IOUTFS = 20 mA, unless otherwise noted.
Table 6.
Parameter
LATENCY
Interface
Interpolation
1×
2×
4×
8×
Inverse Sinc
Digital Gain Adjust
POWER-UP TIME
1
Min
Typ
Max
Unit
17
PClock1 cycles
66
137
251
484
17
12
60
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
μs
PClock is the AD9135/AD9136 internal processing clock and equals the lane rate ÷ 40.
Rev. D | Page 8 of 117
Data Sheet
AD9135/AD9136
LATENCY VARIATION SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,
TA = 25°C, IOUTFS = 20 mA, unless otherwise noted.
Table 7.
Parameter
DAC LATENCY VARIATION
SYNC On
PLL Off
PLL On
Min
Typ
Max
Unit
0
1
+1
DAC clock cycles
DAC clock cycles
−1
JESD204B INTERFACE ELECTRICAL SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,
TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted.
Table 8.
Parameter
JESD204B DATA INPUTS
Input Leakage Current
Logic High
Logic Low
Unit Interval
Common-Mode Voltage
Differential Voltage
VTT Source Impedance
Differential Impedance
Differential Return Loss
Common-Mode Return Loss
DIFFERENTIAL OUTPUTS (SYNCOUTx±)2
Output Differential Voltage
Normal Swing Mode
High Swing Mode
Output Offset Voltage
DETERMINISTIC LATENCY
Fixed
Variable
SYSREF± to LOCAL MULTIFRAME
COUNTER (LMFC) DELAY
Symbol
Test Conditions/Comments
Min
TA = 25°C
Input level = 1.2 V ± 0.25 V, VTT = 1.2 V
Input level = 0 V
UI
VRCM
R_VDIFF
ZTT
ZRDIFF
RLRDIF
RLRCM
AC-coupled, VTT = SVDD121
At dc
At dc
Typ
Max
Unit
714
+1.85
1050
30
120
μA
μA
ps
V
mV
Ω
Ω
dB
dB
235
394
1.27
mV
mV
V
17
2
PClock3 cycles
PClock3 cycles
DAC clock cycles
10
−4
94
−0.05
110
80
100
8
6
VOD
Register 0x2A5[0] = 0
Register 0x2A5[0] = 1
VOS
192
341
1.19
4
1
As measured on the input side of the ac coupling capacitor.
IEEE Standard 1596.3 LVDS compatible.
3
PClock is an AD9135/AD9136 internal processing clock and equals the lane rate ÷ 40.
2
Rev. D | Page 9 of 117
AD9135/AD9136
Data Sheet
AC SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V,1 VTT = 1.2 V,
TA = 25°C, IOUTFS = 20 mA, unless otherwise noted.
Table 9.
Parameter
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fDAC = 983.04 MSPS
fDAC = 983.04 MSPS
fDAC = 1966.08 MSPS
fDAC = 1966.08 MSPS
TWO-TONE INTERMODULATION DISTORTION (IMD)
fDAC =983.04 MSPS
fDAC = 983.04 MSPS
fDAC = 1966.08 MSPS
fDAC = 1966.08 MSPS
NOISE SPECTRAL DENSITY (NSD), SINGLE-TONE
fDAC = 983.04 MSPS
fDAC = 1966.08 MSPS
W-CDMA FIRST ADJACENT CHANNEL LEAKAGE
RATIO (ACLR), SINGLE-CARRIER
fDAC = 983.04 MSPS
fDAC = 983.04 MSPS
fDAC = 1966.08 MSPS
W-CDMA SECOND ACLR, SINGLE-CARRIER
fDAC = 983.04 MSPS
fDAC = 983.04 MSPS
fDAC = 1966.08 MSPS
1
Test Conditions/Comments
−9 dBFS single-tone
fOUT = 20 MHz
fOUT = 150 MHz
fOUT = 20 MHz
fOUT = 170 MHz
−9 dBFS
fOUT = 20 MHz
fOUT = 150 MHz
fOUT = 20 MHz
fOUT = 170 MHz
0 dBFS
fOUT = 150 MHz
fOUT = 150 MHz
0 dBFS
fOUT = 30 MHz
fOUT = 150 MHz
fOUT = 150 MHz
0 dBFS
fOUT = 30 MHz
fOUT = 150 MHz
fOUT = 150 MHz
SVDD12 = 1.3 V for all fDAC = 1966.08 MSPS conditions in Table 9.
Rev. D | Page 10 of 117
Min
Typ
Max
Unit
82
76
81
69
dBc
dBc
dBc
dBc
90
82
90
81
dBc
dBc
dBc
dBc
−162
−163
dBm/Hz
dBm/Hz
82
80
80
dBc
dBc
dBc
84
85
85
dBc
dBc
dBc
Data Sheet
AD9135/AD9136
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 10.
Parameter
I120 to Ground
SERDINx±, VTT, SYNCOUT1±/
SYNCOUT0±, TXENx
OUTx±
SYSREF±
CLK± to Ground
RESET, IRQ, CS, SCLK, SDIO,
SDO to Ground
LDO_BYP1
LDO_BYP2
LDO24
Ambient Operating Temperature (TA)
Operating Junction Temperature
Storage Temperature Range
Rating
−0.3 V to AVDD33 + 0.3 V
−0.3 V to SIOVDD33 + 0.3 V
−0.3 V to AVDD33 + 0.3 V
GND − 0.5 V to +2.5 V
−0.3 V to PVDD12 + 0.3 V
−0.3 V to IOVDD + 0.3 V
−0.3 V to SVDD12 + 0.3 V
−0.3 V to PVDD12 + 0.3 V
−0.3 V to AVDD33 + 0.3 V
−40°C to +85°C
125°C
−65°C to +150°C
The exposed pad (EPAD) must be soldered to the ground plane
for the 88-lead LFCSP. The EPAD provides an electrical, thermal,
and mechanical connection to the board.
Typical θJA, θJB, and θJC values are specified for a 4-layer
JESD51-7 high effective thermal conductivity test board for
leaded surface-mount packages. θJA is obtained in still air
conditions (JESD51-2). Airflow increases heat dissipation,
effectively reducing θJA. θJB is obtained following double-ring
cold plate test conditions (JESD51-8). θJC is obtained with the test
case temperature monitored at the bottom of the exposed pad.
ΨJT and ΨJB are thermal characteristic parameters obtained with
θJA in still air test conditions.
Junction temperature (TJ) can be estimated using the following
equations:
TJ = TT + (ΨJT × P)
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
or
TJ = TB + (ΨJB × P)
where:
TT is the temperature measured at the top of the package.
P is the total device power dissipation.
TB is the temperature measured at the board.
Table 11. Thermal Resistance
Package
88-Lead LFCSP1
1
θJA
22.6
θJB
5.59
θJC
1.17
ΨJT
0.1
ΨJB
5.22
The exposed pad must be securely connected to the ground plane.
ESD CAUTION
Rev. D | Page 11 of 117
Unit
°C/W
AD9135/AD9136
Data Sheet
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
LDO_BYP2
CVDD12
I120
AVDD33
OUT0+
OUT0–
LDO24
CVDD12
DNC
DNC
DNC
AVDD33
CVDD12
AVDD33
OUT1+
OUT1–
LDO24
CVDD12
DNC
DNC
DNC
AVDD33
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
AD9135/AD9136
TOP VIEW
(Not to Scale)
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
IOVDD
CS
SCLK
SDIO
SDO
RESET
IRQ
PROTECT_OUT0
PROTECT_OUT1
PVDD12
PVDD12
GND
GND
DVDD12
SERDIN7+
SERDIN7–
SVDD12
SERDIN6+
SERDIN6–
SVDD12
VTT
SVDD12
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PAD MUST BE SECURELY CONNECTED TO THE GROUND PLANE.
12578-003
SYNCOUT0+
SYNCOUT0–
VTT
SERDIN2+
SERDIN2–
SVDD12
SERDIN3+
SERDIN3–
SVDD12
SVDD12
SVDD12
LDO_BYP1
SIOVDD33
SVDD12
SERDIN4–
SERDIN4+
SVDD12
SERDIN5–
SERDIN5+
VTT
SYNCOUT1–
SYNCOUT1+
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
PVDD12
CLK+
CLK–
PVDD12
SYSREF+
SYSREF–
PVDD12
PVDD12
PVDD12
PVDD12
TXEN0
TXEN1
DVDD12
DVDD12
SERDIN0+
SERDIN0–
SVDD12
SERDIN1+
SERDIN1–
SVDD12
VTT
SVDD12
Figure 3. Pin Configuration
Table 12. Pin Function Descriptions
Pin No.
1
2
Mnemonic
PVDD12
CLK+
3
CLK−
4
5
PVDD12
SYSREF+
6
SYSREF−
7
8
9
10
11
12
13
14
15
PVDD12
PVDD12
PVDD12
PVDD12
TXEN0
TXEN1
DVDD12
DVDD12
SERDIN0+
16
SERDIN0−
17
18
SVDD12
SERDIN1+
Description
1.2 V Supply. PVDD12 provides a clean supply.
PLL Reference/Clock Input, Positive. When the PLL is used, this pin is the positive reference clock input.
When the PLL is not used, this pin is the positive device clock input. This pin is self biased and must be
ac-coupled.
PLL Reference/Clock Input, Negative. When the PLL is used, this pin is the negative reference clock input.
When the PLL is not used, this pin is the negative device clock input. This pin is self biased and must be
ac-coupled.
1.2 V Supply. PVDD12 provides a clean supply.
Positive Reference Clock for Deterministic Latency. This pin is self biased for ac coupling. It can be ac-coupled
or dc-coupled.
Negative Reference Clock for Deterministic Latency. This pin is self biased for ac coupling. It can be ac-coupled
or dc-coupled.
1.2 V Supply. PVDD12 provides a clean supply.
1.2 V Supply. PVDD12 provides a clean supply.
1.2 V Supply. PVDD12 provides a clean supply.
1.2 V Supply. PVDD12 provides a clean supply.
Transmit Enable for DAC0. CMOS levels are determined with respect to IOVDD.
Transmit Enable for DAC1. CMOS levels are determined with respect to IOVDD.
1.2 V Digital Supply.
1.2 V Digital Supply.
Serial Channel Input 0, Positive. CML compliant. SERDIN0+ is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
Serial Channel Input 0, Negative. CML compliant. SERDIN0− is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
1.2 V JESD204B Receiver Supply.
Serial Channel Input 1, Positive. CML compliant. SERDIN1+ is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
Rev. D | Page 12 of 117
Data Sheet
Pin No.
19
Mnemonic
SERDIN1−
20
21
22
23
24
25
26
SVDD12
VTT
SVDD12
SYNCOUT0+
SYNCOUT0−
VTT
SERDIN2+
27
SERDIN2−
28
29
SVDD12
SERDIN3+
30
SERDIN3−
31
32
33
34
35
36
37
SVDD12
SVDD12
SVDD12
LDO_BYP1
SIOVDD33
SVDD12
SERDIN4−
38
SERDIN4+
39
40
SVDD12
SERDIN5−
41
SERDIN5+
42
43
44
45
46
47
48
VTT
SYNCOUT1−
SYNCOUT1+
SVDD12
VTT
SVDD12
SERDIN6−
49
SERDIN6+
50
51
SVDD12
SERDIN7−
52
SERDIN7+
53
54
55
56
57
58
59
60
DVDD12
GND
GND
PVDD12
PVDD12
PROTECT_OUT1
PROTECT_OUT0
IRQ
AD9135/AD9136
Description
Serial Channel Input 1, Negative. CML compliant. SERDIN1− is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
1.2 V JESD204B Receiver Supply.
1.2 V Termination Voltage. Connect VTT to the SVDD12 supply pins.
1.2 V JESD204B Receiver Supply.
Positive LVDS Sync (Active Low) Output Signal Channel Link 0.
Negative LVDS Sync (Active Low) Output Signal Channel Link 0.
1.2 V Termination Voltage. Connect VTT to the SVDD12 supply pins.
Serial Channel Input 2, Positive. CML compliant. SERDIN2+ is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
Serial Channel Input 2, Negative. CML compliant. SERDIN2− is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
1.2 V JESD204B Receiver Supply.
Serial Channel Input 3, Positive. CML compliant. SERDIN3+ is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
Serial Channel Input 3, Negative. CML compliant. SERDIN3− is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
1.2 V JESD204B Receiver Supply.
1.2 V JESD204B Receiver Supply.
1.2 V JESD204B Receiver Supply.
LDO SERDES Bypass. This pin requires a 1 Ω resistor in series with a 1 μF capacitor to ground.
3.3 V Supply for SERDES.
1.2 V JESD204B Receiver Supply.
Serial Channel Input 4, Negative. CML compliant. SERDIN4− is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
Serial Channel Input 4, Positive. CML compliant. SERDIN4+ is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
1.2 V JESD204B Receiver Supply.
Serial Channel Input 5, Negative. CML compliant. SERDIN5− is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
Serial Channel Input 5, Positive. CML compliant. SERDIN5+ is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
1.2 V Termination Voltage. Connect VTT to the SVDD12 supply pins.
Negative LVDS Sync (Active Low) Output Signal Channel Link 1.
Positive LVDS Sync (Active Low) Output Signal Channel Link 1.
1.2 V JESD204B Receiver Supply.
1.2 V Termination Voltage. Connect VTT to the SVDD12 supply pins.
1.2 V JESD204B Receiver Supply.
Serial Channel Input 6, Negative. CML compliant. SERDIN6− is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
Serial Channel Input 6, Positive. CML compliant. SERDIN6+ is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
1.2 V JESD204B Receiver Supply.
Serial Channel Input 7, Negative. CML compliant. SERDIN7− is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
Serial Channel Input 7, Positive. CML compliant. SERDIN7+ is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
1.2 V Digital Supply.
Ground. Connect GND to the ground plane.
Ground. Connect GND to the ground plane.
1.2 V Supply. PVDD12 provides a clean supply.
1.2 V Supply. PVDD12 provides a clean supply.
Power Detection and Protection Pin Output for DAC1. Pin 58 is high when power protection is in process.
Power Detection and Protection Pin Output for DAC0. Pin 59 is high when power protection is in process.
Interrupt Request (Active Low, Open Drain).
Rev. D | Page 13 of 117
AD9135/AD9136
Pin No.
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
Mnemonic
RESET
SDO
SDIO
SCLK
CS
IOVDD
AVDD33
DNC
DNC
DNC
CVDD12
LDO24
OUT1−
OUT1+
AVDD33
CVDD12
AVDD33
DNC
DNC
DNC
CVDD12
LDO24
OUT0−
OUT0+
AVDD33
I120
CVDD12
LDO_BYP2
EPAD
Data Sheet
Description
Reset. This pin is active low. CMOS levels are determined with respect to IOVDD.
Serial Port Data Output. CMOS levels are determined with respect to IOVDD.
Serial Port Data Input/Output. CMOS levels are determined with respect to IOVDD.
Serial Port Clock Input. CMOS levels are determined with respect to IOVDD.
Serial Port Chip Select. This pin is active low. CMOS levels are determined with respect to IOVDD.
IOVDD Supply for CMOS Input/Output and SPI. Operational for 1.8 V IOVDD 3.3 V.
3.3 V Analog Supply for DAC Cores.
Do not connect to this pin.
Do not connect to this pin.
Do not connect to this pin.
1.2 V Clock Supply. Place bypass capacitors as near as possible to Pin 71.
2.4 V LDO. Requires a 1 μF capacitor to ground.
DAC1 Negative Current Output.
DAC1 Positive Current Output.
3.3 V Analog Supply for DAC Cores.
1.2 V Clock Supply. Place bypass capacitors as near as possible to Pin 76.
3.3 V Analog Supply for DAC Cores.
Do not connect to this pin.
Do not connect to this pin.
Do not connect to this pin.
1.2 V Clock Supply. Place bypass capacitors as near as possible to Pin 81.
2.4 V LDO. Requires a 1 μF capacitor to ground.
DAC0 Negative Current Output.
DAC0 Positive Current Output.
3.3 V Analog Supply for DAC Cores.
Output Current Generation Pin for DAC Full-Scale Current. Tie a 4 kΩ resistor from the I120 pin to ground.
1.2 V Clock Supply. Place bypass capacitors as near as possible to Pin 87.
LDO Clock Bypass for DAC PLL. This pin requires a 1 Ω resistor in series with a 1 μF capacitor to ground.
Exposed Pad. The exposed pad must be securely connected to the ground plane.
Rev. D | Page 14 of 117
Data Sheet
AD9135/AD9136
TERMINOLOGY
Integral Nonlinearity (INL)
INL is the maximum deviation of the actual analog output from
the ideal output, determined by a straight line drawn from zero
scale to full scale.
Differential Nonlinearity (DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Offset Error
Offset error is the deviation of the output current from the ideal
of 0 mA. For OUTx+, 0 mA output is expected when all inputs
are set to 0. For OUTx−, 0 mA output is expected when all
inputs are set to 1.
Gain Error
Gain error is the difference between the actual and ideal output
span. The actual span is determined by the difference between
the output when the input is at its minimum code and the
output when the input is at its maximum code.
Output Compliance Range
The output compliance range is the range of allowable voltages
at the output of a current output DAC. Operation beyond the
maximum compliance limits can cause either output stage
saturation or breakdown, resulting in nonlinear performance.
Temperature Drift
Offset drift is a measure of how far from full-scale range (FSR)
the DAC output current is at 25°C (in ppm). Gain drift is a
measure of the slope of the DAC output current across its full
ambient operating temperature range, TA (in ppm/°C).
Power Supply Rejection (PSR)
PSR is the maximum change in the full-scale output as the supplies
are varied from minimum to maximum specified voltages.
Settling Time
Settling time is the time required for the output to reach and
remain within a specified error band around its final value,
measured from the start of the output transition.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels, between the peak amplitude
of the output signal and the peak spurious signal within the dc
to Nyquist frequency of the DAC. Typically, energy in this band
is rejected by the interpolation filters. This specification,
therefore, defines how well the interpolation filters work and
the effect of other parasitic coupling paths on the DAC output.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in decibels.
Interpolation Filter
If the digital inputs to the DAC are sampled at a multiple rate of
fDATA (interpolation rate), a digital filter can be constructed that
has a sharp transition band near fDATA/2. Images that typically
appear around fDAC (output data rate) can be greatly suppressed.
Adjacent Channel Leakage Ratio (ACLR)
ACLR is the ratio in decibels relative to the carrier (dBc)
between the measured power within a channel relative to its
adjacent channel.
Complex Image Rejection
In a traditional two-part upconversion, two images are created
around the second IF frequency. These images have the effect
of wasting transmitter power and system bandwidth. By placing
the real part of a second complex modulator in series with the
first complex modulator, either the upper or lower frequency
image near the second IF can be rejected.
Adjusted DAC Update Rate
The adjusted DAC update rate is defined as the DAC update
rate divided by the smallest interpolating factor. For clarity on
DACs with multiple interpolating factors, the adjusted DAC
update rate for each interpolating factor may be given.
Physical Lane
Physical Lane x refers to SERDINx±.
Logical Lane
Logical Lane x refers to physical lanes after optionally being
remapped by the crossbar block (Register 0x308 to
Register 0x30B).
Link Lane
Link Lane x refers to logical lanes considered per link. When
paging Link 0 (Register 0x300[2] = 0), Link Lane x = Logical
Lane x. When paging Link 1 (Register 0x300[2] = 1, dual link
only), Link Lane x = Logical Lane x + 4.
Rev. D | Page 15 of 117
AD9135/AD9136
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0
–20
–40
–60
–80
–40
–60
100
200
300
400
500
fOUT (MHz)
12578-104
0
–100
0
MEDIAN
300
400
500
0dBFS
–6dBFS
–9dBFS
–12dBFS
–20
SFDR (dBc)
–40
–60
–80
–40
–60
100
200
300
400
500
fOUT (MHz)
12578-305
0
–100
0
100
200
300
400
500
fOUT (MHz)
12578-108
–80
–100
Figure 8. Single-Tone SFDR vs. fOUT in the First Nyquist Zone
over Digital Back Off, fDAC = 1966 MHz
Figure 5. Single-Tone SFDR vs. fOUT in the First Nyquist Zone,
fDAC = 1966 MHz and 2456 MHz
0
0
fDAC = 983MHz
fDAC = 1228MHz
fDAC = 1474MHz
IN-BAND SECOND HARMONIC
IN-BAND THIRD HARMONIC
MAX DIGITAL SPUR
–20
–20
–40
–40
IMD3 (dBc)
–60
–60
–80
–80
–100
0
100
200
300
fOUT (MHz)
400
500
12578-106
–100
Figure 6. Single-Tone Second and Third Harmonics and Maximum Digital Spur
in the First Nyquist Zone, fDAC = 1966 MHz, 0 dB Back Off
Rev. D | Page 16 of 117
0
100
200
300
400
fOUT (MHz)
Figure 9. Two-Tone Third IMD (IMD3) vs. fOUT,
fDAC = 983 MHz, 1228 MHz, and 1474 MHz
500
12578-109
SFDR (dBc)
200
Figure 7. Single-Tone SFDR vs. fOUT in the First Nyquist Zone
over Digital Back Off, fDAC = 983 MHz
fDAC = 1966MHz
fDAC = 2456MHz
–20
100
fOUT (MHz)
Figure 4. Single-Tone SFDR vs. fOUT in the First Nyquist Zone,
fDAC = 983 MHz, 1228 MHz, and 1474 MHz
0
0
12578-107
–80
–100
SFDR (dBc)
0dBFS
–6dBFS
–9dBFS
–12dBFS
–20
SFDR (dBc)
SFDR (dBc)
0
fDAC = 983MHz
fDAC = 1228MHz
fDAC = 1474MHz
Data Sheet
0
fDAC = 1966MHz
fDAC = 2456MHz
–20
–20
–40
–40
IMD3 (dBc)
–60
–80
1MHz TONE SPACING
16MHz TONE SPACING
35MHz TONE SPACING
–60
–80
0
100
200
300
400
500
fOUT (MHz)
100
200
300
400
500
fOUT (MHz)
–130
0dBFS
–6dBFS
–9dBFS
–12dBFS
–20
0
Figure 13. Two-Tone Third IMD (IMD3) vs. fOUT over Tone Spacing at 0 dB
Back Off, fDAC = 983 MHz and 1966 MHz
Figure 10. Two-Tone Third IMD (IMD3) vs. fOUT,
fDAC = 1966 MHz and 2456 MHz
0
–100
12578-110
–100
fDAC = 983MHz
fDAC = 1966MHz
12578-113
IMD3 (dBc)
0
AD9135/AD9136
fDAC = 983MHz
fDAC = 1228MHz
fDAC = 1474MHz
–135
NSD (dBm/Hz)
IMD3 (dBc)
–140
–40
–60
–145
–150
–155
–160
–80
100
200
300
400
500
fOUT (MHz)
–170
0
300
400
500
500
Figure 14. AD9136 Single-Tone (0 dBFS) NSD vs. fOUT,
fDAC = 983 MHz, 1228 MHz, and 1474 MHz
–130
0dBFS
–6dBFS
–9dBFS
–12dBFS
–20
200
fOUT (MHz)
Figure 11. Two-Tone Third IMD (IMD3) vs. fOUT over Digital Back Off,
fDAC = 983 MHz, Each Tone Is at −6 dBFS
0
100
12578-114
0
12578-111
–100
12578-421
–165
fDAC = 983MHz
fDAC = 1228MHz
fDAC = 1474MHz
–135
NSD (dBm/Hz)
IMD3 (dBc)
–140
–40
–60
–145
–150
–155
–160
–80
–100
0
100
200
300
fOUT (MHz)
400
500
12578-112
–165
Figure 12. Two-Tone Third IMD (IMD3) vs. fOUT over Digital Back Off,
fDAC = 1966 MHz, Each Tone Is at −6 dBFS
Rev. D | Page 17 of 117
–170
0
100
200
300
400
fOUT (MHz)
Figure 15. AD9135 Single-Tone (0 dBFS) NSD vs. fOUT,
fDAC = 983 MHz, 1228 MHz, and 1474 MHz
AD9135/AD9136
Data Sheet
–135
–140
–145
–145
NSD (dBm/Hz)
–140
–150
–155
–165
–165
200
300
400
500
–170
–130
fDAC = 1966MHz
fDAC = 2456MHz
–145
NSD (dBm/Hz)
–145
–150
–155
–165
–165
400
500
fOUT (MHz)
–170
12578-422
300
–130
–145
–145
NSD (dBm/Hz)
–140
–150
–155
–165
300
400
500
fOUT (MHz)
12578-116
–165
200
400
500
–155
–160
100
300
–150
–160
0
200
0dBFS
–6dBFS
–9dBFS
–12dBFS
–135
–140
–170
100
Figure 20. AD9136 Single-Tone NSD vs. fOUT over Digital Back Off,
fDAC = 1966 MHz
0dBFS
–6dBFS
–9dBFS
–12dBFS
–135
0
fOUT (MHz)
Figure 17. AD9135 Single-Tone (0 dBFS) NSD vs. fOUT,
fDAC = 1966 MHz and 2456 MHz
–130
500
–155
–160
200
400
–150
–160
100
300
0dBFS
–6dBFS
–9dBFS
–12dBFS
–135
–140
0
200
Figure 19. AD9135 Single-Tone NSD vs. fOUT over Digital Back Off,
fDAC = 983 MHz
–140
–170
100
fOUT (MHz)
–130
–135
0
12578-117
100
12578-115
0
Figure 16. AD9136 Single-Tone (0 dBFS) NSD vs. fOUT,
fDAC = 1966 MHz and 2456 MHz
NSD (dBm/Hz)
–155
–160
fOUT (MHz)
NSD (dBm/Hz)
–150
–160
–170
0dBFS
–6dBFS
–9dBFS
–12dBFS
Figure 18. AD9136 Single-Tone NSD vs. fOUT over Digital Back Off,
fDAC = 983 MHz
–170
0
100
200
300
400
500
fOUT (MHz)
Figure 21. AD9135 Single-Tone NSD vs. fOUT over Digital Back Off,
fDAC = 1966 MHz
Rev. D | Page 18 of 117
12578-424
–135
NSD (dBm/Hz)
–130
fDAC = 1966MHz
fDAC = 2456MHz
12578-423
–130
Data Sheet
–130
PLL OFF
PLL ON
–135
fDAC = 983MHz
fDAC = 1966MHz
–140
NSD (dBm/Hz)
AD9135/AD9136
–145
–150
–155
–160
–170
0
100
200
300
400
500
fOUT (MHz)
12578-118
12578-317
–165
Figure 22. AD9136 Single-Tone NSD (0 dBFS) vs. fOUT, fDAC = 983 MHz and
1966 MHz, PLL On and Off
–130
PLL OFF
PLL ON
–135
fDAC = 983MHz
fDAC = 1966MHz
–140
NSD (dBm/Hz)
Figure 25. AD9136 Four-Carrier W-CDMA ACLR, fOUT = 30 MHz,
fDAC = 983 MHz, 2× Interpolation, PLL Frequency = 122 MHz
–145
–150
–155
–160
–170
0
100
200
300
400
500
fOUT (MHz)
12578-425
12578-417
–165
Figure 23. AD9135 Single-Tone NSD (0 dBFS) vs. fOUT, fDAC = 983 MHz and
1966 MHz, PLL On and Off
–60
fOUT = 30MHz
fOUT = 200MHz
fOUT = 400MHz
–80
PHASE NOISE (dBc/Hz)
Figure 26. AD9135 Four-Carrier W-CDMA ACLR, fOUT = 30 MHz,
fDAC = 983 MHz, 2× Interpolation, PLL Frequency = 122 MHz
PLL OFF
PLL ON
–100
–120
–140
10
100
1k
10k
100k
OFFSET FREQUENCY (Hz)
1M
10M
12578-119
–180
12578-318
–160
Figure 24. AD9136 Single-Tone Phase Noise vs. Offset Frequency over fOUT,
fDAC = 2.0 GHz, PLL On and Off
Rev. D | Page 19 of 117
Figure 27. AD9136 Four-Carrier W-CDMA ACLR, fOUT = 122 MHz,
fDAC = 983 MHz, 2× Interpolation, PLL Frequency = 122 MHz
Data Sheet
12578-418
12578-320
AD9135/AD9136
Figure 31. AD9136 Four-Carrier W-CDMA ACLR, fOUT = 122 MHz,
fDAC = 1966 MHz, 4× Interpolation, PLL Frequency = 122 MHz
11675-420
12578-319
Figure 28. AD9135 Four-Carrier W-CDMA ACLR, fOUT = 122 MHz,
fDAC = 983 MHz, 2× Interpolation, PLL Frequency = 122 MHz
Figure 32. AD9135 Four-Carrier W-CDMA ACLR, fOUT = 122 MHz,
fDAC = 1966 MHz, 4× Interpolation, PLL Frequency = 122 MHz
Figure 30. AD9135 Four-Carrier W-CDMA ACLR, fOUT = 30 MHz,
fDAC = 1966 MHz, 4× Interpolation, PLL Frequency = 245 MHz
12578-433
12578-419
Figure 29. AD9136 Four-Carrier W-CDMA ACLR, fOUT = 30 MHz,
fDAC = 1966 MHz, 4× Interpolation, PLL Frequency = 245 MHz
Figure 33. AD9136 Output Performance of an Ultra Wideband (900 MHz)
QAM Signal, fDAC = 2 GHz, 1× Interpolation, Inverse sinc On,
JESD204B Mode 11
Rev. D | Page 20 of 117
Data Sheet
1300
1200
1100
1000
1500
2000
2500
Figure 34. Total Power Consumption vs. fDAC over Interpolation,
8 SERDES Lanes Enabled, 2 DACs Enabled, Digital Gain, Inverse Sinc and
DAC PLL Disabled
300
1
SUPPLY CURRENT (mA)
200
40
3
4
5
6
7
8
Figure 36. SVDD12 Current vs. Lane Rate over Number of SERDES Lanes and
Supply Voltage Setting
250
60
2
LANE RATE (Gbps)
DVDD12
CVDD12
PVDD12
AVDD33
1.2V SUPPLY
1.3V SUPPLY
3.3V SUPPLY
150
100
400
600
800
1000
1200
1400
1600
fDAC (MHz)
Figure 35. Power Consumption vs. fDAC over Digital Functions
0
400
600
800
100
fDAC (MHz)
1200
1400
1600
12578-329
50
20
12578-327
POWER CONSUMPTION (mW)
400
100
PLL (fDAC /fREF RATIO:4)
DIGITAL GAIN
INVERSE SINC
80
0
200
500
12578-328
1000
fDAC (MHz)
100
1.2V SVDD12 SUPPLY
1.3V SVDD12 SUPPLY
200
900
500
120
2 LANES
4 LANES
8 LANES
600
SVDD12 CURRENT (mA)
1400
700
1×
2×
4×
12578-326
TOTAL POWER CONSUMPTION (mW)
1500
AD9135/AD9136
Figure 37. DVDD12, CVDD12, PVDD12, and AVDD33 Supply Currents vs. fDAC
over Supply Voltage Setting, 2 DACs Enabled
Rev. D | Page 21 of 117
AD9135/AD9136
Data Sheet
THEORY OF OPERATION
The AD9135/AD9136 are 11-/16-bit, dual DACs with a SERDES
interface. Figure 2 shows a detailed functional block diagram of
the AD9135/AD9136. Eight high speed serial lanes carry data at
a maximum speed of 12.4 Gbps, and a 2120 MSPS input data rate
to each DAC. Compared to either LVDS or CMOS interfaces, the
SERDES interface simplifies pin count, board layout, and input
clock requirements to the device.
The clock for the input data is derived from the device clock
(required by the JESD204B specification). This device clock can
be sourced with a PLL reference clock used by the on-chip PLL
to generate a DAC clock or a high fidelity direct external DAC
sampling clock. The device can be configured to operate in one-,
two-, four-, or eight-lane modes, depending on the required
input data rate.
The digital datapath of the AD9135/AD9136 offers four
interpolation modes (1×, 2×, 4×, and 8×) through three half-band
filters with a maximum DAC sample rate of 2.8 GSPS. An inverse
sinc filter is provided to compensate for sinc related roll-off.
The AD9135/AD9136 DAC cores provide a fully differential
current output with a nominal full-scale current of 20 mA. The
full-scale current, IOUTFS, is user adjustable to between 13.9 mA
and 27.0 mA, typically. The differential current outputs are
complementary and are optimized for easy integration with the
Analog Devices the ADRF6720 AQM. The AD9135/AD9136
are capable of multichip synchronization that can both
synchronize multiple DACs and establish a constant and
deterministic latency (latency locking) path for the DACs.
The latency for each of the DACs remains constant from link
establishment to link establishment. An external alignment
(SYSREF±) signal makes the AD9135/AD9136 Subclass 1
compliant. Several modes of SYSREF± signal handling are
available for use in the system.
An SPI configures the various functional blocks and monitors
their statuses. The various functional blocks and the data
interface must be set up in a specific sequence for proper
operation (see the Device Setup Guide section). Simple SPI
initialization routines set up the JESD204B link and are included
in the evaluation board package. The following sections describe
the various blocks of the AD9135/AD9136 in greater detail.
Descriptions of the JESD204B interface, control parameters, and
various registers to set up and monitor the device are provided.
The recommended start-up routine reliably sets up the data link.
Rev. D | Page 22 of 117
Data Sheet
AD9135/AD9136
SERIAL PORT OPERATION
The serial port is a flexible, synchronous serial communications
port that allows easy interfacing with many industry-standard
microcontrollers and microprocessors. The serial input/output
(I/O) is compatible with most synchronous transfer formats,
including both the Motorola SPI and Intel® SSR protocols. The
interface allows read/write access to all registers that configure
the AD9135/AD9136. MSB first or LSB first transfer formats are
supported. The serial port interface can be configured as a 4-wire
interface or a 3-wire interface in which the input and output share
a single-pin I/O (SDIO).
CS 65
The serial clock pin synchronizes data to and from the device
and runs the internal state machines. The maximum frequency
of SCLK is 10 MHz. All data input is registered on the rising edge
of SCLK. All data is driven out on the falling edge of SCLK.
SPI
PORT
12578-044
SCLK 64
Figure 38. Serial Port Interface Pins
There are two phases to a communication cycle with the
AD9135/AD9136. Phase 1 is the instruction cycle (the writing
of an instruction byte into the device), coincident with the first
16 SCLK rising edges. The instruction word provides the serial
port controller with information regarding the data transfer cycle,
Phase 2 of the communication cycle. The Phase 1 instruction
word defines whether the upcoming data transfer is a read or
write, along with the starting register address for the following
data transfer.
A logic high on the CS pin followed by a logic low resets the
serial port timing to the initial state of the instruction cycle.
From this state, the next 16 rising SCLK edges represent the
instruction bits of the current I/O operation.
The remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the device and
the system controller. Phase 2 of the communication cycle is a
transfer of one or more data bytes. Eight × N SCLK cycles are
needed to transfer N bytes during the transfer cycle. Registers
change immediately upon writing to the last bit of each transfer
byte.
DATA FORMAT
The instruction byte contains the information shown in Table 13.
Table 13. Serial Port Instruction Word
I[15] (MSB)
R/W
SERIAL PORT PIN DESCRIPTIONS
Serial Clock (SCLK)
SDO 62
SDIO 63
A14 to A0, Bit 14 to Bit 0 of the instruction word, determine the
register that is accessed during the data transfer portion of the
communication cycle. For multibyte transfers, A[14:0] is the
starting address. The remaining register addresses are generated
by the device based on the address increment bits. If the address
increment bits are set high (Register 0x000, Bit 5 and Bit 2),
multibyte SPI writes start at A[14:0] and increment by 1 every
8 bits sent/received. If the address increment bits are set to 0,
the address decrements by 1 every 8 bits.
I[14:0]
A[14:0]
Chip Select (CS)
An active low input starts and gates a communication cycle.
CS allows more than one device to be used on the same serial
communications lines. The SDIO pin goes to a high impedance
state when this input is high. During the communication cycle,
chip select must stay low.
Serial Data I/O (SDIO)
This pin is a bidirectional data line. In 4-wire mode, this pin
acts as the data input, and SDO acts as the data output.
SERIAL PORT OPTIONS
The serial port can support both MSB first and LSB first data
formats. This functionality is controlled by the LSB first bits
(Register 0x000, Bit 6 and Bit 1). The default is MSB first
(LSBFIRST/LSBFIRST_M = 0).
When the LSB first bits = 0 (MSB first), the instruction and data
bits must be written from MSB to LSB. R/W is followed by
A[14:0] as the instruction word, and D[7:0] is the data-word.
When the LSB first bits = 1 (LSB first), the opposite is true.
A[0:14] is followed by R/W, which is subsequently followed by
D[0:7].
The serial port supports a 3-wire or 4-wire interface. When the
SDO active bits = 1 (Register 0x000, Bit 4 and Bit 3), a 4-wire
interface with a separate input pin (SDIO) and output pin (SDO)
is used. When the SDO active bits = 0, the SDO pin is unused
and the SDIO pin is used for both input and output.
R/W, Bit 15 of the instruction word, determines whether a read
or a write data transfer occurs after the instruction word write.
Logic 1 indicates a read operation, and Logic 0 indicates a write
operation.
Rev. D | Page 23 of 117
AD9135/AD9136
Data Sheet
INSTRUCTION CYCLE
Multibyte data transfers can be performed as well. This is done
by holding the CS pin low for multiple data transfer cycles
(eight SCLKs) after the first data transfer word following the
instruction cycle. The first eight SCLKs following the
instruction cycle read from or write to the register provided in
the instruction cycle. For each additional eight SCLK cycles, the
address is either incremented or decremented and the read/write
occurs on the new register. The direction of the address can be set
using the address increment bits (Register 0x000, Bit 5 and Bit 2).
When the address increment bits is 1, the multicycle addresses
are incremented. When the address increment bits is 0, the
addresses are decremented. A new write cycle can always be
initiated by bringing CS high and then low again.
DATA TRANSFER CYCLE
CS
SDIO
R/W A14 A13
A3
A2 A1
A0 D7 N D6N D5N
D30 D20 D10 D00
Figure 39. Serial Register Interface Timing, MSB First, ADDRINC = 0
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SDIO
A0
A1 A2
A12 A13 A14 R/W D00 D10 D20
D4N D5N D6N D7N
Figure 40. Serial Register Interface Timing, LSB First, ADDRINC = 1
CS
SDIO
DATA BIT n
DATA BIT n – 1
Figure 41. Timing Diagram for Serial Port Register Read
tSCLK
CS
tPWH
tPWL
SDIO
tDH
INSTRUCTION BIT 15
INSTRUCTION BIT 14
Figure 42. Timing Diagram for Serial Port Register Write
Rev. D | Page 24 of 117
12578-047
SCLK
12578-048
SCLK
tDV
tDS
12578-046
SCLK
To prevent confusion and to ensure consistency between devices,
the chip tests the first nibble following the address phase, ignoring
the second nibble. This test is completed independently from the
LSB first bit and ensures that there are extra clock cycles
following the soft reset bits (Register 0x000, Bit 0 and Bit 7).
This only applies when writing to Register 0x000.
tDCS
12578-045
SCLK
Data Sheet
AD9135/AD9136
CHIP INFORMATION
Register 0x003 to Register 0x006 contain chip information, as shown in Table 14.
Table 14. Chip Information
Information
Chip Type
Product ID
Product Grade
Device Revision
Description
The product type is high speed DAC, which is represented by a code of 0x04 in Register 0x003.
Eight MSBs in Register 0x005 and eight LSBs in Register 0x004. The product ID is 0x9144.
Register 0x006[7:4]. The product grade is 0x6 for the AD9136 and 0x4 for the AD9135.
Register 0x006[3:0]. The device revision is 0x08.
Rev. D | Page 25 of 117
AD9135/AD9136
Data Sheet
DEVICE SETUP GUIDE
OVERVIEW
The sequence of steps to properly set up the AD9135/AD9136 is
as follows:
1.
2.
3.
4.
5.
6.
7.
Set up the SPI interface, power up necessary circuit blocks,
make the required writes to the configuration registers, and set
up the DAC clocks (see the Step 1: Start Up the DAC section).
Set the digital features of the AD9135/AD9136 (see the
Step 2: Digital Datapath section).
Set up the JESD204B links (see the Step 3: Transport Layer
section).
Set up the physical layer of the SERDES interface (see the
Step 4: Physical Layer section).
Set up the data link layer of the SERDES interface (see the
Step 5: Data Link Layer section).
Check for errors (see the Step 6: Optional Error Monitoring
section).
Optionally, enable any needed features as described in the
Step 7: Optional Features section.
The register writes listed in Table 15 to Table 21 give the register
writes necessary to set up the AD9135/AD9136. Consider printing
this setup guide and filling in the Value column with the appropriate variable values for the conditions of the desired application.
The notation 0x, shaded in gray, indicates register settings that
must be filled in by the user. To fill in the unknown register values,
select the correct settings for each variable listed in the Variable
column of Table 15 to Table 21. The Description column describes
how to set variables or provides a link to a section where this is
described. A variable is noted by concatenating multiple terms. For
example, PdDACs is a variable corresponding to the value that is
determined for Register 0x011[6:3] in the Device Setup Guide
section.
STEP 1: START UP THE DAC
This section describes how to set up the SPI interface, power up
necessary circuit blocks, write to the required configuration
registers, and set up the DAC clocks, listed in Table 15.
Table 15. Power-Up and DAC Initialization Settings
Addr.
0x000
0x000
0x011
Bit No.
7
[6:3]
2
Value1
0xBD
0x3C
0x
0
Variable
PdDACs
0x080
0
0x
PdClocks
0x081
0x
PdSysref
1
Description
Soft reset.
Deassert reset, set 4-wire SPI.
Power up band gap.
PdDACs = 0x05 to power up
DAC0/DAC1. PdDACs = 0x07
if only using DAC0.
Power up master DAC.
PdClocks = 0 if DAC0/DAC1
are being used. PdClocks =
0x40 if only using DAC0.
PdSysref = 0x00 for Subclass 1.
PdSysref = 0x10 for Subclass 0.
See the Subclass Setup section
for details on subclass.
The registers in Table 16 must be written from their default
values to be the values listed in the table for the device to work
correctly. These registers must be written after any soft reset,
hard reset, or power-up occurs.
Table 16. Required Device Configurations
Addr.
0x12D
0x146
0x2A4
0x232
0x333
Value
0x8B
0x01
0xFF
0xFF
0x01
Description
Digital datapath configuration
Digital datapath configuration
Clock configuration
SERDES interface configuration
SERDES interface configuration
If using the optional DAC PLL, also set the registers in Table 17.
Table 17. Optional DAC PLL Configuration Procedure
Addr.
0x087
Value1
0x62
0x088
0xC9
0x089
0x0E
0x08A
0x12
0x08D
0x7B
0x1B0
0x00
0x1B9
0x24
0x1BC
0x0D
0x1BE
0x02
0x1BF
0x8E
0x1C0
0x2A
0x1C1
0x2A
0x1C4
0x08B
0x08C
0x085
Various
0x7E
0x
0x
0x
0x
0x083
0x10
1
Variable
LODivMode
RefDivMode
BCount
LookUpVals
Description
Optimal DAC PLL loop filter
settings
Optimal DAC PLL loop filter
settings
Optimal DAC PLL loop filter
settings
Optimal DAC PLL charge pump
settings
Optimal DAC LDO settings for
DAC PLL
Power DAC PLL blocks when
power machine disabled
Optimal DAC PLL charge pump
settings
Optimal DAC PLL VCO control
settings
Optimal DAC PLL VCO power
control settings
Optimal DAC PLL VCO calibration
settings
Optimal DAC PLL lock counter
length setting
Optimal DAC PLL charge pump
setting
Optimal DAC PLL varactor settings
See the DAC PLL Setup section
See the DAC PLL Setup section
See the DAC PLL Setup section
See Table 25 in the DAC PLL Setup
section for the list of register
addresses and values for each.
Enable the DAC PLL2
0x denotes a register value that the user must fill in. See the Variable and
Description columns for information on selecting the appropriate register
value.
2
Verify that Register 0x084[1] reads back 1 after enabling the DAC PLL to
indicate that the DAC PLL has locked.
0x denotes a register value that the user must fill in. See the Variable and
Description columns for information on selecting the appropriate register value.
Rev. D | Page 26 of 117
Data Sheet
AD9135/AD9136
STEP 2: DIGITAL DATAPATH
Table 19. Transport Layer Settings
This section describes which interpolation filters to use and
how to set the data format being used. Additional digital
features are available, including digital gain scaling and an
inverse sinc filter used to improve pass-band flatness. Table 22
provides further details on the feature blocks available.
Addr.
0x200
0x201
Bit
No.
0x300
Value1
0x00
0x
Variable
UnusedLanes
0x
6
CheckSumMode
3
DualLink
2
CurrentLink
Table 18. Digital Datapath Settings
Addr.
0x112
Bit
No.
Variable
InterpMode
Description
Select interpolation mode;
see the Interpolation section.
0x450
0x
DID
DataFmt = 0 if twos
complement; DataFmt = 1
if unsigned binary.
0x451
0x
BID
0x denotes a register value that the user must fill in. See the Variable and
Description columns for information on selecting the appropriate register value.
0x452
0x
LID
0x110
0x
7
1
Value1
0x
DataFmt
STEP 3: TRANSPORT LAYER
0x453
This section describes how to set up the JESD204B links. The
parameters are determined by the desired JESD204B operating
mode. See the JESD204B Setup section for details.
Table 19 shows the register settings for the transport layer. If
using dual-link mode, perform writes from Register 0x300 to
Register 0x47D with CurrentLink = 0 and then repeat the same
set of register writes with CurrentLink = 1 (Register 0x200 and
Register 0x201 need only be written once).
See the JESD204B
Setup section.
See the JESD204B
Setup section.
See the JESD204B
Setup section.
Set DID to match the
device ID sent by the
transmitter.
Set BID to match the
bank ID sent by the
transmitter.
Set LID to match the
lane ID sent by the
transmitter.
0x
7
Scrambling
[4:0]
L − 12
0x454
0x
F − 12
0x455
0x
K − 12
0x456
0x
M − 12
0x457
0x458
0x
0x
N − 12
[7:5]
Subclass
NP − 12
[4:0]
0x459
See the JESD204B
Setup section.
See the JESD204B
Setup section.
See the JESD204B
Setup section.
See the JESD204B
Setup section.
See the JESD204B
Setup section.
N = 16.
See the JESD204B
Setup section.
NP = 16.
0x
[7:5]
JESDVer
[4:0]
S − 12
0x45A
JESDVer = 1 for
JESD204B, JESDVer = 0
for JESD204A.
See the JESD204B
Setup section.
0x
7
[4:0]
HD
0x45D
0
0x
CF
Lane0Checksum
0x46C
0x
Lanes
0x476
0x
F
0x47D
0x
Lanes
1
Description
Power up the interface.
See the JESD204B
Setup section.
See the JESD204B
Setup section.
CF must equal 0.
See the JESD204B
Setup section.
Deskew lanes. See the
JESD204B Setup
section.
See the JESD204B
Setup section.
Enable lanes. See the
JESD204B Setup
section.
0x denotes a register value that the user must fill in. See the Variable and
Description columns for information on selecting the correct register value.
2
This JESD204B link parameter is programmed in n − 1 notation as noted. For
example, if the setup requires L = 8 (8 lanes per link), program L − 1 or 7 into
Register 0x453[4:0].
Rev. D | Page 27 of 117
AD9135/AD9136
Data Sheet
STEP 4: PHYSICAL LAYER
STEP 5: DATA LINK LAYER
This section describes how to set up the physical layer of the
SERDES interface. In this section, the input termination settings
are configured along with the CDR sampling and SERDES PLL.
This section describes how to set up the data link layer of the
SERDES interface. This section deals with SYSREF signal
processing, setting deterministic latency, and establishing the
link.
Table 20. Device Configurations and Physical Layer Settings
Addr.
0x2AA
0x2AB
0x2B1
0x2B2
0x2A7
0x2AE
0x314
0x230
Bit
No.
Table 21. Data Link Layer Settings
Value1
0xB7
0x87
0xB7
0x87
0x01
0x01
0x01
0x
5
[4:2]
1
0x206
0x206
0x289
2
[1:0]
Halfrate
0x2
OvSmp
0x00
0x01
0x
1
PLLDiv
0x284
0x285
0x286
0x287
0x62
0xC9
0x0E
0x12
0x28A
0x28B
0x7B
0x00
0x290
0x89
0x294
0x24
0x296
0x297
0x299
0x03
0x0D
0x02
0x29A
0x8E
0x29C
0x2A
0x29F
0x78
0x2A0
0x06
0x280
0x268
0x01
0x
[7:6]
[5:0]
1
Variable
EqMode
0x22
Description
SERDES interface termination
setting
SERDES interface termination
setting
Addr.
0x301
Autotune PHY setting
Autotune PHY setting
SERDES SPI configuration
Set up the CDR; see the SERDES
Clocks Setup section
SERDES PLL default configuration
Set up the CDR; see the SERDES
Clocks Setup section
Reset the CDR
Release the CDR reset
SERDES PLL configuration
Set the CDR oversampling for
PLL; see the SERDES Clocks
Setup section
Optimal SERDES PLL loop filter
Optimal SERDES PLL loop filter
Optimal SERDES PLL loop filter
Optimal SERDES PLL charge
pump
Optimal SERDES PLL VCO LDO
Optimal SERDES PLL
configuration
Optimal SERDES PLL VCO
varactor
Optimal SERDES PLL charge
pump
Optimal SERDES PLL VCO
Optimal SERDES PLL VCO
Optimal SERDES PLL
configuration
Optimal SERDES PLL VCO
varactor
Optimal SERDES PLL charge
pump
Optimal SERDES PLL VCO
varactor
Optimal SERDES PLL VCO
varactor
Enable the SERDES PLL2
See the Equalization Mode
Setup section
Required value (default)
Value1
0x
Variable
Subclass
0x304
0x
LMFCDel
0x305
0x
LMFCDel
0x306
0x
LMFCVar
0x307
0x
LMFCVar
0x03A
0x01
0x03A
0x81
0x03A
0xC1
SYSREF±
Signal
0x308
to
0x30B
0x
XBarVals
0x334
0x
InvLanes
0x300
1
0x denotes a register value that the user must fill in. See the Variable and
Description columns for information on selecting the correct register value.
2
Verify that Register 0x281[0] reads back 1 after enabling the SERDES PLL to
indicate that the SERDES PLL has locked.
Bit
No.
0x
6
3
2
CheckSumMode
DualLink
CurrentLink
[1:0]
EnLinks
Description
See the JESD204B
Setup section.
See the Link Latency
Setup section.
See the Link Latency
section.
See the Link Latency
Setup section.
See the Link Latency
Setup section.
Set sync mode = oneshot sync; see the
Syncing LMFC Signals
section for other sync
options.
Enable the sync
machine.
Arm the sync
machine.
If Subclass = 1, ensure
that at least one
SYSREF± edge is sent
to the device.2
If remapping lanes,
set up crossbar; see
the Crossbar Setup
section.
Invert the polarity of
the desired logical
lanes. Bit x of InvLanes
must be a 1 for each
Logical Lane x to
invert.
Enable the links.
See the JESD204B
Setup section.
Set to 0 to access
Link 0 status or 1 for
Link 1 status
readbacks. See the
JESD204B Setup
section.
EnLinks = 3 if
DualLink = 1 (enables
Link 0 and Link 1);
EnLinks = 1 if
DualLink = 0 (enables
Link 0 only).
0x denotes a register value that the user must fill in. See the Variable and
Description columns for information on selecting the correct register value.
2
Verify that Register 0x03B[3] reads back 1 after sending at least one SYSREF±
edge to the device to indicate that the LMFC sync machine has properly locked.
Rev. D | Page 28 of 117
Data Sheet
AD9135/AD9136
STEP 6: OPTIONAL ERROR MONITORING
Table 22. Optional Features
For JESD204B error monitoring, see the JESD204B Error
Monitoring section. For other error checks, see the Interrupt
Request Operation section.
Feature
Inverse Sinc
Default
On
Digital Gain
2.7 dB
DC Offset
Off
Group Delay
0
Downstream
Protection
Off
Self Calibration
Off
STEP 7: OPTIONAL FEATURES
There are a number of optional features that can be enabled.
Table 22 provides links to the sections describing each feature.
These features can be enabled during the Digital Datapath
configuration step, or after the link is set up, because it is not
required to configure them for the link to be established, unlike
interpolation. Unless otherwise noted, these features are paged
as described in the DAC Paging section. Paging is particularly
important for DAC specific settings like digital gain and dc offset.
Rev. D | Page 29 of 117
Description
Improves pass-band flatness. See the
Inverse Sinc section.
Multiplies data by a factor. Can
compensate inverse sinc usage or
balance I/Q amplitude. See the Digital
Gain section.
Used to cancel LO leakage. See the
DC Offset section.
Used to control overall latency. See
the Group Delay section.
Used to protect downstream
components. See the Downstream
Protection section.
Used to improve DAC linearity. Not
paged by the dual paging register.
See the Self Calibration section.
AD9135/AD9136
Data Sheet
DAC PLL SETUP
INTERPOLATION
This section explains how to select appropriate values for
LODivMode, RefDivMode, and BCount in the Step 1: Start Up
the DAC section. These parameters depend on the desired DAC
clock frequency (fDAC) and DAC reference clock frequency (fREF).
When using the DAC PLL, the reference clock signal is applied
to the CLK± differential pins (Pin 2 and Pin 3).
The transmit path can use zero to three cascaded interpolation
filters, which each provides a 2× increase in output data rate and
a low-pass function. Table 26 shows the different interpolation
modes and the respective usable bandwidth along with the
maximum fDATA rate attainable.
Table 23. DAC PLL LODivMode Settings
LO_DIV_MODE,
Register 0x08B[1:0]
1
2
3
DAC Frequency Range (MHz)
1500 to 2800
750 to 1500
420 to 750
Table 24. DAC PLL RefDivMode Settings
DAC PLL Reference
Frequency (fREF) (MHz)
35 to 80
80 to 160
160 to 320
320 to 640
640 to 1000
Divide by
(RefDivFactor)
1
2
4
8
16
REF_DIV_MODE,
Register 0x08C[2:0]
0
1
2
3
4
The VCO frequency (fVCO) is related to the DAC clock frequency
according to the following equation:
fVCO = fDAC × 2LODivMode + 1
where 6 GHz fVCO 12 GHz.
BCount must be between 6 and 127 and is calculated based on
fDAC and fREF as follows:
BCount = floor((fDAC)/(2 × fREF/RefDivFactor))
where RefDivFactor = 2RefDivMode (see Table 24).
Finally, to finish configuring the DAC PLL, set the VCO control
registers up as described in Table 25 based on the VCO frequency
(fVCO). Write the registers listed in the table with the corresponding
LookUpVals.
Table 25. VCO Control Lookup Table Reference
VCO Frequency
Range (GHz)
fVCO < 6.3
6.3 ≤ fVCO < 7.25
fVCO ≥ 7.25
Register
0x1B5
Setting
0x08
0x09
0x09
Register
0x1BB
Setting
0x03
0x03
0x13
Register
0x1C5
Setting
0x07
0x06
0x06
For more information on the DAC PLL, see the DAC Input
Clock Configurations section.
Table 26. Interpolation Modes and Their Usable Bandwidth
Interpolation
Mode
1× (bypass)
InterpMode
0x00
Usable
Bandwidth
0.5 × fDATA
2×
0x01
0.4 × fDATA
4×
8×
0x03
0x04
0.4 × fDATA
0.4 × fDATA
Maximum fDATA
(MSPS)
2120 (SERDES
limited)
1060 (SERDES
limited)
700
350
The usable bandwidth is defined for 1×, 2×, 4×, and 8× modes
as the frequency band over which the filters have a pass-band
ripple of less than ±0.001 dB and an image rejection of greater
than 85 dB. For more information, see the Interpolation Filters
section.
JESD204B SETUP
This section explains how to select a JESD204B operating mode
for a desired application. This section in turn defines appropriate
values for CheckSumMode, UnusedLanes, DualLink, CurrentLink,
Scrambling, L, F, K, M, N, NP, Subclass, S, HD, Lane0Checksum,
and Lanes needed for the Step 3: Transport Layer section.
Note that DualLink, Scrambling, F, K, N, NP, S, HD, and
Subclass must be set the same on the transmit side. For Mode 8,
Mode 9, and Mode 10, the number of converters (M) and the
lane count (L) on the transmit side must also match the receive
side. For Mode 11, Mode 12, and Mode 13, M and L on the
transmit side do not match the receive side. See Table 28 for
details.
For a summary of how a JESD204B system works and what each
parameter means, see the JESD204B Serial Data Interface section.
Available Operating Modes
Table 27. JESD204B Operating Modes (Single- or Dual-Link)
(Applies to Both JESD204B Tx and Rx)
Parameter
M (Converter Count)
L (Lane Count)
S ((Samples per Converter) per Frame)
F ((Octets per Frame) per Lane)
1
81
1
4
2
1
Mode
9
1
2
1
1
10
1
1
1
2
Mode 8 can only be used with 1× interpolation. Other interpolation options
are not available in this mode.
Rev. D | Page 30 of 117
Data Sheet
AD9135/AD9136
Table 28. JESD204B Operating Modes (Single-Link Only)
Parameter
M (Converter Count) (Tx Setting)
AD9135 and AD9136 M Setting1
(Rx Setting)
L (Lane Count) (Tx Setting)
AD9135 and AD9136 L Setting1
(Rx Setting)
S ((Samples per Converter) per Frame)
F ((Octets per Frame) per Lane)
112
2
1
Mode
12
2
1
13
2
1
8
4
4
2
2
1
2
1
1
1
1
2
1
Note that for Mode 11 to Mode 13, the M and L parameters programmed on
the receive side do not match the parameters on the transmit side. The
parameters on the transmit side reflect the true number of converters and
lanes per link.
2
Mode 11 can only be used with 1× interpolation. Other interpolation options
are not available in this mode.
For a particular application, the number of converters to use per
link (M) and the fDATA (DataRate) are known. The LaneRate and
number of lanes (L) can be traded off as follows:
DataRate = (DACRate)/(InterpolationFactor)
LaneRate = (20 × DataRate × M)/L
where LaneRate is between 1.44 Gbps and 12.4 Gbps.
Octets per frame per lane (F) and samples per convertor per
frame (S) define how the data is packed. If F = 1, the high density
setting must be set to one (HD = 1). Otherwise, set HD = 0.
Converter resolution and bits per sample (N and NP) must both
be set to 16. Frames per multiframe (K) must be set to 32 for
Mode 8, Mode 9, Mode 11, and Mode 12. Other modes can use
either K = 16 or K = 32.
DualLink
CurrentLink
Set CurrentLink to either 0 or 1 depending on whether Link 0
or Link 1, respectively, needs to be configured.
Lanes
Lanes is used to enable and deskew particular lanes in two
thermometer coded registers. The lanes setting for each of the
modes is given in Table 29.
Table 29. Lanes Setting per JESD Operating Mode
JESD Mode ID
Lanes
8
0x0F
9
0x03
10
0x01
11
0xFF
12
0x33
13
0x11
UnusedLanes
UnusedLanes is used to turn off unused circuit blocks to save
power. Each physical lane that is not being used (SERDINx±)
must be powered off by writing a 1 to the corresponding bit of
Register 0x201.
For example, if using Mode 9 in dual-link mode and sending
data on SERDIN0±, SERDIN1±, SERDIN4±, and SERDIN5±,
set UnusedLanes = 0xCC to power off Physical Lane 2, Lane 3,
Lane 6, and Lane 7.
CheckSumMode
CheckSumMode must match the checksum mode used on the
transmit side. If the checksum used is the sum of fields in the
link configuration table, CheckSumMode = 0. If summing the
registers containing the packed link configuration fields,
CheckSumMode = 1. For more information on the how to
calculate the two checksum modes, see the Lane0Checksum
section.
Lane0Checksum
DualLink sets up two independent JESD204B links, which
allows each link to be reset independently. If this functionality
is desired, set DualLink to 1; if a single link is desired, set
DualLink to 0. Note that Link 0 and Link 1 must have identical
parameters. The operating modes available when using dual- or
single-link mode are shown in Table 27. Additional single-link
modes that are available are shown in Table 28.
Scrambling
Scrambling is a feature that makes the spectrum of the link data
independent. This avoids spectral peaking and provides some
protection against data dependent errors caused by frequency
selective effects in the electrical interface. Set this variable to 1
if scrambling is being used, or to 0 if it is not.
Subclass
Subclass determines whether the latency of the device is
deterministic, meaning it requires an external synchronization
signal. See the Subclass Setup section for more information.
Lane0Checksum can be used for error checking purposes to
ensure that the transmitter is set up as expected.
If CheckSumMode = 0, the checksum is the lower eight bits of
the sum of the L − 1, M − 1, K − 1, N − 1, NP − 1, S − 1,
Scrambling, HD, Subclass, and JESDVer variables.
If CheckSumMode = 1, Lane0Checksum is the lower eight bits
of the sum of Register 0x450 to Register 0x45A. Select whether
to sum by fields or by registers, matching the setting on the
transmitter.
DAC Power-Down Setup
As described in the Step 1: Start Up the DAC section, PdDACs
must be set to 5 if both converters are being used either in a
single- or dual-link mode. If only one DAC is being used (M = 1
and in single-link mode), PdDACs must be set to 7.
Rev. D | Page 31 of 117
AD9135/AD9136
Data Sheet
SERDES CLOCKS SETUP
Link Delay Setup
This section describes how to select the appropriate Halfrate,
OvSmp, and PLLDiv settings in the Step 4: Physical Layer
section. These parameters depend solely on the lane rate (the
lane rate is established in the JESD204B Setup section).
LMFCVar and LMFCDel are used to impose delays such that all
lanes in a system arrive in the same LMFC cycle.
Table 30. SERDES Lane Rate Configuration Settings
Lane Rate (Gbps)
1.44 to 3.1
2.88 to 6.2
5.75 to 12.4
Halfrate
0
0
1
OvSmp
1
0
0
PLLDiv
2
1
0
The unit used internally for delays is the period of the internal
processing clock (PClock), whose rate is 1/40th the lane rate.
Delays that are not in PClock cycles must be converted before
they are used.
Some useful internal relationships are defined by
PClockPeriod = 40/LaneRate
Halfrate and OvSmp set how the clock detect and recover (CDR)
circuit samples. See the SERDES PLL section for an explanation
of how that circuit blocks works and the role of PLLDiv in the
block.
EQUALIZATION MODE SETUP
Set EqMode = 1 for a low power setting. Select this mode if the
insertion loss in the printed circuit board (PCB) is less than
12 dB. For insertion losses greater than 12 dB but less than
17.5 dB, set EqMode = 0. More details can be found in the
Equalization section.
LINK LATENCY SETUP
This section describes the steps necessary to guarantee
multichip deterministic latency in Subclass 1 and to guarantee
synchronization of links within a device in Subclass 0. Use this
section to fill in LMFCDel, LMFCVar, and Subclass in the Step 5:
Data Link Layer section. For more information, see the Syncing
LMFC Signals section.
PClockPeriod can be used to convert from time to PClock
cycles when needed.
PClockFactor = 4/F (frames per PClock)
PClockFactor is used to convert from units of PClock cycles to
FrameClock cycles, which is needed to set LMFCDel in
Subclass 1.
PClocksPerMF= K/PClockFactor (PClocks per LMFC cycle)
where PClocksPerMF is the number or PClock cycles in a
multiframe cycle.
The values for PClockFactor and PClockPerMF are given per
JESD mode in Table 31.
Table 31. PClockFactor and PClockPerMF
JESD Mode ID
PClockFactor
PClockPerMF (K = 32)
PClockPerMF (K = 16)
1
8
4
8
N/A1
9
4
8
N/A1
10
2
16
8
11
4
8
N/A1
12
4
8
N/A1
13
2
16
8
N/A means not applicable.
Subclass Setup
With Known Delays
The AD9135/AD9136 support JESD204B Subclass 0 and
Subclass 1 operation.
With information about all the system delays, LMFCVar and
LMFCDel can be calculated directly.
Subclass 1
This mode gives deterministic latency and allows links to be
synced to within ½ DAC clock periods. It requires an external
SYSREF± signal that is accurately phase aligned to the DAC clock.
Subclass 0
This mode does not require any signal on the SYSREF± pins,
which can be left disconnected.
Subclass 0 still requires that all lanes arrive within the same
LMFC cycle and that the two DACs must be synchronized to
each other; they are synchronized to an internal clock instead of
to the SYSREF± signal.
RxFixed (the fixed receiver delay in PClock cycles) and RxVar
(the variable receiver delay in PClock cycles) can be found in
Table 8. TxFixed (the fixed transmitter delay in PClock cycles)
and TxVar (the variable receiver delay in PClock cycles) can be
found in the data sheet of the transmitter used. PCBFixed (the
fixed PCB trace delay in PClock cycles) can be extracted from
software; because this is generally much smaller than a PClock
cycle, it can also be omitted. For both the PCB and transmitter
delays, convert the delays into PClock cycles.
For each lane,
Set Subclass to 0 or 1 as desired.
MinDelayLane = floor(RxFixed + TxFixed + PCBFixed)
MaxDelayLane = ceiling(RxFixed + RxVar + TxFixed +
TxVar + PCBFixed))
Rev. D | Page 32 of 117
Data Sheet
AD9135/AD9136
For safety, add a guard band of 1 PClock cycle to each end of
the link delay as in the following equations:
LMFCVar = (MaxDelay + 1) − (MinDelay − 1)
where:
MinDelay is the minimum of all MinDelayLane values across
lanes, links, and devices.
MaxDelay is the maximum of all MaxDelayLane values across
lanes, links, and devices.
Note that if LMFCVar must be more than 10, the AD9135/
AD9136 cannot tolerate the variable delay in the system.
Table 32. Register Configuration and Procedure for OneShot Sync
Addr.
0x301
0x03A
Bit.
No.
Value1
0x
Variable
Subclass
0x01
0x03A
0x81
0x03A
0xC1
SYSREF±
Signal
For Subclass 1
LMFCDel = ((MinDelay − 1) × PClockFactor) % K
For Subclass 0
0x
0x300
LMFCDel = (MinDelay − 1) % PClockPerMF
Program the same LMFCDel and LMFCVar across all links and
devices.
See the Link Delay Setup Example, with Known Delays section
for an example calculation.
6
CheckSumMode
3
DualLink
2
CurrentLink
Set to 0 to access
Link 0 status or 1
for Link 1 status
readbacks. See the
JESD204B Setup
section.
[1:0]
EnLinks
EnLinks = 3 if in
DualLink mode to
enable Link 0 and
Link 1; EnLinks = 1
if not in DualLink
mode to enable
Link 0
Without Known Delays
If comprehensive delay information is not available or known,
the AD9135/AD9136 can read back the link latency between
the local LMFC for each link (LMFCRX) and the last arriving
LMFC boundary in PClock cycles. This information is then
used to calculate LMFCVar and LMFCDel.
For each link (on each device),
1.
2.
3.
4.
5.
Power up the board.
Follow the steps in Table 15 through Table 21 of the Device
Setup Guide.
Set the subclass and perform a sync. For one-shot sync,
perform the writes in Table 32. See the Syncing LMFC
Signals section for alternate sync modes.
Record DYN_LINK_LATENCY_0 (Register 0x302) as a
value of Delay for that link and power cycle.
Record DYN_LINK_LATENCY_1 (Register 0x303) as a
value of Delay for that link and power cycle the system.
Repeat Step 1 to Step 5 twenty times for each device in the
system. Keep a single list of the Delay values across all runs and
devices.
1
Description
Set subclass
Set sync mode to
one-shot sync
Enable the sync
machine
Arm the sync
machine
If Subclass = 1,
ensure that at
least one SYSREF±
edge is sent to the
device
Enable the links
See the JESD204B
Setup section
See the JESD204B
Setup section
0x denotes a register value that the user must fill in. See the Variable and
Description columns for information on selecting the appropriate register value.
The list of Delay values is used to calculate LMFCDel and
LMFCVar, however, first some of the Delay values may need to
be remapped.
The maximum possible value for DYN_LINK_LATENCY_x
is one less than the number of PClocks in a multiframe
(PClocksPerMF). It is possible that a rollover condition may
be encountered; that is, the set of recorded Delay values
may roll over the edge of a multiframe. If so, Delay values
may be near both 0 and PClocksPerMF. If this occurs, add
PClocksPerMF to the set of values near 0.
For example, for Delay value readbacks of 6, 7, 0, and 1, the 0
and 1 Delay values must be remapped to 8 and 9, making the
new set of Delay values 6, 7, 8, and 9.
Rev. D | Page 33 of 117
AD9135/AD9136
Data Sheet
Across power cycles, links, and devices,
CROSSBAR SETUP
Register 0x308 to Register 0x30B allow arbitrary mapping of
physical lanes (SERDINx±) to logical lanes used by the SERDES
deframers.
MinDelay is the minimum of all Delay measurements
MaxDelay is the maximum of all Delay measurements
For safety, a guard band of 1 PClock cycle is added to each end
of the link delay and calculate LMFCVar and LMFCDel with
the following equation:
LMFCVar = (MaxDelay + 1) − (MinDelay − 1)
Note that if LMFCVar must be more than 10, the AD9135/
AD9136 cannot tolerate the variable delay in the system.
For Subclass 1
LMFCDel = ((MinDelay − 1) × PClockFactor)
For Subclass 0
LMFCDel = (MinDelay − 1) % PClockPerMF
Program the same LMFCDel and LMFCVar across all links and
devices.
See the Link Delay Setup Example, Without Known Delay
section for an example calculation.
Table 33. Crossbar Registers
Address
0x308
0x308
0x309
0x309
0x30A
0x30A
0x30B
0x30B
Bits
[2:0]
[5:3]
[2:0]
[5:3]
[2:0]
[5:3]
[2:0]
[5:3]
Logical Lane
LOGICAL_LANE0_SRC
LOGICAL_LANE1_SRC
LOGICAL_LANE2_SRC
LOGICAL_LANE3_SRC
LOGICAL_LANE4_SRC
LOGICAL_LANE5_SRC
LOGICAL_LANE6_SRC
LOGICAL_LANE7_SRC
Write each LOGICAL_LANEy_SRC with the number (x) of the
desired physical lane (SERDINx±) from which to receive data.
By default, all logical lanes use the corresponding physical lane
as their data source. For example, by default LOGICAL_LANE0_
SRC = 0, meaning that Logical Lane 0 receives data from
Physical Lane 0 (SERDIN0±). To use SERDIN4± as the source
for Logical Lane 0, write LOGICAL_LANE0_SRC = 4.
Rev. D | Page 34 of 117
Data Sheet
AD9135/AD9136
JESD204B SERIAL DATA INTERFACE
JESD204B OVERVIEW
The AD9135/AD9136 have eight JESD204B data ports that
receive data. The eight JESD204B ports can be configured as
part of a single JESD204B link or as part of two separate
JESD204B links (dual-link mode) that share a single system
reference (SYSREF±) and device clock (CLK±).
The JESD204B serial interface hardware consists of three layers:
the physical layer, the data link layer, and the transport layer.
These sections of the hardware are described in subsequent
sections, including information for configuring every aspect of
the interface. Figure 43 shows the communication layers
implemented in the AD9135/AD9136 serial data interface to
recover the clock and deserialize, descramble, and deframe the
data before it is sent to the digital signal processing section of
the device.
The physical layer establishes a reliable channel between the
transmitter and the receiver, the data link layer unpacks the
data into octets and descrambles the data, and the transport
layer receives the descrambled JESD204B frames and converts
them to DAC samples.
A number of JESD204B parameters (L, F, K, M, N, NP, S, HD,
and Scrambling) defines how the data is packed and instruct the
device how to turn the serial data into samples. These parameters
are defined in detail in the Transport Layer section.
Only certain combinations of parameters are supported. Each
supported combination is called a mode. In total, six modes are
supported by the AD9135/AD9136. There are three supported
single-link modes, as described in Table 35, and three modes that
can operate in either single- or dual-link mode, as described in
Table 34. These tables show the associated clock rates when the
lane rate is 10 Gbps.
For a particular application, the number of converters to use (M)
and DataRate are known. Calculate LaneRate and number of
lanes (L) as follows:
DataRate = (DACRate)/(InterpolationFactor)
LaneRate = (20 × DataRate × M)/L
where LaneRate must be between 1.44 Gbps and 12.4 Gbps.
Achieving and recovering synchronization of the lanes is very
important. To simplify the interface to the transmitter, the
AD9135/AD9136 designate a master synchronization signal for
each JESD204B link. In single-link mode, SYNCOUT0± is used as
the master signal for all lanes; in dual-link mode, SYNCOUT0± is
used as the master signal for Link 0, and SYNCOUT1± is used as
the master signal for Link 1. If any lane in a link loses
synchronization, a resynchronization request is sent to the
transmitter via the synchronization signal of the link. The
transmitter stops sending data and instead sends synchronization
characters to all lanes in that link until resynchronization is
achieved.
SYNCOUT0±
SYNCOUT1±
PHYSICAL
LAYER
SERDIN0±
DATA LINK
LAYER
DESERIALIZER
I DATA[15:0] OR [11:0]
QBD/
DESCRAMBLER
FRAME TO
SAMPLES
TO
DAC
Q DATA[15:0] OR [11:0]
DESERIALIZER
12578-004
SERDIN7±
TRANSPORT
LAYER
SYSREF±
Figure 43. Functional Block Diagram of Serial Link Receiver
Rev. D | Page 35 of 117
AD9135/AD9136
Data Sheet
Table 34. Single-Link and Dual-Link JESD204B Operating Modes
Parameter
M (Converter Counts)
L (Lane Counts)
S ((Samples per Converter) per Frame)
F ((Octets per Frame) per Lane)
Example Clocks for 10 Gbps Lane Rate
PClock Rate (MHz)
Frame Rate (MHz)
Data Rate (MHz)
8
1
4
2
1
250
1000
2000
Mode
9
1
2
1
1
10
1
1
1
2
250
1000
1000
250
500
500
The AD9135/AD9136 autocalibrate the input termination to
50 Ω. Before running the termination calibration, write to
Register 0x2AA, Register 0x2AB, Register 0x2B1, and Register
0x2B2 as described in Table 36 to guarantee proper calibration.
The termination calibration begins when Register 0x2A7[0] and
Register 0x2AE[0] transition from low to high. Register 0x2A7
controls autocalibration for PHY 0, PHY 1, PHY 6, and PHY 7.
Register 0x2AE controls autocalibration for PHY 2, PHY 3,
PHY 4, and PHY 5.
The PHY termination autocalibration routine is shown in Table 36.
Table 36. PHY Termination Autocalibration Routine
8
4
4
2
13
2
1
2
1
2
1
1
1
1
2
250
1000
2000
250
1000
1000
250
500
500
Note that for Mode 11 to Mode 13, the M and L parameters programmed on
the receive side do not match the parameters on the transmit side. The
parameters on the transmit side reflect the true number of converters and
lanes per link.
PHYSICAL LAYER
The physical layer of the JESD204B interface, hereafter referred
to as the deserializer, has eight identical channels. Each channel
consists of the terminators, an equalizer, a clock and data recovery
(CDR) circuit, and the 1:40 demux function (see Figure 45).
Value
0xB7
0x87
0xB7
0x87
0x01
0x01
Description
SERDES interface termination configuration
SERDES interface termination configuration
SERDES interface termination configuration
SERDES interface termination configuration
Autotune PHY terminations
Autotune PHY terminations
The input termination voltage of the DAC is sourced externally
via the VTT pins (Pin 21, Pin 25, Pin 42, and Pin 46). Set VTT by
connecting it to SVDD12. It is recommended that the JESD204B
inputs be ac-coupled to the JESD204B transmit device using
100 nF capacitors.
Receiver Eye Mask
The AD9135/AD9136 comply with the JESD204B specification
regarding the receiver eye mask and are capable of capturing
data that complies with this mask. Figure 44 shows the receiver
eye mask normalized to the data rate interval with a VTT swing
of 600 mV. See the JESD204B specification for more information
regarding the eye mask and permitted receiver eye opening.
LV-OIF-11G-SR RECEIVER EYE MASK
(3.125Mbps ≥ UI ≤ 12.5Gbps)
525
JESD204B data is input to the AD9135/AD9136 via the SERDINx±
1.2 V differential input pins as per the JESD204B specification.
Interface Power-Up and Input Termination
Before using the JESD204B interface, it must be powered up by
setting Register 0x200[0] = 0. In addition, each physical lane that is
not being used (SERDINx±) must be powered down. To do so,
set the corresponding Bit x for Physical Lane x in Register 0x201 to
0 if the physical lane is being used, and to 1 if it is not being used.
55
0
–55
–525
0
0.35
0.5
0.65
TIME (UI)
Figure 44. Receiver Eye Mask
DESERIALIZER
SERDINx±
TERMINATION
EQUALIZER
CDR
1:40
SPI CONTROL
FROM PLL
Figure 45. Deserializer Block Diagram
Rev. D | Page 36 of 117
12578-006
1
11
2
1
Address
0x2AA
0x2AB
0x2B1
0x2B2
0x2A7
0x2AE
1.00
12578-007
Parameter
M (Converter Count) (Tx setting)
AD9135 and AD9136 M Setting1
(Rx Setting)
L (Lane Count) (Tx setting)
AD9135 and AD9136 L Setting1
(Rx Setting)
S ((Samples per Converter) per Frame)
F ((Octets per Frame) per Lane)
Example Clocks for 10 Gbps Lane Rate
PClock Rate (MHz)
Frame Rate (MHz)
Data Rate (MHz)
Mode
12
2
1
AMPLITUDE (mV)
Table 35. Single-Link JESD204B Operating Modes
Data Sheet
AD9135/AD9136
Clock Relationships
Register 0x280 controls the synthesizer enable and recalibration.
The following clocks rates are used throughout the rest of the
JESD204B section. The relationship between any of the clocks
can be derived from the following equations:
To enable the SERDES PLL, first set the PLL divider register
according to Table 37, and then enable the SERDES PLL by
writing 1 to Register 0x280[0].
DataRate = (DACRate)/(InterpolationFactor)
Confirm that the SERDES PLL is working by reading
Register 0x281. If Register 0x281[0] = 1, the SERDES PLL has
locked. If Register 0x281[3] = 1, the SERDES PLL was successfully
calibrated. If Register 0x281[4] or Register 0x281[5] are high, the
PLL has reached the upper or lower end of its calibration band and
must be recalibrated by writing 0 and then 1 to Register 0x280[2].
LaneRate = (20 × DataRate × M)/L
ByteRate = LaneRate/10
where:
M is the JESD204B parameter for converters per link.
L is the JESD204B parameter for lanes per link.
SERDES PLL Fixed Register Writes
This relationship comes from 8-bit/10-bit encoding, where each
byte is represented by 10 bits.
To optimize the SERDES PLL across all operating conditions,
the register writes in Table 38 are recommended.
PClockRate = ByteRate/4
Table 38. SERDES PLL Fixed Register Writes
The processing clock is used for a quad-byte decoder.
FrameRate = ByteRate/F
where F is defined as bytes per frame per lane.
PClockFactor = FrameRate/PClockRate = 4/F
where F is the JESD204B parameter for octets per frame per lane.
SERDES PLL
Functional Overview of the SERDES PLL
The independent SERDES PLL uses integer-N techniques to
achieve clock synthesis. The entire SERDES PLL is integrated
on-chip, including the VCO and the loop filter. The SERDES
PLL VCO operates over the range of 5.65 GHz to 12.04 GHz.
In the SERDES PLL, a VCO divider block divides the VCO clock
by 2 to generate a 2.825 GHz to 6.2 GHz quadrature clock for the
deserializer cores. This clock is the input to the clock and data
recovery block that is described in the Clock and Data Recovery
section.
The reference clock to the SERDES PLL is always running at a
frequency, fREF, that is equal to 1/40 of the lane rate (PClockRate).
This clock is divided by the DivFactor value to deliver a clock to
the PFD block that is between 35 MHz and 80 MHz. Table 37
includes the respective SERDES_PLL_DIV_MODE register
settings for each of the desired DivFactor options available.
Address
0x284
0x285
0x286
0x287
0x28A
0x28B
0x290
0x294
0x296
0x297
0x299
0x29A
0x29C
0x29F
0x2A0
Divide by
(DivFactor)
1
2
4
Description
Optimal SERDES PLL loop filter
Optimal SERDES PLL loop filter
Optimal SERDES PLL loop filter
Optimal SERDES PLL charge pump
Optimal SERDES PLL VCO LDO
Optimal SERDES PLL configuration
Optimal SERDES PLL VCO varactor
Optimal SERDES PLL charge pump
Optimal SERDES PLL VCO
Optimal SERDES PLL VCO
Optimal SERDES PLL configuration
Optimal SERDES PLL VCO varactor
Optimal SERDES PLL charge pump
Optimal SERDES PLL VCO varactor
Optimal SERDES PLL VCO varactor
SERDES PLL IRQ
SERDES PLL lock and lost signals are available as IRQ events.
Use Register 0x01F[3:2] to enable these signals, and then use
Register 0x023[3:2] to read back their statuses and reset the IRQ
signals. See the Interrupt Request Operation section for more
information.
Table 37. SERDES PLL Divider Settings
LaneRate (Gbps)
1.44 to 3.1
2.88 to 6.2
5.75 to 12.4
Value
0x62
0xC9
0x0E
0x12
0x7B
0x00
0x89
0x24
0x03
0x0D
0x02
0x8E
0x2A
0x78
0x06
SERDES_PLL_DIV_MODE,
Register 0x289[1:0]
2
1
0
Rev. D | Page 37 of 117
AD9135/AD9136
Data Sheet
2.825GHz TO 6.2GHz
OUTPUT
VCO
LDO
CHARGE
PUMP
PFD
80MHz
REF DIVIDER MAX
N = 1, 2, 4
fREF
BIT RATE ÷ 40
DIVIDER
(1, 2, 4)
C1
R1
UP
C2
C3
I Q
LC VCO
5.65GHz TO 12.4GHz
÷2
DOWN
÷80
R3
ALC CAL
CAL CONTROL BITS
12578-011
FO CAL
3.2mA
Figure 46. SERDES PLL Synthesizer Block Diagram Including VCO Divider Block
Clock and Data Recovery
Equalization
The deserializer is equipped with a CDR circuit. Instead of
recovering the clock from the JESD204B serial lanes, the CDR
recovers the clocks from the SERDES PLL. The 2.825 GHz to
6.2 GHz output from the SERDES PLL, shown in Figure 46, is
the input to the CDR.
To compensate for signal integrity distortions for each PHY
channel due to PCB trace length and impedance, the AD9135/
AD9136 employ an easy to use, low power equalizer on each
JESD204B channel. The AD9135/AD9136 equalizers can
compensate for insertion losses far greater than required by the
JESD204B specification. The equalizers have two modes of
operation that are determined by the EQ_POWER_MODE
register setting in Register 0x268[7:6]. In low power mode
(Register 0x268[7:6] = 2b’01) and operating at the maximum
lane rate of 10 Gbps, the equalizer can compensate for up to 12 dB
of insertion loss. In normal mode (Register 0x268[7:6] = 2b’00),
the equalizer can compensate for up to 17.5 dB of insertion loss.
This performance is shown in Figure 47 as an overlay to the
JESD204B specification for insertion loss. Figure 47 shows the
equalization performance at 10.0 Gbps, near the maximum
baud rate for the AD9135/AD9136.
A CDR sampling mode must be selected to generate the lane
rate clock inside the device. If the desired lane rate is greater
than 5.65 GHz, half rate CDR operation must be used. If the
desired lane rate is less than 5.65 GHz, disable half rate operation.
If the lane rate is less than 2.825 GHz, disable half rate operation
and enable 2× oversampling to recover the appropriate lane rate
clock. Table 39 gives a breakdown of CDR sampling settings that
must be set dependent on the LaneRate.
Table 39. CDR Operating Modes
LaneRate (Gbps)
1.44 to 3.1
2.88 to 6.2
5.75 to 12.4
ENHALFRATE,
Register 0x230[5]
0
0
1
CDR_OVERSAMP,
Register 0x230[1]
1
0
0
The CDR circuit synchronizes the phase used to sample the data on
each serial lane independently. This independent phase adjustment
per serial interface ensures accurate data sampling and eases the
implementation of multiple serial interfaces on a PCB.
After configuring the CDR circuit, reset it and then release the
reset by writing 1 and then 0 to Register 0x206[0].
Power-Down Unused PHYs
Note that any unused and enabled lanes consume extra power
unnecessarily. Each lane that is not being used (SERDINx±)
must be powered off by writing a 1 to the corresponding bit of
PHY_PD (Register 0x201).
Figure 48 and Figure 49 are provided as points of reference for
hardware designers and show the insertion loss for various
lengths of well laid out stripline and microstrip transmission
lines. See the Hardware Considerations section for specific layout
recommendations for the JESD204B channel.
Low power mode is recommended if the insertion loss of the
JESD204B PCB channels is less than that of the most lossy
supported channel for low power mode (shown in Figure 47).
If the insertion loss is greater than that, but still less than that of
the most lossy supported channel for normal mode (shown in
Figure 47), use normal mode. At 10 Gbps operation, the equalizer
in normal mode consumes about 4 mW more power per lane
used than in low power equalizer mode. Note that either mode
can be used in conjunction with transmitter preemphasis to
ensure functionality and/or to optimize for power.
Rev. D | Page 38 of 117
Data Sheet
AD9135/AD9136
0
JESD204B SPEC ALLOWED
CHANNEL LOSS
2
INSERTION LOSS (dB)
4
AD9135/AD9136
ALLOWED
CHANNEL LOSS
(LOW POWER MODE)
6
8
EXAMPLE OF
AD9135/AD9136
COMPATIBLE
CHANNEL (LOW
POWER MODE)
10
12
EXAMPLE OF
AD9135/AD9136
COMPATIBLE
CHANNEL
(NORMAL MODE)
AD9135/AD9136
ALLOWED
CHANNEL LOSS
(NORMAL MODE)
14
16
DATA LINK LAYER
EXAMPLE OF
JESD204B
COMPLIANT
CHANNE L
18
20
22
24
5.0
7.5
12578-339
2.5
FREQUENCY (GHz)
Figure 47. Insertion Loss Allowed
0
The AD9135/AD9136 can operate as a single-link or dual-link
high speed JESD204B serial data interface. When operating in
dual-link mode, configure both links with the same JESD204B
parameters because they share a common device clock and system
reference. All eight lanes of the JESD204B interface handle link
layer communications such as code group synchronization,
frame alignment, and frame synchronization.
–5
ATTENUATION (dB)
–10
–15
–20
STRIPLINE = 6”
STRIPLINE = 10”
STRIPLINE = 15”
STRIPLINE = 20”
STRIPLINE = 25”
STRIPLINE = 30”
–25
–30
–40
1
2
3
4
5
6
7
8
9
10
FREQUENCY (GHz)
12578-009
–35
0
Figure 48. Insertion Loss of 50 Ω Striplines on FR4
0
–5
–15
–20
6” MICROSTRIP
10” MICROSTRIP
15” MICROSTRIP
20” MICROSTRIP
25” MICROSTRIP
30” MICROSTRIP
–30
–35
–40
0
1
2
3
4
5
6
7
8
9
FREQUENCY (GHz)
10
The AD9135/AD9136 decode 8-bit/10-bit control characters,
allowing marking of the start and end of the frame and
alignment between serial lanes. Each AD9135/AD9136 serial
interface link can issue a synchronization request by setting its
SYNCOUT0±/ SYNCOUT1± signal low. The synchronization
protocol follows Section 4.9 of the JESD204B standard. When a
stream of four consecutive /K/ symbols is received, the
AD9135/AD9136 deactivate the synchronization request by
setting the SYNCOUT0±/ SYNCOUT1± signal high at the next
internal LMFC rising edge. Then, the AD9135/AD9136 wait for
the transmitter to issue an ILAS. During the ILAS sequence, all
lanes are aligned using the /A/ to /R/ character transition as
described in the JESD204B Serial Link Establishment section.
Elastic buffers hold early arriving lane data until the alignment
character of the latest lane arrives. At this point, the buffers for
all lanes are released and all lanes are aligned (see Figure 52).
12578-010
ATTENUATION (dB)
–10
–25
The data link layer of the AD9135/AD9136 JESD204B interface
accepts the deserialized data from the PHYs and deframes and
descrambles them so that data octets are presented to the
transport layer to be put into DAC samples. Figure 50 shows
the link mode block diagrams for single-link and dual-link
configurations and the interaction between the physical layer
and logical layer. The DACs can only be configured in
sequential order; for example, in Mode 10, when in single-link
mode, the AD9135/AD9136 only uses Logical Lane 0 and
DAC0. Logical lanes must be set according to Table 29 for the
desired mode. See the Mode Configuration Maps section for
further details on each of the mode configurations supported.
The architecture of the data link layer is shown in Figure 51.
The data link layer consists of a synchronization FIFO for each
lane, a crossbar switch, a deframer, and descrambler.
Figure 49. Insertion Loss of 50 Ω Microstrips on FR4
Rev. D | Page 39 of 117
AD9135/AD9136
Data Sheet
LOGICAL LANE 0/LINK 0 LANE 0
SERDIN1±/PHYSICAL LANE 1
LOGICAL LANE 1/LINK 0 LANE 1
SERDIN2±/PHYSICAL LANE 2
SERDIN3±/PHYSICAL LANE 3
SERDIN4±/PHYSICAL LANE 4
SERDIN5±/PHYSICAL LANE 5
LOGICAL LANE 2/LINK 0 LANE 2
CROSSBAR
REGISTER
0x308
TO
REGISTER
0x30B
DAC0
LOGICAL LANE 3/LINK 0 LANE 3
LOGICAL LANE 4/LINK 0 LANE 4
LOGICAL LANE 6/LINK 0 LANE 6
SERDIN7±/PHYSICAL LANE 7
LOGICAL LANE 7/LINK 0 LANE 7
LOGICAL LANE 0/LINK 0 LANE 0
SERDIN1±/PHYSICAL LANE 1
LOGICAL LANE 1/LINK 0 LANE 1
SERDIN2±/PHYSICAL LANE 2
LOGICAL LANE 2/LINK 0 LANE 2
SERDIN5±/PHYSICAL LANE 5
DAC1
LOGICAL LANES
SERDIN0±/PHYSICAL LANE 0
SERDIN4±/PHYSICAL LANE 4
QUAD-BYTE
DEFRAMER
(QBD0)
LOGICAL LANE 5/LINK 0 LANE 5
SERDIN6±/PHYSICAL LANE 6
SERDIN3±/PHYSICAL LANE 3
DAC CORE
QBD
SERDIN0±/PHYSICAL LANE 0
PHYSICAL LANES
CROSSBAR
REGISTER
0x308
TO
REGISTER
0x30B
DAC0
QUAD-BYTE
DEFRAMER 1
(QBD1)
DAC1
LOGICAL LANE 4/LINK 1 LANE 0
LOGICAL LANE 5/LINK 1 LANE 1
SERDIN6±/PHYSICAL LANE 6
LOGICAL LANE 6/LINK 1 LANE 2
SERDIN7±/PHYSICAL LANE 7
LOGICAL LANE 7/LINK 1 LANE 3
LOGICAL LANES
12578-550
PHYSICAL LANES
QUAD-BYTE
DEFRAMER 0
(QBD0)
LOGICAL LANE 3/LINK 0 LANE 3
Figure 50. Link Mode Functional Diagram
DATA LINK LAYER
SYNCOUTx±
QUAD-BYTE
DEFRAMER
QBD
DES_DATA0
SERDIN0_CLK
SERDIN0
FIFO
CROSS
BAR
SWITCH
SYSREF
SERDIN7
FIFO
LANE 0 OCTETS
LANE 7 OCTETS
SYSTEM CLOCK
PHASE DETECT
12578-012
DES_DATA7
SERDIN7_CLK
DESCRAMBLE
DUAL-LINK MODE
LOGICAL
LAYER
CROSSBAR
10-BIT/8-BIT DECODE
SINGLE-LINK MODE
PHYSICAL
LAYER (PHY)
PCLK
SPI CONTROL
Figure 51. Data Link Layer Block Diagram
Rev. D | Page 40 of 117
Data Sheet
AD9135/AD9136
L RECEIVE LANES
(EARLIEST ARRIVAL) K K K R D D
D D A R Q C
L RECEIVE LANES
(LATEST ARRIVAL) K K K K K K K R D D
C
D D A R Q C
D D A R D D
C
D D A R D D
0 CHARACTER ELASTIC BUFFER DELAY OF LATEST ARRIVAL
4 CHARACTER ELASTIC BUFFER DELAY OF EARLIEST ARRIVAL
L ALIGNED
RECEIVE LANES K K K K K K K R D D
D D A R Q C
C
12578-013
K = K28.5 CODE GROUP SYNCHRONIZATION COMMA CHARACTER
A = K28.3 LANE ALIGNMENT SYMBOL
F = K28.7 FRAME ALIGNMENT SYMBOL
R = K28.0 START OF MULTIFRAME
Q = K28.4 START OF LINK CONFIGURATION DATA
C = JESD204B LINK CONFIGURATION PARAMETERS
D = Dx.y DATA SYMBOL
D D A R D D
Figure 52. Lane Alignment During ILAS
JESD204B Serial Link Establishment
A brief summary of the high speed serial link establishment
process for Subclass 1 is provided. See Section 5.3.3 of the
JESD204B specifications document for complete details.
After the last /A/ character of the last ILAS, multiframe data
begins streaming. The receiver adjusts the position of the /A/
character such that it aligns with the internal LMFC of the
receiver at this point.
Step 1: Code Group Synchronization
Step 3: Data Streaming
Each receiver must locate K (K28.5) characters in its input data
stream. After four consecutive K characters are detected on all
link lanes, the receiver block deasserts the SYNCOUTx± signal
to the transmitter block at the receiver LMFC edge.
In this phase, data is streamed from the transmitter block to the
receiver block.
The transmitter captures the change in the SYNCOUTx± signal,
and at a future transmitter LMFC rising edge, starts the initial
lane alignment sequence (ILAS).
The receiver block processes and monitors the data it receives
for errors, including
Step 2: Initial Lane Alignment Sequence
The main purposes of this phase are to align all the lanes of the
link and to verify the parameters of the link.
Before the link is established, write each of the link parameters
to the receiver device to designate how data is sent to the
receiver block.
The ILAS consists of four or more multiframes. The last character
of each multiframe is a multiframe alignment character, /A/.
The first, third, and fourth multiframes are populated with
predetermined data values. Note that Section 8.2 of the
JESD204B specifications document describes the data ramp that
is expected during ILAS. By default, the AD9135/AD9136 do
not require this ramp. Register 0x47E[0] can be set high to
require the data ramp. The deframer uses the final /A/ of each
lane to align the ends of the multiframes within the receiver.
The second multiframe contains an R (K28.0), Q (K28.4), and
then data corresponding to the link parameters. Additional
multiframes can be added to the ILAS if needed by the receiver.
By default, the AD9135/AD9136 use four multiframes in the ILAS
(this can be changed in Register 0x478). If using Subclass 1,
exactly four multiframes must be used.
Optionally, data can be scrambled. Scrambling does not start
until the very first octet following the ILAS.
Bad running disparity (8-bit/10-bit error)
Not in table (8-bit/10-bit error)
Unexpected control character
Bad ILAS
Interlane skew error (through character replacement)
If any of these errors exist, they are reported back to the
transmitter in one of a few ways (see the JESD204B Error
Monitoring section for details).
SYNCOUTx± signal assertion: resynchronization
(SYNCOUTx± signal pulled low) is requested at each error
for the last two errors. For the first three errors, an optional
resynchronization request can be asserted when the error
counter reaches a set error threshold.
For the first three errors, each multiframe with an error in
it causes a small pulse on SYNCOUTx±.
Errors can optionally trigger an IRQ event, which can be
sent to the transmitter.
Various test modes for verifying the link integrity can be found
in the JESD204B Test Modes section.
Rev. D | Page 41 of 117
AD9135/AD9136
Data Sheet
Lane FIFO
The FIFOs in front of the crossbar switch and deframer
synchronize the samples sent on the high speed serial data
interface with the deframer clock by adjusting the phase of the
incoming data. The FIFO absorbs timing variations between the
data source and the deframer; this allows up to two PClock
cycles of drift from the transmitter. The FIFO_STATUS_REG_0
register and FIFO_STATUS_REG_1 register (Register 0x30C
and Register 0x30D, respectively) can be monitored to identify
whether the FIFOs are full or empty.
Lane FIFO IRQ
An aggregate lane FIFO error bit is also available as an IRQ
event. Use Register 0x01F[1] to enable the FIFO error bit, and
then use Register 0x023[1] to read back its status and reset the
IRQ signal. See the Interrupt Request Operation section for
more information.
Crossbar Switch
Register 0x308 to Register 0x30B allow arbitrary mapping of
physical lanes (SERDINx±) to logical lanes used by the SERDES
deframers.
Table 40. Crossbar Registers
Address
0x308
0x308
0x309
0x309
0x30A
0x30A
0x30B
0x30B
Bits
[2:0]
[5:3]
[2:0]
[5:3]
[2:0]
[5:3]
[2:0]
[5:3]
Logical Lane
LOGICAL_LANE0_SRC
LOGICAL_LANE1_SRC
LOGICAL_LANE2_SRC
LOGICAL_LANE3_SRC
LOGICAL_LANE4_SRC
LOGICAL_LANE5_SRC
LOGICAL_LANE6_SRC
LOGICAL_LANE7_SRC
In single-link mode, Deframer 0 is used exclusively and Deframer 1
remains inactive. In dual-link mode, both QBDs are active and
must be configured separately using the LINK_PAGE bit
(Register 0x300[2]) to select which link to configure. The
LINK_MODE bit (Register 0x300[3]) is 1 for dual-link, or 0 for
single-link.
Each deframer uses the JESD204B parameters that the user has
programmed into the register map to identify how the data has
been packed and how to unpack it. The JESD204B parameters
are described in detail in the Transport Layer section; many of
the parameters are also needed in the transport layer to convert
JESD204B frames into samples.
Descrambler
The AD9135/AD9136 provide an optional descrambler block
using a self synchronous descrambler with a polynomial: 1 +
x14 + x15.
Enabling data scrambling reduces spectral peaks that are
produced when the same data octets repeat from frame to
frame. It also makes the spectrum data independent so that
possible frequency selective effects on the electrical interface do
not cause data dependent errors. Descrambling of the data is
enabled by setting the SCR bit (Register 0x453[7]) to 1.
Syncing LMFC Signals
The first step in guaranteeing synchronization across links and
devices begins with syncing the LMFC signals. Each DAC has
its own LMFC signal. In Subclass 0, the LMFC signals for each
of the two DACs are synchronized to an internal processing
clock. In Subclass 1, all LMFC signals (for all DACs and devices)
are synchronized to an external SYSREF signal. All LMFC sync
registers are paged as described in the DAC Paging section.
SYSREF Signal
Write each LOGICAL_LANEy_SRC with the number (x) of the
desired physical lane (SERDINx±) from which to receive data.
By default, all logical lanes use the corresponding physical lane
as their data source. For example, by default LOGICAL_LANE0_
SRC = 0; thus, Logical Lane 0 receives data from Physical Lane 0
(SERDIN0±). If instead the user wants to use SERDIN4± as the
source for Logical Lane 0, the user must write LOGICAL_LANE0_
SRC = 4.
Lane Inversion
Register 0x334 allows inversion of desired logical lanes, which
can be used to ease routing of the SERDINx± signals. For each
Logical Lane x, set Bit x of Register 0x334 to 1 to invert it.
Deframers
The AD9135/AD9136 consist of two quad-byte deframers (QBDs).
Each deframer receives the 8-bit/10-bit encoded data from the
deserializer (via the crossbar switch), decodes it, and descrambles it
into JESD204B frames before passing it to the transport layer to be
converted to DAC samples. The deframer processes four symbols
(or octets) per processing clock (PClock) cycle.
The SYSREF signal is a differential source synchronous input that
synchronizes the LMFC signals in both the transmitter and receiver
in a JESD204B Subclass 1 system to achieve deterministic latency.
The SYSREF signal is an active high signal that is sampled by
the device clock rising edge. It is best practice that the device clock
and SYSREF signals be generated by the same source, such as
the AD9516-1 clock generator, so that the phase alignment
between the signals is fixed. When designing for optimum
deterministic latency operation, consider the timing
distribution skew of the SYSREF signal in a multipoint link
system (multichip).
The AD9135/AD9136 support a single pulse or step, or a periodic
SYSREF± signal. The periodicity can be continuous, strobed, or
gapped periodic. The SYSREF± signal can always be dc-coupled
(with a common-mode voltage of 0 V to 2 V). When dc-coupled, a
small amount of common-mode current ( 4/SYSREF
frequency. In addition, the edge rate must be sufficiently fast—
at least 1.3 V/ns is recommended per Table 5—to meet the
SYSREF± vs. DAC clock keepout window (KOW) requirements.
Continuous mode differs from one-shot mode in two ways.
First, no SPI cycle is required to arm the device; the alignment
edge seen after continuous mode is enabled results in a phase
check. Second, a phase check (and when necessary, clock rotation)
occurs on every alignment edge in continuous mode. The one
caveat to the previous statement is that when a phase rotation cycle
is underway, subsequent alignment edges are ignored until the
logic lane is ready again.
It is possible to use ac-coupled mode without meeting the
frequency to time-constant constraint by using SYSREF±
hysteresis (Register 0x081 and Register 0x082). However, this
increases the DAC clock KOW (Table 5 does not apply) by an
amount depending on SYSREF± frequency, level of hysteresis,
capacitor choice, and edge rate.
The maximum acceptable phase error (in DAC clock cycles)
between the alignment edge and the LMFC edge is set in the
error window tolerance register. If continuous sync mode is
used with a nonzero error window tolerance, a phase check
occurs on every SYSREF± pulse, but an alignment occurs only if
the phase error is greater than the specified error window
tolerance. If the jitter of the SYSREF signal violates the KOW
specification given in Table 5 and therefore causes phase error
uncertainty, the error tolerance can be increased to avoid
constant clock rotations. Note that this means the latency is less
deterministic by the size of the window.
1.2V
2kΩ
SYSREF–
2kΩ
~800mV
12578-015
SYSREF+
Figure 53. SYSREF± Input Circuit
Sync Processing Modes Overview
The AD9135/AD9136 support various LMFC sync processing
modes. These modes are one-shot, continuous, windowed
continuous, and monitor modes. All sync processing modes
perform a phase check to see that the LMFC is phase aligned to an
alignment edge. In Subclass 1, the SYSREF pulse acts as the
alignment edge; in Subclass 0, an internal processing clock acts as
the alignment edge. If the signals are not in phase, a clock rotation
occurs to align the signals. The sync modes are described in the
following sections. See the Sync Procedure section for details on
the procedure for syncing the LMFC signals.
One-Shot Sync Mode (SYNCMODE = 0x1)
In one-shot sync mode, a phase check occurs on only the first
alignment edge that is received after the sync machine is armed. If
the phase error is larger than a specified window error tolerance, a
phase adjustment occurs. Though an LMFC synchronization
occurs only once, the SYSREF signal can still be continuous.
Continuous Sync Mode (SYNCMODE = 0x2)
Continuous mode can only be used in Subclass 1 with a periodic
SYSREF signal. In continuous mode, a phase check/alignment
occurs on every alignment edge.
For debug purposes, SYNCARM (Register 0x03A[6]) can be
used to inform the user that alignment edges are being received
in continuous mode. Because the SYNCARM bit is self cleared
after an alignment edge is received, the user can arm the sync
(SYNCARM (Register 0x03A[6]) = 1), and then read back
SYNCARM. If SYNCARM = 0, the alignment edges are being
received and phase checks are occurring. Arming the sync
machine in this mode does not affect the operation of the device.
One-Shot Then Monitor Sync Mode (SYNCMODE = 0x9)
In one-shot then monitor mode, the user can monitor the phase
error in real time. Use this sync mode with a periodic SYSREF
signal. A phase check and alignment occurs on the first alignment
edge received after the sync machine is armed. On all subsequent
alignment edges, the phase is monitored and reported, but no clock
phase adjustment occurs.
The phase error can be monitored on the SYNC_CURRERR_L
register (Register 0x03C[3:0]). Immediately after an alignment
occurs, CURRERROR = 0 indicates that there is no difference
between the alignment edge and the LMFC edge. On every
subsequent alignment edge, the phase is checked. If the
alignment is lost, the phase error is reported in the SYNC_
CURRERR_L register in DAC clock cycles. If the phase error is
beyond the selected window tolerance (Register 0x034[2:0]), one
bit of Register 0x03D[7:6] is set high depending on whether the
phase error is on the low or high side.
When an alignment occurs, snapshots of the last phase error
(Register 0x03C[3:0]) and the corresponding error flags
(Register 0x03D[7:6]) are placed into readable registers for
reference (Register 0x038 and Register 0x039, respectively).
Rev. D | Page 43 of 117
AD9135/AD9136
Data Sheet
Sync Procedure
LMFC Sync IRQ
The procedure for enabling the sync is as follows:
The sync status bits (SYNC_LOCK, SYNC_ROTATE,
SYNC_TRIP, and SYNC_WLIM) are available as IRQ events.
1.
2.
3.
4.
5.
6.
7.
Set Register 0x008 to 0x03 to sync the LMFC for both
DAC0 and DAC1.
Set the desired sync processing mode. The sync processing
mode settings are listed in Table 41.
For Subclass 1, set the error window according to the
uncertainty of the SYSREF signal relative to the DAC clock
and the tolerance of the application for deterministic
latency uncertainty. Sync window tolerance settings are
given in Table 42.
Enable sync by writing 1 to SYNCENABLE
(Register 0x03A[7]).
If in one-shot mode, arm the sync machine by writing 1 to
SYNCARM (Register 0x03A[6]).
If in Subclass 1, ensure that at least one SYSREF± pulse is
sent to the device.
Check the status by reading the following bit fields:
a) SYNC_BUSY (Register 0x03B[7]) = 0 to indicate that
the sync logic is no longer busy.
b) SYNC_LOCK (Register 0x03B[3]) = 1 to indicate that
the signals are aligned. This bit updates on every
phase check.
c) SYNC_WLIM (Register 0x03B[1]) = 0 to indicate that
the phase error is not beyond the specified error
window. This bit updates on every phase check.
d) SYNC_ROTATE (Register 0x03B[2]) = 1. If the phases
were not aligned before the sync and an alignment
occurred, this bit indicates that a clock alignment
occurred. This bit is sticky and can be cleared only by
writing to the SYNCCLRSTKY control bit
(Register 0x03A[5]).
e) SYNC_TRIP (Register 0x03B[0]) = 1 to indicate that
the alignment edge was received and a phase check
occurred. This bit is sticky and can be cleared only by
writing to the SYNCCLRSTKY control bit
(Register 0x03A[5]).
Table 41. Sync Processing Modes
Sync Processing Mode
One-shot
Continuous
One-shot then monitor
SYNCMODE (Register 0x03A[3:0])
0x01
0x02
0x09
Use Register 0x021[3:0] to enable the sync status bits for DAC0
and then use Register 0x025[3:0] to read back their statuses and
to reset the IRQ signals.
Use Register 0x022[3:0] to enable the sync status bits for DAC1
and then use Register 0x026[3:0] to read back their statuses and
to reset the IRQ signals.
See the Interrupt Request Operation section for more information.
Deterministic Latency
JESD204B systems contain various clock domains distributed
throughout each system. Data traversing from one clock
domain to a different clock domain can lead to ambiguous
delays in the JESD204B link. These ambiguities lead to
nonrepeatable latencies across the link from power cycle to
power cycle with each new link establishment. Section 6 of the
JESD204B specification addresses the issue of deterministic
latency with mechanisms defined as Subclass 1 and Subclass 2.
The AD9135/AD9136 support JESD204B Subclass 0 and
Subclass 1 operation, but not Subclass 2. Write the subclass to
Register 0x301[2:0] and once per link to Register 0x458[7:5].
Subclass 0
This mode does not require any signal on the SYSREF± pins,
which can be left disconnected.
Subclass 0 still requires that all lanes arrive within the same LMFC
cycle and that the two DACs be synchronized to each other.
Minor Subclass 0 Caveats
Because the AD9135/AD9136 require an ILAS, the nonmultiple
converter device alignment single lane (NMCDA-SL) case from
the JESD204A specification is supported only when using the
optional ILAS.
Error reporting using SYNCOUTx± is not supported when
using Subclass 0 with F = 1.
Subclass 1
This mode gives deterministic latency and allows links to be
synced to within ½ of a DAC clock period. It requires an
external SYSREF± signal that is accurately phase aligned to the
DAC clock.
Table 42. Sync Window Tolerance
Sync Error Window
Tolerance
±½ DAC clock cycles
±1 DAC clock cycles
±2 DAC clock cycles
±3 DAC clock cycles
ERRWINDOW (Register 0x034[2:0])
0x00
0x01
0x02
0x03
Rev. D | Page 44 of 117
Data Sheet
AD9135/AD9136
account for any amount of fixed delay. As a result, the LMFC
period must only be larger than the variation in the link delays,
and the AD9135/AD9136 can achieve proper performance with
a smaller total latency. Figure 54 and Figure 55 show a case
where the link delay is larger than an LMFC period. Note that it
can be accommodated by delaying LMFCRx.
DETERMINISTIC LATENCY REQUIREMENTS
Several key factors are required for achieving deterministic
latency in a JESD204B Subclass 1 system.
LMFC
ILAS
ALIGNED DATA
DATA
LATE ARRIVING
LMFC REFERENCE
EARLY ARRIVING
LMFC REFERENCE
Link Delay
Figure 54. Link Delay > LMFC Period Example
POWER CYCLE
VARIANCE
The link delay of a JESD204B system is the sum of fixed and
variable delays from the transmitter, channel, and receiver as
shown in Figure 56.
LMFC
ILAS
ALIGNED DATA
For proper functioning, all lanes on a link must be read during
the same LMFC period. Section 6.1 of the JESD204B
specification states that the LMFC period must be larger than
the maximum link delay. For the AD9135/AD9136, this is not
necessarily the case; instead, the AD9135/AD9136 use a local
LMFC for each link (LMFCRx) that can be delayed from the
SYSREF aligned LMFC. Because the LMFC is periodic, this can
DATA
LMFCRX
LMFC_DELAY_x
LMFC REFERENCE FOR ALL POWER CYCLES
FRAME CLOCK
Figure 55. LMFC_DELAY_x, to Compensate for Link Delay > LMFC
LINK DELAY = DELAYFIXED + DELAYVARIABLE
LOGIC DEVICE
(JESD204B Tx)
CHANNEL
JESD204B Rx
DSP
DAC
POWER CYCLE
VARIANCE
LMFC
ALIGNED DATA
CGS
ILAS
DATA
FIXED DELAY
VARIABLE
DELAY
Figure 56. JESD204B Link Delay = Fixed Delay + Variable Delay
Rev. D | Page 45 of 117
12578-019
POWER CYCLE
VARIANCE
12578-018
SYSREF± signal distribution skew within the system must
be less than the desired uncertainty.
SYSREF± setup and hold time requirements must be met
for each device in the system.
The total latency variation across all lanes, links, and
devices must be ≤10 PClock periods. This includes both
variable delays and the variation in fixed delays from lane
to lane, link to link, and device to device in the system.
12578-017
AD9135/AD9136
Data Sheet
1.
The method to set the LMFCDel and LMFCVar values is
described in the Link Delay Setup section.
Setting LMFCDel appropriately ensures that all the corresponding
data samples arrive in the same LMFC period. Then LMFCVar
is written into the receive buffer delay (RBD) to absorb all link
delay variation. This ensures that all data samples have arrived
before reading. By setting these to fixed values across runs and
devices, deterministic latency is achieved.
2.
The RBD described in the JESD204B specification takes values
from 1 frame clock cycle to K frame clock cycles, whereas the
RBD of the AD9135/AD9136 take values from 0 PClock cycles
to 10 PClock cycles. As a result, up to 10 PClock cycles of total
delay variation can be absorbed. Because LMFCVar is in PClock
cycles, and LMFCDel is in frame clock cycles, a conversion
between these two units is needed. The PClockFactor, or
number of frame clock cycles per PClock cycle, is equal to 4/F.
For more information on this relationship, see the Clock
Relationships section.
3.
4.
Two examples follow that show how to determine LMFCVar
and LMFCDel. After they are calculated, write LMFCDel into
both Register 0x304 and Register 0x305 for all devices in the
system, and write LMFCVar to both Register 0x306 and
Register 0x307 for all devices in the system.
5.
Link Delay Setup Example, with Known Delays
All the known system delays can be used to calculate LMFCVar
and LMFCDel as described in the Link Delay Setup section.
6.
The example shown in Figure 57 is demonstrated in the
following steps according to the procedure outlined in the Link
Delay Setup section. Note that this example is in Subclass 1 to
achieve deterministic latency, which has a PClockFactor (4/F)
of two frame clock cycles per PClock Cycle, and uses K = 32
(frames/multiframe). Because PCBFixed JESD_K
Unsupported Window Limit.
Unsupported SYSREF window limit
Unsupported M/L/S/F Selection.
This JESD combination is not supported
Unsupported K Values. 16 and 32 are
supported.
K value unsupported
Rev. D | Page 93 of 117
Reset
0x0
Access
R
0x0
R
0x0
R
0x0
0x0
R
R
0x0
0x0
R
R
0x0
R
0x0
R
0x0
R
0x0
0x0
R
R
0x0
R
0x0
R
0x0
R
AD9135/AD9136
Address
Name
Data Sheet
Bit No.
1
Bit Name
ERR_SUBCLASS
0
ERR_INTSUPP
Settings
1
1
0x034
SYNC_ERRWINDOW
[7:2]
[1:0]
RESERVED
ERRWINDOW
0x038
SYNC_LASTERR_L
[7:4]
[3:0]
RESERVED
LASTERROR
0x039
SYNC_LASTERR_H
7
LASTUNDER
1
6
LASTOVER
1
0x03A
SYNC_CONTROL
[5:0]
7
RESERVED
SYNCENABLE
1
0
6
SYNCARM
1
5
SYNCCLRSTKY
4
SYNCCLRLAST
[3:0]
SYNCMODE
0b0001
0b0010
0b1000
0b1001
0x03B
SYNC_STATUS
7
SYNC_BUSY
1
[6:4]
3
RESERVED
SYNC_LOCK
2
SYNC_ROTATE
1
1
1
SYNC_WLIM
1
0
SYNC_TRIP
1
Description
Unsupported Subclass Value. 0 and 1 are
supported.
Unsupported subclass value
Unsupported Interpolation Rate Factor. 1, 2,
4, 8 are supported.
Unsupported interpolation rate factor
Reserved.
LMFC Sync Error Window. The error window
allows the SYSREF sample phase to vary
within the confines of the window without
triggering a clock adjustment. This is useful if
SYSREF cannot be guaranteed to always
arrive in the same period of the device clock
associated with the target phase.
Error window tolerance = ± ERRWINDOW
Reserved.
LMFC Sync Last Alignment Error. 4-bit twos
complement value that represents the phase
error (in number of DAC clock cycles) when the
clocks were last adjusted.
LMFC Sync Last Error Under Flag.
Last phase error was beyond lower window
tolerance boundary
LMFC Sync Last Error Over Flag.
Last phase error was beyond upper window
tolerance boundary
Reserved.
LMFC Sync Logic Enable.
Enable sync logic
Disable sync logic
LMFC Sync Arming Strobe.
Sync one-shot armed
LMFC Sync Sticky Bit Clear. On a rising edge,
this bit clears SYNC_ROTATE and SYNC_TRIP.
LMFC Sync Clear Last Error. On a rising edge,
this bit clears LASTERROR, LASTUNDER,
LASTOVER.
LMFC Sync Mode.
Sync one-shot mode
Sync continuous mode
Sync monitor only mode
Sync one-shot, then monitor
LMFC Sync Machine Busy.
Sync logic SM is busy
Reserved.
LMFC Sync Alignment Locked.
Sync logic aligned within window
LMFC Sync Rotated.
Sync logic rotated with SYSREF (sticky)
LMFC Sync Alignment Limit Range.
Phase error outside window threshold
LMFC Sync Tripped After Arming.
Sync received SYSREF pulse (sticky)
Rev. D | Page 94 of 117
Reset
0x0
Access
R
0x0
R
0x0
0x0
R
R/W
0x0
R
R
0x0
R
0x0
R
0x0
0x0
R
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R
0x0
0x0
R
R
0x0
R
0x0
R
0x0
R
Data Sheet
AD9135/AD9136
Address
0x03C
Name
SYNC_CURRERR_L
Bit No.
[7:4]
[3:0]
Bit Name
RESERVED
CURRERROR
0x03D
SYNC_CURRERR_H
7
CURRUNDER
Settings
1
6
CURROVER
1
[5:0]
[7:2]
[1:0]
RESERVED
RESERVED
DACFSC_0[9:8]
DACGAIN0_0
DACGAIN1_1
[7:0]
[7:2]
[1:0]
DACFSC_0[7:0]
RESERVED
DACFSC_1[9:8]
DACGAIN1_0
CLKCFG0
[7:0]
7
DACFSC_1[7:0]
PD_CLK0
6
PD_CLK1
5
PD_CLK_DIG
4
PD_SERDES_PCLK
3
PD_CLK_REC
[2:0]
RESERVED
0x040
DACGAIN0_1
0x041
0x044
0x045
0x080
Description
Reserved.
LMFC Sync Alignment Error. 4-bit twos
complement value that represents the phase
error in number of DAC clock cycles (that is,
number of DAC clocks between LMFC edge and
SYSREF edge).
When an adjustment of the clocks is made
on any given SYSREF, the value of the phase
error is placed into SYNC_ LASTERR, and
SYNC_CURRERR is forced to 0.
LMFC Sync Current Error Under Flag.
Current phase error is beyond lower window
tolerance boundary
LMFC Sync Current Error Over Flag.
Current phase error is beyond upper window
tolerance boundary
Reserved.
Reserved.
2 MSBs of I-Channel DAC Gain DAC0. A 10-bit
twos complement value that is mapped to
analog full-scale current for DAC0 as shown:
01111111111 = 27.0 mA
0000000000 = 20.48 mA
1000000000 = 13.9 mA
8 LSBs of I-Channel DAC Gain DAC0.
Reserved.
2 MSBs of Q-Channel DAC Gain DAC1. A
10-bit twos complement value that is
mapped to analog full-scale current for DAC
as shown in Register 0x040.
01111111111 = 27.0 mA
0000000000 = 20.48 mA
1000000000 = 13.9 mA
8 LSBs of Q-Channel DAC Gain DAC1.
Power-Down Clock for DAC0. This bit
disables the digital and analog clocks for
DAC0.
Power-Down Clock for DAC1. This bit
disables the digital and analog clocks for
DAC1.
Power-Down Clocks to all DACs. This bit
disables the digital and analog clocks for
both duals. This includes all reference clocks,
PCLK, DAC clocks, and digital clocks.
Serdes PLL Clock Power-Down. This bit
disables the reference clock to the SERDES
PLL, which is needed to have an operational
serial interface.
Clock Receiver Power-Down. This bit powers
down the analog DAC clock receiver block.
With this bit set, clocks are not passed to
internal nets.
Reserved.
Rev. D | Page 95 of 117
Reset
0x0
0x0
Access
R
R
0x0
R
0x0
R
0x0
0x0
0x0
R
R
R/W
0x0
0x0
0x0
R/W
R
R/W
0x0
0x1
R/W
R/W
0x1
R/W
0x1
R/W
0x1
R/W
0x1
R/W
0x0
R
AD9135/AD9136
Address
0x081
Name
SYSREF_ACTRL0
Data Sheet
Bit No.
[7:5]
4
Bit Name
RESERVED
PD_SYSREF
3
HYS_ON
2
SYSREF_RISE
Settings
0
1
0x082
0x083
0x084
SYSREF_ACTRL1
DACPLLCNTRL
DACPLLSTATUS
[1:0]
HYS_CNTRL1
[7:0]
7
HYS_CNTRL0
RECAL_DACPLL
[6:5]
4
RESERVED
ENABLE_DACPLL
[3:0]
7
RESERVED
DACPLL_
OVERRANGE_H
6
DACPLL_
OVERRANGE_L
5
DACPLL_CAL_
VALID
[4:2]
1
RESERVED
DACPLL_LOCK
0x085
DACINTEGERWORD0
0
[7:0]
RESERVED
B_COUNT
0x087
DACLOOPFILT1
[7:4]
LF_C2_WORD
[3:0]
LF_C1_WORD
[7:4]
LF_R1_WORD
[3:0]
LF_C3_WORD
0x088
DACLOOPFILT2
Description
Reserved.
Power-Down SYSREF Buffer. This bit powers
down the SYSREF receiver. For Subclass 1
operation to work, this buffer must be enabled.
Hysteresis Enabled. This bit enables the
programmable hysteresis control for the
SYSREF receiver. Using hysteresis gives some
noise resistance, but delays the SYSREF±
edge an amount depending on HYS_CNTRL
and the SYSREF± edge rate. The SYSREF±
KOW is not guaranteed when using
hysteresis.
Select DAC Clock Edge to Sample SYSREF.
Use falling edge of DAC clock to sample
SYSREF for alignment
Use rising edge of DAC clock to sample
SYSREF for alignment
Hysteresis Control Bits[9:8]. HYS_CNTRL is a
10-bit thermometer-coded number. Each bit
set adds 10 mV of differential hysteresis to
the SYSREF receiver.
Hysteresis Control Bits[7:0].
Recalibrate DAC PLL. On a rising edge of this bit,
recalibrate the DAC PLL.
Reserved.
Synthesizer Enable. This bit enables and
calibrates the DAC PLL.
Reserved.
DAC PLL High Overrange. This bit indicates
that the DAC PLL hit the upper edge of its
operating band. Recalibrate.
DAC PLL Low Overrange. This bit indicates
that the DAC PLL hit the lower edge of its
operating band. Recalibrate.
DAC PLL Calibration Valid. This bit indicates
that the DAC PLL has been successfully
calibrated.
Reserved.
DAC PLL Lock Bit. This bit is set high by the PLL
when it has achieved lock.
Reserved.
Integer Division Word. This bit controls the
integer feedback divider for the DAC PLL.
Determine the frequency of the DAC clock by
the following equations (see the Clock
Multiplication section for more details):
fDAC = fREF/(REF_DIVRATE) × 2 × B_COUNT
fVCO = fREF/(REF_DIVRATE) × 2 × B_COUNT ×
LO_DIV_MODE
Minimum value is 6.
C2 Control Word. Set this control to 0x6 for
optimal performance.
C1 Control Word. Set this control to 0x2 for
optimal performance.
R1 Control Word. Set this control to 0xC for
optimal performance.
C3 Control Word. Set this control to 0x9 for
optimal performance.
Rev. D | Page 96 of 117
Reset
0x0
0x1
Access
R
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
0x0
R/W
R/W
0x0
0x0
R
R/W
0x0
0x0
R
R
0x0
R
0x0
R
0x0
0x0
R
R
0x0
0x8
R
R/W
0x8
R/W
0x8
R/W
0x8
R/W
0x8
R/W
Data Sheet
Address
0x089
Name
DACLOOPFILT3
AD9135/AD9136
Bit No.
7
Bit Name
LF_BYPASS_R3
6
LF_BYPASS_R1
5
LF_BYPASS_C2
4
LF_BYPASS_C1
[3:0]
LF_R3_WORD
0x08A
DACCPCNTRL
[7:6]
[5:0]
RESERVED
CP_CURRENT
0x08B
DACLOGENCNTRL
[7:2]
[1:0]
RESERVED
LO_DIV_MODE
Settings
01
10
11
0x08C
DACLDOCNTRL1
[7:3]
[2:0]
RESERVED
REF_DIV_MODE
000
001
010
011
100
0x08D
DACLDOCNTRL2
[7:0]
DAC_LDO
0x0E2
CAL_CTRL_GLOBAL
[7:2]
1
RESERVED
CAL_START_AVG
0
CAL_EN_AVG
1
Description
Bypass R3 Resistor. When this bit is set,
bypass the R3 capacitor (set to 0 pF) when
R3_WORD is set to 0. Set this control to 0x0 for
optimal performance.
Bypass R1 Resistor. When this bit is set,
bypass the R1 capacitor (set to 0 pF) when
R1_WORD is set to 0. Set this control to 0x0 for
optimal performance.
Bypass C2 Capacitor. When this bit is set,
bypass the C2 capacitor (set to 0 pF) when
C2_WORD is set to 0. Set this control to 0x0 for
optimal performance.
Bypass C1 Capacitor. When this bit is set,
bypass the C1 capacitor (set to 0 pF) when
C1_WORD is set to 0. Set this control to 0x0 for
optimal performance.
R3 Control Word. Set this control to 0xE for
optimal performance.
Reserved.
Charge Pump Current Control. Set this control
to 0x12 for optimal performance.
Reserved.
This range controls the RF clock divider
between the VCO and DAC clock rates. The
options are 4×, 8×, or 16× division. Choose the
LO_DIV_MODE so that 6 GHz < fVCO < 12 GHz
(see the Clock Multiplication section for more
details):
DAC clock = VCO/4
DAC clock = VCO/8
DAC clock = VCO/16
Reserved.
Reference Clock Division Ratio. This field
controls the amount of division that is done
to the input clock at the CLK+/CLK− pins
before it is presented to the PLL as a reference
clock. The reference clock frequency must be
between 35 MHz and 80 MHz, but the
CLK+/CLK− input frequency can range from
35 MHz to 1 GHz. The user sets this division
to achieve a 35 MHz to 80 MHz PLL reference
frequency. For more details see the Clock
Multiplication section.
1
2
4
8
16
DAC PLL LDO setting. This register must be
written to 0x7B for optimal performance.
Reserved.
Averaged Calibration Start. On rising edge,
calibrate the DACs. Only use if calibrating all
DACs.
Averaged Calibration Enable. Set prior to
starting calibration with CAL_START_AVG.
While this bit is set, calibration can be
performed, and the results are applied.
Enable averaged calibration
Rev. D | Page 97 of 117
Reset
0x0
Access
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x8
R/W
0x0
0x20
R
R/W
0x0
0x2
R
R/W
0x0
0x1
R
R/W
0x2B
R/W
0x0
0x0
R
R/W
0x0
R/W
AD9135/AD9136
Address
0x0E7
Name
CAL_CLKDIV
Data Sheet
Bit No.
[7:4]
Bit Name
RESERVED
3
CAL_CLK_EN
Settings
1
0
0x0E8
CAL_PAGE
[2:0]
[7:4]
[3:0]
RESERVED
RESERVED
CAL_PAGE
0x0E9
CAL_CTRL
7
CAL_FIN
6
CAL_ACTIVE
5
CAL_ERRHI
4
CAL_ERRLO
[3:2]
1
RESERVED
CAL_START
1
1
1
1
0
1
0
CAL_EN
0
1
Description
Must write the default value for proper
operation.
Enable Self Calibration Clock.
Enable calibration clock
Disable calibration clock
Reserved.
Reserved.
DAC Calibration Paging. Selects which of the
DACs are being accessed for calibration or
calibration readback. This paging affects
Register 0x0E9 and Register 0x0ED.
Calibration: any number of DACs can be
accessed simultaneously to write and
calibrate. Write a 1 to Bit 0 to include DAC0.
Write a 1 to Bit 2 to include DAC1.
Readback: only one DAC at a time can be
accessed when reading back CAL_CTRL
(Register 0x0E9). Write a 1 to Bit 0 to read
from DAC0 or write a 1 to Bit 2 to read from
DAC1 (the other bits must be 0).
Calibration finished. This bit is high when the
calibration has completed. If the calibration
completes and either CAL_ERRHI or CAL_
ERRLO is high, then the calibration cannot be
considered valid and are considered a timeout
event.
Calibration ran and is finished
Calibration Active. This bit is high while the
calibration is in progress.
Calibration is running
SAR Data Error: Too High. This bit is set at the
end of a calibration cycle if any of the calibration DACs has overranged to the high side.
This typically means that the algorithm adjusts
the calibration preset of the calibration DACs
and runs another cycle.
Data saturated high
SAR Data Error: Too Low. This bit is set at the
end of a calibration cycle if any of the calibration DACs has overranged to the low side.
This typically means that the algorithm adjusts
the calibration preset of the calibration DACs
and runs another cycle.
Data saturated low
Reserved.
Calibration Start. The rising edge of this bit
kicks off a calibration sequence for the DACs
that have been selected in the CAL_INDX
register.
Normal operation
Start calibration state machine
Calibration Enable. Enable the calibration
DAC of the converter. Enable to calibration
engine and machines. Prepare for a calibration
start. For calibration coefficients to be applied
to the calibrated DACs, this bit must be high.
Do not use calibration DACs
Use calibration DACs
Rev. D | Page 98 of 117
Reset
0x3
Access
R/W
0x0
R/W
0x0
0x0
0xF
R
R
R/W
0x0
R
0x0
R
0x0
R
0x0
R
0x0
0x0
R
R/W
0x0
R/W
Data Sheet
AD9135/AD9136
Address
0x0ED
Name
CAL_INIT
Bit No.
[7:0]
Bit Name
CAL_INIT
Settings
0x110
DATA_FORMAT
7
BINARY_FORMAT
0
1
0x111
DATAPATH_CTRL
[6:0]
7
RESERVED
INVSINC_ENABLE
1
0
6
5
RESERVED
DIG_GAIN_ENABLE
1
0
0x112
INTERP_MODE
[4:0]
[7:3]
[2:0]
RESERVED
RESERVED
INTERP_MODE
000
001
011
100
0x11F
TXEN_SM_0
[7:6]
FALL_COUNTERS
[5:4]
RISE_COUNTERS
3
2
RESERVED
PROTECT_OUT_
INVERT
0
1
[1:0]
RESERVED
0x121
TXEN_RISE_COUNT_0
[7:0]
RISE_COUNT_0
0x122
TXEN_RISE_COUNT_1
[7:0]
RISE_COUNT_1
0x123
TXEN_FALL_
COUNT_0
[7:0]
FALL_COUNT_0
0x124
TXEN_FALL_
COUNT_1
[7:0]
FALL_COUNT_1
0x12D
DEVICE_CONFIG_
REG_0
DIE_TEMP_CTRL0
[7:0]
DEVICE_CONFIG_0
[7:1]
RESERVED
0
AUXADC_ENABLE
0x12F
0
1
Description
Initialize Calibration. Must be written to 0xA2
before starting calibration or averaged
calibration.
Binary or Twos Complementary Format on
the Data Bus.
Input data is twos complement
Input data is offset binary
Reserved.
Enable Inverse Sinc Filter.
Enable inverse sinc filter
Disable inverse sinc filter
Reserved.
Enable Digital Gain.
Enable digital gain function
Disable digital gain function
Reserved
Reserved.
Interpolation Mode.
1× mode
2× mode
4× mode
8× mode
Fall Counters. The number of counters to use
to delay TX_PROTECT fall from TXENx falling
edge. Must be set to 1 or 2.
Rise Counters. The number of counters to
use to delay TX_PROTECT rise from TXENx
rising edge.
Reserved.
PROTECT_OUTx Invert.
PROTECT_OUTx is high when output is valid.
Suitable for enabling downstream
components during transmission
PROTECT_OUTx is high when output is
invalid. Suitable for disabling downstream
components when not transmitting
Must write the default value for proper
operation.
First counter used to delay TX_PROTECT rise
from TXENx rising edge. Delays by 32 ×
RISE_COUNT_0 DAC clock cycles.
Second counter used to delay TX_PROTECT
rise from TXENx rising edge. Delays by 32 ×
RISE_COUNT_1 DAC clock cycles.
First counter used to delay TX_PROTECT fall
from TXENx falling edge. Delays by 32 ×
FALL_COUNT_0 DAC clock cycles. Must be
set to a minimum of 0x12.
Second counter used to delay TX_PROTECT
fall from TXENx falling edge. Delays by 32 ×
FALL_COUNT_1 DAC clock cycles.
Must be set to 0x8B for proper digital
datapath configuration.
Must write the default value for proper
operation.
Enables the AUX ADC Block.
AUX ADC disable
AUX ADC enable
Rev. D | Page 99 of 117
Reset
0xA6
Access
R/W
0x0
R/W
0x0
0x1
R
R/W
0x0
0x1
R
R/W
0x0
0x0
0x1
R
R
R/W
0x2
R/W
0x0
R/W
0x0
0x0
R
R/W
0x3
R/W
0xF
R/W
0x0
R/W
0xFF
R/W
0xFF
R/W
0x46
R/W
0x10
R/W
0x0
R/W
AD9135/AD9136
Data Sheet
Address
0x132
0x133
0x134
Name
DIE_TEMP0
DIE_TEMP1
DIE_TEMP_UPDATE
Bit No.
[7:0]
[7:0]
[7:1]
0
0x135
DC_OFFSET_CTRL
[7:1]
0
Bit Name
DIE_TEMP[7:0]
DIE_TEMP[15:8]
RESERVED
DIE_TEMP_
UPDATE
RESERVED
DC_OFFSET_ON
0x136
DAC_DC_OFFSET_1
PART0
[7:0]
LSB_OFFSET[7:0]
0x137
DAC_DC_OFFSET_
1PART1
[7:0]
LSB_OFFSET[15:8]
0x13A
DAC_DC_OFFSET_
2PART
[7:5]
[4:0]
RESERVED
SIXTEENTH_
OFFSET
0x13C
DAC_DIG_GAIN0
[7:0]
DAC_DIG_
GAIN[7:0]
0x13D
DAC_DIG_GAIN1
[7:4]
[3:0]
0x140
GAIN_RAMP_UP_
STEP0
[7:0]
RESERVED
DAC_DIG_
GAIN[11:8]
GAIN_RAMP_UP_
STEP[7:0]
Settings
1
x
0x0
0xFFF
0x141
0x142
GAIN_RAMP_UP_
STEP1
GAIN_RAMP_DOWN_
STEP0
[7:4]
RESERVED
[3:0]
GAIN_RAMP_UP_
STEP[11:8]
GAIN_RAMP_
DOWN_STEP[7:0]
[7:0]
0
0xFFF
0x143
0x146
0x147
GAIN_RAMP_
DOWN_STEP1
DEVICE_CONFIG_
REG_1
BSM_STAT
[7:4]
RESERVED
[3:0]
[7:0]
GAIN_RAMP_
DOWN_STEP[11:8]
DEVICE_CONFIG_1
[7:6]
SOFTBLANKRB
00
01
10
11
[5:0]
RESERVED
Description
Aux ADC Readback Value.
Aux ADC Readback Value.
Reserved.
Die Temperature Update. On a rising edge, a
new temperature code is generated.
Reserved.
DC Offset On.
Enables dc offset module
8 LSBs of DC Offset. LSB_OFFSET is a 16-bit
twos complement number that is added to
incoming data. Applies to the DAC selected
by DAC_PAGE (Register 0x008 [1:0]).
8 MSBs of DC Offset. LSB_OFFSET is a 16-bit
twos complement number that is added to
incoming data. Applies to the DAC selected
by DAC_PAGE (Register 0x008 [1:0]).
Reserved.
SIXTEENTH_OFFSET is a 5-bit twos
complement number in 16ths of an LSB that
is added to incoming I data.
x/16 LSB DC offset
8 LSBs of DAC Digital Gain. DAC_DIG_GAIN is
the digital gain of the DAC selected by
DAC_PAGE (Register 0x008 [1:0]). The digital
gain is a multiplier from 0 to 4095/2048 in
steps of 1/2048.
Reserved.
4 MSBs of DAC Digital Gain
Reset
0x0
0x0
0x0
0x0
Access
R
R
R
R/W
0x0
0x0
R
R/W
0x0
R/W
0x0
R/W
0x0
0x0
R
R/W
0xEA
R/W
0x0
0xA
R
R/W
8 LSBs of Gain Ramp Up Step.
GAIN_RAMP_UP_STEP controls the amplitude
step size of the BSM’s ramping feature when
the gain is being ramped to its assigned value.
Smallest ramp up step size
Largest ramp up step size
Reserved.
0x4
R/W
0x0
R
0x0
R/W
0x9
R/W
0x0
R
0x0
R/W
0x0
R/W
0x0
R
0x0
R
4 MSBs of Gain Ramp Up Step. See Register
0x140 for description.
8 LSBs of Gain Ramp Down Step.
GAIN_RAMP_DOWN_STEP controls the
amplitude step size of the BSM’s ramping
feature when the gain is being ramped to zero.
Smallest ramp down step size
Largest ramp down step size
Reserved.
4 MSBs of Gain Ramp Down Step. See
Register 0x142 for description.
Must be set to 0x01 for proper digital
datapath configuration.
Blanking State.
Data is fully blanked
Ramping from data process to full blanking
Ramping from fully blanked to data process
Data is being processed
Reserved.
Rev. D | Page 100 of 117
Data Sheet
Address
0x14B
Name
PRBS
AD9135/AD9136
Bit No.
7
6
Bit Name
RESERVED
PRBS_GOOD
Settings
0
1
[5:3]
2
RESERVED
PRBS_MODE
0
1
1
PRBS_RESET
0
1
0
PRBS_EN
0
1
0x14C
0x1B0
PRBS_ERROR
DACPLLT0
[7:0]
[7:0]
PRBS_COUNT
DAC_PLL_PWR
0x1B5
DACPLLT5
[7:4]
RESERVED
[3:0]
VCO_VAR
0x1B9
DACPLLT9
[7:0]
DAC_PLL_CP1
0x1BB
DACPLLTB
[7:5]
[4:3]
RESERVED
VCO_BIAS_TCF
[2:0]
VCO_BIAS_REF
0x1BC
DACPLLTC
[7:0]
DAC_PLL_VCO_
CTRL
0x1BE
DACPLLTE
[7:0]
DAC_PLL_VCO_
PWR
0x1BF
DACPLLTF
[7:0]
DAC_PLL_VCOCAL
0x1C0
DACPLLT10
[7:0]
0x1C1
DACPLLT11
[7:0]
DAC_PLL_LOCK_
CNTR
DAC_PLL_CP2
0x1C4
DACPLLT17
[7:0]
DAC_PLL_VAR1
0x1C5
DACPLLT18
[7:0]
DAC_PLL_VAR2
0x200
MASTER_PD
[7:1]
0
RESERVED
SPI_PD_MASTER
0x201
PHY_PD
[7:0]
SPI_PD_PHY
Description
Reserved.
Good Data Indicator.
Incorrect sequence detected
Correct PRBS sequence detected
Reserved.
Polynomial Select
7-bit: x7 + x6 + 1
15-bit: x15 + x14 + 1
Reset Error Counters.
Normal operation
Reset counters
Enable PRBS Checker.
Disable
Enable
Error Count Value.
DAC PLL PD settings. This register must be
written to 0x00 for optimal performance.
Must write the default value for proper
operation.
Varactor KVO Setting. See Table 73 for
optimal settings based on the fVCO being
used.
DAC PLL Charge Pump settings. This register
must be written to 0x24 for optimal
performance.
Reserved.
Temperature Coefficient for VCO Bias. See
Table 73 for optimal settings based on the
fVCO being used.
VCO Bias Control. See Table 73 for optimal
settings based on the fVCO being used.
DAC PLL VCO control settings. This register
must be written to 0x0D for optimal
performance.
DAC PLL VCO power control settings. This
register must be written to 0x02 for optimal
performance.
DAC PLL VCO calibration settings. This
register must be written to 0x8E for optimal
performance.
This register must be written to 0x2A for
optimal performance.
This register must be written to0x2A for
optimal performance.
DAC PLL Varactor setting. Must be set to
0x7E for proper DAC PLL configuration.
DAC PLL Varactor setting. See Table 73 for
optimal settings based on the fVCO being
used.
Reserved.
Power Down the Entire JESD Receiver Analog
(All Eight Channels Plus Bias).
SPI Override to Power Down the Individual
PHYs.
Set Bit x to power down the corresponding
SERDINx± PHY
Rev. D | Page 101 of 117
Reset
0x0
0x0
Access
R
R
0x0
0x0
R
R/W
0x0
R/W
0x0
R/W
0x0
0xFA
R
R/W
0x8
R/W
0x3
R/W
0x34
R/W
0x0
0x1
R
R/W
0x4
R/W
0x00
R/W
0x00
R/W
0x8D
R/W
0x2E
R/W
0x24
R/W
0x33
R/W
0x08
R/W
0x0
0x1
R
R/W
0x0
R/W
AD9135/AD9136
Address
0x203
Name
GENERIC_PD
0x206
CDR_RESET
Data Sheet
Bit No.
[7:2]
1
Bit Name
RESERVED
SPI_SYNC1_PD
Settings
Description
Reserved.
Power down LVDS buffer for SYNCOUT0±.
0x232
0x268
CDR_OPERATING_
MODE_REG_0
DEVICE_CONFIG_
REG_3
EQ_BIAS_REG
SPI_SYNC2_PD
Power down LVDS buffer for SYNCOUT1±.
0x0
R/W
[7:1]
0
RESERVED
SPI_CDR_RESETN
Reserved.
Resets the Digital Control Logic for All PHYs.
Hold CDR in reset
Enable CDR
Reserved.
Enables Half-Rate CDR Operation. Set to 1
when 5.75 Gbps ≤ lane rate ≤ 12.4 Gbps.
Must write the default value for proper
operation.
Enables Oversampling of the Input Data. Set
to 1 when 1.44 Gbps ≤ lane rate ≤ 3.1 Gbps.
Reserved.
Must be set to 0xFF for proper JESD interface
configuration.
Control the Equalizer Power/Insertion Loss
Capability.
Normal mode
Low power mode
Must write the default value for proper
operation.
Reserved.
Recalibrate SERDES PLL. On a rising edge,
recalibrate the SERDES PLL.
Reserved.
Enable the SERDES PLL. Setting this bit
enables and calibrates the SERDES PLL.
Reserved.
SERDES PLL High Overrange. This bit
indicates that the SERDES PLL hit the lower
edge of its operating band. Recalibrate.
SERDES PLL Low Overrange. This bit
indicates that the SERDES PLL hit the lower
edge of its operating band. Recalibrate.
SERDES PLL Calibration Valid. This bit
indicates that the SERDES PLL has been
successfully calibrated.
Reserved.
SERDES PLL Lock. This bit is set high by the PLL
when it has achieved lock.
SERDES PLL loop filter setting. This register
must be written to 0x62 for optimal
performance.
SERDES PLL loop filter setting. This register
must be written to 0xC9 for optimal
performance.
SERDES PLL loop filter setting. This register
must be written to 0x0E for optimal
performance.
SERDES PLL charge pump setting. This
register must be written to 0x12 for optimal
performance.
0x0
0x1
R
R/W
0x0
0x1
R
R/W
0x2
R/W
0x0
R/W
0x0
0x0
R
R/W
0x1
R/W
0x22
R/W
0x0
0x0
R
R/W
0x0
0x0
R
R/W
0x0
0x0
R
R
0x0
R
0x0
R
0x0
0x0
R
R
0x77
R/W
0x87
R/W
0x08
R/W
0x3F
R/W
[7:6]
5
RESERVED
ENHALFRATE
[4:2]
RESERVED
1
CDR_OVERSAMP
0
[7:0]
RESERVED
DEVICE_CONFIG_3
[7:6]
EQ_POWER_
MODE
00
01
0x280
0x281
SERDESPLL_
ENABLE_CNTRL
PLL_STATUS
Access
R
R/W
0
0
1
0x230
Reset
0x0
0x0
[5:0]
RESERVED
[7:3]
2
RESERVED
RECAL_SERDESPLL
1
0
RESERVED
ENABLE_
SERDESPLL
RESERVED
SERDES_PLL_
OVERRANGE_H
[7:6]
5
4
SERDES_PLL_
OVERRANGE_L
3
SERDES_PLL_CAL_
VALID_RB
[2:1]
0
0x284
LOOP_FILTER_1
[7:0]
RESERVED
SERDES_PLL_
LOCK_RB
LOOP_FILTER_1
0x285
LOOP_FILTER_2
[7:0]
LOOP_FILTER_2
0x286
LOOP_FILTER_3
[7:0]
LOOP_FILTER_3
0x287
SERDES_PLL_CP1
[7:0]
SERDES_PLL_CP1
Rev. D | Page 102 of 117
Data Sheet
Address
0x289
Name
REF_CLK_DIVIDER_
LDO
AD9135/AD9136
Bit No.
[7:3]
2
Bit Name
RESERVED
DEVICE_CONFIG_4
[1:0]
SERDES_PLL_DIV_
MODE
Settings
00
01
10
0x28A
VCO_LDO
[7:0]
SERDES_PLL_
VCO_LDO
0x28B
SERDES_PLL_PD1
[7:0]
SERDES_PLL_PD1
0x290
SERDESPLL_VAR1
[7:0]
SERDES_PLL_VAR1
0x294
SERDES_PLL_CP2
[7:0]
SERDES_PLL_CP2
0x296
SERDESPLL_VCO1
[7:0]
0x297
SERDESPLL_VCO2
[7:0]
0x299
SERDES_PLL_PD2
[7:0]
SERDES_PLL_
VCO1
SERDES_PLL_
VCO2
SERDES_PLL_PD2
0x29A
SERDESPLL_VAR2
[7:0]
SERDES_PLL_VAR2
0x29C
SERDES_PLL_CP3
[7:0]
SERDES_PLL_CP3
0x29F
SERDESPLL_VAR3
[7:0]
SERDES_PLL_VAR3
0x2A0
SERDESPLL_VAR4
[7:0]
SERDES_PLL_VAR4
0x2A4
DEVICE_CONFIG_
REG_8
SYNCOUTB_SWING
[7:0]
DEVICE_CONFIG_8
[7:1]
0
RESERVED
SYNCOUTB_
SWING_MD
0x2A5
0
1
0x2A7
0x2AA
0x2AB
TERM_BLK1_
CTRLREG0
DEVICE_CONFIG_
REG_9
DEVICE_CONFIG_
REG_10
[7:1]
RESERVED
0
RCAL_TERMBLK1
[7:0]
DEVICE_CONFIG_
9
DEVICE_CONFIG_
10
[7:0]
Description
Reserved.
Must be set to 1 for proper SERDES PLL
configuration.
SERDES PLL Reference Clock Division Factor.
This field controls the division of the SERDES
PLL reference clock before it is fed into the
SERDES PLL Phase Frequency Detector (PFD).
It must be set so fREF/DivFactor is between
35 MHz and 80 MHz.
Divide by 4 for 5.75 Gbps to 12.4 Gbps lane
rate
Divide by 2 for 2.88 Gbps to 6.2 Gbps lane
rate
Divide by 1 for 1.44 Gbps to 3.1 Gbps lane rate
SERDES PLL VCO LDO setting. This register
must be written to 0x7B for optimal
performance.
SERDES PLL PD setting. This register must be
written to 0x00 for optimal performance.
SERDES PLL Varactor setting. This register
must be written to 0x89 for optimal
performance.
SERDES PLL Charge Pump setting. This
register must be set to 0x24 for optimal
performance.
SERDES PLL VCO setting. This register must
be set to 0x03 for optimal performance.
SERDES PLL VCO setting. This register must
be set to 0x0D for optimal performance.
SERDES PLL PD setting. This register must be
set to 0x02 for optimal performance.
SERDES PLL Varactor setting. This register
must be set to 0x8E for optimal performance.
SERDES PLL Charge Pump setting. Must be
set to 0x2A for proper SERDES PLL
configuration.
SERDES PLL Varactor setting. Must be set to
0x78 for proper SERDES PLL configuration.
SERDES PLL Varactor setting. This register
must be set to 0x06 for optimal performance.
Must be set to 0xFF for proper clock
configuration.
Reserved.
SYNCOUTx± Swing Mode. Sets the output
differential swing mode for the SYNCOUTx±
pins. See Table 8 for details.
Normal Swing Mode
High Swing Mode
Reserved.
Reset
0x0
0x0
Access
R
R/W
0x0
R/W
0x2B
R/W
0x7F
R/W
0x83
R/W
0xB0
R/W
0x0C
R/W
0x00
R/W
0x00
R/W
0xFE
R/W
0x17
R/W
0x33
R/W
0x08
R/W
0x4B
R/W
0x0
0x0
R
R/W
0x0
R
Termination Calibration. The rising edge of
this bit calibrates PHY0, PHY1, PHY6, and PHY7
terminations to 50 Ω.
Must be set to 0xB7 for proper JESD interface
termination configuration.
Must be set to 0x87 for proper JESD interface
termination configuration.
0x0
R/W
0xC3
R/W
0x93
R/W
Rev. D | Page 103 of 117
AD9135/AD9136
Data Sheet
Address
0x2AE
Name
TERM_BLK2_
CTRLREG0
Bit No.
[7:1]
0
Bit Name
RESERVED
RCAL_TERMBLK2
0x2B1
DEVICE_CONFIG_
REG_11
DEVICE_CONFIG_
REG_12
GENERAL_JRX_
CTRL_0
[7:0]
DEVICE_CONFIG_
11
DEVICE_CONFIG_
12
RESERVED
CHECKSUM_MODE
0x2B2
0x300
[7:0]
7
6
Settings
0
1
[5:4]
3
RESERVED
LINK_MODE
0
1
2
LINK_PAGE
0
1
[1:0]
LINK_EN
0b00
0b01
0b10
0b11
0x301
GENERAL_JRX_CTRL_1
[7:3]
[2:0]
RESERVED
SUBCLASSV_
LOCAL
000
001
0x302
DYN_LINK_LATENCY_0
[7:5]
[4:0]
RESERVED
DYN_LINK_
LATENCY_0
0x303
DYN_LINK_LATENCY_1
[7:5]
[4:0]
RESERVED
DYN_LINK_
LATENCY_1
Description
Reserved.
Terminal Calibration. The rising edge of this
bit calibrates PHY2, PHY3, PHY4 and PHY5
terminations to 50 Ω.
Must be set to 0xB7 for proper JESD interface
termination configuration.
Must be set to 0x87 for proper JESD interface
termination configuration.
Reserved.
Checksum Mode. This bit controls the locally
generated JESD204B link parameter checksum
method. The value is stored in the FCMP
registers (Register 0x40E, Register 0x416,
Register 0x41E, Register 0x426, Register
0x42E, Register 0x436, Register 0x43E, and
Register 0x446).
Checksum is calculated by summing the
individual fields in the link configuration
table as defined in Section 8.3, Table 20 of
the JESD204B standard
Checksum is calculated by summing the registers containing the packed link configuration
fields (Σ[0x400:0x40A] modulo 256).
Reserved.
Link Mode. This register selects either singlelink or dual-link mode.
Single-link mode
Dual-link mode
Link Paging. Selects which link’s register map
is used. This paging affects Registers 0x401
to 0x47E.
Use Link 0 register map
Use Link 1 register map
Link Enable. These bits bring up the JESD204B
receiver digital circuitry: Bit 0 for Link 0 and
Bit 1 for Link 1. Enable the link only after the
following has occurred: all JESD204B parameters are set, the DAC PLL is enabled and
locked (Register 0x084[1] = 1), and the
JESD204B PHY is enabled (Register 0x200 =
0x00) and calibrated (Register 0x281[2] = 0).
Disable both JESD Link 1 and JESD Link 0
Disable JESD Link 1, enable JESD Link 0
Enable JESD Link 1, disable JESD Link 0
Enable both JESD Link 1 and JESD Link 0
Reserved.
JESD204B Subclass.
Subclass 0
Subclass 1
Reserved.
Dynamic Link Latency: Link 0. Latency
between the LMFCRx for Link 0 and the last
arriving LMFC boundary in units of PCLK
cycles. See the Deterministic Latency section.
Reserved.
Dynamic Link Latency: Link 1. Latency
between the LMFCRx for Link 1 and the last
arriving LMFC boundary in units of PCLK
cycles. See the Deterministic Latency section.
Rev. D | Page 104 of 117
Reset
0x0
0x0
Access
R
R/W
0xC3
R/W
0x93
R/W
0x0
0x0
R
R/W
0x0
0x0
R
R/W
0x0
R/W
0x0
R/W
0x0
0x1
R
R/W
0x0
0x0
R
R
0x0
0x0
R
R
Data Sheet
AD9135/AD9136
Address
0x304
Name
LMFC_DELAY_0
Bit No.
[7:5]
[4:0]
Bit Name
RESERVED
LMFC_DELAY_0
Settings
0x305
LMFC_DELAY_1
[7:5]
[4:0]
RESERVED
LMFC_DELAY_1
0x306
LMFC_VAR_0
[7:5]
[4:0]
RESERVED
LMFC_VAR_0
0x307
LMFC_VAR_1
[7:5]
[4:0]
RESERVED
LMFC_VAR_1
0x308
XBAR_LN_0_1
[7:6]
[5:3]
RESERVED
LOGICAL_LANE1_
SRC
[2:0]
LOGICAL_LANE0_
SRC
[7:6]
[5:3]
RESERVED
LOGICAL_LANE3_
SRC
[2:0]
LOGICAL_LANE2_
SRC
[7:6]
[5:3]
RESERVED
LOGICAL_LANE5_
SRC
[2:0]
LOGICAL_LANE4_
SRC
[7:6]
[5:3]
RESERVED
LOGICAL_LANE7_
SRC
[2:0]
LOGICAL_LANE6_
SRC
[7:0]
LANE_FIFO_FULL
x
x
0x309
XBAR_LN_2_3
x
x
0x30A
XBAR_LN_4_5
x
x
0x30B
XBAR_LN_6_7
x
x
0x30C
FIFO_STATUS_REG_0
Description
Reserved.
LMFC Delay: Link 0 Delay from the LMFC to
LMFCRx for Link 0. In units of frame clock
cycles for subclass 1 and PCLK cycles for
subclass 0. See the Deterministic Latency
section.
Reserved.
LMFC Delay: Link 1. Delay from the LMFC to
LMFCRx for Link 1. In units of frame clock
cycles for subclass 1 and PCLK cycles for
subclass 0. See the Deterministic Latency
section.
Reserved.
Variable Delay Buffer: Link 0. Sets when data is
read from a buffer to be consistent across links
and power cycles. In units of PCLK cycles. See
the Deterministic Latency section.
This setting must not be more than 10.
Reserved.
Variable Delay Buffer: Link 1. Sets when data is
read from a buffer to be consistent across links
and power cycles. In units of PCLK cycles. See
the Deterministic Latency section.
This setting must not be more than 10.
Reserved.
Logical Lane 1 Source. Selects a physical lane
to be mapped onto Logical Lane 1.
Data is from SERDINx
Logical Lane 0 Source. Selects a physical lane
to be mapped onto Logical Lane 0.
Data is from SERDINx
Reserved.
Logical Lane 3 Source. Selects a physical lane
to be mapped onto Logical Lane 3.
Data is from SERDINx
Logical Lane 2 source. Selects a physical lane
to be mapped onto Logical Lane 2.
Data is from SERDINx
Reserved.
Logical Lane 5 Source. Selects a physical lane
to be mapped onto Logical Lane 5.
Data is from SERDINx
Logical Lane 4 Source. Selects a physical lane
to be mapped onto Logical Lane 4.
Data is from SERDINx
Reserved.
Logical Lane 7 Source. Selects a physical lane
to be mapped onto Logical Lane 7.
Data is from SERDINx
Logical Lane 6 Source. Selects a physical lane
to be mapped onto Logical Lane 6.
Data is from SERDINx
FIFO Full Flags for Each Logical Lane. A full
FIFO indicates an error in the JESD204B
configuration or with a system clock.
If the FIFO for Lane x is full, Bit x in this
register will be high.
Rev. D | Page 105 of 117
Reset
0x0
0x0
Access
R
R/W
0x0
0x0
R
R/W
0x0
0x6
R
R/W
0x0
0x6
R
R/W
0x0
0x1
R
R/W
0x0
R/W
0x0
0x3
R
R/W
0x2
R/W
0x0
0x5
R
R/W
0x4
R/W
0x0
0x7
R
R/W
0x6
R/W
0x0
R
AD9135/AD9136
Data Sheet
Address
0x30D
Name
FIFO_STATUS_REG_1
Bit No.
[7:0]
Bit Name
LANE_FIFO_EMPTY
0x312
SYNCB_GEN_1
[7:6]
[5:4]
RESERVED
SYNCB_ERR_DUR
Settings
0
1
2
0x314
SERDES_SPI_REG
[3:0]
[7:0]
0x315
PHY_PRBS_TEST_EN
[7:0]
RESERVED
SERDES_SPI_
CONFIG
PHY_TEST_EN
0x316
PHY_PRBS_TEST_CTRL
7
[6:4]
RESERVED
PHY_SRC_ERR_CNT
[3:2]
PHY_PRBS_PAT_SEL
x
00
01
10
1
PHY_TEST_START
0
1
0
PHY_TEST_RESET
0
1
0x317
0x318
0x319
0x31A
0x31B
0x31C
0x31D
PHY_PRBS_TEST_
THRESHOLD_LOBITS
PHY_PRBS_TEST_
THRESHOLD_
MIDBITS
PHY_PRBS_TEST_
THRESHOLD_HIBITS
PHY_PRBS_TEST_
ERRCNT_LOBITS
[7:0]
PHY_PRBS_TEST_
ERRCNT_MIDBITS
PHY_PRBS_TEST_
ERRCNT_HIBITS
PHY_PRBS_TEST_
STATUS
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
PHY_PRBS_
THRESHOLD[7:0]
PHY_PRBS_
THRESHOLD[15:8]
PHY_PRBS_
THRESHOLD[23:16]
PHY_PRBS_ERR_
CNT[7:0]
PHY_PRBS_ERR_
CNT[15:8]
PHY_PRBS_ERR_
CNT[23:16]
PHY_PRBS_PASS
Description
FIFO Empty Flags for Each Logical Lane. An
empty FIFO indicates an error in the JESD204B
configuration or with a system clock.
If the FIFO for Logical Lane x is empty, Bit x in
this register will be high.
Reserved.
Duration of SYNCOUTx± Low for Error. The
duration applies to both SYNCOUT0 and
SYNCOUT1. A sync error is asserted at the
end of a multiframe whenever one or more
disparity, not in table or unexpected control
character errors are encountered.
½ PCLK cycle
1 PCLK cycle
2 PCLK cycles
Reserved.
SERDES SPI Configuration. Must be written to
0x01 as part of the Physical Layer setup step.
PHY Test Enable. Enables the PHY BER test.
Set Bit x to enable the PHY test for Lane x.
Reserved.
PHY Error Count Source. Selects which PHY
errors are being reported in Register 0x31A
to Register 0x31C.
Report Lane x error count
PHY PRBS Pattern Select. Selects the PRBS
pattern for PHY BER test.
PRBS7
PRBS15
PRBS31
PHY PRBS Test Start. Starts and stops the PHY
PRBS test.
Test stopped
Test in progress
PHY PRBS Test Reset. Resets the PHY PRBS
test state machine and error counters.
Enable PHY PRBS test state machine
Hold PHY PRBS test state machine in reset
8 LSBs of PHY PRBS Error Threshold.
Reset
0x0
Access
R
0x0
R/W
0x0
0x0
R/W
R/W
0x0
R/W
0x0
0x0
R
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
8 ISBs of PHY PRBS Error Threshold.
0x0
R/W
8 MSBs of PHY PRBS Error Threshold.
0x0
R/W
8 LSBs of PHY PRBS Error Count.
Reported PHY BERT error count from lane
selected using Register 0x316[6:4].
8 ISBs of PHY PRBS Error Count.
0x0
R
0x0
R
8 MSBs of PHY PRBS Error Count.
0x0
R
PHY PRBS Test Pass/Fail.
Bit x corresponds to PHY PRBS pass/fail for
Physical Lane x.
The bit is set to 1 while the error count for
Physical Lane x is less than
PHY_PRBS_THRESHOLD.
0xFF
R
Rev. D | Page 106 of 117
Data Sheet
Address
0x32C
Name
SHORT_TPL_TEST_0
AD9135/AD9136
Bit No.
[7:6]
[5:4]
Bit Name
RESERVED
SHORT_TPL_SP_
SEL
[3:2]
SHORT_TPL_DAC_
SEL
Settings
x
0
2
1
SHORT_TPL_TEST_
RESET
0
1
0
SHORT_TPL_TEST_
EN
0
1
0x32D
SHORT_TPL_TEST_1
[7:0]
SHORT_TPL_REF_
SP_LSB
0x32E
SHORT_TPL_TEST_2
[7:0]
SHORT_TPL_REF_
SP_MSB
0x32F
SHORT_TPL_TEST_3
[7:1]
0
RESERVED
SHORT_TPL_FAIL
0
1
0x333
[7:0]
DEVICE_CONFIG_
13
JESD_BIT_INVERSE
0x400
DEVICE_CONFIG_
REG_13
JESD_BIT_INVERSE_
CTRL
DID_REG
[7:0]
DID_RD
0x401
BID_REG
[7:4]
ADJCNT_RD
[3:0]
BID_RD
7
6
RESERVED
ADJDIR_RD
5
PHADJ_RD
[4:0]
LID0_RD
0x334
0x402
LID0_REG
[7:0]
Description
Reserved.
Short Transport Layer Sample Select. Selects
which sample to check from the DAC
selected via Bits[3:2].
Sample x
Short Transport Layer Test DAC Select.
Selects which DAC to sample.
Sample from DAC0
Sample from DAC1
Short Transport Layer Test Reset. Resets the
result of short transport layer test.
Not reset
Reset
Short Transport Layer Test Enable. See the
Subclass 0 section for details on how to
perform this test.
Disable
Enable
Short Transport Layer Test Reference, Sample
LSB. This is the lower eight bits of the
expected DAC sample. It is used to compare
with the received DAC sample at the output
of the JESD204B receiver.
Short Transport Layer Test Reference, Sample
MSB. This is the upper eight bits of the
expected DAC sample. It is used to compare
with the received DAC sample at the output
of the JESD204B receiver.
Reserved.
Short Transport Layer Test Fail. This bit shows
whether the selected DAC sample matches
the reference sample. If they match, it is a
test pass, otherwise it is a test fail.
Test pass
Test fail
Must be set to 0x01 for proper JESD interface
configuration.
Logical Lane Invert. Set Bit x high to invert
the JESD deserialized data on Logical Lane x.
Device Identification Number. Link
information received on Link Lane 0 as
specified in Section 8.3 of JESD204B.
Adjustment Resolution to DAC LMFC. Link
information received on Link Lane 0 as
specified in Section 8.3 of JESD204B.
Must be 0.
Bank Identification: Extension to DID. Link
information received on Link Lane 0 as
specified in Section 8.3 of JESD204B.
Reserved.
Direction to Adjust DAC LMFC. Link information
received on Link Lane 0 as specified in
Section 8.3 of JESD204B. Must be 0.
Phase Adjustment Request to DAC Link
information received on Link Lane 0 as
specified in Section 8.3 of JESD204B. Must be 0.
Lane Identification for Lane 0. Link
information received on Link Lane 0 as
specified in Section 8.3 of JESD204B.
Rev. D | Page 107 of 117
Reset
0x0
0x0
Access
R
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
0x0
R
R
00
R/W
0x0
R/W
0x0
R
0x0
R
0x0
R
0x0
0x0
R
R
0x0
R
0x0
R
AD9135/AD9136
Address
0x403
Name
SCR_L_REG
Data Sheet
Bit No.
7
Bit Name
SCR_RD
Settings
0
1
[6:5]
[4:0]
RESERVED
L-1_RD
0
1
3
7
0x404
F_REG
[7:0]
F-1_RD
0
1
3
0x405
K_REG
[7:5]
[4:0]
RESERVED
K-1_RD
0x0F
0x1F
0x406
M_REG
[7:0]
M-1_RD
0
1
0x407
CS_N_REG
[7:6]
CS_RD
5
[4:0]
RESERVED
N-1_RD
[7:5]
SUBCLASSV_RD
[4:0]
NP-1_RD
0x0F
0x408
NP_REG
0x0F
Description
Transmit Scrambling Status.
Link information received on Link Lane 0 as
specified in Section 8.3 of JESD204B.
Scrambling is disabled
Scrambling is enabled
Reserved.
Number of Lanes per Converter Device. Link
information received on Link Lane 0 as
specified in Section 8.3 of JESD204B.
One lane per converter
Two lanes per converter
Four lanes per converter
Eight lanes per converter (single link only)
Number of Octets per Frame. Settings of 1, 2
and 4 octets per frame are valid. Link
information received on Link Lane 0 as
specified in Section 8.3 of JESD204B.
(One octet per frame) per lane
(Two octets per frame) per lane
(Four octets per frame) per lane
Reserved.
Number of Frames per Multiframe. Settings
of 16 or 32 are valid. Link information
received on Link Lane 0 as specified in
Section 8.3 of JESD204B.
16 frames per multiframe
32 frames per multiframe
Number of converters per device. Link
information received on Link Lane 0 as
specified in Section 8.3 of JESD204B. Must be
0 or 1.
One converter per device
Two converters per device
Number of Control Bits per Sample. Link
information received on Link Lane 0 as
specified in Section 8.3 of JESD204B. CS must
be 0.
Reserved.
Converter Resolution. Link information
received on Link Lane 0 as specified in
Section 8.3 of JESD204B. Converter
resolution must be 16.
Converter resolution of 16
Device Subclass Version. Link information
received on Link Lane 0 as specified in
Section 8.3 of JESD204B.
Total Number of Bits per Sample. Link
information received on Link Lane 0 as
specified in Section 8.3 of JESD204B. Must be
16 bits per sample.
16 bits per sample.
Rev. D | Page 108 of 117
Reset
0x0
Access
R
0x0
0x0
R
R
0x0
R
0x0
0x0
R
R
0x0
R
0x0
R
0x0
0x0
R
R
0x0
R
0x0
R
Data Sheet
Address
0x409
Name
S_REG
AD9135/AD9136
Bit No.
[7:5]
Bit Name
JESDV_RD
Settings
000
001
[4:0]
S-1_RD
0
1
0x40A
HD_CF_REG
7
HD_RD
0
1
[6:5]
[4:0]
RESERVED
CF_RD
0x40B
RES1_REG
[7:0]
RES1_RD
0x40C
RES2_REG
[7:0]
RES2_RD
0x40D
CHECKSUM_REG
[7:0]
FCHK0_RD
0x40E
COMPSUM0_REG
[7:0]
FCMP0_RD
0x412
LID1_REG
[7:5]
[4:0]
RESERVED
LID1_RD
0x415
CHECKSUM1_REG
[7:0]
FCHK1_RD
0x416
COMPSUM1_REG
[7:0]
FCMP1_RD
0x41A
LID2_REG
0x41D
0x41E
CHECKSUM2_REG
COMPSUM2_REG
[7:5]
[4:0]
[7:0]
[7:0]
RESERVED
LID2_RD
FCHK2_RD
FCMP2_RD
0x422
LID3_REG
0x425
0x426
CHECKSUM3_REG
COMPSUM3_REG
[7:5]
[4:0]
[7:0]
[7:0]
RESERVED
LID3_RD
FCHK3_RD
FCMP3_RD
Description
JESD204 Version. Link information received
on Link Lane 0 as specified in Section 8.3 of
JESD204B.
JESD204A
JESD204B
Number of Samples per Converter per Frame
Cycle. Settings of one and two are valid. Link
information received on Link Lane 0 as
specified in Section 8.3 of JESD204B.
One sample per converter per frame
Two samples per converter per frame
High Density Format. See Section 5.1.3 of the
JESD294B standard. Link information
received on Link Lane 0 as specified in
Section 8.3 of JESD204B.
Low density mode
High density mode: link information received
on Lane 0 as specified in Section 8.3 of
JESD204B
Reserved.
Number of Control Words per Frame Clock
Period per Link. Link information received on
Link Lane 0 as specified in Section 8.3 of
JESD204B. Bits[4:0] must be 0.
Reserved Field 1. Link information received on
Link Lane 0 as specified in Section 8.3 of
JESD204B.
Reserved Field 2. Link information received on
Link Lane 0 as specified in Section 8.3 of
JESD204B.
Checksum for Link Lane 0. Link information
received on Link Lane 0 as specified in
Section 8.3 of JESD204B.
Computed Checksum for Link Lane 0. The
JESD204B receiver computes the checksum
of the link information received on Lane 0 as
specified in Section 8.3 of JESD204B. The
computation method is set by the
CHECKSUM_MODE bit (Address 0x300[6])
and must match the likewise calculated
checksum in Register 0x40D.
Reserved.
Lane Identification for Link Lane 1.Link
information received on Lane 0 as specified
in section 8.3 of JESD204B.
Checksum for Link Lane 1. Link information
received on Lane 0 as specified in Section 8.3
of JESD204B.
Computed Checksum for Link Lane 1. See the
description for Register 0x40E.
Reserved.
Lane Identification for Link Lane 2.
Checksum for Link Lane 2.
Computed Checksum for Link Lane 2 (see the
description for Register 0x40E).
Reserved.
Lane Identification for Link Lane 3.
Checksum for Link Lane 3.
Computed Checksum for Link Lane 3 (see the
description for Register 0x40E).
Rev. D | Page 109 of 117
Reset
0x0
Access
R
0x0
R
0x0
R
0x0
0x0
R
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
0x0
R
R
0x0
R
0x0
R
0x0
0x0
0x0
0x0
R
R
R
R
0x0
0x0
0x0
0x0
R
R
R
R
AD9135/AD9136
Address
0x42A
Name
LID4_REG
0x42D
0x42E
CHECKSUM4_REG
COMPSUM4_REG
0x432
LID5_REG
0x435
0x436
CHECKSUM5_REG
COMPSUM5_REG
0x43A
LID6_REG
0x43D
0x43E
CHECKSUM6_REG
COMPSUM6_REG
0x442
LID7_REG
0x445
0x446
Data Sheet
Bit No.
[7:5]
[4:0]
[7:0]
[7:0]
Bit Name
RESERVED
LID4_RD
FCHK4_RD
FCMP4_RD
[7:5]
[4:0]
[7:0]
[7:0]
RESERVED
LID5_RD
FCHK5_RD
FCMP5_RD
[7:5]
[4:0]
[7:0]
[7:0]
RESERVED
LID6_RD
FCHK6_RD
FCMP6_RD
CHECKSUM7_REG
COMPSUM7_REG
[7:5]
[4:0]
[7:0]
[7:0]
RESERVED
LID7_RD
FCHK7_RD
FCMP7_RD
0x450
ILS_DID
[7:0]
DID
0x451
ILS_BID
[7:4]
ADJCNT
[3:0]
BID
7
6
5
RESERVED
ADJDIR
PHADJ
[4:0]
LID0
7
SCR
0x452
0x453
ILS_LID0
ILS_SCR_L
Settings
0
1
[6:5]
[4:0]
RESERVED
L-1
0
1
3
7
0x454
ILS_F
[7:0]
F-1
0
1
3
0x455
ILS_K
[7:5]
[4:0]
RESERVED
K-1
0x0F
0x1F
Description
Reserved.
Lane Identification for Link Lane 4.
Checksum for Link Lane 4.
Computed Checksum for Link Lane 4 (see the
description for Register 0x40E).
Reserved.
Lane Identification for Link Lane 5.
Checksum for Link Lane 5.
Computed Checksum for Link Lane 5 (see the
description for Register 0x40E).
Reserved.
Lane Identification for Link Lane 6.
Checksum for Link Lane 6.
Computed Checksum for Link Lane 6 (see the
description for Register 0x40E).
Reserved.
Lane Identification for Link Lane 7.
Checksum for Link Lane 7.
Computed Checksum for Link Lane 7 (see the
description for Register 0x40E).
Device Identification Number. Link information
received on Link Lane 0 as specified in
Section 8.3 of JESD204B. Must be set to value
read in Register 0x400.
Adjustment Resolution to DAC LMFC Must
be set to 0.
Bank Identification: Extension to DID Must be
set to value read in Register 0x401[3:0].
Reserved.
Direction to Adjust DAC LMFC. Must be set to 0.
Phase Adjustment Request to DAC. Must be
set to 0.
Lane Identification for Link Lane 0. Must be set
to the value read in Register 0x402[4:0].
Receiver Descrambling Enable.
Descrambling is disabled
Descrambling is enabled
Reserved.
Number of Lanes per Converter Device. See
Table 34 and Table 35.
One lane per converter
Two lanes per converter
Four lanes per converter
Eight lanes per converter (single link only)
Number of Octets per Lane per Frame. Settings
of 1, 2, and 4 (octets per lane) per frame are
valid. See Table 34 and Table 35.
(One octet per lane) per frame
(Two octets per lane) per frame
(Four octets per lane) per frame
Reserved.
Number of Frames per Multiframe. Settings
of 16 or 32 are valid. Must be set to 32 when
F = 1 (Register 0x476).
16 frames per multiframe
32 frames per multiframe
Rev. D | Page 110 of 117
Reset
0x0
0x0
0x0
0x0
Access
R
R
R
R
0x0
0x0
0x0
0x0
R
R
R
R
0x0
0x0
0x0
0x0
R
R
R
R
0x0
0x0
0x0
0x0
R
R
R
R
0x0
R/W
0x0
R/W
0x0
R/W
0x0
0x0
0x0
R
R/W
R/W
0x0
R/W
0x1
R/W
0x0
0x3
R
R/W
0x0
R/W
0x0
0x1F
R
R/W
Data Sheet
Address
0x456
Name
ILS_M
AD9135/AD9136
Bit No.
[7:0]
Bit Name
M-1
Settings
0
1
0x457
ILS_CS_N
[7:6]
CS
5
[4:0]
RESERVED
N-1
[7:5]
SUBCLASSV
0
0x0F
0x458
ILS_NP
0
1
[4:0]
NP-1
0xF
0x459
ILS_S
[7:5]
JESDV
000
001
[4:0]
S-1
0
1
0x45A
ILS_HD_CF
7
HD
0
1
[6:5]
[4:0]
RESERVED
CF
0x45B
0x45C
0x45D
ILS_RES1
ILS_RES2
ILS_CHECKSUM
[7:0]
[7:0]
[7:0]
RES1
RES2
FCHK0
0x46B
ERRCNTRMON_RB
[7:0]
READERRORCNTR
0x46B
ERRCNTRMON
7
[6:4]
RESERVED
LANESEL
[3:2]
[1:0]
RESERVED
CNTRSEL
x
00
01
10
0x46C
0x46D
LANEDESKEW
BADDISPARITY_RB
[7:0]
[7:0]
LANEDESKEW
BADDIS
Description
Number of Converters per Device. See Table 34
and Table 35.
One converter per link
Two converters per link
Number of Control Bits per Sample. Must be
set to 0. Control bits are not supported.
Zero control bits per sample
Reserved.
Converter Resolution. Must be set to 16 bits
of resolution.
Converter resolution of 16.
Device Subclass Version.
Subclass 0
Subclass 1
Total Number of Bits per Sample. Must be set
to 16 bits per sample.
16 bits per sample.
JESD204 Version.
JESD204A
JESD204B
Number of Samples per Converter per Frame
Cycle. Settings of one and two are valid.
One sample per converter per frame
Two samples per converter per frame
High Density Format. If F = 1, HD must be set
to 1. Otherwise, HD must be set to 0. See
Section 5.1.3 of JESD204B standard.
Low density mode
High density mode
Reserved.
Number of Control Words per Frame Clock
Period per Link. Must be set to 0. Control bits
are not supported.
Reserved Field 1.
Reserved Field 2.
Checksum for Link Lane 0. Calculated
checksum. Calculation depends on 0x300[6].
Read JESD204B Error Counter. After selecting
the lane and error counter by writing to
LANESEL and CNTRSEL (both in this same
register), the selected error counter is read
back here.
Reserved.
Link Lane select for JESD204B error counter.
Selects the lane whose errors are read back
in this register.
Selects Link Lane x
Reserved.
JESD204B Error Counter Select. Selects the
type of error that are read back in this register.
BADDISCNTR: bad running disparity counter
NITCNTR: not in table error counter
UCCCNTR: Unexpected control character counter
Lane Deskew. Setting Bit x deskews Link Lane x
Bad Disparity Character Error (BADDIS). Bit x
is set when the bad disparity error count for
Link Lane x reaches the threshold in
Register 0x47C.
Rev. D | Page 111 of 117
Reset
0x1
Access
R/W
0x0
R/W
0x0
0xF
R
R/W
0x1
R/W
0xF
R/W
0x1
R/W
0x0
R/W
0x1
R/W
0x0
0x0
R
R/W
0x0
0x0
0x45
R/W
R/W
R/W
0x0
R
0x0
0x0
R
W
0x0
0x0
R
W
0xF
0x0
R/W
R
AD9135/AD9136
Address
0x46D
Name
BADDISPARITY
Data Sheet
Bit No.
7
Bit Name
RST_IRQ_DIS
Settings
6
DISABLE_ERR_
CNTR_DIS
5
RST_ERR_CNTR_DIS
[4:3]
[2:0]
RESERVED
LANE_ADDR_DIS
0x46E
NIT_RB
[7:0]
NIT
0x46E
NIT_W
7
RST_IRQ_NIT
6
DISABLE_ERR_
CNTR_NIT
5
RST_ERR_CNTR_NIT
[4:3]
[2:0]
RESERVED
LANE_ADDR_NIT
0x46F
UNEXPECTEDCONTROL_RB
[7:0]
UCC
0x46F
UNEXPECTEDCONTROL_W
7
RST_IRQ_UCC
6
DISABLE_ERR_
CNTR_UCC
5
[4:3]
[2:0]
RST_ERR_CNTR_
UCC
RESERVED
LANE_ADDR_UCC
[7:0]
CODEGRPSYNC
0x470
CODEGRPSYNCFLG
0
1
0x471
FRAMESYNCFLG
[7:0]
FRAMESYNC
0
1
0x472
GOODCHKSUMFLG
[7:0]
GOODCHECKSUM
0
1
Description
BADDIS IRQ Reset. Reset BADDIS IRQ for lane
selected via Bits[2:0] by writing 1 to this bit.
BADDIS Error Counter Disable. Disable the
BADDIS error counter for lane selected via
Bits[2:0] by writing 1 to this bit.
BADDIS Error Counter Reset. Reset BADDIS
error counter for lane selected via Bits[2:0] by
writing 1 to this bit.
Reserved.
Link Lane Address for Functions Described in
Bits[7:5].
Not in table Character Error (NIT). Bit x is set
when Link Lane x’s NIT error count reaches
the threshold in Register 0x47C.
IRQ Reset. Reset IRQ for lane selected via
Bits[2:0] by writing 1 to this bit.
Disable Error Counter. Disable the error
counter for lane selected via Bits[2:0] by
writing 1 to this bit.
Reset Error Counter. Reset error counter for lane
selected via Bits[2:0] by writing 1 to this bit.
Reserved.
Link Lane Address for Functions Described in
Bits[7:5].
Unexpected Control Character Error (UCC).
Bit x is set when Link Lane x’s UCC error
count reaches the threshold in Register 0x47C.
IRQ Reset. Reset IRQ for lane selected via
Bits[2:0] by writing 1 to this bit.
Disable Error Counter. Disable the error
counter for lane selected via Bits[2:0] by
writing 1 to this bit.
Reset Error Counter. Reset error counter for
lane selected via Bits[2:0] by writing 1 to this bit.
Reserved.
Link Lane Address for Functions Described in
Bits[7:5].
Code Group Sync Flag (from Each Instantiated
Lane). Writing 1 to Bit 7 resets the IRQ. The
associated IRQ flag is located in Register
0x47A[0]. A loss of CODEGRPSYNC triggers
sync request assertion. See the SYNCOUTx±,
SYSREF±, and CLK± Signals section and the
Deterministic Latency section.
Synchronization is lost
Synchronization is achieved
Frame Sync Flag (from Each Instantiated
Lane). This register indicates the live status
for each lane. Writing 1 to Bit 7 resets the
IRQ. A loss of frame sync automatically
initiates a synchronization sequence.
Synchronization is lost
Synchronization is achieved
Good Checksum Flag (from Each Instantiated
Lane). Writing 1 to Bit 7 resets the IRQ.
The associated IRQ flag is located in
Register 0x47A[2].
Last computed checksum is not correct
Last computed checksum is correct
Rev. D | Page 112 of 117
Reset
0x0
Access
W
0x0
W
0x0
W
0x0
0x0
R
W
0x0
R
0x0
W
0x0
W
0x0
W
0x0
0x0
R
W
0x0
R
0x0
W
0x0
W
0x0
W
0x0
0x0
R
W
0x0
R/W
0x0
R/W
0x0
R/W
Data Sheet
AD9135/AD9136
Address
0x473
Name
INITLANESYNCFLG
Bit No.
[7:0]
Bit Name
INITIALLANESYNC
0x476
CTRLREG1
[7:0]
F
Settings
1
2
4
0x477
CTRLREG2
7
ILAS_MODE
1
0
[6:4]
3
0x478
KVAL
[2:0]
[7:0]
RESERVED
THRESHOLD_
MASK_EN
RESERVED
KSYNC
0x47A
IRQVECTOR_MASK
7
BADDIS_MASK
x
1
6
NIT_MASK
1
5
UCC_MASK
1
4
3
2
1
0
0x47A
IRQVECTOR_FLAG
7
RESERVED
INITIALLANESYNC_
MASK
1
BADCHECKSUM_
MASK
1
FRAMESYNC_
MASK
1
CODEGRPSYNC_
MASK
1
BADDIS_FLAG
1
6
NIT_FLAG
1
Description
Initial Lane Sync Flag (from Each Instantiated
Lane). Writing 1 to Bit 7 resets the IRQ. The
associated IRQ flag is located in Register
0x47A[3]. Loss of synchronization is also
reported on SYNCOUT1± or SYNCOUT0±. See
the SYNCOUTx±, SYSREF±, and CLK± Signals
section and the Deterministic Latency section.
Number of Octets per Frame. Settings of 1, 2,
and 4 are valid. See Table 34 and Table 35.
One octet per frame
Two octets per frame
Four octets per frame
ILAS Test Mode. Defined in Section 5.3.3.8 of
JESD204B specification.
JESD204B receiver is constantly receiving
ILAS frames
Normal link operation
Reserved.
Threshold Mask Enable. Set this bit if using
SYNC_ASSERTION_MASK (Register 0x47B[7:5]).
Reserved.
Number of K Multiframes During ILAS
(Divided by Four). Sets the number of
multiframes to send initial lane alignment
sequence. Cannot be set to 0.
4× multiframes during ILAS
Bad Disparity Mask.
If the bad disparity count reaches
ERRORTHRESH on any lane, IRQ is pulled low.
Not in table Mask.
If the not in table character count reaches
ERRORTHRESH on any lane, IRQ is pulled low.
Unexpected Control Character Mask.
If the unexpected control character count
reaches ERRORTHRESH on any lane, IRQ is
pulled low.
Reserved.
Initial Lane Sync Mask.
If initial lane sync (0x473) fails on any lane,
IRQ is pulled low.
Bad Checksum Mask.
If there is a bad checksum (0x472) on any
lane, IRQ is pulled low.
Frame Sync Mask
If frame sync (0x471) fails on any lane, IRQ is
pulled low.
Code Group Sync Machine Mask.
If code group sync (0x470) fails on any lane,
IRQ is pulled low.
Bad Disparity Error Count.
Bad disparity character count reached
ERRORTHRESH (0x47C) on at least one lane.
Read Register 0x46D to determine which
lanes are in error.
Not in table Error Count
Not in table character count reached
ERRORTHRESH (0x47C) on at least one lane.
Read Register 0x46E to determine which
lanes are in error.
Rev. D | Page 113 of 117
Reset
0x0
Access
R/W
0x1
R/W
0x0
R/W
0x0
0x0
R
R/W
0x0
0x1
R
R/W
0x0
W
0x0
W
0x0
W
0x0
0x0
R
W
0x0
W
0x0
W
0x0
W
0x0
R
0x0
R
AD9135/AD9136
Address
Name
Data Sheet
Bit No.
5
Bit Name
UCC_FLAG
Settings
1
4
3
2
1
0
0x47B
SYNCASSERTIONMASK
7
RESERVED
INITIALLANESYNC_
FLAG
1
BADCHECKSUM_
FLAG
1
FRAMESYNC_
FLAG
1
CODEGRPSYNC_
FLAG
1
BADDIS_S
1
6
NIT_S
1
5
UCC_S
1
4
CMM
1
3
CMM_ENABLE
1
0
0x47C
ERRORTHRES
[2:0]
[7:0]
0x47D
LANEENABLE
[7:0]
RESERVED
ETH
LANE_ENA
Description
Unexpected Control Character Error Count
Unexpected control character count reached
ERRORTHRESH (0x47C) on at least one lane.
Read Register 0x46F to determine which
lanes are in error.
Reserved.
Initial Lane Sync Flag.
Initial lane sync failed on at least one lane.
Read Register 0x473 to determine which
lanes are in error
Bad Checksum Flag.
Bad checksum on at least one lane. Read
Register 0x472 to determine which lanes are in
error.
Frame Sync Flag.
Frame sync failed on at least one lane. Read
Register 0x471 to determine which lanes are
in error.
Code Group Sync Flag.
Code group sync failed on at least one lane.
Read Register 0x470 to determine which
lanes are in error
Bad Disparity Error on Sync.
Asserts a sync request on SYNCOUTx± when
the bad disparity character count reaches the
threshold in Register 0x47C
Not in table Error on Sync.
Asserts a sync request on SYNCOUTx± when
the not in table character count reaches the
threshold in Register 0x47C
Unexpected Control Character Error on Sync.
Asserts a sync request on SYNCOUTx± when
the unexpected control character count
reaches the threshold in Register 0x47C
Configuration Mismatch IRQ. If
CMM_ENABLE is high, this bit latches on a
rising edge and pull IRQ low. When latched,
write a 1 to clear this bit. If CMM_ENABLE is
low, this bit is non-functional.
Link Lane 0 configuration registers (Register
0x450 to Register 0x45D) do not match the
JESD204B transmit settings (Register 0x400
to Register 0x40D)
Configuration Mismatch IRQ Enable.
Enables IRQ generation if a configuration
mismatch is detected
Configuration mismatch IRQ disabled
Reserved.
Error Threshold. Bad disparity, not in table,
and unexpected control character errors are
counted and compared to the error
threshold value. When the count reaches the
threshold, either an IRQ is generated or the
SYNCOUTx± signal is asserted per the mask
register settings, or both. Function is
performed in all lanes.
Lane Enable. Setting Bit x enables Link Lane x.
This register must be programmed before
receiving the code group pattern for proper
operation.
Rev. D | Page 114 of 117
Reset
0x0
Access
R
0x0
0x0
R
R
0x0
R
0x0
R
0x0
R
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x1
R/W
0x0
0xFF
R
R/W
0xF
R/W
Data Sheet
Address
0x47E
Name
RAMP_ENA
AD9135/AD9136
Bit No.
[7:1]
0
Bit Name
RESERVED
ENA_RAMP_
CHECK
Settings
0
1
0x520
DIG_TEST0
[7:2]
RESERVED
0x521
DC_TEST_VALUE0
1
0
[7:0]
0x522
DC_TEST_VALUE1
[7:0]
DC_TEST_MODE
RESERVED
DC_TEST_
VALUE[7:0]
DC_TEST_
VALUE[15:8]
Description
Reserved.
Enable Ramp Checking at the Beginning of
ILAS.
Disable ramp checking at beginning of ILAS;
ILAS data need not be a ramp
Enable ramp checking; ILAS data needs to be
a ramp starting at 00-01-02; otherwise, the
ramp ILAS fails and the device does not start up
Must write default value for proper
operation.
DC Test Mode
Reserved.
DC Value LSB of DC Test Mode for DAC0 and
DAC1.
DC value MSB of DC Test Mode for DAC0 and
DAC1.
Rev. D | Page 115 of 117
Reset
0x0
0x0
Access
R
W
0x7
R/W
0x0
0x0
0x0
R/W
R/W
R/W
0x0
R/W
AD9135/AD9136
Data Sheet
OUTLINE DIMENSIONS
12.10
12.00 SQ
11.90
0.28
0.23
0.18
0.60 MAX
0.60
MAX
67
66
88
PIN 1
INDICATOR
1
PIN 1
INDICATOR
11.85
11.75 SQ
11.65
0.50
BSC
0.50
0.40
0.30
22
23
45
44
TOP VIEW
BOTTOM VIEW
10.50
REF
0.70
0.65
0.60
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.045
0.025
0.005
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
08-10-2012-A
12° MAX
0.90
0.85
0.80
7.55
7.40 SQ
7.25
EXPOSED PAD
COMPLIANT TO JEDEC STANDARDS MO-220-VRRD
Figure 91. 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
12 mm × 12 mm Body, Very Thin Quad
(CP-88-6)
Dimensions shown in millimeters
12.10
12.00 SQ
11.90
0.30
0.25
0.20
0.60 MAX
0.60
MAX
67
88
66
1
PIN 1
INDICATOR
PIN 1
INDICATOR
0.50
BSC
7.55
7.40 SQ
7.25
EXPOSED
PAD
0.65
0.55
0.45
22
44
TOP VIEW
0.90
0.85
0.80
PKG-004598
SEATING
PLANE
12° MAX
SIDE VIEW
0.190~0.245 REF
0.70
0.65
0.60
0.50
0.40
0.30
45
0.045
0.025
0.005
COPLANARITY
0.08
23
BOTTOM VIEW
10.50
REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220
Figure 92. 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ] (Variable Lead Length)
12 mm × 12 mm Body, Very Thin Quad
(CP-88-9)
Dimensions shown in millimeters
Rev. D | Page 116 of 117
1.00
0.90
0.80
0.80
0.70
0.60
11-09-2018-B
11.85
11.75 SQ
11.65
Data Sheet
AD9135/AD9136
ORDERING GUIDE
Model1
AD9135BCPZ
AD9135BCPZRL
AD9135BCPAZ
AD9135BCPAZRL
AD9136BCPZ
AD9136BCPZRL
AD9136BCPAZ
AD9136BCPAZRL
AD9136-FMC-EBZ
AD9135-FMC-EBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
88-Lead LFCSP_VQ
88-Lead LFCSP_VQ
88-Lead LFCSP_VQ (Variable Lead Length)
88-Lead LFCSP_VQ (Variable Lead Length)
88-Lead LFCSP_VQ
88-Lead LFCSP_VQ
88-Lead LFCSP_VQ (Variable Lead Length)
88-Lead LFCSP_VQ (Variable Lead Length)
FMC Evaluation Board
FMC Evaluation Board
Z = RoHS Compliant Part.
©2014–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12578-0-4/19(D)
Rev. D | Page 117 of 117
Package Option
CP-88-6
CP-88-6
CP-88-9
CP-88-9
CP-88-6
CP-88-6
CP-88-9
CP-88-9
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