Dual, 16-Bit, 1600 MSPS, TxDAC+
Digital-to-Analog Converter
AD9142A
Data Sheet
FEATURES
GENERAL DESCRIPTION
Supports input data rate up to 575 MHz
Very small inherent latency variation: 85 dBc (bandwidth = 300 MHz) at ZIF
Flexible 16-bit LVDS interface
Supports word and byte load
Data interface DLL
Sample error detection and parity
Multiple chip synchronization
Fixed latency and data generator latency compensation
Selectable 2×, 4×, 8× interpolation filter
Low power architecture
fS/4 power saving coarse mixer
Input signal power detection
Emergency stop for downstream analog circuitry
protection
FIFO error detection
On-chip numeric control oscillator allows carrier placement
anywhere in the DAC Nyquist bandwidth
Transmit enable function for extra power saving
High performance, low noise PLL clock multiplier
Digital gain and phase adjustment for sideband suppression
Digital inverse sinc filter
Low power: 1.8 W at 1.6 GSPS, 1.5 W at 1.25 GSPS, full
operating conditions
72-lead LFCSP
The AD9142A is a dual, 16-bit, high dynamic range digital-toanalog converter (DAC) that provides a sample rate of 1600 MSPS,
permitting a multicarrier generation up to the Nyquist frequency.
The AD9142A TxDAC+® includes features optimized for direct
conversion transmit applications, including complex digital modulation, input signal power detection, and gain, phase, and offset
compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x
F-MOD series and the ADRF670x series from Analog Devices,
Inc. A 3-wire serial port interface provides for the programming/
readback of many internal parameters. Full-scale output current
can be programmed over a range of 9 mA to 33 mA. The
AD9142A is available in a 72-lead LFCSP.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
APPLICATIONS
Wide signal bandwidth (BW) enables emerging wideband
and multiband wireless applications.
Advanced low spurious and distortion design techniques
provide high quality synthesis of wideband signals from
baseband to high intermediate frequencies.
Very small inherent latency variation simplifies both software
and hardware design in the system. It allows easy multichip
synchronization for most applications.
New low power architecture improves power efficiency
(mW/MHz/channel) by 30%.
Input signal power and FIFO error detection simplify
designs for downstream analog circuitry protection.
Programmable transmit enable function allows easy design
balance between power consumption and wakeup time.
Wireless communications: 3G/4G and MC-GSM base stations,
wideband repeaters, software defined radios
Wideband communications: point-to-point, LMDS/MMDS
Transmit diversity/MIMO
Instrumentation
Automated test equipment
Rev. A
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Technical Support
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AD9142A
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Datapath Configuration ............................................................ 35
Applications ....................................................................................... 1
Digital Quadrature Gain and Phase Adjustment ................... 35
General Description ......................................................................... 1
DC Offset Adjustment ............................................................... 35
Product Highlights ........................................................................... 1
Inverse Sinc Filter ....................................................................... 36
Revision History ............................................................................... 4
Input Signal Power Detection and Protection ........................ 36
Functional Block Diagram .............................................................. 5
Transmit Enable Function ......................................................... 37
Specifications..................................................................................... 6
Digital Function Configuration ............................................... 37
DC Specifications ......................................................................... 6
Multidevice Synchronization and Fixed Latency ....................... 38
Digital Specifications ................................................................... 8
Very Small Inherent Latency Variation ................................... 38
DAC Latency Specifications ........................................................ 9
Further Reducing the Latency Variation................................. 38
Latency Variation Specifications ................................................ 9
Synchronization Implementation ............................................ 39
AC Specifications........................................................................ 10
Synchronization Procedures ..................................................... 39
Operating Speed Specifications ................................................ 10
Interrupt Request Operation ........................................................ 40
Absolute Maximum Ratings ..................................................... 11
Interrupt Working Mechanism ................................................ 40
Thermal Resistance .................................................................... 11
Interrupt Service Routine .......................................................... 40
ESD Caution ................................................................................ 11
Temperature Sensor ....................................................................... 41
Pin Configuration and Function Descriptions ........................... 12
DAC Input Clock Configurations ................................................ 42
Typical Performance Characteristics ........................................... 15
Driving the DACCLK and REFCLK Inputs ........................... 42
Terminology .................................................................................... 20
Direct Clocking .......................................................................... 42
Serial Port Operation ..................................................................... 21
Clock Multiplication .................................................................. 42
Data Format ................................................................................ 21
PLL Settings ................................................................................ 43
Serial Port Pin Descriptions ...................................................... 21
Configuring the VCO Tuning Band ........................................ 43
Serial Port Options ..................................................................... 21
Automatic VCO Band Select .................................................... 43
Data Interface .................................................................................. 23
Manual VCO Band Select ......................................................... 43
LVDS Input Data Ports .............................................................. 23
PLL Enable Sequence ................................................................. 43
Word Interface Mode ................................................................. 23
Analog Outputs............................................................................... 44
Byte Interface Mode ................................................................... 23
Transmit DAC Operation.......................................................... 44
Data Interface Configuration Options .................................... 23
Interfacing to Modulators ......................................................... 45
DLL Interface Mode ................................................................... 23
Reducing LO Leakage and Unwanted Sidebands .................. 46
Parity ............................................................................................ 26
Example Start-Up Routine ............................................................ 47
SED Operation ............................................................................ 26
Device Configuration and Start-Up Sequence 1 .................... 47
SED Example ............................................................................... 27
Device Configuration and Start-Up Sequence 2 .................... 47
Delay Line Interface Mode ........................................................ 27
Device Configuration Register Map and Description ............... 49
FIFO Operation .............................................................................. 29
SPI Configure Register .............................................................. 52
Resetting the FIFO ..................................................................... 30
Power-Down Control Register ................................................. 52
Serial Port Initiated FIFO Reset ............................................... 30
Interrupt Enable0 Register ........................................................ 52
Frame Initiated FIFO Reset ....................................................... 30
Interrupt Enable1 Register ........................................................ 53
Digital Datapath.............................................................................. 32
Interrupt Flag0 Register............................................................. 53
Interpolation Filters ................................................................... 32
Interrupt Flag1 Register............................................................. 53
Digital Modulation ..................................................................... 34
Interrupt Select0 Register .......................................................... 54
Rev. A | Page 2 of 72
Data Sheet
AD9142A
Interrupt Select1 Register...........................................................54
NCO Frequency Tuning Word 3 Register ............................... 64
Frame Mode Register..................................................................54
NCO Phase Offset 0 Register .................................................... 64
Data Control 0 Register ..............................................................55
NCO Phase Offset 1 Register .................................................... 64
Data Control 1 Register ..............................................................55
IQ Phase Adjust 0 Register ........................................................ 64
Data Control 2 Register ..............................................................55
IQ Phase Adjust 1 Register ........................................................ 64
Data Control 3 Register ..............................................................55
Power Down Data Input 0 Register .......................................... 65
Data Status 0 Register .................................................................55
IDAC DC Offset 0 Register ....................................................... 65
DAC Clock Receiver Control Register .....................................56
IDAC DC Offset 1 Register ....................................................... 65
Ref Clock Receiver Control Register ........................................56
QDAC DC Offset 0 Register ...................................................... 65
PLL Control 0 Register ...............................................................56
QDAC DC Offset 1 Register ...................................................... 65
PLL Control 2 Register ...............................................................57
IDAC Gain Adjust Register ....................................................... 65
PLL Control 3 Register ...............................................................57
QDAC Gain Adjust Register...................................................... 66
PLL Status 0 Register ..................................................................57
Gain Step Control 0 Register ..................................................... 66
PLL Status 1 Register ..................................................................58
Gain Step Control 1 Register ..................................................... 66
IDAC FS Adjust LSB Register ....................................................58
Tx Enable Control Register ....................................................... 66
IDAC FS Adjust MSB Register ..................................................58
DAC Output Control Register .................................................. 67
QDAC FS Adjust LSB Register ..................................................58
DLL Cell Enable 0 Register ........................................................ 67
QDAC FS Adjust MSB Register ................................................58
DLL Cell Enable 1 Register ........................................................ 67
Die Temperature Sensor Control Register ...............................59
SED Control Register ................................................................. 67
Die Temperature LSB Register ..................................................59
SED Pattern I0 Low Bits Register.............................................. 68
Die Temperature MSB Register .................................................59
SED Pattern I0 High Bits Register ............................................ 68
Chip ID Register..........................................................................59
SED Pattern Q0 Low Bits Register ............................................ 68
Interrupt Configuation Register ...............................................59
SED Pattern Q0 High Bits Register .......................................... 68
Sync Control Register .................................................................60
SED Pattern I1 Low Bits Register.............................................. 68
Frame Reset Control Register ....................................................60
SED Pattern I1 High Bits Register ............................................ 68
FIFO Level Configuration Register ..........................................60
SED Pattern Q1 Low Bits Register ............................................ 68
FIFO Level Readback Register ..................................................61
SED Pattern Q1 High Bits Register .......................................... 69
FIFO Control Register ................................................................61
Parity Control Register ............................................................... 69
Data Format Select Register.......................................................61
Parity Error Rising Edge Register ............................................. 69
Datapath Control Register .........................................................61
Parity Error Falling Edge Register ............................................ 69
Interpolation Control Register ..................................................62
Version Register .......................................................................... 69
Over Threshold Control 0 Register ..........................................62
DAC Latency and System Skews ................................................... 70
Over Threshold Control 1 Register ..........................................62
DAC Latency Variations............................................................. 70
Over Threshold Control 2 Register ..........................................62
FIFO Latency Variation.............................................................. 70
Input Power Readback LSB Register ........................................62
Clock Generation Latency Variation ........................................ 71
Input Power Readback MSB Register .......................................63
Correcting System Skews ........................................................... 71
NCO Control Register ................................................................63
Packaging and Ordering Information .......................................... 72
NCO Frequency Tuning Word 0 Register ...............................63
Outline Dimensions ................................................................... 72
NCO Frequency Tuning Word 1 Register ...............................63
Ordering Guide ........................................................................... 72
NCO Frequency Tuning Word 2 Register ...............................63
Rev. A | Page 3 of 72
AD9142A
Data Sheet
REVISION HISTORY
5/14—Rev. 0 to Rev. A
Change to Table 25 ......................................................................... 51
Changes to Table 103...................................................................... 69
12/13—Revision 0: Initial Version
Rev. A | Page 4 of 72
Data Sheet
AD9142A
FUNCTIONAL BLOCK DIAGRAM
INPUT POWER
DETECTION
HB2
2×
NCO
HB3
2×
fDAC /4
MOD
IOUT1P
IOUT1N
DAC CLK
16
DAC 2
16-BIT
IOUT2P
IOUT2N
GAIN 1
DAC_CLK
INTERP
MODE CTRL3
INTERP
MODE CTRL2
INTERP
MODE CTRL1
FIFO CTRL
SED CTRL
INTERFACE CTRL
FRAMEP/PARITYP
FRAMEN/PARITYN
DAC 1
16-BIT
10
GAIN 2
HB1
2×
16
OVERTHRESHOLD
PROTECTION
FIFO
8-SAMPLE
SED
LVDS DATA
RECEIVER
D0P/D0N
INV
SINC
COMPLEX
MODULATION
D15P/D15N
DC OFFSET
CONTROL
AD9142A
GAIN AND PHASE
CONTROL
DLL
13-TAP
DCIP/DCIN
10
REF
AND
BIAS
VREF
FSADJ
INTERNAL CLOCK TIMING AND CONTROL LOGIC
SERIAL
INPUT/OUTPUT
PORT
POWER-ON
RESET
MULTICHIP
SYNCHRONIZATION
DAC_CLK
CLOCK
MULTIPLIER
CLK
RCVR
DACCLKP
DACCLKN
REF
RCVR
REFP/SYNCP
REFN/SYNCN
11901-001
IRQ2
RESET
TXEN
CS
IRQ1
SCLK
SYNC
SDIO
PROGRAMMING
REGISTERS
Figure 1.
Rev. A | Page 5 of 72
AD9142A
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
MAIN DAC OUTPUTS
Offset Error
Gain Error
Full-Scale Output Current
Output Compliance Range
Output Resistance
Gain DAC Monotonicity
Settling Time to Within ±0.5 LSB
MAIN DAC TEMPERATURE DRIFT
Offset
Gain
Reference Voltage
REFERENCE
Internal Reference Voltage
Output Resistance
ANALOG SUPPLY VOLTAGES
AVDD33
CVDD18
DIGITAL SUPPLY VOLTAGES
DVDD18
DVDD18 Variation over Operating
Conditions 1
POWER CONSUMPTION
2× Mode
NCO OFF
NCO ON
2× Mode
NCO OFF
NCO ON
4× Mode
NCO OFF
NCO ON
4× Mode
NCO OFF
NCO ON
4× Mode
NCO OFF
NCO ON
4× Mode
NCO OFF
NCO ON
Test Conditions/Comments
Min
Typ
16
Max
±2.1
±3.7
With internal reference
Based on a 10 kΩ external resistor between FSADJ and AVSS
−0.001
−3.2
19.06
−1.0
0
+2
19.8
LSB
LSB
+0.001
+4.7
20.6
+1.0
10
Guaranteed
20
% FSR
% FSR
mA
V
MΩ
ns
0.04
100
30
1.17
Unit
Bits
ppm/°C
ppm/°C
ppm/°C
1.19
V
kΩ
5
3.13
1.7
3.3
1.8
3.47
1.9
V
V
1.7
−2.5%
1.8
1.9
+2.5%
V
V
fDAC = 737.28 MSPS
925
1217
mW
mW
1135
1520
mW
mW
852
1144
mW
mW
1040
1425
mW
mW
1230
1725
mW
mW
1405
1990
mW
mW
fDAC = 983.04 MSPS
fDAC = 737.28 MSPS
fDAC = 983.04 MSPS
fDAC = 1228.8 MSPS
fDAC = 1474.56 MSPS
Rev. A | Page 6 of 72
Data Sheet
Parameter
8× Mode
NCO OFF
NCO ON
Phase-Lock Loop (PLL)
Inverse Sinc
Reduced Power Mode (Power-Down)
AVDD33
CVDD18
DVDD18
OPERATING RANGE
1
AD9142A
Test Conditions/Comments
fDAC = 1600 MSPS
Min
Typ
Max
Unit
96.6
1.5
42.3
8.6
+85
mW
mW
mW
mW
mW
mA
mA
mA
°C
1350
1984
70
113
fDAC = 1474.56 MSPS
−40
+25
This term specifies the maximum allowable variation of DVDD18 over operating conditions compared with the DVDD18 presented to the device at the time the data
interface DLL is enabled.
Rev. A | Page 7 of 72
AD9142A
Data Sheet
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted.
Table 2.
Parameter
CMOS INPUT LOGIC LEVEL
Input
Logic High
Logic Low
CMOS OUTPUT LOGIC LEVEL
Output
Logic High
Logic Low
LVDS RECEIVER INPUTS
Input Voltage Range
Input Differential Threshold
Input Differential Hysteresis
Receiver Differential Input Impedance
DLL SPEED RANGE
DAC UPDATE RATE
DAC Adjusted Update Rate
DAC CLOCK INPUT (DACCLKP, DACCLKN)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
REFCLK/SYNCCLK INPUT (REFP/SYNCP, REFN/SYNCN)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
Input Clock Frequency
SERIAL PORT INTERFACE
Maximum Clock Rate
Minimum Pulse Width
High
Low
SDIO to SCLK Setup Time
SDIO to SCLK Hold Time
CS to SCLK Setup Time
CS to SCLK Hold Time
SDIO to SCLK Delay
Symbol
Min
DVDD18 = 1.8 V
DVDD18 = 1.8 V
1.2
DVDD18 = 1.8 V
DVDD18 = 1.8 V
Data, frame signal, and DCI inputs
1.4
VIA or VIB
VIDTH
VIDTHH to VIDTHL
RIN
Typ
825
−175
0.6
V
V
0.4
V
V
575
1600
575
500
1.25
2000
mV
V
100
500
1.25
2000
mV
V
MHz
1.03 GHz ≤ fVCO ≤ 2.07 GHz
SCLK
450
40
MHz
12.5
12.5
Wait time for valid output from
SDIO
Time for SDIO to relinquish the
output bus
1.5
0.68
2.38
9.6
11
Rev. A | Page 8 of 72
1.4
8.5
1.2
With 2 mA loading
With 2 mA loading
mV
mV
mV
Ω
MHz
MSPS
MSPS
100
Self biased input, ac-coupled
VIH
VIL
IIH
IIL
Unit
20
100
2× interpolation
tPWH
tPWL
tDS
tDH
tDCSB
tDCSB
tDV
Max
1675
+175
250
SDIO High-Z to CS
SDIO LOGIC LEVEL
Voltage Input High
Voltage Input Low
Voltage Output High
Voltage Output Low
Test Conditions/Comments
1.36
0
ns
ns
ns
ns
ns
ns
ns
ns
1.8
0
0.5
2
0.45
V
V
V
V
Data Sheet
AD9142A
DAC LATENCY SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, FIFO level is set to 4 (half of the FIFO depth), unless
otherwise noted.
Table 3.
Parameter
WORD INTERFACE MODE
2× Interpolation
4× Interpolation
8× Interpolation
BYTE INTERFACE MODE
2× Interpolation
4× Interpolation
8× Interpolation
INDIVIDUAL FUNCTION BLOCKS
Modulation
Fine
Coarse
Inverse Sinc
Phase Compensation
Gain Compensation
Test Conditions/Comments
Fine/coarse modulation, inverse sinc, gain/phase compensation off
Min
Typ
Max
134
244
481
DACCLK cycles
DACCLK cycles
DACCLK cycles
145
271
506
DACCLK cycles
DACCLK cycles
DACCLK cycles
17
10
20
12
16
DACCLK cycles
DACCLK cycles
DACCLK cycles
DACCLK cycles
DACCLK cycles
Fine/coarse modulation, inverse sinc, gain/phase compensation off
LATENCY VARIATION SPECIFICATIONS
Table 4.
Parameter
DAC LATENCY VARIATION 1
SYNC Off
SYNC On
1
Unit
Min
Typ
Max
Unit
1
0
2
1
DACCLK cycles
DACCLK cycles
DAC latency is defined as the elapsed time from a data sample clocked at the input to the AD9142A until the analog output begins to change.
Rev. A | Page 9 of 72
AD9142A
Data Sheet
AC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted.
Table 5.
Parameter
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fDAC = 737.28 MSPS
BW = 125 MHz
BW = 270 MHz
fDAC = 983.04 MSPS
BW = 360 MHz
fDAC = 1228.8 MSPS
BW = 200 MHz
BW = 500 MHz
fDAC = 1474.56 MSPS
BW = 737 MHz
BW = 400 MHz
TWO-TONE INTERMODULATION DISTORTION (IMD)
fDAC = 737.28 MSPS
fDAC = 983.04 MSPS
fDAC = 1228.8 MSPS
fDAC = 1474.56 MSPS
NOISE SPECTRAL DENSITY (NSD)
fDAC = 737.28 MSPS
fDAC = 983.04 MSPS
fDAC = 1228.8 MSPS
fDAC = 1474.56 MSPS
W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR)
fDAC = 983.04 MSPS
fDAC = 1228.8 MSPS
fDAC = 1474.56 MSPS
W-CDMA SECOND (ACLR)
fDAC = 983.04 MSPS
fDAC = 1228.8 MSPS
fDAC = 1474.56 MSPS
Test Conditions/Comments
−14 dBFS single tone
fOUT = 200 MHz
Min
Typ
Max
Unit
85
80
dBc
dBc
85
dBc
85
75
dBc
dBc
85
80
dBc
dBc
80
82
80
85
79
dBc
dBc
dBc
dBc
dBc
−160
−161.5
−164.5
−166
−162.5
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
dBm/Hz
81
83
80
81
80
dBc
dBc
dBc
dBc
dBc
85
86
86
86
85
dBc
dBc
dBc
dBc
dBc
fOUT = 200 MHz
fOUT = 280 MHz
fOUT = 10 MHz
fOUT = 280 MHz
−12 dBFS each tone
fOUT = 200 MHz
fOUT = 200 MHz
fOUT = 280 MHz
fOUT = 10 MHz
fOUT = 280 MHz
Eight-tone, 500 kHz tone spacing
fOUT = 200 MHz
fOUT = 200 MHz
fOUT = 280 MHz
fOUT = 10 MHz
fOUT = 280 MHz
Single carrier
fOUT = 200 MHz
fOUT = 20 MHz
fOUT = 280 MHz
fOUT = 20 MHz
fOUT = 280 MHz
Single carrier
fOUT = 200 MHz
fOUT = 20 MHz
fOUT = 280 MHz
fOUT = 20 MHz
fOUT = 280 MHz
OPERATING SPEED SPECIFICATIONS
Table 6.
Interpolation
Factor
2×
4×
8×
DVDD18, CVDD18 = 1.8 V ± 5%
fDCI (MSPS)
fDAC (MSPS)
Maximum
Maximum
575
1150
350
1400
175
1400
DVDD18, CVDD18 = 1.9 V ± 5%
or 1.8 V ± 2%
fDCI (MSPS)
fDAC (MSPS)
Maximum
Maximum
575
1150
375
1500
187.5
1500
Rev. A | Page 10 of 72
DVDD18, CVDD18 = 1.9 V ± 2%
fDCI (MSPS)
fDAC (MSPS)
Maximum
Maximum
575
1150
400
1600
200
1600
Data Sheet
AD9142A
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 7.
Parameter
AVDD33 to GND
DVDD18, CVDD18 to GND
FSADJ, VREF, IOUT1P, IOUT1N, IOUT2P,
IOUT2N to GND
D15P to D0P, D15N to D0N,
FRAMEP/PARITYP, FRAMEN/PARITYN,
DCIP, DCIN to GND
DACCLKP, DACCLKN, REFP, SYNCP,
REFN, SYNCN to GND
RESET, IRQ1, IRQ2, CS, SCLK, SDIO
to GND
Junction Temperature
Storage Temperature Range
Rating
−0.3 V to +3.6 V
−0.3 V to +2.1 V
−0.3 V to AVDD33 + 0.3 V
−0.3 V to DVDD18 + 0.3 V
−0.3 V to CVDD18 + 0.3 V
The exposed pad (EPAD) must be soldered to the ground plane
(AVSS) for the 72-lead LFCSP. The EPAD provides an electrical,
thermal, and mechanical connection to the board.
Typical θJA, θJB, and θJC values are specified for a 4-layer board in
still air. Airflow increases heat dissipation, effectively reducing
θJA and θJB.
Table 8. Thermal Resistance
−0.3 V to DVDD18 + 0.3 V
Package
72-Lead LFCSP
125°C
−65°C to +150°C
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. A | Page 11 of 72
θJA
20.7
θJB
10.9
θJC
1.1
Unit
°C/W
Conditions
EPAD soldered
to ground plane
AD9142A
Data Sheet
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
CVDD18
CVDD18
VREF
FSADJ
AVDD33
IOUT1P
IOUT1N
AVDD33
CVDD18
CVDD18
DACCLKP
DACCLKN
CVDD18
CVDD18
AVDD33
IOUT2N
IOUT2P
AVDD33
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
AD9142A
TOP VIEW
(Not to Scale)
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
CS
SCLK
SDIO
IRQ1
IRQ2
DVDD18
DVDD18
D0N
D0P
D1N
D1P
DVDD18
D2N
D2P
D3N
D3P
D4N
D4P
NOTES
1. EXPOSED PAD (EPAD) MUST BE SOLDERED TO THE GROUND
PLANE (AVSS, DVSS, CVSS). THE EPAD PROVIDES AN ELECTRICAL, THERMAL, AND MECHANICAL CONNECTION TO THE BOARD.
11901-002
DVDD18
D11P
D11N
D10P
D10N
D9P
D9N
D8P
D8N
DCIP
DCIN
D7P
D7N
D6P
D6N
D5P
D5N
DVDD18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CVDD18
REFP/SYNCP
REFN/SYNCN
CVDD18
RESET
TXEN
DVDD18
FRAMEP/PARITYP
FRAMEN/PARITYN
D15P
D15N
DVDD18
D14P
D14N
D13P
D13N
D12P
D12N
Figure 2. Pin Configuration
Table 9. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
Mnemonic
CVDD18
REFP/SYNCP
REFN/SYNCN
CVDD18
RESET
TXEN
7
DVDD18
8
9
10
11
12
FRAMEP/PARITYP
FRAMEN/PARITYN
D15P
D15N
DVDD18
13
14
15
16
17
18
19
D14P
D14N
D13P
D13N
D12P
D12N
DVDD18
20
21
22
23
D11P
D11N
D10P
D10N
Description
1.8 V PLL Supply. CVDD18 supplies the clock receivers, clock multiplier, and clock distribution.
PLL Reference Clock/Synchronization Clock Input, Positive.
PLL Reference Clock/Synchronization Clock Input, Negative.
1.8 V PLL Supply. CVDD18 supplies the clock receivers, clock multiplier, and clock distribution.
Reset, Active Low. CMOS levels with respect to DVDD18. Recommended reset pulse length is 1 µs.
Active High Transmit Path Enable. CMOS levels with respect to DVDD18. A low level on this pin triggers
three selectable actions in the DAC. See Table 87 for details.
1.8 V Digital Supply. Pin 7 supplies power to the digital core, digital data ports, serial port input/output
pins, RESET, IRQ1, and IRQ2.
Frame/Parity Input, Positive.
Frame/Parity Input, Negative.
Data Bit 15 (MSB), Positive.
Data Bit 15 (MSB), Negative.
1.8 V Digital Supply. Pin 12 supplies the power to the digital core and digital data ports, serial port
input/output pins, RESET, IRQ1, and IRQ2.
Data Bit 14, Positive.
Data Bit 14, Negative.
Data Bit 13, Positive.
Data Bit 13, Negative.
Data Bit 12, Positive.
Data Bit 12, Negative.
1.8 V Digital Supply. Pin 19 supplies power to the digital core, digital data ports, serial port input/output
pins, RESET, IRQ1, and IRQ2.
Data Bit 11, Positive.
Data Bit 11, Negative.
Data Bit 10, Positive.
Data Bit 10, Negative.
Rev. A | Page 12 of 72
Data Sheet
Pin No.
24
25
26
27
28
29
30
31
32
33
34
35
36
Mnemonic
D9P
D9N
D8P
D8N
DCIP
DCIN
D7P
D7N
D6P
D6N
D5P
D5N
DVDD18
37
38
39
40
41
42
43
D4P
D4N
D3P
D3N
D2P
D2N
DVDD18
44
45
46
47
48
D1P
D1N
D0P
D0N
DVDD18
49
DVDD18
50
IRQ2
51
IRQ1
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
SDIO
SCLK
CS
AVDD33
IOUT2P
IOUT2N
AVDD33
CVDD18
CVDD18
DACCLKN
DACCLKP
CVDD18
CVDD18
AVDD33
IOUT1N
IOUT1P
AVDD33
FSADJ
VREF
AD9142A
Description
Data Bit 9, Positive.
Data Bit 9, Negative.
Data Bit 8, Positive.
Data Bit 8, Negative.
Data Clock Input, Positive.
Data Clock Input, Negative.
Data Bit 7, Positive.
Data Bit 7, Negative.
Data Bit 6, Positive.
Data Bit 6, Negative.
Data Bit 5, Positive.
Data Bit 5, Negative.
1.8 V Digital Supply. Pin 36 supplies power to the digital core, digital data ports, serial port input/output
pins, RESET, IRQ1, and IRQ2.
Data Bit 4, Positive.
Data Bit 4, Negative.
Data Bit 3, Positive.
Data Bit 3, Negative.
Data Bit 2, Positive.
Data Bit 2, Negative.
1.8 V Digital Supply. Pin 43 supplies power to the digital core, digital data ports, serial port input/output
pins, RESET, IRQ1, and IRQ2.
Data Bit 1, Positive.
Data Bit 1, Negative.
Data Bit 0, Positive.
Data Bit 0, Negative.
1.8 V Digital Supply. Pin 48 supplies power to the digital core, digital data ports, serial port input/output
pins, RESET, IRQ1, and IRQ2.
1.8 V Digital Supply. Pin 49 supplies power to the digital core, digital data ports, serial port input/output
pins, RESET, IRQ1, and IRQ2.
Second Interrupt Request. Open-drain, active low output. Connect an external pull-up to DVDD18
through a 10 kΩ resistor.
First Interrupt Request. Open-drain, active low output. Connect an external pull-up to DVDD18 through
a 10 kΩ resistor.
Serial Port Data Input/Output. CMOS levels with respect to DVDD18.
Serial Port Clock Input. CMOS levels with respect to DVDD18.
Serial Port Chip Select. Active low (CMOS levels with respect to DVDD18).
3.3 V Analog Supply.
QDAC Positive Current Output.
QDAC Negative Current Output.
3.3 V Analog Supply.
1.8 V Clock Supply. Supplies clock receivers and clock distribution.
1.8 V Clock Supply. Supplies clock receivers and clock distribution.
DAC Clock Input, Negative.
DAC Clock Input, Positive.
1.8 V Clock Supply. Supplies clock receivers and clock distribution.
1.8 V Clock Supply. Supplies clock receivers and clock distribution.
3.3 V Analog Supply.
IDAC Negative Current Output.
IDAC Positive Current Output.
3.3 V Analog Supply.
Full-Scale Current Output Adjust. Place a 10 kΩ resistor from this pin to GND.
Voltage Reference. Nominally 1.2 V output. Decouple VREF to GND.
Rev. A | Page 13 of 72
AD9142A
Pin No.
71
72
Mnemonic
CVDD18
CVDD18
EPAD
Data Sheet
Description
1.8 V Clock Supply. Pin 71 supplies the clock receivers, clock multiplier, and clock distribution.
1.8 V Clock Supply. Pin 72 supplies the clock receivers, clock multiplier, and clock distribution.
Exposed Pad. The exposed pad (EPAD) must be soldered to the ground plane (AVSS, DVSS, CVSS). The
EPAD provides an electrical, thermal, and mechanical connection to the board.
Rev. A | Page 14 of 72
Data Sheet
AD9142A
TYPICAL PERFORMANCE CHARACTERISTICS
0
–60
fDAC = 737.28MHz
fDAC = 983.04MHz
fDAC = 1228.8MHz
fDAC = 1474.56MHz
–10
–65
IN-BAND SFDR (dBc)
–20
–30
SFDR (dBc)
BW
BW
BW
BW
–40
–50
–60
= 80MHz, –6dBFS
= 80MHz, –12dBFS
= 300MHz, –6dBFS
= 300MHz, –12dBFS
–70
–75
–80
–70
–85
–80
100
200
300
400
500
600
700
800
fOUT (MHz)
11901-003
0
< –85
Figure 3. Single Tone (0 dBFS) SFDR vs. fOUT in the First Nyquist Zone over fDAC
0
–60
IN-BAND SFDR (dBc)
–40
–50
–60
–70
–80
100
120
140
160
180
200
= 80MHz, –6dBFS
= 80MHz, –12dBFS
= 300MHz, –6dBFS
= 300MHz, –12dBFS
–70
–75
–80
–85
0
100
200
300
400
500
600
700
800
fOUT (MHz)
< –85
11901-005
–100
Figure 4. Single Tone Second Harmonic vs. fOUT in the First Nyquist Zone
over Digital Back Off, fDAC = 1474.56 MHz
0
–60
BW
BW
BW
BW
–65
IN-BAND SFDR (dBc)
–30
–40
–50
–60
–70
150
200
250
300
Figure 7. In-Band, Single Tone SFDR (Excluding Second Harmonic) vs. fOUT in
80 MHz and 300 MHz BW, fDAC = 983.04 MHz
0dBFS
–6dBFS
–12dBFS
–16dBFS
–20
100
fOUT (MHz)
0
–10
50
11901-006
–85 MEANS ≤ –85
–90
THIRD HARMONIC (dBc)
80
–80
= 80MHz, –6dBFS
= 80MHz, –12dBFS
= 300MHz, –6dBFS
= 300MHz, –12dBFS
–70
–75
–80
–85
–85 MEANS ≤ –85
–90
0
100
200
300
400
fOUT (MHz)
500
600
700
800
< –85
11901-007
–100
Figure 5. Single Tone Third Harmonic vs. fOUT in the First Nyquist Zone
over Digital Back Off, fDAC = 1474.56 MHz
0
50
100
150
200
fOUT (MHz)
250
300
350
11901-008
SECOND HARMONIC (dBc)
BW
BW
BW
BW
–65
–30
60
Figure 6. In-Band, Single Tone SFDR (Excluding Second Harmonic) vs. fOUT in
80 MHz and 300 MHz Bandwidths, fDAC = 737.28 MHz
0dBFS
–6dBFS
–12dBFS
–16dBFS
–20
40
fOUT (MHz)
0
–10
20
11901-004
–85 MEANS ≤ –85
–90
Figure 8. In-Band, Single Tone SFDR (Excluding Second Harmonic) vs. fOUT in
80 MHz and 300 MHz Bandwidths, fDAC = 1228.8 MHz
Rev. A | Page 15 of 72
AD9142A
–60
BW
BW
BW
BW
–65
0
= 80MHz, –6dBFS
= 80MHz, –12dBFS
= 300MHz, –6dBFS
= 300MHz, –12dBFS
0.6MHz TONE SPACING
16MHz TONE SPACING
35MHz TONE SPACING
–20
–70
–40
IMD (dBc)
IN-BAND SFDR (dBc)
Data Sheet
–75
–80
–60
–80
–85
–100
0
50
100
150
200
250
300
350
fOUT (MHz)
–120
11901-009
< –85
0
–20
300
400
500
600
700
800
Figure 12. Two Tone, Third IMD vs. fOUT over Tone Spacing,
fDAC = 1474.56 MHz
–152
fDAC = 737.28MHz
fDAC = 983.04MHz
fDAC = 1228.8MHz
fDAC = 1474.56MHz
–10
200
fOUT (MHz)
Figure 9. In-Band, Single Tone SFDR (Excluding Second Harmonic) vs. fOUT in
80 MHz and 300 MHz Bandwidths, fDAC = 1474.56 MHz
0
100
11901-010
–85 MEANS ≤ –85
fDAC = 737.28MHz
fDAC = 983.04MHz
fDAC = 1228.8MHz
fDAC = 1474.56MHz
–154
–156
NSD (dBm/Hz)
IMD (dBc)
–30
–40
–50
–158
–160
–162
–60
–164
–70
–166
–80
–90
300
400
500
600
700
800
fOUT (MHz)
0
300
400
500
600
700
800
800
Figure 13. Single Tone (0 dBFS) NSD vs. fOUT over fDAC
–152
0dBFS
–6dBFS
–9dBFS
–20
200
fOUT (MHz)
Figure 10. Two Tone, Third IMD vs. fOUT over fDAC
0
100
11901-012
200
11901-014
100
11901-011
–168
0
0dBFS
–6dBFS
–12dBFS
–16dBFS
–154
–156
NSD (dBm/Hz)
–60
–158
–160
–162
–80
–164
–100
–166
–168
–120
0
100
200
300
400
500
600
700
800
fOUT (MHz)
11901-013
IMD (dBc)
–40
0
100
200
300
400
500
600
700
fOUT (MHz)
Figure 14. Single Tone NSD vs. fOUT over Digital Back Off,
fDAC = 1474.56 MHz
Figure 11. Two Tone, Third IMD vs. fOUT over Digital Back Off,
fDAC = 1474.56 MHz
Rev. A | Page 16 of 72
Data Sheet
–150
AD9142A
–60
737.2MHz
983.04MHz
1228.8MHz
1474.56MHz
–152
–154
–65
–156
–70
–158
ACLR (dBc)
NSD (dBm/Hz)
fDAC = 1474.56MHz, PLL OFF, 0dBFS
fDAC = 1474.56MHz, PLL ON, 0dBFS
fDAC = 1228.8MHz, PLL OFF, 0dBFS
fDAC = 1228.8MHz, PLL ON, 0dBFS
–160
–162
–75
–80
–164
–166
–85
0
100
200
300
400
500
600
700
800
fOUT (MHz)
Figure 15. 1C WCDMA NSD vs. fOUT, over fDAC
–150
–90
11901-200
–170
0
100
200
300
400
500
600
700
fOUT (MHz)
800
11901-101
–168
Figure 18. 1C WCDMA, Second Adjacent ACLR vs. fOUT, PLL On and Off
PLL OFF
PLL ON
–152
–154
NSD (dBm/Hz)
–156
–158
–160
–162
–164
0
100
200
300
400
500
600
700
800
fOUT (MHz)
11901-015
–168
11901-016
–166
Figure 16. Single Tone NSD vs. fOUT, fDAC = 1474.28 MHz, PLL On and Off
–60
fDAC = 1474.56MHz, PLL OFF, 0dBFS
fDAC = 1474.56MHz, PLL ON, 0dBFS
fDAC = 1228.8MHz, PLL OFF, 0dBFS
fDAC = 1228.8MHz, PLL ON, 0dBFS
–65
–70
–75
–85
0
100
200
300
400
500
600
700
800
fOUT (MHz)
Figure 17. 1C WCDMA, First Adjacent ACLR vs. fOUT, PLL On and Off
11901-017
–80
11901-100
ACLR (dBc)
Figure 19. Two Tone, Third IMD Performance,
IF = 280 MHz, fDAC = 1474.28 MHz
Figure 20. 1C WCDMA ACLR Performance, IF = 280 MHz, fDAC = 1474.28 MHz
Rev. A | Page 17 of 72
Data Sheet
Figure 21. Single Tone fDAC = 1474.56 MHz,
fOUT = 280 MHz, −14 dBFS
1600
1400
2×
4×
8×
1200
1000
800
600
400
200
400
600
800
1000
1200
1400
1600
fDAC (MHz)
11901-021
11901-018
TOTAL BASELINE POWER CONSUMPTION (mW)
AD9142A
Figure 24. Total Power Baseline Consumption vs. fDAC over Interpolation
600
DVDD SUPPLY CURRENT (mA)
500
2×
4×
8×
400
300
200
11901-019
0
200
400
600
800
1000
1200
1400
1600
fDAC (MHz)
11901-024
100
Figure 25. DVDD18 Supply Current vs. fDAC over Interpolation
Figure 22. 4C WCDMA ACLR Performance,
IF = 280 MHz, fDAC = 1474.28 MHz
350
DVDD18 SUPPLY CURRENT (mA)
300
NCO
INVERSE SINC
DIGITAL GAIN AND PHASE
fS/4 MODULATION
250
200
150
100
Figure 23. Single Tone SFDR fDAC = 1474.56 MHz,
4× Interpolation, fOUT = 10 MHz, −14 dBFS
0
200
400
600
800
1000
1200
1400
1600
fDAC (MHz)
Figure 26. DVDD18 Supply Current vs. fDAC over Digital Functions
Rev. A | Page 18 of 72
11901-022
11901-020
50
Data Sheet
CVDD18, PLL ON
CVDD18, PLL OFF
AVDD33
200
150
100
50
200
400
600
800
1000
1200
1400
fDAC (MHz)
1600
11901-023
SUPPLY CURRENT (mA)
250
AD9142A
Figure 27. CVDD18, AVDD33 Supply Current vs. fDAC
Rev. A | Page 19 of 72
AD9142A
Data Sheet
TERMINOLOGY
Integral Nonlinearity (INL)
INL is the maximum deviation of the actual analog output from
the ideal output, determined by a straight line drawn from zero
scale to full scale.
Settling Time
Settling time is the time required for the output to reach and
remain within a specified error band around its final value,
measured from the start of the output transition.
Differential Nonlinearity (DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels, between the peak amplitude
of the output signal and the peak spurious signal within the dc
to Nyquist frequency of the DAC. Typically, the interpolation
filters reject energy in this band. This specification, therefore,
defines how well the interpolation filters work and the effect of
other parasitic coupling paths on the DAC output.
Offset Error
Offset error is the deviation of the output current from the ideal
of 0 mA. For IOUT1P, 0 mA output is expected when all inputs
are set to 0. For IOUT1N, 0 mA output is expected when all
inputs are set to 1.
Gain Error
Gain error is the difference between the actual and ideal output
span. The actual span is determined by the difference between
the output when all inputs are set to 1 and the output when all
inputs are set to 0.
Output Compliance Range
The output compliance range is the range of allowable voltage
at the output of a current output DAC. Operation beyond the
maximum compliance limits can cause either output stage
saturation or breakdown, resulting in nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from
the ambient (25°C) value to the value at either TMIN or TMAX.
For offset and gain drift, the drift is reported in ppm of fullscale range (FSR) per degree Celsius. For reference drift, the
drift is reported in ppm per degree Celsius.
Power Supply Rejection (PSR)
PSR is the maximum change in the full-scale output as the
supplies are varied from minimum to maximum specified
voltages.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in decibels.
Interpolation Filter
If the digital inputs to the DAC are sampled at a multiple rate of
fDATA (interpolation rate), a digital filter can be constructed that
has a sharp transition band near fDATA/2. Images that typically
appear around fDAC (output data rate) can be greatly suppressed.
Adjacent Channel Leakage Ratio (ACLR)
ACLR is the ratio in decibels relative to the carrier (dBc) between
the measured power within a channel relative to its adjacent
channel.
Complex Image Rejection
In a traditional two-part upconversion, two images are created
around the second IF frequency. These images have the effect
of wasting transmitter power and system bandwidth. By placing
the real part of a second complex modulator in series with the
first complex modulator, either the upper or lower frequency
image near the second IF can be rejected.
Rev. A | Page 20 of 72
Data Sheet
AD9142A
SERIAL PORT OPERATION
54 CS
SPI
PORT 53 SCLK
52 SDIO
11901-025
The serial port is a flexible, synchronous serial communications
port that allows easy interfacing to many industry standard microcontrollers and microprocessors. The serial I/O is compatible
with most synchronous transfer formats, including both the
Motorola® SPI and Intel® SSR protocols. The interface allows
read/write access to all registers that configure the AD9142A.
MSB-first or LSB-first transfer formats are supported. The serial
port interface is a 3-wire only interface. The input and output
share a single pin input/output (SDIO).
SERIAL PORT PIN DESCRIPTIONS
Serial Clock (SCLK)
The serial clock pin synchronizes data to and from the device
and runs the internal state machines. The maximum frequency
of SCLK is 40 MHz. All data input is registered on the rising edge
of SCLK. All data is driven out on the falling edge of SCLK.
Chip Select (CS)
Figure 28. Serial Port Interface Pins
There are two phases to a communication cycle with the AD9142A.
Phase 1 is the instruction cycle (the writing of an instruction
byte into the device), coincident with the first 16 SCLK rising
edges. The instruction word provides the serial port controller
with information regarding the data transfer cycle, Phase 2, of
the communication cycle. The Phase 1 instruction word defines
whether the upcoming data transfer is a read or write, along with
the starting register address for the next data transfer in the
cycle.
A logic high on the CS pin, followed by a logic low, resets the
serial port timing to the initial state of the instruction cycle.
From this state, the next 16 rising SCLK edges represent the
instruction bits of the current I/O operation.
The remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the device and
the system controller. Phase 2 of the communication cycle is a
transfer of one data byte. Registers change immediately upon
writing to the last bit of each transfer byte, except for the frequency
tuning word and NCO phase offsets, which change only when
the frequency tuning word (FTW) update bit is set.
DATA FORMAT
The instruction byte contains the information shown in Table 10.
Table 10. Serial Port Instruction Word
I15 (MSB)
R/W
A14 to A0 (Bit 14 to Bit 0 of the instruction word) determine
the register that is accessed during the data transfer portion of
the communication cycle. For multibyte transfers, A14 is the
starting address; the device generates the remaining register
addresses based on the SPI_LSB_FIRST bit.
I[14:0]
A[14:0]
R/W (Bit 15 of the instruction word) determines whether a read
or a write data transfer occurs after the instruction word write.
Logic 1 indicates a read operation and Logic 0 indicates a write
operation.
CS is an active low input that starts and gates a communication
cycle. It allows more than one device to be used on the same serial
communications line. The SDIO pins enter a high impedance
state when the CS input is high. During the communication
cycle, CS should stay low.
Serial Data I/O (SDIO)
The SDIO pin is a bidirectional data line.
SERIAL PORT OPTIONS
The serial port can support both MSB-first and LSB-first data
formats. This functionality is controlled by the SPI_LSB_FIRST bit
(Register 0x00, Bit 6). The default is MSB first (LSB_FIRST = 0).
When SPI_LSB_FIRST = 0 (MSB first), the instruction and data
bits must be written from MSB to LSB. Multibyte data transfers
in MSB-first format start with an instruction word that includes the
register address of the most significant data byte. Subsequent data
bytes must follow from high address to low address. In MSB-first
mode, the serial port internal word address generator decrements
for each data byte of the multibyte communication cycle.
When SPI_LSB_FIRST = 1 (LSB first), the instruction and data
bits must be written from LSB to MSB. Multibyte data transfers
in LSB-first format start with an instruction word that includes the
register address of the least significant data byte. Subsequent data
bytes must follow from low address to high address. In LSB-first
mode, the serial port internal word address generator increments
for each data byte of the multibyte communication cycle.
If the MSB-first mode is active, the serial port controller data
address decrements from the data address written toward 0x00
for multibyte I/O operations. If the LSB-first mode is active, the
serial port controller data address increments from the data
address written toward 0xFF for multibyte I/O operations.
Rev. A | Page 21 of 72
AD9142A
Data Sheet
tDCSB
INSTRUCTION CYCLE
tSCLK
DATA TRANSFER CYCLE
CS
CS
tPWH
SCLK
R/W A14 A13
A3
A2 A1
A0 D7N D6N D5N
D30 D20 D10 D00
tDS
SDIO
INSTRUCTION BIT 14
Figure 31. Timing Diagram for Serial Port Register Write
Figure 29. Serial Register Interface Timing, MSB First
INSTRUCTION CYCLE
tDH
INSTRUCTION BIT 15
11901-028
SCLK
11901-026
SDIO
tPWL
CS
DATA TRANSFER CYCLE
CS
A0
A1
A2
A12 A13 A14 R/W D00 D10 D20
D4N D5N D6N D7N
11901-027
SDIO
tDV
SDIO
DATA BIT n
DATA BIT n – 1
Figure 32. Timing Diagram for Serial Port Register Read
Figure 30. Serial Register Interface Timing, LSB First
Rev. A | Page 22 of 72
11901-029
SCLK
SCLK
Data Sheet
AD9142A
DATA INTERFACE
LVDS INPUT DATA PORTS
Table 12. Data Interface Configuration Options
The AD9142A has a 16-bit LVDS bus that accepts 16-bit I and
Q data either in word (16-bit) or byte (8-bit) formats. In the
word interface mode, the data is sent over the entire 16-bit data
bus. In the byte interface mode, the data is sent over the lower
8-bit (D7 to D0) LVDS bus. Table 11 lists the pin assignment of
the bus and the SPI register configuration for each mode.
Register 0x26
DATA_FORMAT (Bit 7)
DATA_PAIRING (Bit 6)
DATA_BUS_INVERT (Bit 5)
Table 11. LVDS Input Data Modes
Interface Mode
Word
Byte
Pin Assignment
D15 to D0
D7 to D0
SPI Register Configuration
Register 0x26, Bit 0 = 0
Register 0x26, Bit 0 = 1
WORD INTERFACE MODE
In word interface mode, the digital clock input (DCI) signal is a
reference bit that generates a double data rate (DDR) data
sampling clock. Time align the DCI signal with the data. The
IDAC data follows the rising edge of the DCI, and the QDAC
data follows the falling edge of the DCI, as shown in Figure 33.
WORD INTERFACE MODE
I0
Q0
I1
Q1
11901-030
INPUT DATA[15:0]
DCI
Figure 33. Timing Diagram for Word Interface Mode
BYTE INTERFACE MODE
In byte interface mode, the required sequence of the input data
stream is I[15:8], I[7:0], Q[15:8], Q[7:0]. A frame signal is
required to align the order of input data bytes properly. Time
align both the DCI signal and frame signal with the data. The
rising edge of the frame indicates the start of the sequence. The
frame can be either a one shot or periodical signal as long as its
first rising edge is correctly captured by the device. For a one
shot frame, the frame pulse must be held at high for at least one
DCI cycle. For a periodical frame, the frequency needs to be
fDCI/(2 × n)
Figure 34 is an example of signal timing in byte mode.
BYTE INTERFACE MODE
I0[15:8]
I0[7:0]
Q0[15:8]
Q0[7:0]
Figure 34. Timing Diagram for Byte Interface Mode
DATA INTERFACE CONFIGURATION OPTIONS
To provide more flexibility for the data interface, some
additional options are listed in Table 12.
11901-031
DCI
FRAME
DLL INTERFACE MODE
A source synchronous LVDS interface is used between the data
host and AD9142A to achieve high data rates while simplifying
the interface. The FPGA or ASIC feeds the AD9142A with 16-bit
input data. Along with the input data, the FPGA or ASIC
provides a DDR (double data rate) data clock input (DCI).
A delay locked loop (DLL) circuit designed to operate with DCI
clock rates between 250 and 575 MHz is used to generate a phaseshifted version of the DCI, called DSC (data sampling clock), to
register the input data on both the rising and falling edges.
As shown in Figure 35, the DCI clock edges must be coincident
with the data bit transitions with minimum skew and jitter. The
nominal sampling point of the input data occurs in the middle
of the DCI clock edges because this point corresponds to the
center of the data eye. This is also equivalent to a nominal phase
shift of 90°of the DCI clock.
The data timing requirements are defined by a data valid
window (DVW) that is dependent on the data clock input skew,
input data jitter, and the variations of the DLL delay line across
delay settings. The DVW is defined as
DVW = tDATA PERIOD − tDATA SKEW – tDATA JITTER
The available margin for data interface timing is given by
tMARGIN = DVW − (tS + tH)
The difference between the setup and hold times, which is also
called the keep out window, or KOW, is the area where data
transitions should not happen. The timing margin allows
tuning of the DLL delay setting by the user, see Figure 36.
where n is a positive integer, that is, 1, 2, 3, …
INPUT DATA[7:0]
Description
Select between binary and twos
complement formats.
Indicate I/Q data pairing on data input.
This allows the I and Q data that is
received to be paired in various ways.
Swaps the bit order of the data input
port. Remaps the input data from
D[15:0] to D[0:15].
From the figure, it can be seen that the ideal location for the
DSC signal is 90° out of phase from the DCI input. However,
due to skew of the DCI relative to the data, it may be necessary
to change the DSC phase offset to sample the data at the center
of its eye diagram. The sampling instance can be varied in discrete
increments by offsetting the nominal DLL phase shift value of
90° via Register 0x0A, Bits[3:0]. This register is a signed value.
The MSB is the sign and the LSBs are the magnitude. The
following equation defines the phase offset relationship:
Phase Offset = 90° ± n × 11.25°, |n| < 7
where n is the DLL phase offset setting.
Rev. A | Page 23 of 72
AD9142A
Data Sheet
Table 13. DLL Phase Setup and Hold Times (Guaranteed)
Figure 35 shows the DSC setup and hold times with respect to
the DCI signal and data signals.
Frequency,
fDCI (MHz)
307
DATA
DCI
368
11901-135
DSC
tS
tH
491
Time (ps)
tS
tH
tS
tH
tS
tH
Data Port Setup and Hold Times (ps)
at DLL Phase
−3
0
+3
−125
−385
−695
834
1120
1417
−70
−305
−534
753
967
1207
−81
−245
−402
601
762
928
Figure 35. LVDS Data Port Setup and Hold Times
Table 13 lists the values that are guaranteed over the operating
conditions. These values were taken with a 50% duty cycle and a
DCI swing of 450 mV p-p. For best performance, the duty cycle
variation should be kept below ±5%, and the DCI input should
be as high as possible, up to 1200 mV p-p.
tDATA JITTER
tH
tS
INPUT DATA
DATA EYE
tDATA PERIOD
DCI
DATA SAMPLE CLOCK
tDATA JITTER
tDCI SKEW
INPUT DATA
DLL PHASE
DELAY
tH AND tS
DATA EYE
tDATA PERIOD
11901-037
DCI
DATA SAMPLE CLOCK
Figure 36. LVDS Data Port Timing Requirements
Rev. A | Page 24 of 72
Data Sheet
AD9142A
Table 14. DLL Phase Setup and Hold Times (Typical)
Frequency,
fDCI 1 (MHz)
250
275
300
325
350
375
400
425
450
475
500
525
550
575
1
Time
(ps)
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
−6
−93
468
−87
451
−82
422
−46
405
−23
383
−7
401
−46
385
4
358
11
354
−15
355
9
313
−7
311
−5
300
8
312
−5
−196
579
−172
537
−166
500
−114
483
−92
451
−82
466
−98
445
−52
408
−34
406
−51
399
−28
354
−52
356
−39
340
−28
348
−4
−312
707
−264
646
−256
598
−190
563
−180
524
−150
504
−161
503
−110
465
−92
457
−95
451
−77
399
−100
395
−74
378
−66
379
−3
−416
825
−364
757
−341
703
−271
647
−252
607
−225
569
−243
546
−170
524
−147
516
−147
499
−128
445
−147
438
−107
423
−102
414
Data Port Setup and Hold Times (ps) at DLL Phase
−2
−1
0
+1
+2
+3
−530 −658
−770
−878
−983
−1093
947
1067
1188
1315
1442
1570
−464 −556
−653
−756
−859
−956
878
977
1092
1218
1311
1423
−426 −515
−622
−715
−809
−900
803
897
1000
1105
1203
1303
−358 −447
−538
−612
−706
−806
740
832
914
1000
1100
1200
−328 −409
−491
−574
−654
−731
682
762
844
930
1011
1097
−315 −391
−461
−526
−595
−661
641
718
783
863
941
1025
−303 −384
−448
−513
−578
−643
604
674
748
826
890
965
−229 −297
−394
−449
−517
−579
595
625
692
762
829
900
−209 −269
−324
−386
−446
−509
573
637
693
731
792
852
−198 −255
−313
−366
−425
−480
556
613
675
727
779
815
−183 −233
−288
−333
−390
−438
500
555
615
668
726
783
−187 −237
−285
−335
−387
−436
489
537
592
645
692
746
−147 −192
−249
−302
−352
−397
468
510
560
610
659
710
−143 −181
−245
−280
−336
−366
453
496
544
599
654
708
+4
−1193
1697
−1053
1537
−1001
1411
−891
1292
−819
1186
−726
1106
−713
1039
−641
966
−564
917
−530
873
−495
825
−483
799
−440
756
−406
759
+5
−1289
1777
−1151
1653
−1097
1522
−966
1380
−889
1277
−786
1187
−771
1110
−704
1032
−622
983
−585
930
−545
881
−530
850
−486
810
−443
806
+6
−1412
1876
−1251
1728
−1184
1612
−1044
1476
−959
1358
−853
1264
−833
1178
−752
1097
−672
1042
−640
988
−594
934
−581
909
−529
865
−488
847
Table 14 shows characterization data for selected fDCI frequencies. Other frequencies are possible, and Table 14 can be used to estimate performance.
Table 14 shows the typical times for various DCI clock frequencies
that are required to calculate the data valid margin. The amount
of margin that is available for tuning of the DSC sampling point
can be determined using Table 14.
Maximizing the opening of the eye in both the DCI and data signals
improves the reliability of the data port interface. Differential
controlled impedance traces of equal length (that is, delay) should
be used between the host processor and the AD9142A input. To
ensure coincident transitions with the data bits, the DCI signal
should be implemented as an additional data line with an
alternating (010101…) bit sequence from the same output
drivers used for the data.
The DCI signal is ac-coupled by default; thus, removing the DCI
signal may cause DAC output chatter due to randomness on the
DCI input. To avoid this, it is recommended that the DAC output is
disabled whenever the DCI signal is not present. To do this,
program the DAC output current power down bit in Register 0x01,
Bit 7 and Bit 6 to 1. When the DCI signal is again present, the DAC
output can be enabled by setting Register 0x01, Bit 7 and Bit 6 to 0.
Register 0x0D optimizes the DLL stability over the operating
frequency range. Table 15 shows the recommended setting.
Table 15. DLL Configuration Options
DCI Speed
≥350 MHz