AD9144BCPZ

Quad, 16-Bit, 2.8 GSPS, TxDAC+® Digital-to-Analog Converter AD9144 Data Sheet FEATURES TYPICAL APPLICATION CIRCUIT Supports input data rate >1 GSPS Proprietary low spurious and distortion design 6-carrier GSM IMD = 77 dBc at 75 MHz IF SFDR = 82 dBc at dc IF, −9 dBFS Flexible 8-lane JESD204B interface Support quad or dual DAC mode at 2.8 GSPS Multiple chip synchronization Fixed latency Data generator latency compensation Selectable 1×, 2×, 4×, 8× interpolation filter Low power architecture Input signal power detection Emergency stop for downstream analog circuitry protection Transmit enable function allows extra power saving High performance, low noise phase-locked loop (PLL) clock multiplier Digital inverse sinc filter Low power: 1.6 W at 1.6 GSPS, 1.7 W at 2.0 GSPS, full operating conditions 88-lead LFCSP with exposed pad QUAD MOD ADRF6720 LPF DAC 0°/90° PHASE SHIFTER JESD204B SYNCOUTx± SYSREF± DAC AD9144 LO_IN MOD_SPI QUAD MOD ADRF6720 QUAD DAC LPF DAC 0°/90° PHASE SHIFTER JESD204B SYNCOUTx± LO_IN MOD_SPI CLK± DAC SPI 11675-001 DAC Figure 1. APPLICATIONS Wireless communications 3G/4G W-CDMA base stations Wideband repeaters Software defined radios Wideband communications Point-to-point Local multipoint distribution service (LMDS) and multichannel multipoint distribution service (MMDS) Transmit diversity, multiple input/multiple output (MIMO) Instrumentation Automated test equipment PRODUCT HIGHLIGHTS 1. GENERAL DESCRIPTION The AD9144 is a quad, 16-bit, high dynamic range digital-toanalog converter (DAC) that provides a maximum sample rate of 2.8 GSPS, permitting a multicarrier generation up to the Nyquist frequency. The DAC outputs are optimized to interface seamlessly with the ADRF6720 analog quadrature modulator (AQM) from Analog Devices, Inc. An optional 3-wire or 4-wire serial port interface (SPI) provides for programming/readback of many internal parameters. Full-scale output current can be programmed over a typical range of 13.9 mA to 27.0 mA. The AD9144 is available in an 88-lead LFCSP. Rev. C 2. 3. 4. 5. 6. Greater than 1 GHz, ultrawide complex signal bandwidth enables emerging wideband and multiband wireless applications. Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies. JESD204B Subclass 1 support simplifies multichip synchronization in software and hardware design. Fewer pins for data interface width with a serializer/ deserializer (SERDES) JESD204B eight-lane interface. Programmable transmit enable function allows easy design balance between power consumption and wake-up time. Small package size with 12 mm × 12 mm footprint. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014–2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9144 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 JESD204B Setup ......................................................................... 30 Applications ....................................................................................... 1 SERDES Clocks Setup ................................................................ 32 General Description ......................................................................... 1 Equalization Mode Setup .......................................................... 32 Typical Application Circuit ............................................................. 1 Link Latency Setup ..................................................................... 32 Product Highlights ........................................................................... 1 Crossbar Setup ............................................................................ 34 Revision History ............................................................................... 3 JESD204B Serial Data Interface .................................................... 35 Functional Block Diagram .............................................................. 5 JESD204B Overview .................................................................. 35 Specifications..................................................................................... 6 Physical Layer ............................................................................. 36 DC Specifications ......................................................................... 6 Data Link Layer .......................................................................... 39 Digital Specifications ................................................................... 7 Transport Layer .......................................................................... 48 Maximum DAC Update Rate Speed Specifications by Supply ..... 8 JESD204B Test Modes ............................................................... 61 JESD204B Serial Interface Speed Specifications ...................... 8 JESD204B Error Monitoring..................................................... 62 SYSREF to DAC Clock Timing Specifications ......................... 9 Hardware Considerations ......................................................... 64 Digital Input Data Timing Specifications ................................. 9 Digital Datapath ............................................................................. 68 Latency Variation Specifications .............................................. 10 Dual Paging ................................................................................. 68 JESD204B Interface Electrical Specifications ......................... 10 Data Format ................................................................................ 68 AC Specifications........................................................................ 11 Interpolation Filters ................................................................... 68 Absolute Maximum Ratings.......................................................... 12 Digital Modulation ..................................................................... 69 Thermal Resistance .................................................................... 12 Inverse Sinc ................................................................................. 70 ESD Caution ................................................................................ 12 Digital Gain, Phase Adjust, DC Offset, and Group Delay .... 70 Pin Configuration and Function Descriptions ........................... 13 I to Q Swap .................................................................................. 71 Terminology .................................................................................... 16 NCO Alignment ......................................................................... 71 Typical Performance Characteristics ........................................... 17 Downstream Protection ............................................................ 73 Theory of Operation ...................................................................... 22 Datapath PRBS ........................................................................... 75 Serial Port Operation ..................................................................... 23 DC Test Mode ............................................................................. 75 Data Format ................................................................................ 23 Interrupt Request Operation ........................................................ 76 Serial Port Pin Descriptions ...................................................... 23 Interrupt Service Routine .......................................................... 76 Serial Port Options ..................................................................... 23 DAC Input Clock Configurations ................................................ 77 Chip Information ............................................................................ 25 Driving the CLK± Inputs .......................................................... 77 Device Setup Guide ........................................................................ 26 DAC PLL Fixed Register Writes ............................................... 77 Overview...................................................................................... 26 Clock Multiplication .................................................................. 77 Step 1: Start Up the DAC ........................................................... 26 Starting the PLL .......................................................................... 79 Step 2: Digital Datapath ............................................................. 27 Analog Outputs............................................................................... 80 Step 3: Transport Layer .............................................................. 27 Transmit DAC Operation.......................................................... 80 Step 4: Physical Layer ................................................................. 28 Device Power Dissipation.............................................................. 83 Step 5: Data Link Layer .............................................................. 28 Temperature Sensor ................................................................... 83 Step 6: Optional Error Monitoring .......................................... 29 Start-Up Sequence .......................................................................... 84 Step 7: Optional Features ........................................................... 29 Step 1: Start Up the DAC ........................................................... 84 DAC PLL Setup ........................................................................... 30 Step 2: Digital Datapath............................................................. 84 Interpolation ............................................................................... 30 Step 3: Transport Layer .............................................................. 85 Rev. C | Page 2 of 126 Data Sheet AD9144 Step 4: Physical Layer..................................................................85 Device Configuration Register Map ......................................... 87 Step 5: Data Link Layer ..............................................................86 Device Configuration Register Descriptions .......................... 95 Step 6: Error Monitoring ............................................................86 Outline Dimensions ......................................................................125 Register Maps and Descriptions ....................................................87 Ordering Guide .........................................................................126 REVISION HISTORY 4/2019—Rev. B to Rev. C Changes to Figure 75 ......................................................................76 Updated Outline Dimensions ......................................................125 Changes to Ordering Guide .........................................................126 3/2017—Rev. A to Rev. B Changed 10.64 Gbps to 12.4 Gbps, 2.76 Gbps to 3.1 Gbps, and 5.52 Gbps to 6.2 Gbps ................................................... Throughout Changes to Table 4 ............................................................................ 7 Change to Device Revision Parameter; Table 14 ........................24 Changes to Function Overview of the SERDES PLL Section ...36 Changes to Figure 38 ......................................................................37 Changes to Table 97 ........................................................................86 Changes to Table 98 ........................................................................94 6/2015—Rev. 0 to Rev. A Changed Functional Block Diagram Section to Typical Application Circuit Section.............................................................. 1 Changes to Figure 1........................................................................... 1 Changed Detailed Functional Block Diagram Section to Functional Block Diagram Section ................................................. 4 Deleted Reference Voltage Parameter, Table 1 .............................. 5 Changes to Output Voltage (VOUT) Logic High Parameter, Output Voltage (VOUT) Logic Low Parameter, and SYSREF± Frequency Parameter, Table 2 .......................................................... 6 Changes to Table 4 ............................................................................ 7 Changes to Interpolation Parameter, Table 6 ................................ 8 Deleted Sync Off, Subclass Mode 0 Parameter, Table 7 ............... 9 Changed Junction Temperature Parameter to Operating Junction Temperature, Table 10 ....................................................11 Changes to Terminology Section ..................................................15 Changes to Figure 26 Caption .......................................................19 Changes to Figure 29 Caption .......................................................20 Change to Device Revision Parameter, Table 14 .........................24 Changes to Step 1: Start Up the DAC Section, Table 16, and Table 17 .............................................................................................25 Changes to Step 3: Transport Layer Section and Table 19 .........26 Changes to Table 20 and Table 21 .................................................27 Changes to Step 7: Optional Features Section .............................28 Added Table 25; Renumbered Sequentially .................................29 Changes to DAC PLL Setup Section and Table 26 ......................29 Changes to Lane0Checksum Section ...........................................30 Changes to Table 30 and Subclass 0 Section ................................31 Changes to Table 33 ........................................................................32 Changes to Table 37 ........................................................................35 Changes to Table 38 ........................................................................36 Added SERDES PLL Fixed Register Writes Section and Table 39 ............................................................................................. 36 Changes to Figure 38 and Table 40 ............................................... 37 Changes to Figure 29 and Data Link Layer Section ................... 38 Added Figure 42; Renumbered Sequentially ............................... 39 Changes to Figure 44 ...................................................................... 40 Changes to Continuous Sync Mode (SYNCMOD = 0x2) Section .............................................................................................. 42 Changes to Subclass 0 Section ....................................................... 43 Changes to Figure 53 ...................................................................... 50 Changes to Table 49 and Figure 54 ............................................... 51 Changes to Table 50 and Figure 55 ............................................... 52 Changes to Table 51 and Figure 56 ............................................... 53 Changes to Table 52 and Figure 57 ............................................... 54 Changes to Table 53, Table 54, and Figure 58 ............................. 55 Changes to Table 55 and Figure 59 ............................................... 56 Changes to Table 56 and Figure 60 ............................................... 57 Changes to Table 57 and Figure 61 ............................................... 58 Changes to Table 58 and Figure 62 ............................................... 59 Changes to Power Supply Recommendations Section ............... 63 Added Figure 64 .............................................................................. 64 Changes to Figure 68 ...................................................................... 66 Changes to Table 66 ........................................................................ 67 Changes to Table 70, Table 71, Table 72, and I to Q Swap Section .............................................................................................. 70 Changes to Power Detection and Protection Section ................ 72 Changes to DC Test Mode Section ............................................... 73 Moved Figure 75 and Table 78 ...................................................... 75 Deleted Table 80; Renumbered Sequentially ............................... 76 Added DAC PLL Fixed Register Writes Section and Table 79 ............................................................................................. 76 Changes to Clock Multiplication Section .................................... 76 Added Loop Filter Section and Charge Pump Section .............. 77 Added Temperature Tracking Section and Table 83 .................. 78 Changes to Starting the PLL Section and Figure 79 ................... 78 Changes to Transmit DAC Operation Section ............................ 79 Changes to Self Calibration Section ............................................. 81 Added Figure 86 and Figure 87 ..................................................... 81 Changes to Device Power Dissipation Section............................ 82 Changes to Table 88 and Table 89 ................................................. 83 Changes to Table 93 ........................................................................ 84 Changes to Table 94, Table 95, and Table 96 ............................... 85 Changes to Table 97 ........................................................................ 86 Changes to Table 98 ........................................................................ 94 Deleted Lookup Tables for Three Different DAC PLL Reference Frequencies Section and Table 96 to Table 98 ........................... 122 Added Figure 89 ............................................................................ 124 Rev. C | Page 3 of 126 AD9144 Data Sheet Updated Outline Dimensions ..................................................... 124 Changes to Ordering Guide ........................................................ 125 7/2014—Revision 0: Initial Version Rev. C | Page 4 of 126 Data Sheet AD9144 FUNCTIONAL BLOCK DIAGRAM DACCLK SERDES PLL HB2 HB1 OUT3+ COMPLEX MODULATION HB3 HB2 I-GAIN PHASE ADJUST I-OFFSET OUT2+ ÷4, ÷8 HB3 FSC HB2 HB1 OUT2– COMPLEX MODULATION HB3 OUT1+ FSC PDP0 SERDIN0± HB1 INV SINC SERDIN7± NCO MODE CONTROL OUT3– DACCLK fDAC CLOCK DATA RECOVERY AND CLOCK FORMATTER VTT INV SINC PDP1 FSC Q-OFFSET Q-GAIN NCO MODE CONTROL I-GAIN OUT1– Q-OFFSET Q-GAIN PHASE ADJUST DACCLK I-OFFSET fDAC HB1 PROTECT_OUT0 PROTECT_OUT1 FSC PLL_CTRL SERIAL I/O PORT POWER-ON RESET DAC ALIGN DETECT CLK_SEL CONFIG REGISTERS CLOCK DISTRIBUTION AND CONTROL LOGIC DACCLK OUT0– REF AND BIAS SYSREF Rx CLK Rx I120 SYSREF+ SYSREF– CLK+ CLK– 11675-002 DAC PLL TXEN1 IRQ TXEN0 PLL_LOCK RESET SYNCOUT1+ SYNCOUT1– OUT0+ ÷4, ÷8 HB3 SYNCHRONIZATION LOGIC SDO SDIO SCLK CS SYNCOUT0+ SYNCOUT0– HB2 Figure 2. Rev. C | Page 5 of 126 AD9144 Data Sheet SPECIFICATIONS DC SPECIFICATIONS AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V, TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY Differential Nonlinearity (DNL) Integral Nonlinearity (INL) MAIN DAC OUTPUTS Gain Error I/Q Gain Mismatch Full-Scale Output Current Maximum Setting Minimum Setting Output Compliance Range Output Resistance Output Capacitance Gain DAC Monotonicity Settling Time MAIN DAC TEMPERATURE DRIFT Offset Gain REFERENCE Internal Reference Voltage ANALOG SUPPLY VOLTAGES AVDD33 PVDD12 CVDD12 DIGITAL SUPPLY VOLTAGES SIOVDD33 VTT DVDD12 Test Conditions/Comments Min Typ 16 Max Unit Bits With calibration ±1.0 ±2.0 With internal reference LSB LSB −2.5 −0.6 +2 +5.5 +0.6 % FSR % FSR 25.5 13.1 −250 27.0 13.9 28.6 14.8 +750 mA mA mV MΩ pF Based on a 4 kΩ external resistor between I120 and GND 0.2 3.0 Guaranteed 20 To within ±0.5 LSB ns 0.04 32 ppm ppm/°C 1.2 V 3.13 1.14 1.14 3.3 1.2 1.2 3.47 1.26 1.26 V V V 3.13 1.1 3.3 1.2 3.47 1.37 V V 1.14 1.274 1.2 1.3 1.26 1.326 V V 1.14 1.274 1.71 1.2 1.3 1.8 1.26 1.326 3.47 V V V 1.59 1.84 W 126 95.3 101 518.2 234 11 36 134 112.4 111 654 255 12 50 mA mA mA mA mA mA µA SVDD12 IOVDD POWER CONSUMPTION 4× Interpolation Mode, JESD Mode 4, 8 SERDES Lanes AVDD33 PVDD12 CVDD12 SVDD12 DVDD12 SIOVDD33 IOVDD fDAC = 1.6 GSPS, IF = 40 MHz, NCO off, PLL on, digital gain on, inverse sinc on, DAC FSC = 20 mA Includes VTT Rev. C | Page 6 of 126 Data Sheet AD9144 DIGITAL SPECIFICATIONS AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V, TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted. Table 2. Parameter CMOS INPUT LOGIC LEVEL Input Voltage (VIN) Logic High Low Symbol CMOS OUTPUT LOGIC LEVEL Output Voltage (VOUT) Logic High Low Test Conditions/Comments Min Typ Max Unit 1.8 V ≤ IOVDD ≤ 3.3 V 1.8 V ≤ IOVDD ≤ 3.3 V 0.7 × IOVDD 0.3 × IOVDD V V 1.8 V ≤ IOVDD ≤ 3.3 V 1.8 V ≤ IOVDD ≤ 3.3 V 0.75 × IOVDD 0.25 × IOVDD V V 1× interpolation 2 (see Table 4) 2× interpolation 3 4× interpolation 8× interpolation 1060 2120 2800 2800 MSPS MSPS MSPS MSPS 1× interpolation 2× interpolation 4× interpolation 8× interpolation 1060 1060 700 350 MSPS MSPS MSPS MSPS MAXIMUM DAC UPDATE RATE 1 ADJUSTED DAC UPDATE RATE INTERFACE 4 Number of JESD204B Lanes JESD204B Serial Interface Speed Minimum Maximum DAC CLOCK INPUT (CLK+, CLK−) Differential Peak-to-Peak Voltage Common-Mode Voltage Maximum Clock Rate REFCLK Frequency (PLL Mode) SYSTEM REFERENCE INPUT (SYSREF+, SYSREF−) Differential Peak-to-Peak Voltage Common-Mode Voltage SYSREF± Frequency 5 SYSREF TO DAC CLOCK 6 Setup Time Hold Time Keep Out Window SPI Maximum Clock Rate Minimum SCLK Pulse Width High Low SDIO to SCLK Setup Time Hold Time 8 Per lane Per lane, SVDD12 = 1.3 V ± 2% 1.44 Gbps Gbps 2000 1000 mV mV MHz MHz 2000 mV 2000 fDATA/(K × S) mV Hz 12.4 400 Self biased input, ac-coupled 6.0 GHz ≤ fVCO ≤ 12.0 GHz Lanes 1000 600 2800 35 400 1000 0 SYSREF differential swing = 0.4 V, slew rate = 1.3 V/ns, common modes tested: ac-coupled, 0 V, 0.6 V, 1.25 V, 2.0 V tSSD tHSD KOW SCLK 131 119 ps ps ps 20 IOVDD = 1.8 V 10 tPWH tPWL MHz 8 12 tDS tDH 5 2 Rev. C | Page 7 of 126 ns ns ns ns AD9144 Parameter SDO to SCLK Data Valid Window CS to SCLK Setup Time Hold Time Data Sheet Symbol Test Conditions/Comments Min Typ Max Unit tDV 25 ns tSCS 5 ns tHCS 2 ns See Table 3 for detailed specifications for DAC update rate conditions. Maximum speed for 1× interpolation is limited by the JESD interface. See Table 4 for details. Maximum speed for 2× interpolation is limited by the JESD interface. See Table 4 for details. 4 See Table 4 for detailed specifications for JESD speed conditions. 5 K, F, and S are JESD204B transport layer parameters. See Table 44 for the full definitions. 6 See Table 5 for detailed specifications for SYSREF to DAC clock timing conditions. 1 2 3 MAXIMUM DAC UPDATE RATE SPEED SPECIFICATIONS BY SUPPLY AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V, TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted. Table 3. Parameter MAXIMUM DAC UPDATE RATE Test Conditions/Comments DVDD12, CVDD12 = 1.2 V ± 5% DVDD12, CVDD12 = 1.2 V ± 2% DVDD12, CVDD12 = 1.3 V ± 2% Min 2.23 2.41 2.80 Typ Max Unit GSPS GSPS GSPS JESD204B SERIAL INTERFACE SPEED SPECIFICATIONS AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V, TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted. Table 4. Parameter HALF RATE FULL RATE OVERSAMPLING Test Conditions/Comments SVDD12 = 1.2 V ± 5% SVDD12 = 1.2 V ±2% SVDD12 = 1.3 V ± 2% SVDD12 = 1.2 V ± 5% SVDD12 = 1.2 V ± 2% SVDD12 = 1.3 V ± 2% SVDD12 = 1.2 V ± 5% SVDD12 = 1.2 V ± 2% SVDD12 = 1.3 V ± 2% Rev. C | Page 8 of 126 Min 5.75 5.75 5.75 2.88 2.88 2.88 1.44 1.44 1.44 Typ Max 11.4 12.0 12.4 5.98 6.06 6.2 3.0 3.04 3.1 Unit Gbps Gbps Gbps Gbps Gbps Gbps Gbps Gbps Gbps Data Sheet AD9144 SYSREF TO DAC CLOCK TIMING SPECIFICATIONS AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V, TA = −40°C to +85°C, IOUTFS = 20 mA, SYSREF± common-mode voltages = 0.0 V, 0.6 V, 1.25 V, and 2.0 V, unless otherwise noted. Table 5. Parameter SYSREF DIFFERENTIAL SWING = 0.4 V, SLEW RATE = 1.3 V/ns Setup Time Hold Time SYSREF DIFFERENTIAL SWING = 0.7 V, SLEW RATE = 2.28 V/ns Setup Time Hold Time SYSREF SWING = 1.0 V, SLEW RATE = 3.26 V/ns Setup Time Hold Time Test Conditions/Comments Min Typ Max Unit AC-coupled DC-coupled AC-coupled DC-coupled 126 131 92 119 ps ps ps ps AC-coupled DC-coupled AC-coupled DC-coupled 96 104 77 95 ps ps ps ps AC-coupled DC-coupled AC-coupled DC-coupled 83 90 68 84 ps ps ps ps DIGITAL INPUT DATA TIMING SPECIFICATIONS AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V, TA = 25°C, IOUTFS = 20 mA, unless otherwise noted. Table 6. Parameter LATENCY Interface Interpolation 1× 2× 4× 8× Inverse Sinc Fine Modulation Coarse Modulation fS/8 fS/4 Digital Phase Adjust Digital Gain Adjust Power-Up Time Dual A Only Dual B Only All DACs 1 Test Conditions/Comments Min Register 0x011 from 0x60 to 0x00 Register 0x011 from 0x18 to 0x00 Register 0x011 from 0x7C to 0x00 PClock is the AD9144 internal processing clock and equals the lane rate ÷ 40. Rev. C | Page 9 of 126 Typ Max Unit 17 PClock 1 cycles 58 137 251 484 17 20 DAC clock cycles DAC clock cycles DAC clock cycles DAC clock cycles DAC clock cycles DAC clock cycles 8 4 12 12 DAC clock cycles DAC clock cycles DAC clock cycles DAC clock cycles 60 60 60 µs µs µs AD9144 Data Sheet LATENCY VARIATION SPECIFICATIONS AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V, TA = 25°C, IOUTFS = 20 mA, unless otherwise noted. Table 7. Parameter DAC LATENCY VARIATION SYNC On PLL Off PLL On Min Typ Max Unit 0 1 +1 DACCLK cycles DACCLK cycles −1 JESD204B INTERFACE ELECTRICAL SPECIFICATIONS AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V, TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted. Table 8. Parameter JESD204B DATA INPUTS Input Leakage Current Logic High Logic Low Unit Interval Common-Mode Voltage Differential Voltage VTT Source Impedance Differential Impedance Differential Return Loss Common-Mode Return Loss DIFFERENTIAL OUTPUTS (SYNCOUT±) 2 Output Differential Voltage Output Offset Voltage Output Differential Voltage DETERMINISTIC LATENCY Fixed Variable SYSREF±-to-LMFC DELAY 1 2 3 Symbol Test Conditions/Comments Min 25°C Input level = 1.2 V ± 0.25 V, VTT = 1.2 V Input level = 0 V UI VRCM R_VDIFF ZTT ZRDIFF RLRDIF RLRCM VOD VOS VOD AC-coupled, VTT = SVDD12 1 At dc At dc High swing mode: Register 0x2A5[0] = 1 94 −0.05 110 100 8 6 192 1.19 341 4 As measured on the input side of the ac coupling capacitor. IEEE Standard 1596.3 LVDS compatible. PClock is the AD9144 internal processing clock and equals the lane rate ÷ 40. Rev. C | Page 10 of 126 Max Unit 714 +1.85 1050 30 120 µA µA ps V mV Ω Ω dB dB 235 1.27 394 mV V mV 17 2 PClock 3 cycles PClock3 cycles DAC clock cycles 10 −4 80 Normal swing mode: Register 0x2A5[0] = 0 Typ Data Sheet AD9144 AC SPECIFICATIONS AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, 1 VTT = 1.2 V, TA = 25°C, IOUTFS = 20 mA, unless otherwise noted. Table 9. Parameter SPURIOUS-FREE DYNAMIC RANGE (SFDR) fDAC = 983.04 MSPS fDAC = 983.04 MSPS fDAC = 1966.08 MSPS fDAC = 1966.08 MSPS TWO-TONE INTERMODULATION DISTORTION (IMD) fDAC =983.04 MSPS fDAC = 983.04 MSPS fDAC = 1966.08 MSPS fDAC = 1966.08 MSPS NOISE SPECTRAL DENSITY (NSD), SINGLE-TONE fDAC = 983.04 MSPS fDAC = 1966.08 MSPS W-CDMA FIRST ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER fDAC = 983.04 MSPS fDAC = 983.04 MSPS fDAC = 1966.08 MSPS W-CDMA SECOND ACLR, SINGLE CARRIER fDAC = 983.04 MSPS fDAC = 983.04 MSPS fDAC = 1966.08 MSPS 1 Test Conditions/Comments −9 dBFS single-tone fOUT = 20 MHz fOUT = 150 MHz fOUT = 20 MHz fOUT = 170 MHz −9 dBFS fOUT = 20 MHz fOUT = 150 MHz fOUT = 20 MHz fOUT = 170 MHz 0 dBFS fOUT = 150 MHz fOUT = 150 MHz 0 dBFS fOUT = 30 MHz fOUT = 150 MHz fOUT = 150 MHz 0 dBFS fOUT = 30 MHz fOUT = 150 MHz fOUT = 150 MHz SVDD12 = 1.3 V for all fDAC = 1966.08 MSPS conditions in Table 9. Rev. C | Page 11 of 126 Min Typ Max Unit 82 76 81 69 dBc dBc dBc dBc 90 82 90 81 dBc dBc dBc dBc −162 −163 dBm/Hz dBm/Hz 82 80 80 dBc dBc dBc 84 85 85 dBc dBc dBc AD9144 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 10. Parameter I120 to Ground SERDINx±, VTT, SYNCOUT1±/ SYNCOUT0±, TXENx OUTx± SYSREF± CLK± to Ground RESET, IRQ, CS, SCLK, SDIO, SDO, PROTECT_OUTx to Ground LDO_BYP1 LDO_BYP2 LDO24 Ambient Operating Temperature (TA) Operating Junction Temperature Storage Temperature Rating −0.3 V to AVDD33 + 0.3 V −0.3 V to SIOVDD33 + 0.3 V −0.3 V to AVDD33 + 0.3 V GND − 0.5 V to +2.5 V −0.3 V to PVDD12 + 0.3 V −0.3 V to IOVDD + 0.3 V −0.3 V to SVDD12 + 0.3 V −0.3 V to PVDD12 + 0.3 V −0.3 V to AVDD33 + 0.3 V −40°C to +85°C 125°C −65°C to +150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. The exposed pad (EPAD) must be soldered to the ground plane for the 88-lead LFCSP. The EPAD provides an electrical, thermal, and mechanical connection to the board. Typical θJA, θJB, and θJC values are specified for a 4-layer JESD51-7 high effective thermal conductivity test board for leaded surface-mount packages. θJA is obtained in still air conditions (JESD51-2). Airflow increases heat dissipation, effectively reducing θJA. θJB is obtained following double-ring cold plate test conditions (JESD51-8). θJC is obtained with the test case temperature monitored at the bottom of the exposed pad. ΨJT and ΨJB are thermal characteristic parameters obtained with θJA in still air test conditions. Junction temperature (TJ) can be estimated using the following equations: TJ = TT + (ΨJT × P), or TJ = TB + (ΨJB × P) where: TT is the temperature measured at the top of the package. P is the total device power dissipation. TB is the temperature measured at the board. Table 11. Thermal Resistance Package 88-Lead LFCSP1 1 θJA 22.6 θJB 5.59 θJC 1.17 ΨJT 0.1 ΨJB 5.22 The exposed pad must be securely connected to the ground plane. ESD CAUTION Rev. C | Page 12 of 126 Unit °C/W Data Sheet AD9144 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 LDO_BYP2 CVDD12 I120 AVDD33 OUT0+ OUT0– LDO24 CVDD12 LDO24 OUT1– OUT1+ AVDD33 CVDD12 AVDD33 OUT2+ OUT2– LDO24 CVDD12 LDO24 OUT3– OUT3+ AVDD33 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 AD9144 TOP VIEW (Not to Scale) 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 IOVDD CS SCLK SDIO SDO RESET IRQ PROTECT_OUT0 PROTECT_OUT1 PVDD12 PVDD12 GND GND DVDD12 SERDIN7+ SERDIN7– SVDD12 SERDIN6+ SERDIN6– SVDD12 VTT SVDD12 NOTES 1. THE EXPOSED PAD MUST BE SECURELY CONNECTED TO THE GROUND PLANE. 11675-003 SYNCOUT0+ SYNCOUT0– VTT SERDIN2+ SERDIN2– SVDD12 SERDIN3+ SERDIN3– SVDD12 SVDD12 SVDD12 LDO_BYP1 SIOVDD33 SVDD12 SERDIN4– SERDIN4+ SVDD12 SERDIN5– SERDIN5+ VTT SYNCOUT1– SYNCOUT1+ 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 PVDD12 CLK+ CLK– PVDD12 SYSREF+ SYSREF– PVDD12 PVDD12 PVDD12 PVDD12 TXEN0 TXEN1 DVDD12 DVDD12 SERDIN0+ SERDIN0– SVDD12 SERDIN1+ SERDIN1– SVDD12 VTT SVDD12 Figure 3. Pin Configuration Table 12. Pin Function Descriptions Pin No. 1 2 Mnemonic PVDD12 CLK+ 3 CLK− 4 5 PVDD12 SYSREF+ 6 SYSREF− 7 8 9 10 11 12 13 14 15 PVDD12 PVDD12 PVDD12 PVDD12 TXEN0 TXEN1 DVDD12 DVDD12 SERDIN0+ 16 SERDIN0− 17 18 SVDD12 SERDIN1+ 19 SERDIN1− Description 1.2 V Supply. PVDD12 provides a clean supply. PLL Reference/Clock Input, Positive. When the PLL is used, this pin is the positive reference clock input. When the PLL is not used, this pin is the positive device clock input. This pin is self biased and must be ac-coupled. PLL Reference/Clock Input, Negative. When the PLL is used, this pin is the negative reference clock input. When the PLL is not used, this pin is the negative device clock input. This pin is self biased and must be ac-coupled. 1.2 V Supply. PVDD12 provides a clean supply. Positive Reference Clock for Deterministic Latency. This pin is self biased for ac coupling. It can be ac-coupled or dc-coupled. Negative Reference Clock for Deterministic Latency. This pin is self biased for ac coupling. It can be ac-coupled or dc-coupled. 1.2 V Supply. PVDD12 provides a clean supply. 1.2 V Supply. PVDD12 provides a clean supply. 1.2 V Supply. PVDD12 provides a clean supply. 1.2 V Supply. PVDD12 provides a clean supply. Transmit Enable for DAC0 and DAC1. The CMOS levels are determined with respect to IOVDD. Transmit Enable for DAC2 and DAC3. The CMOS levels are determined with respect to IOVDD. 1.2 V Digital Supply. 1.2 V Digital Supply. Serial Channel Input 0, Positive. CML compliant. SERDIN0+ is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. Serial Channel Input 0, Negative. CML compliant. SERDIN0− is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 1.2 V JESD204B Receiver Supply. Serial Channel Input 1, Positive. CML compliant. SERDIN1+ is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. Serial Channel Input 1, Negative. CML compliant. SERDIN1− is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. Rev. C | Page 13 of 126 AD9144 Pin No. 20 21 22 23 24 25 26 Mnemonic SVDD12 VTT SVDD12 SYNCOUT0+ SYNCOUT0− VTT SERDIN2+ 27 SERDIN2− 28 29 SVDD12 SERDIN3+ 30 SERDIN3− 31 32 33 34 35 36 37 SVDD12 SVDD12 SVDD12 LDO_BYP1 SIOVDD33 SVDD12 SERDIN4− 38 SERDIN4+ 39 40 SVDD12 SERDIN5− 41 SERDIN5+ 42 43 44 45 46 47 48 VTT SYNCOUT1− SYNCOUT1+ SVDD12 VTT SVDD12 SERDIN6− 49 SERDIN6+ 50 51 SVDD12 SERDIN7− 52 SERDIN7+ 53 54 55 56 57 58 59 60 61 DVDD12 GND GND PVDD12 PVDD12 PROTECT_OUT1 PROTECT_OUT0 IRQ RESET Data Sheet Description 1.2 V JESD204B Receiver Supply. 1.2 V Termination Voltage. Connect VTT to the SVDD12 supply pins. 1.2 V JESD204B Receiver Supply. Positive LVDS Sync (Active Low) Output Signal Channel Link 0. Negative LVDS Sync (Active Low) Output Signal Channel Link 0. 1.2 V Termination Voltage. Connect VTT to the SVDD12 supply pins. Serial Channel Input 2, Positive. CML compliant. SERDIN2+ is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. Serial Channel Input 2, Negative. CML compliant. SERDIN2− is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 1.2 V JESD204B Receiver Supply. Serial Channel Input 3, Positive. CML compliant. SERDIN3+ is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. Serial Channel Input 3, Negative. CML compliant. SERDIN3− is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 1.2 V JESD204B Receiver Supply. 1.2 V JESD204B Receiver Supply. 1.2 V JESD204B Receiver Supply. LDO SERDES Bypass. This pin requires a 1 Ω resistor in series with a 1 µF capacitor to ground. 3.3 V Supply for SERDES. 1.2 V JESD204B Receiver Supply. Serial Channel Input 4, Negative. CML compliant. SERDIN4− is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. Serial Channel Input 4, Positive. CML compliant. SERDIN4+ is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 1.2 V JESD204B Receiver Supply. Serial Channel Input 5, Negative. CML compliant. SERDIN5− is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. Serial Channel Input 5, Positive. CML compliant. SERDIN5+ is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 1.2 V Termination Voltage. Connect VTT to the SVDD12 supply pins. Negative LVDS Sync (Active Low) Output Signal Channel Link 1. Positive LVDS Sync (Active Low) Output Signal Channel Link 1. 1.2 V JESD204B Receiver Supply. 1.2 V Termination Voltage. Connect VTT to the SVDD12 supply pins. 1.2 V JESD204B Receiver Supply. Serial Channel Input 6, Negative. CML compliant. SERDIN6− is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. Serial Channel Input 6, Positive. CML compliant. SERDIN6+ is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 1.2 V JESD204B Receiver Supply. Serial Channel Input 7, Negative. CML compliant. SERDIN7− is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. Serial Channel Input 7, Positive. CML compliant. SERDIN7+ is internally terminated to the VTT pin voltage using a calibrated 50 Ω resistor. This pin is ac-coupled only. 1.2 V Digital Supply. Ground. Connect GND to the ground plane. Ground. Connect GND to the ground plane. 1.2 V Supply. PVDD12 provides a clean supply. 1.2 V Supply. PVDD12 provides a clean supply. Power Detection Protection Pin Output for DAC2 and DAC3. Pin 58 is high when power protection is in process. Power Detection Protection Pin Output for DAC0 and DAC1. Pin 59 is high when power protection is in process. Interrupt Request (Active Low, Open Drain). Reset. This pin is active low. CMOS levels are determined with respect to IOVDD. Rev. C | Page 14 of 126 Data Sheet Pin No. 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 Mnemonic SDO SDIO SCLK CS IOVDD AVDD33 OUT3+ OUT3− LDO24 CVDD12 LDO24 OUT2− OUT2+ AVDD33 CVDD12 AVDD33 OUT1+ OUT1− LDO24 CVDD12 LDO24 OUT0− OUT0+ AVDD33 I120 CVDD12 LDO_BYP2 EPAD AD9144 Description Serial Port Data Output. CMOS levels are determined with respect to IOVDD. Serial Port Data Input/Output. CMOS levels are determined with respect to IOVDD. Serial Port Clock Input. CMOS levels are determined with respect to IOVDD. Serial Port Chip Select. This pin is active low; CMOS levels are determined with respect to IOVDD. IOVDD Supply for CMOS Input/Output and SPI. Operational for 1.8 V ≤ IOVDD ≤ 3.3 V. 3.3 V Analog Supply for DAC Cores. DAC3 Positive Current Output. DAC3 Negative Current Output. 2.4 V LDO. Requires a 1 µF capacitor to ground. 1.2 V Clock Supply. Place bypass capacitors as near as possible to Pin 71. 2.4 V LDO. Requires a 1 µF capacitor to ground. DAC2 Negative Current Output. DAC2 Positive Current Output. 3.3 V Analog Supply for DAC Cores. 1.2 V Clock Supply. Place bypass capacitors as near as possible to Pin 76. 3.3 V Analog Supply for DAC Cores. DAC1 Positive Current Output. DAC1 Negative Current Output. 2.4 V LDO. Requires a 1 µF capacitor to ground. 1.2 V Clock Supply. Place bypass capacitors as near as possible to Pin 81. 2.4 V LDO. Requires a 1 µF capacitor to ground. DAC0 Negative Current Output. DAC0 Positive Current Output. 3.3 V Analog Supply for DAC Cores. Output Current Generation Pin for DAC Full-Scale Current. Tie a 4 kΩ resistor from the I120 pin to ground. 1.2 V Clock Supply. Place bypass capacitors as near as possible to Pin 87. LDO Clock Bypass for DAC PLL. This pin requires a 1 Ω resistor in series with a 1 µF capacitor to ground. Exposed Pad. The exposed pad must be securely connected to the ground plane. Rev. C | Page 15 of 126 AD9144 Data Sheet TERMINOLOGY Integral Nonlinearity (INL) INL is the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Offset Error Offset error is the deviation of the output current from the ideal of 0 mA. For OUTx+, 0 mA output is expected when all inputs are set to 0. For OUTx−, 0 mA output is expected when all inputs are set to 1. Gain Error Gain error is the difference between the actual and ideal output span. The actual span is determined by the difference between the output when the input is at its minimum code and the output when the input is at its maximum code. Output Compliance Range The output compliance range is the range of allowable voltages at the output of a current output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. Temperature Drift Offset drift is a measure of how far from full-scale range (FSR) the DAC output current is at 25°C (in ppm). Gain drift is a measure of the slope of the DAC output current across its full ambient operating temperature range, TA, (in ppm/°C). Power Supply Rejection (PSR) PSR is the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. Settling Time Settling time is the time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal within the dc to Nyquist frequency of the DAC. Typically, energy in this band is rejected by the interpolation filters. This specification, therefore, defines how well the interpolation filters work and the effect of other parasitic coupling paths on the DAC output. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Interpolation Filter If the digital inputs to the DAC are sampled at a multiple rate of fDATA (interpolation rate), a digital filter can be constructed that has a sharp transition band near fDATA/2. Images that typically appear around fDAC (output data rate) can be greatly suppressed. Adjacent Channel Leakage Ratio (ACLR) ACLR is the ratio in decibels relative to the carrier (dBc) between the measured power within a channel relative to its adjacent channel. Complex Image Rejection In a traditional two part upconversion, two images are created around the second IF frequency. These images have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected. Adjusted DAC Update Rate The adjusted DAC update rate is defined as the DAC update rate divided by the smallest interpolating factor. For clarity on DACs with multiple interpolating factors, the adjusted DAC update rate for each interpolating factor may be given. Physical Lane Physical Lane x refers to SERDINx±. Logical Lane Logical Lane x refers to physical lanes after optionally being remapped by the crossbar block (Register 0x308 to Register 0x30B). Link Lane Link Lane x refers to logical lanes considered per link. When paging Link 0 (Register 0x300[2] = 0), Link Lane x = Logical Lane x. When paging Link 1 (Register 0x300[2] = 1, dual-link only), Link Lane x = Logical Lane x + 4. Rev. C | Page 16 of 126 Data Sheet AD9144 TYPICAL PERFORMANCE CHARACTERISTICS 0 –20 –40 –60 –80 –60 200 300 400 500 fOUT (MHz) –100 200 300 400 500 Figure 7. Single-Tone SFDR vs. fOUT in the First Nyquist Zone over Digital Back Off, fDAC = 983 MHz 0 fDAC = 1966MHz fDAC = 2456MHz MEDIAN –20 100 fOUT (MHz) Figure 4. Single-Tone SFDR vs. fOUT in the First Nyquist Zone, fDAC = 983 MHz, 1228 MHz, and 1474 MHz 0 0 11675-107 100 11675-104 0 0dBFS –6dBFS –9dBFS –12dBFS –20 –40 SFDR (dBc) –60 –80 –40 –60 –100 100 200 300 400 500 fOUT (MHz) –100 11675-305 0 0 100 200 300 400 500 fOUT (MHz) Figure 5. Single-Tone SFDR vs. fOUT in the First Nyquist Zone, fDAC = 1966 MHz and 2456 MHz 11675-108 –80 Figure 8. Single-Tone SFDR vs. fOUT in the First Nyquist Zone over Digital Back Off, fDAC = 1966 MHz 0 0 IN-BAND SECOND HARMONIC IN-BAND THIRD HARMONIC MAX DIGITAL SPUR –20 –40 –40 IMD3 (dBc) –20 –60 –80 fDAC = 983MHz fDAC = 1228MHz fDAC = 1474MHz –60 –80 0 100 200 300 fOUT (MHz) 400 500 11675-106 –100 Figure 6. Single-Tone Second and Third Harmonics and Maximum Digital Spur in the First Nyquist Zone, fDAC = 1966 MHz, 0 dB Back Off Rev. C | Page 17 of 126 –100 0 100 200 300 400 fOUT (MHz) Figure 9. Two-Tone Third IMD (IMD3) vs. fOUT, fDAC = 983 MHz, 1228 MHz, and 1474 MHz 500 11675-109 SFDR (dBc) –40 –80 –100 SFDR (dBc) 0dBFS –6dBFS –9dBFS –12dBFS –20 SFDR (dBc) SFDR (dBc) 0 fDAC = 983MHz fDAC = 1228MHz fDAC = 1474MHz AD9144 0 fDAC = 1966MHz fDAC = 2456MHz –20 –20 –40 –40 IMD3 (dBc) –60 –80 1MHz TONE SPACING 16MHz TONE SPACING 35MHz TONE SPACING –60 –80 0 100 200 300 400 500 fOUT (MHz) Figure 10. Two-Tone Third IMD (IMD3) vs. fOUT, fDAC = 1966 MHz and 2456 MHz 0 –100 11675-110 –100 fDAC = 983MHz fDAC = 1966MHz 0 100 200 300 400 500 fOUT (MHz) 11675-113 IMD3 (dBc) 0 Data Sheet Figure 13. Two-Tone Third IMD (IMD3) vs. fOUT over Tone Spacing at 0 dB Back Off, fDAC = 983 MHz and 1966 MHz –130 0dBFS –6dBFS –9dBFS –12dBFS fDAC = 983MHz fDAC = 1228MHz fDAC = 1474MHz –135 –20 NSD (dBm/Hz) IMD3 (dBc) –140 –40 –60 –145 –150 –155 –160 –80 100 200 300 400 500 fOUT (MHz) –170 0 100 200 300 400 500 11675-114 0 11675-111 –100 500 11675-115 –165 fOUT (MHz) Figure 11. Two-Tone Third IMD (IMD3) vs. fOUT over Digital Back Off, fDAC = 983 MHz, Each Tone Is at −6 dBFS Figure 14. Single-Tone (0 dBFS) NSD vs. fOUT, fDAC = 983 MHz, 1228 MHz, and 1474 MHz –130 0 0dBFS –6dBFS –9dBFS –12dBFS –20 fDAC = 1966MHz fDAC = 2456MHz –135 NSD (dBm/Hz) IMD3 (dBc) –140 –40 –60 –145 –150 –155 –160 –80 –100 0 100 200 300 fOUT (MHz) 400 500 11675-112 –165 Figure 12. Two-Tone Third IMD (IMD3) vs. fOUT over Digital Back Off, fDAC = 1966 MHz, Each Tone Is at −6 dBFS Rev. C | Page 18 of 126 –170 0 100 200 300 400 fOUT (MHz) Figure 15. Single-Tone (0 dBFS) NSD vs. fOUT, fDAC = 1966 MHz and 2456 MHz Data Sheet –130 AD9144 –60 0dBFS –6dBFS –9dBFS –12dBFS –135 –80 PHASE NOISE (dBc/Hz) –140 NSD (dBm/Hz) fOUT = 30MHz fOUT = 200MHz fOUT = 400MHz –145 –150 –155 PLL: OFF PLL: ON –100 –120 –140 –160 –160 –180 0 100 200 300 400 500 fOUT (MHz) 11675-116 –170 Figure 16. Single-Tone NSD vs. fOUT over Digital Back Off, fDAC = 983 MHz –130 10 100 1k 10k 100k 1M 10M OFFSET FREQUENCY (Hz) Figure 19. Single-Tone Phase Noise vs. Offset Frequency over fOUT, fDAC = 2.0 GHz, PLL On and Off 0dBFS –6dBFS –9dBFS –12dBFS –135 NSD (dBm/Hz) –140 –145 –150 –155 –160 0 100 200 300 400 500 fOUT (MHz) 11675-117 –170 Figure 17. Single-Tone NSD vs. fOUT over Digital Back Off, fDAC = 1966 MHz –130 Figure 20. 1C WCDMA ACLR, fOUT = 30 MHz, fDAC = 983 MHz, 2× Interpolation, PLL Frequency = 122 MHz PLL OFF PLL ON –135 fDAC = 983MHz fDAC = 1966MHz –140 –145 –150 –155 –160 –170 0 100 200 300 400 fOUT (MHz) 500 11675-316 –165 11675-118 NSD (dBm/Hz) 11675-315 –165 Figure 18. Single-Tone NSD (0 dBFS) vs. fOUT, fDAC = 983 MHz and 1966 MHz, PLL On and Off Figure 21. 1C WCDMA ACLR, fOUT = 122 MHz, fDAC = 983 MHz, 2× Interpolation, PLL Frequency = 122 MHz Rev. C | Page 19 of 126 11675-119 –165 Data Sheet 11675-317 11675-320 AD9144 Figure 25. 4C WCDMA ACLR, fOUT = 245 MHz, fDAC = 1966 MHz, 4× Interpolation, PLL Frequency = 245 MHz Figure 22. 4C WCDMA ACLR, fOUT = 30 MHz, fDAC = 983 MHz, 2× Interpolation, PLL Frequency = 122 MHz 1800 1× 2× 4× 8× POWER CONSUMPTION (mW) 1700 1600 1500 1400 1300 1200 Figure 23. 4C WCDMA ACLR, fOUT = 122 MHz, fDAC = 983 MHz, 2× Interpolation, PLL Frequency = 122 MHz 1000 0 1000 500 1500 2000 2500 fDAC (MHz) 11675-326 11675-318 1100 Figure 26. Total Power Consumption vs. fDAC over Interpolation, 8 SERDES Lanes Enabled, 4 DACs Enabled, NCO, Digital Gain, Inverse Sinc and DAC PLL Disabled 120 POWER CONSUMPTION (mW) 100 NCO PLL (fDAC /fREF RATIO:4) DIGITAL GAIN INVERSE SINC 80 60 40 0 200 400 600 800 1000 1200 1400 1600 fDAC (MHz) Figure 24. 4C WCDMA ACLR, fOUT = 30 MHz, fDAC = 1966 MHz, 4× Interpolation, PLL Frequency = 245 MHz Figure 27. Power Consumption vs. fDAC over Digital Functions Rev. C | Page 20 of 126 11675-327 11675-319 20 Data Sheet 700 AD9144 2 LANES 4 LANES 8 LANES 350 1.2V SVDD12 SUPPLY 1.3V SVDD12 SUPPLY 300 SUPPLY CURRENT (mA) 500 400 300 200 1.2V SUPPLY 1.3V SUPPLY 3.3V SUPPLY 250 200 150 100 50 1 2 3 4 5 LANE RATE (Gbps) 6 7 8 0 200 11675-328 100 Figure 28. SVDD12 Current vs. Lane Rate over Number of SERDES Lanes and Supply Voltage Setting 400 600 800 100 fDAC (MHz) 1200 1400 1600 11675-329 SVDD12 CURRENT (mA) 600 DVDD12 CVDD12 PVDD12 AVDD33 Figure 29. DVDD12, CVDD12, PVDD12, and AVDD33 Supply Current vs. fDAC over Supply Voltage Setting, 4 DACs Enabled Rev. C | Page 21 of 126 AD9144 Data Sheet THEORY OF OPERATION The AD9144 is a 16-bit, quad DAC with a SERDES interface. Figure 2 shows a detailed functional block diagram of the AD9144. Eight high speed serial lanes carry data at a maximum speed of 12.4 Gbps, and a 1.06 GSPS input data rate to the DACs. Compared to either LVDS or CMOS interfaces, the SERDES interface simplifies pin count, board layout, and input clock requirements to the device. The clock for the input data is derived from the device clock (required by the JESD204B specification). This device clock can be sourced with a PLL reference clock used by the on-chip PLL to generate a DAC clock or a high fidelity direct external DAC sampling clock. The device can be configured to operate in one-, two-, four-, or eight-lane modes, depending on the required input data rate. To add application flexibility, the quad DAC can be configured as a dual-link device with each JESD204B link providing data for a dual DAC pair. The digital datapath of the AD9144 offers four interpolation modes (1×, 2×, 4×, and 8×) through three half-band filters with a maximum DAC sample rate of 2.8 GSPS. An inverse sinc filter is provided to compensate for sinc related roll-off. The AD9144 DAC cores provide a fully differential current output with a nominal full-scale current of 20 mA. The full-scale current, IOUTFS, is user adjustable to between 13.9 mA and 27.0 mA, typically. The differential current outputs are complementary and are optimized for easy integration with the Analog Devices ADRF6720 AQM. The AD9144 is capable of multichip synchronization that can both synchronize multiple DACs and establish a constant and deterministic latency (latency locking) path for the DACs. The latency for each of the DACs remains constant from link establishment to link establishment. An external alignment (SYSREF±) signal makes the AD9144 Subclass 1 compliant. Several modes of SYSREF± signal handling are available for use in the system. An SPI configures the various functional blocks and monitors their statuses. The various functional blocks and the data interface must be set up in a specific sequence for proper operation (see the Device Setup Guide section). Simple SPI initialization routines set up the JESD204B link and are included in the evaluation board package. The following sections describe the various blocks of the AD9144 in greater detail. Descriptions of the JESD204B interface, control parameters, and various registers to set up and monitor the device are provided. The recommended start-up routine reliably sets up the data link. Rev. C | Page 22 of 126 Data Sheet AD9144 SERIAL PORT OPERATION The serial port is a flexible, synchronous serial communications port that allows easy interfacing with many industry-standard microcontrollers and microprocessors. The serial input/output (I/O) is compatible with most synchronous transfer formats, including both the Motorola SPI and Intel® SSR protocols. The interface allows read/write access to all registers that configure the AD9144. MSB first or LSB first transfer formats are supported. The serial port interface can be configured as a 4-wire interface or a 3-wire interface in which the input and output share a singlepin I/O (SDIO). SDO 62 SCLK 64 CS 65 SPI PORT Serial Clock (SCLK) Figure 30. Serial Port Interface Pins There are two phases to a communication cycle with the AD9144. Phase 1 is the instruction cycle (the writing of an instruction byte into the device), coincident with the first 16 SCLK rising edges. The instruction word provides the serial port controller with information regarding the data transfer cycle, Phase 2 of the communication cycle. The Phase 1 instruction word defines whether the upcoming data transfer is a read or write, along with the starting register address for the following data transfer. A logic high on the CS pin followed by a logic low resets the serial port timing to the initial state of the instruction cycle. From this state, the next 16 rising SCLK edges represent the instruction bits of the current I/O operation. The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the device and the system controller. Phase 2 of the communication cycle is a transfer of one or more data bytes. Eight × N SCLK cycles are needed to transfer N bytes during the transfer cycle. Registers change immediately upon writing to the last bit of each transfer byte, except for the frequency tuning word (FTW) and numerically controlled oscillator (NCO) phase offsets, which change only when the frequency tuning word FTW_UPDATE_REQ bit is set. DATA FORMAT The instruction byte contains the information shown in Table 13. Table 13. Serial Port Instruction Word I[15] (MSB) R/W I[14:0] A[14:0] A14 to A0, Bit 14 to Bit 0 of the instruction word, determine the register that is accessed during the data transfer portion of the communication cycle. For multibyte transfers, A[14:0] is the starting address. The remaining register addresses are generated by the device based on the ADDRINC bit. If ADDRINC is set high (Register 0x000, Bit 5 and Bit 2), multibyte SPI writes start on A[14:0] and increment by 1 every 8 bits sent/received. If ADDRINC is set to 0, the address decrements by 1 every 8 bits. SERIAL PORT PIN DESCRIPTIONS 11675-044 SDIO 63 R/W, Bit 15 of the instruction word, determines whether a read or a write data transfer occurs after the instruction word write. Logic 1 indicates a read operation, and Logic 0 indicates a write operation. The serial clock pin synchronizes data to and from the device and runs the internal state machines. The maximum frequency of SCLK is 10 MHz. All data input is registered on the rising edge of SCLK. All data is driven out on the falling edge of SCLK. Chip Select (CS) An active low input starts and gates a communication cycle. CS allows more than one device to be used on the same serial communications lines. The SDIO pin goes to a high impedance state when this input is high. During the communication cycle, chip select must stay low. Serial Data I/O (SDIO) This pin is a bidirectional data line. In 4-wire mode, this pin acts as the data input, and SDO acts as the data output. SERIAL PORT OPTIONS The serial port can support both MSB first and LSB first data formats. This functionality is controlled by the LSBFIRST bit (Register 0x000, Bit 6 and Bit 1). The default is MSB first (LSBFIRST = 0). When LSBFIRST = 0 (MSB first), the instruction and data bits must be written from MSB to LSB. R/W is followed by A[14:0] as the instruction word, and D[7:0] is the data-word. When LSBFIRST = 1 (LSB first), the opposite is true. A[0:14] is followed by R/W, which is subsequently followed by D[0:7]. The serial port supports a 3-wire or 4-wire interface. When SDOACTIVE = 1 (Register 0x000, Bit 4 and Bit 3), a 4-wire interface with a separate input pin (SDIO) and output pin (SDO) is used. When SDOACTIVE = 0, the SDO pin is unused and the SDIO pin is used for both input and output. Rev. C | Page 23 of 126 AD9144 Data Sheet To prevent confusion and to ensure consistency between devices, the chip tests the first nibble following the address phase, ignoring the second nibble. This is completed independently from the LSB first bit and ensures that there are extra clock cycles following the soft reset bits (Register 0x000, Bit 0 and Bit 7). This only applies when writing to Register 0x000. INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SDIO R/W A14 A13 A3 A2 A1 A0 D7 N D6N D5N D30 D20 D10 D00 11675-045 SCLK Figure 31. Serial Register Interface Timing, MSB First, ADDRINC = 0 INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK SDIO A0 A1 A2 A12 A13 A14 R/W D00 D10 D20 D4N D5 N D6 N D7N 11675-046 Multibyte data transfers can be performed as well. This is done by holding the CS pin low for multiple data transfer cycles (eight SCLKs) after the first data transfer word following the instruction cycle. The first eight SCLKs following the instruction cycle read from or write to the register provided in the instruction cycle. For each additional eight SCLK cycles, the address is either incremented or decremented and the read/write occurs on the new register. The direction of the address can be set using ADDRINC (Register 0x000, Bit 5 and Bit 2). When ADDRINC is 1, the multicycle addresses are incremented. When ADDRINC is 0, the addresses are decremented. A new write cycle can always be initiated by bringing CS high and then low again. Figure 32. Serial Register Interface Timing, LSB First, ADDRINC = 1 CS tDV SDIO DATA BIT n DATA BIT n – 1 Figure 33. Timing Diagram for Serial Port Register Read tSCS tHCS CS tPWH tPWL tDS SDIO tDH INSTRUCTION BIT 15 INSTRUCTION BIT 14 INSTRUCTION BIT 0 Figure 34. Timing Diagram for Serial Port Register Write Rev. C | Page 24 of 126 11675-047 SCLK 11675-048 SCLK Data Sheet AD9144 CHIP INFORMATION Register 0x003 to Register 0x006 contain chip information, as shown in Table 14. Table 14. Chip Information Information Chip Type Product ID Product Grade Device Revision Description The product type is high speed DAC, which is represented by a code of 0x04 in Register 0x003. 8 MSBs in Register 0x005 and 8 LSBs in Register 0x004. The product ID is 0x9144. Register 0x006[7:4]. The product grade is 0x00. Register 0x006[3:0]. The device revision is 0x08. Rev. C | Page 25 of 126 AD9144 Data Sheet DEVICE SETUP GUIDE OVERVIEW The sequence of steps to properly set up the AD9144 is as follows: 1. 2. 3. 4. 5. 6. Set up the SPI interface, power up necessary circuit blocks, make required writes to the configuration registers, and set up the DAC clocks (see the Step 1: Start Up the DAC section). Set the digital features of the AD9144 (see the Step 2: Digital Datapath section). Set up the JESD204B links (see the Step 3: Transport Layer section). Set up the physical layer of the SERDES interface (see the Step 4: Physical Layer section). Set up the data link layer of the SERDES interface (see the Step 5: Data Link Layer section). Check for errors (see the Step 6: Optional Error Monitoring section). Optionally, enable any needed features as described in the Step 7: Optional Features section. The registers in Table 16 must be written from their default values to be the values listed in the table for the device to work correctly. These registers must be written after any soft reset, hard reset, or power-up occurs. Table 16. Required Device Configurations Addr. 0x12D 0x146 0x2A4 0x232 0x333 Value 0x8B 0x01 0xFF 0xFF 0x01 If using the optional DAC PLL, also set the registers in Table 17. Table 17. Optional DAC PLL Configuration Procedure Addr. 0x087 Value1 0x62 0x088 0xC9 0x089 0x0E 0x08A 0x12 0x08D 0x7B 0x1B0 0x00 0x1B9 0x24 STEP 1: START UP THE DAC 0x1BC 0x0D This section describes how to set up the SPI interface, power up necessary circuit blocks, write required configuration registers, and set up the DAC clocks, as listed in Table 15. 0x1BE 0x02 0x1BF 0x8E 0x1C0 0x2A 0x1C1 0x2A 0x1C4 0x7E 0x08B 0x08C 0x085 Various 0x 0x 0x 0x 0x083 0x10 7. The register writes listed in Table 15 to Table 21 give the register writes necessary to set up the AD9144. Consider printing out this setup guide and filling in the Value column with appropriate variable values for the conditions of the desired application. The notation 0x, shaded in gray, indicates register settings that must be filled in by the user. To fill in the unknown register values, select the correct settings for each variable listed in the Variable column of Table 15 to Table 21. The Description column describes how to set variables or provides a link to a section where this is described. Table 15. Power-Up and DAC Initialization Settings Addr. 0x000 0x000 0x011 Bit No. 7 [6:3] 2 0x080 0x081 1 Value 0xBD 0x3C 0x 0 1 Variable PdDACs 0 0x 0x PdClocks PdSysref Description Soft reset. Deassert reset, set 4-wire SPI. Power up band gap. PdDACs = 0 if all 4 DACs are being used. If not, see the DAC Power-Down Setup section. Power up master DAC. PdClocks = 0 if all 4 DACs are being used. If not, see the DAC Power-Down Setup section. PdSysref = 0x00 for Subclass 1. PdSysref = 0x10 for Subclass 0. See the Subclass Setup section for details on subclass. Description Digital datapath configuration Digital datapath configuration Clock configuration SERDES interface configuration SERDES interface configuration Variable LODivMode RefDivMode BCount LookUpVals Description Optimal DAC PLL loop filter settings Optimal DAC PLL loop filter settings Optimal DAC PLL loop filter settings Optimal DAC PLL charge pump settings Optimal DAC LDO settings for DAC PLL Power DAC PLL blocks when power machine is disabled Optimal DAC PLL charge pump settings Optimal DAC PLL VCO control settings Optimal DAC PLL VCO power control settings Optimal DAC PLL VCO calibration settings Optimal DAC PLL lock counter length setting Optimal DAC PLL charge pump setting Optimal DAC PLL varactor settings See the DAC PLL Setup section See the DAC PLL Setup section See the DAC PLL Setup section See Table 25 in the DAC PLL Setup section for the list of register addresses and values for each. Enable DAC PLL2 0x denotes a register value that the user must fill in. See the Variable and Description columns for information on selecting the appropriate register value. 2 Verify that Register 0x084[1] reads back 1 after enabling the DAC PLL to indicate that the DAC PLL has locked. 1 0x denotes a register value that the user must fill in. See the Variable and Description columns for information on selecting the appropriate register value. Rev. C | Page 26 of 126 Data Sheet AD9144 STEP 2: DIGITAL DATAPATH Table 19. Transport Layer Settings This section describes which interpolation filters to use and how to set the data format being used. Additional digital features are available including fine and coarse modulation, digital gain scaling, and an inverse sinc filter used to improve pass-band flatness. Table 22 provides further details on the feature blocks available. Addr. 0x200 0x201 Addr. 0x112 Bit No. 0x110 Variable InterpMode Description Select interpolation mode; see the Interpolation section. DataFmt DataFmt = 0 if twos complement; DataFmt = 1 if unsigned binary. 0x 7 1 Value 0x 0x denotes a register value that the user must fill in. See the Variable and Description columns for information on selecting the appropriate register value. 0x 0x300 Table 18. Digital Datapath Settings 1 Bit No. Value1 Variable 0x00 UnusedLanes 0x 6 CheckSumMode 3 DualLink 2 CurrentLink 0x450 0x DID 0x451 0x BID 0x452 0x LID 0x453 See the JESD204B Setup section for details on these variables. Set DID to match the device ID sent by the transmitter. Set BID to match the bank ID sent by the transmitter. Set LID to match the lane ID sent by the transmitter. 0x 7 [4:0] This section describes how to set up the JESD204B links. The parameters are determined by the desired JESD204B operating mode. See the JESD204B Setup section for details. 0x454 0x Scrambling L − 12 F − 12 0x455 0x K − 12 Table 19 shows the register settings for the transport layer. If using dual-link mode, perform writes from Register 0x300 to Register 0x47D with CurrentLink = 0 and then repeat the same set of register writes with CurrentLink = 1 (Register 0x200 and Register 0x201 need only be written once). 0x456 0x M − 12 0x457 0x458 0x 0x N − 12 STEP 3: TRANSPORT LAYER Description Power up the interface. See the JESD204B Setup section. 5 Subclass [4:0] NP − 12 0x459 See the JESD204B Setup section. See the JESD204B Setup section. See the JESD204B Setup section. See the JESD204B Setup section. N = 16. See the JESD204B Setup section. NP = 16. 0x 5 JESDVer [4:0] S − 12 0x45A JESDVer = 1 for JESD204B, JESDVer = 0 for JESD204A. See the JESD204B Setup section. 0x 7 [4:0] HD 0x45D 0 0x CF Lane0Checksum 0x46C 0x Lanes 0x476 0x F 0x47D 0x Lanes See the JESD204B Setup section. CF must equal 0. See the JESD204B Setup section. Deskew lanes. See the JESD204B Setup section. See the JESD204B Setup section. Enable lanes. 0x denotes a register value that the user must fill in. See the Variable and Description columns for information on selecting the correct register value. 2 This JESD204B link parameter is programmed in n − 1 notation as noted. For example, if the setup requires L = 8 (8 lanes per link), program L − 1 or 7 into Register 0x453[4:0]. 1 Rev. C | Page 27 of 126 AD9144 Data Sheet STEP 4: PHYSICAL LAYER STEP 5: DATA LINK LAYER This section describes how to set up the physical layer of the SERDES interface. In this section, the input termination settings are configured along with the CDR sampling and SERDES PLL. This section describes how to set up the data link layer of the SERDES interface. This section deals with SYSREF processing, setting deterministic latency, and establishing the link. Table 20. Device Configurations and Physical Layer Settings Table 21. Data Link Layer Settings Addr. 0x2AA 0x2AB 0x2B1 0x2B2 0x2A7 0x2AE 0x314 0x230 Bit No. Value1 0xB7 0x87 0xB7 0x87 0x01 0x01 0x01 0x 5 [4:2] Halfrate 0x2 1 0x206 0x206 0x289 2 [1:0] OvSmp 0x00 0x01 0x 1 PLLDiv 0x284 0x285 0x286 0x287 0x62 0xC9 0x0E 0x12 0x28A 0x28B 0x7B 0x00 0x290 0x89 0x294 0x24 0x296 0x297 0x299 0x03 0x0D 0x02 0x29A 0x8E 0x29C 0x2A 0x29F 0x78 0x2A0 0x06 0x280 0x268 0x01 0x [7:6] [5:0] Variable EqMode 0x22 Description SERDES interface termination setting SERDES interface termination setting Autotune PHY setting Autotune PHY setting SERDES SPI configuration Set up CDR; see the SERDES Clocks Setup section SERDES PLL default configuration Set up CDR; see the SERDES Clocks Setup section Reset CDR Release CDR reset SERDES PLL configuration Set CDR oversampling for PLL; see the SERDES Clocks Setup section Optimal SERDES PLL loop filter Optimal SERDES PLL loop filter Optimal SERDES PLL loop filter Optimal SERDES PLL charge pump Optimal SERDES PLL VCO LDO Optimal SERDES PLL configuration Optimal SERDES PLL VCO varactor Optimal SERDES PLL charge pump Optimal SERDES PLL VCO Optimal SERDES PLL VCO Optimal SERDES PLL configuration Optimal SERDES PLL VCO varactor Optimal SERDES PLL charge pump Optimal SERDES PLL VCO varactor Optimal SERDES PLL VCO varactor Enable SERDES PLL2 See the Equalization Mode Setup section Required value (default) Addr. 0x301 Value1 0x Variable Subclass 0x304 0x LMFCDel 0x305 0x LMFCDel 0x306 0x LMFCVar 0x307 0x LMFCVar 0x03A 0x01 0x03A 0x81 0x03A 0xC1 SYSREF± Signal 0x308 to 0x30B 0x XBarVals 0x334 0x InvLanes 0x300 0x 6 3 2 CheckSumMode DualLink CurrentLink [1:0] EnLinks Description See the JESD204B Setup section. See the Link Latency Setup section. See the Link Latency section. See the Link Latency Setup section. See the Link Latency Setup section. Set sync mode = one-shot sync; see the Syncing LMFC Signals section for other sync options. Enable the sync machine. Arm the sync machine. If Subclass = 1, ensure that at least one SYSREF± edge is sent to the device.2 If remapping lanes, set up crossbar; see the Crossbar Setup section. Invert polarity of desired logical lanes. Bit x of InvLanes must be a 1 for each Logical Lane x to invert. Enable the links. See the JESD204B Setup section. Set to 0 to access Link 0 status or 1 for Link 1 status readbacks. See the JESD204B Setup section. EnLinks = 3 if DualLink = 1 (enables Link 0 and Link 1); EnLinks = 1 if DualLink = 0 (enables Link 0 only). 0x denotes a register value that the user must fill in. See the Variable and Description columns for information on selecting the correct register value. 2 Verify that Register 0x03B[3] reads back 1 after sending at least one SYSREF± edge to the device to indicate that the LMFC sync machine has properly locked. 1 0x denotes a register value that the user must fill in. See the Variable and Description columns for information on selecting the correct register value. 2 Verify that Register 0x281[0] reads back 1 after enabling the SERDES PLL to indicate that the SERDES PLL has locked. Rev. C | Page 28 of 126 1 Bit No. Data Sheet AD9144 Table 22. Optional Features STEP 6: OPTIONAL ERROR MONITORING Feature Digital Modulation Default Off STEP 7: OPTIONAL FEATURES Inverse Sinc On There are a number of optional features that can be enabled. Table 22 provides links to the sections describing each feature. These features can be enabled during the digital datapath configuration step or after the link is set up, because it is not required to configure them for the link to be established, unlike interpolation. Unless otherwise noted, these features are paged as described in the Dual Paging section. Paging is particularly important for dual specific settings like digital gain, phase adjust, and dc offset. Digital Gain 2.7 dB Phase Adjust Off DC Offset Off Group Delay 0 Downstream Protection Off Self Calibration Off For JESD204B error monitoring, see the JESD204B Error Monitoring section. For other error checks, see the Interrupt Request Operation section. Rev. C | Page 29 of 126 Description Modulates the data with a desired carrier. See the Digital Modulation section. Improves pass-band flatness. See the Inverse Sinc section. Multiplies data by a factor. Can compensate inverse sinc usage or balance I/Q amplitude. See the Digital Gain section. Used to balance I/Q phase. See the Phase Adjust section. Used to cancel LO leakage. See the DC Offset section. Used to control overall latency. See the Group Delay section. Used to protect downstream components. See the Downstream Protection section. Used to improve DAC linearity. Not paged by the dual paging register. See the Self Calibration section. AD9144 Data Sheet DAC PLL SETUP INTERPOLATION This section explains how to select the appropriate LODivMode, RefDivMode, and BCount in the Step 1: Start Up the DAC section. These parameters depend on the desired DAC clock frequency (fDACCLK) and DAC reference clock frequency (fREF). When using the DAC PLL, the reference clock signal is applied to the CLK± differential pins (Pin 2 and Pin 3). The transmit path can use zero to three cascaded interpolation filters, which each provides a 2× increase in output data rate and a low-pass function. Table 26 shows the different interpolation modes and the respective usable bandwidth along with the maximum fDATA rate attainable. Table 23. DAC PLL LODivMode Settings Interpolation Mode 1× (bypass) InterpMode 0x00 Usable Bandwidth 0.5 × fDATA 2× 0x01 0.4 × fDATA 4× 8× 0x03 0x04 0.4 × fDATA 0.4 × fDATA DAC Frequency Range (MHz) 1500 to 2800 750 to 1500 420 to 750 LODivMode, Register 0x08B[1:0] 1 2 3 Table 24. DAC PLL RefDivMode Settings DAC PLL Reference Frequency (fREF) (MHz) 35 to 80 80 to 160 160 to 320 320 to 640 640 to 1000 Divide by (RefDivFactor) 1 2 4 8 16 RefDivMode, Register 0x08C[2:0] 0 1 2 3 4 The VCO frequency (fVCO) is related to the DAC clock frequency according to the following equation: fVCO = fDACCLK × 2LODivMode + 1 where 6 GHz ≤ fVCO ≤ 12 GHz. BCount must be between 6 and 127 and is calculated based on fDACCLK and fREF as follows: BCount = floor((fDACCLK)/(2 × fREF/RefDivFactor)) where RefDivFactor = 2RefDivMode (see Table 24). Table 25. VCO Control Lookup Table Reference Register 0x1B5 Setting 0x08 0x09 0x09 Register 0x1BB Setting 0x03 0x03 0x13 Max fDATA (MHz) 1060 (SERDES limited) 1060 (SERDES limited) 700 350 The usable bandwidth is defined for 1×, 2×, 4×, and 8× modes as the frequency band over which the filters have a pass-band ripple of less than ±0.001 dB and an image rejection of greater than 85 dB. For more information, see the Interpolation Filters section. JESD204B SETUP This section explains how to select a JESD204B operating mode for a desired application. This section defines appropriate values for CheckSumMode, UnusedLanes, DualLink, CurrentLink, Scrambling, L, F, K, M, N, NP, Subclass, S, HD, Lane0Checksum, and Lanes needed for the Step 3: Transport Layer section. Note that DualLink, Scrambling, L, F, K, M, N, NP, S, HD, and Subclass must be set the same on the transmit side. For a summary of how a JESD204B system works and what each parameter means, see the JESD204B Serial Data Interface section. Available Operating Modes Finally, to finish configuring the DAC PLL, set the VCO control registers up as described in Table 25 based on the VCO frequency (fVCO). Write the registers listed in the table with the corresponding LookUpVals. VCO Frequency Range (GHz) fVCO < 6.3 6.3 ≤ fVCO < 7.25 fVCO ≥ 7.25 Table 26. Interpolation Modes and Their Usable Bandwidth Register 0x1C5 Setting 0x07 0x06 0x06 For more information on the DAC PLL, see the DAC Input Clock Configurations section. Table 27. JESD204B Operating Modes (Single-Link Only) Parameter M (Converter Count) L (Lane Count) S ((Samples per Converter) per Frame) F ((Octets per Frame) per Lane) 0 4 8 1 1 1 4 8 2 2 Mode 2 4 4 1 2 3 4 2 1 4 Table 28. JESD204B Operating Modes (Single- or Dual-Link) Parameter M (Converter Count) L (Lane Count) S ((Samples per Converter) per Frame) F ((Octets per Frame) per Lane) Rev. C | Page 30 of 126 4 2 4 1 1 5 2 4 2 2 Mode 6 7 2 2 2 1 1 1 2 4 9 1 2 1 1 10 1 1 1 2 Data Sheet AD9144 For a particular application, the number of converters to use (M) and the fDATA (DataRate) are known. The LaneRate and number of lanes (L) can be traded off as follows: DataRate = (DACRate)/(InterpolationFactor) LaneRate = (20 × DataRate × M)/L where LaneRate is between 1.44 Gbps and 12.4 Gbps. Octets per frame per lane (F) and samples per convertor per frame (S) define how the data is packed. If F = 1, the high density setting must be set to one (HD = 1). Otherwise, set HD = 0. Converter resolution and bits per sample (N and NP) must both be set to 16. Frames per multiframe (K) must be set to 32 for Mode 0, Mode 4 and Mode 9. Other modes can use either K = 16 or K = 32. DualLink DualLink sets up two independent JESD204B links, which allows each link to be reset independently. If this functionality is desired, set DualLink to 1; if a single link is desired, set DualLink to 0. Note that Link 0 and Link 1 must have identical parameters. The operating modes available when using dual-link mode are shown in Table 28. In addition to these operating modes, the modes in Table 28 can also be used when using single-link mode. Scrambling Scrambling is a feature that makes the spectrum of the link data independent. This avoids spectral peaking and provides some protection against data dependent errors caused by frequency selective effects in the electrical interface. Set to 1 if scrambling is being used, or to 0 if it is not. Subclass Subclass determines whether the latency of the device is deterministic, meaning it requires an external synchronization signal. See the Subclass Setup section for more information. CurrentLink Set CurrentLink to either 0 or 1 depending on whether Link 0 or Link 1, respectively, needs to be configured. Lanes Lanes is used to enable and deskew particular lanes in two thermometer coded registers. CheckSumMode CheckSumMode must match the checksum mode used on the transmit side. If the checksum used is the sum of fields in the link configuration table, CheckSumMode = 0. If summing the registers containing the packed link configuration fields, CheckSumMode = 1. For more information on the how to calculate the two checksum modes, see the Lane0Checksum section. Lane0Checksum Lane0Checksum can be used for error checking purposes to ensure that the transmitter is set up as expected. Both CheckSumMode calculations use the fields contained in Register 0x450 to Register 0x45A. Select whether to sum by fields or by registers, matching the setting on the transmitter. If CheckSumMode = 0, the summation is computed by fields. The checksum is the lower 8 bits of the sum of the DID, ADJCNT, BID, ADJDIR, PHADJ, LID, Scrambling, L – 1, F − 1, K − 1, M − 1, CS, N − 1, Subclass, NP − 1, JESDVer, S − 1, HD, and CF variables. If CheckSumMode = 1, the summation is computed by registers. The checksum is the sum of Register 0x450 to Register 0x45A, Modulo 256. DAC Power-Down Setup As described in the Step 1: Start Up the DAC section, PdDACs must be set to 0 if all 4 converters are being used. If fewer than four converters are being used, the unused converters must be powered down. Table 29 can be used to determine which DACs are powered down based on the number of converters per link (M) and whether the device is in DualLink mode. Table 29. DAC Power-Down Configuration Settings M (Converters per link) 1 1 2 2 4 DualLink 0 1 0 1 0 DACs to Power Down 0 1 2 3 0 1 1 1 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 PdDACs 0b0111 0b0101 0b0011 0b0000 0b0000 PdClocks Lanes = (2L) − 1. UnusedLanes UnusedLanes is used to turn off unused circuit blocks to save power. Each physical lane that is not being used (SERDINx±) must be powered off by writing a 1 to the corresponding bit of Register 0x201. If both DACs in DAC Dual B (DAC2 and DAC3) are powered down, the clock for DAC Dual B can be powered down. In this case, PdClocks = 0x40; if not, PdClocks = 0x00. For example, if using Mode 6 in dual-link mode and sending data on SERDIN0±, SERDIN1±, SERDIN4±, and SERDIN5±, set UnusedLanes = 0xCC to power off Physical Lane 2, Lane 3, Lane 6, and Lane 7. Rev. C | Page 31 of 126 AD9144 Data Sheet SERDES CLOCKS SETUP This section describes how to select the appropriate Halfrate, OvSmp, and PLLDiv settings in the Step 4: Physical Layer section. These parameters depend solely on the lane rate (the lane rate is established in the JESD204B Setup section). Table 30. SERDES Lane Rate Configuration Settings Lane Rate (Gbps) 1.44 to 3.1 2.88 to 6.2 5.75 to 12.4 Halfrate 0 0 1 OvSmp 1 0 0 PLLDiv 2 1 0 Delays that are not in PClock cycles must be converted before they are used. Some useful internal relationships are defined as follows: PClockPeriod = 40/LaneRate The PClockPeriod can be used to convert from time to PClock cycles when needed. PClockFactor = 4/F (frames per PClock) The PClockFactor is used to convert from units of PClock cycles to frame clock cycles, which is needed to set LMFCDel in Subclass 1. Halfrate and OvSmp set how the clock detect and recover (CDR) circuit sample. See the SERDES PLL section for an explanation of how that circuit blocks works and the role of PLLDiv in the block. PClocksPerMF = K/PClockFactor (PClocks per LMFC cycle) where PClocksPerMF is the number or PClock cycles in a multiframe cycle. EQUALIZATION MODE SETUP Set EqMode = 1 for a low power setting. Select this mode if the insertion loss in the printed circuit board (PCB) is less than 12 dB. For insertion losses greater than 12 dB, but less than 17.5 dB, set EqMode = 0. More details can be found in the Equalization section. LINK LATENCY SETUP This section describes the steps necessary to guarantee multichip deterministic latency in Subclass 1 and to guarantee synchronization of links within a device in Subclass 0. Use this section to fill in LMFCDel, LMFCVar, and Subclass in the Step 5: Data Link Layer section. For more information, see the Syncing LMFC Signals section. The values for PClockFactor and PClockPerMF are given per JESD mode in Table 31 and Table 32. Table 31. PClockFactor and PClockPerMF per LMFC JESD Mode ID PClockFactor PClockPerMF (K = 32) PClockPerMF (K = 16) 1 0 4 8 N/A1 1 2 16 8 2 2 16 8 3 1 32 16 N/A means not applicable. Table 32. PClockFactor and PClockPerMF per LMFC JESD Mode ID PClockFactor PClockPerMF (K = 32) PClockPerMF (K = 16) Subclass Setup 1 The AD9144 supports JESD204B Subclass 0 and Subclass 1 operation. With Known Delays 4 4 8 N/A1 5 2 16 8 6 2 16 8 7 1 32 16 9 4 8 N/A1 10 2 16 8 N/A means not applicable. With information about all the system delays, LMFCVar and LMFCDel can be calculated directly. Subclass 1 This mode gives deterministic latency and allows links to be synced to within ½ DAC clock periods. It requires an external SYSREF± signal that is accurately phase aligned to the DAC clock. Subclass 0 This mode does not require any signal on the SYSREF± pins (the pins can be left disconnected). Subclass 0 still requires that all lanes arrive within the same LMFC cycle and that the dual DACs must be synchronized to each other (they are synchronized to an internal clock instead of to the SYSREF± signal). RxFixed (the fixed receiver delay in PClock cycles) and RxVar (the variable receiver delay in PClock cycles) can be found in Table 8. TxFixed (the fixed transmitter delay in PClock cycles) and TxVar (the variable receiver delay in PClock cycles) can be found in the data sheet of the transmitter used. PCBFixed (the fixed PCB trace delay in PClock cycles) can be extracted from software; because this is generally much smaller than a PClock cycle, it can also be omitted. For both the PCB and transmitter delays, convert the delays into PClock cycles. For each lane MinDelayLane = floor(RxFixed + TxFixed + PCBFixed) Set Subclass to 0 or 1 as desired. MaxDelayLane = ceiling(RxFixed + RxVar + TxFixed + TxVar + PCBFixed)) Link Delay Setup LMFCVar and LMFCDel are used to impose delays such that all lanes in a system arrive in the same LMFC cycle. The unit used internally for delays is the period of the internal processing clock (PClock), whose rate is 1/40th the lane rate. where: MinDelay is the minimum of all MinDelayLane values across lanes, links, and devices. MaxDelay is the maximum of all MaxDelayLane values across lanes, links, and devices. Rev. C | Page 32 of 126 Data Sheet AD9144 For safety, add a guard band of 1 PClock cycle to each end of the link delay as in the following equations: LMFCVar = (MaxDelay + 1) − (MinDelay − 1) Note that if LMFCVar must be more than 10, the AD9144 is unable to tolerate the variable delay in the system. For Subclass 1 LMFCDel = ((MinDelay − 1) × PClockFactor) % K For Subclass 0 LMFCDel = (MinDelay − 1) % PClockPerMF Program the same LMFCDel and LMFCVar across all links and devices. See the Link Delay Setup Example, with Known Delays section for an example calculation. Table 33. Register Configuration and Procedure for OneShot Sync Addr. 0x301 0x03A Bit. No. Value1 0x 0x01 0x03A 0x81 0x03A 0xC1 Variable Subclass SYSREF± Signal 0x300 Without Known Delays If comprehensive delay information is not available or known, the AD9144 can read back the link latency between the LMFCRX and the last arriving LMFC boundary in PClock cycles. This information is then used to calculate LMFCVar and LMFCDel. 0x 6 CheckSumMode 3 DualLink 2 CurrentLink [1:0] EnLinks For each link (on each device) 1. 2. 3. 4. 5. Power up the board. Follow the steps in Table 15 through Table 21 of the Device Setup Guide. Set the subclass and perform a sync. For one-shot sync, perform the writes in Table 33. See the Syncing LMFC Signals section for alternate sync modes. Record DYN_LINK_LATENCY_0 (Register 0x302) as a value of Delay for that link and power cycle. Record DYN_LINK_LATENCY_1 (Register 0x303) as a value of Delay for that link and power cycle the system. Repeat Step 1 to Step 5 twenty times for each device in the system. Keep a single list of the Delay values across all runs and devices. 1 Description Set subclass Set sync mode to one-shot sync Enable the sync machine Arm the sync machine If Subclass = 1, ensure that at least one SYSREF± edge is sent to the device. Enable the links See the JESD204B Setup section See the JESD204B Setup section Set to 0 to access Link 0 status or 1 for Link 1 status readbacks. See the JESD204B Setup section. EnLinks = 3 if in DualLink mode to enable Link 0 and Link 1; EnLinks = 1 if not in DualLink mode to enable Link 0 0x denotes a register value that the user must fill in. See the Variable and Description columns for information on selecting the appropriate register value. The list of delay values is used to calculate LMFCDel and LMFCVar; however, first some of the delay values may need to be remapped. The maximum possible value for DYN_LINK_LATENCY_x is one less than the number of PClocks in a multiframe (PClocksPerMF). It is possible that a rollover condition may be encountered, meaning the set of recorded Delay values might roll over the edge of a multiframe. If so, Delay values may be near both 0 and PClocksPerMF. If this occurs, add PClocksPerMF to the set of values near 0. For example, for Delay value readbacks of 6, 7, 0, and 1, the 0 and 1 Delay values must be remapped to 8 and 9, making the new set of Delay values 6, 7, 8, and 9. Rev. C | Page 33 of 126 AD9144 Data Sheet Across power cycles, links, and devices CROSSBAR SETUP • • Register 0x308 to Register 0x30B allow arbitrary mapping of physical lanes (SERDINx±) to logical lanes used by the SERDES deframers. MinDelay is the minimum of all Delay measurements MaxDelay is the maximum of all Delay measurements For safety, a guard band of 1 PClock cycle is added to each end of the link delay and calculate LMFCVar and LMFCDel with the following equation: LMFCVar = (MaxDelay + 1) − (MinDelay − 1) Note that if LMFCVar must be more than 10, the AD9144 is unable to tolerate the variable delay in the system. For Subclass 1 LMFCDel = ((MinDelay − 1) × PClockFactor) % K For Subclass 0 LMFCDel = (MinDelay − 1) % PClockPerMF Program the same LMFCDel and LMFCVar across all links and devices. See the Link Delay Setup Example, Without Known Delay section for an example calculation. Table 34. Crossbar Registers Address 0x308 0x308 0x309 0x309 0x30A 0x30A 0x30B 0x30B Bits [2:0] [5:3] [2:0] [5:3] [2:0] [5:3] [2:0] [5:3] Logical Lane LOGICAL_LANE0_SRC LOGICAL_LANE1_SRC LOGICAL_LANE2_SRC LOGICAL_LANE3_SRC LOGICAL_LANE4_SRC LOGICAL_LANE5_SRC LOGICAL_LANE6_SRC LOGICAL_LANE7_SRC Write each LOGICAL_LANEy_SRC with the number (x) of the desired physical lane (SERDINx±) from which to obtain data. By default, all logical lanes use the corresponding physical lane as their data source. For example, by default LOGICAL_LANE0_ SRC = 0, meaning that Logical Lane 0 receives data from Physical Lane 0 (SERDIN0±). If instead the user wants to use SERDIN4± as the source for Logical Lane 0, the user must write LOGICAL_LANE0_SRC = 4. Rev. C | Page 34 of 126 Data Sheet AD9144 JESD204B SERIAL DATA INTERFACE JESD204B OVERVIEW Only certain combinations of parameters are supported. Each supported combination is called a mode. In total, there are 10 single-link modes supported by the AD9144, as described in Table 35. In dual-link mode, there are six supported modes, as described in Table 36. Each of these tables shows the associated clock rates when the lane rate is 10 Gbps. The AD9144 has eight JESD204B data ports that receive data. The eight JESD204B ports can be configured as part of a single JESD204B link or as part of two separate JESD204B links (duallink mode) that share a single system reference (SYSREF±) and device clock (CLK±). For a particular application, the number of converters to use (M) and the DataRate are known. The LaneRate and number of lanes (L) can be traded off as follows: The JESD204B serial interface hardware consists of three layers: the physical layer, the data link layer, and the transport layer. These sections of the hardware are described in subsequent sections, including information for configuring every aspect of the interface. Figure 35 shows the communication layers implemented in the AD9144 serial data interface to recover the clock and deserialize, descramble, and deframe the data before it is sent to the digital signal processing section of the device. DataRate = (DACRate)/(InterpolationFactor) LaneRate = (20 × DataRate × M)/L where LaneRate must be between 1.44 Gbps and 12.4 Gbps. Achieving and recovering synchronization of the lanes is very important. To simplify the interface to the transmitter, the AD9144 designates a master synchronization signal for each JESD204B link. In single-link mode, SYNCOUT0± is used as the master signal for all lanes; in dual-link mode, SYNCOUT0± is used as the master signal for Link 0, and SYNCOUT1± is used as the master signal for Link 1. If any lane in a link loses synchronization, a resynchronization request is sent to the transmitter via the synchronization signal of the link. The transmitter stops sending data and instead sends synchronization characters to all lanes in that link until resynchronization is achieved. The physical layer is responsible for establishing a reliable channel between the transmitter and the receiver, the data link layer is responsible for unpacking the data into octets and descrambling the data, and the transport layer receives the descrambled JESD204B frames and converts them to DAC samples. There are a number of JESD204B parameters (L, F, K, M, N, NP, S, HD, and Scrambling) that define how the data is packed and tell the device how to turn the serial data into samples. These parameters are defined in detail in the Transport Layer section. SYNCOUT0± SYNCOUT1± DATA LINK LAYER PHYSICAL LAYER SERDIN0± TRANSPORT LAYER DESERIALIZER TO DAC FRAME TO SAMPLES QBD/ DESCRAMBLER SERDIN7± DUAL A I DATA[15:0] DUAL A Q DATA[15:0] DUAL B I DATA[15:0] DESERIALIZER 11675-004 DUAL B Q DATA[15:0] SYSREF± Figure 35. Functional Block Diagram of Serial Link Receiver Table 35. Single-Link JESD204B Operating Modes Parameter M (Converter Counts) L (Lane Counts) S (Samples per Converter per Frame) F (Octets per Frame per Lane) Example Clocks for 10 Gbps Lane Rate PClock (MHz) Frame Clock (MHz) Sample Clock (MHz) 0 4 8 1 1 1 4 8 2 2 2 4 4 1 2 3 4 2 1 4 4 2 4 1 1 250 1000 1000 250 500 1000 250 500 500 250 250 250 250 1000 1000 Rev. C | Page 35 of 126 Mode 5 2 4 2 2 250 500 1000 6 2 2 1 2 7 2 1 1 4 9 1 2 1 1 10 1 1 1 2 250 500 500 250 250 250 250 1000 1000 250 500 500 AD9144 Data Sheet Table 36. Dual-Link JESD204B Operating Modes for Link 0 and Link 1 Mode Parameter M (Converter Counts) L (Lane Counts) S (Samples per Converter per Frame) F (Octets/Frame per Lane) Example Clock for 10 Gbps Lane Rate PClock (MHz) Frame Clock (MHz) Sample Clock (MHz) 4 2 4 1 1 5 2 4 2 2 6 2 2 1 2 7 2 1 1 4 9 1 2 1 1 10 1 1 1 2 250 1000 1000 250 500 1000 250 500 500 250 250 250 250 1000 1000 250 500 500 PHYSICAL LAYER Table 37. PHY Termination Autocalibration Routine The physical layer of the JESD204B interface, hereafter referred to as the deserializer, has eight identical channels. Each channel consists of the terminators, an equalizer, a clock and data recovery (CDR) circuit, and the 1:40 demux function (see Figure 36). Address 0x2AA 0x2AB 0x2B1 0x2B2 0x2A7 0x2AE TERMINATION EQUALIZER CDR 1:40 11675-006 SPI CONTROL FROM SERDES PLL Figure 36. Deserializer Block Diagram JESD204B data is input to the AD9144 via the SERDINx± 1.2 V differential input pins as per the JESD204B specification. Interface Power-Up and Input Termination Before using the JESD204B interface, it must be powered up by setting Register 0x200[0] = 0. In addition, each physical lane that is not being used (SERDINx±) must be powered down. To do so, set the corresponding Bit x for Physical Lane x in Register 0x201 to 0 if the physical lane is being used, and to 1 if it is not being used. Description SERDES interface termination configuration SERDES interface termination configuration SERDES interface termination configuration SERDES interface termination configuration Autotune PHY terminations Autotune PHY terminations The input termination voltage of the DAC is sourced externally via the VTT pins (Pin 21, Pin 23, Pin 40, and Pin 43). Set VTT by connecting it to SVDD12. It is recommended that the JESD204B inputs be ac-coupled to the JESD204B transmit device using 100 nF capacitors. Receiver Eye Mask The AD9144 complies with the JESD204B specification regarding the receiver eye mask and is capable of capturing data that complies with this mask. Figure 37 shows the receiver eye mask normalized to the data rate interval with a 600 mV VTT swing. See the JESD204B specification for more information regarding the eye mask and permitted receiver eye opening. The AD9144 autocalibrates the input termination to 50 Ω. Before running the termination calibration, Register 0x2AA, Register 0x2AB, Register 0x2B1, and Register 0x2B2 must be written as described in Table 37 to guarantee proper calibration. The termination calibration begins when Register 0x2A7[0] and Register 0x2AE[0] transition from low to high. Register 0x2A7 controls autocalibration for PHY 0, PHY 1, PHY 6, and PHY 7. Register 0x2AE controls autocalibration for PHY 2, PHY 3, PHY 4, and PHY 5. The PHY termination autocalibration routine is as shown in Table 37. Rev. C | Page 36 of 126 LV-OIF-11G-SR RECEIVER EYE MASK 525 55 0 –55 –525 0 0.35 0.5 0.65 TIME (UI) Figure 37. Receiver Eye Mask 1.00 11675-007 SERDINx± AMPLITUDE (mV) DESERIALIZER Value 0xB7 0x87 0xB7 0x87 0x01 0x01 Data Sheet AD9144 Clock Relationships Register 0x280 controls the synthesizer enable and recalibration. The following clocks rates are used throughout the rest of the JESD204B section. The relationship between any of the clocks can be derived from the following equations: To enable the SERDES PLL, first set the PLL divider register according to Table 38, then enable the SERDES PLL by writing Register 0x280[0] to 1. DataRate = (DACRate)/(InterpolationFactor) Confirm that the SERDES PLL is working by reading Register 0x281. If Register 0x281[0] = 1, the SERDES PLL has locked. If Register 0x281[3] = 1, the SERDES PLL was successfully calibrated. If Register 0x281[4] or Register 0x281[5] are high, the PLL hit the upper or lower end of its calibration band and must be recalibrated by writing 0 and then 1 to Register 0x280[2]. LaneRate = (20 × DataRate × M)/L ByteRate = LaneRate/10 This comes from 8-bit/10-bit encoding, where each byte is represented by 10 bits. PClockRate = ByteRate/4 SERDES PLL Fixed Register Writes The processing clock is used for a quad-byte decoder. To optimize the SERDES PLL across all operating conditions, the register writes in Table 39 are recommended. FrameRate = ByteRate/F where F is defined as (bytes per frame) per lane. Table 39. SERDES PLL Fixed Register Writes PClockFactor = FrameRate/PClockRate = 4/F where: M is the JESD204B parameter for converters per link. L is the JESD204B parameter for lanes per link. F is the JESD204B parameter for octets per frame per lane. SERDES PLL Functional Overview of the SERDES PLL The independent SERDES PLL uses integer-N techniques to achieve clock synthesis. The entire SERDES PLL is integrated on-chip, including the VCO and the loop filter. The SERDES PLL VCO operates over the range of 5.65 GHz to 12.4 GHz. In the SERDES PLL, a VCO divider block divides the VCO clock by 2 to generate a 2.825 GHz to 6.2 GHz quadrature clock for the deserializer cores. This clock is the input to the clock and data recovery block that is described in the Clock and Data Recovery section. The reference clock to the SERDES PLL is always running at a frequency, fREF = 1/40 of the lane rate = PClockRate. This clock is divided by a DivFactor to deliver a clock to the PFD block that is between 35 MHz and 80 MHz. Table 38 includes the respective SERDES_PLL_DIV_MODE register settings for each of the desired DivFactor options available. Register Address 0x284 0x285 0x286 0x287 0x28A 0x28B 0x290 0x294 0x296 0x297 0x299 0x29A 0x29C 0x29F 0x2A0 Divide by (DivFactor) 1 2 4 Description Optimal SERDES PLL loop filter Optimal SERDES PLL loop filter Optimal SERDES PLL loop filter Optimal SERDES PLL charge pump Optimal SERDES PLL VCO LDO Optimal SERDES PLL configuration Optimal SERDES PLL VCO varactor Optimal SERDES PLL charge pump Optimal SERDES PLL VCO Optimal SERDES PLL VCO Optimal SERDES PLL configuration Optimal SERDES PLL VCO varactor Optimal SERDES PLL charge pump Optimal SERDES PLL VCO varactor Optimal SERDES PLL VCO varactor SERDES PLL IRQ SERDES PLL lock and lost signals are available as IRQ events. Use Register 0x01F[3:2] to enable these signals, and then use Register 0x023[3:2] to read back their statuses and reset the IRQ signals. See the Interrupt Request Operation section for more information. Table 38. SERDES PLL Divider Settings LaneRate (Gbps) 1.44 to 3.1 2.88 to 6.2 5.75 to 12.4 Register Value 0x62 0xC9 0x0E 0x12 0x7B 0x00 0x89 0x24 0x03 0x0D 0x02 0x8E 0x2A 0x78 0x06 SERDES_PLL_DIV_MODE, Register 0x289[1:0] 2 1 0 Rev. C | Page 37 of 126 AD9144 Data Sheet 2.825GHz TO 6.2GHz OUTPUT VCO LDO CHARGE PUMP I Q PFD 80MHz MAX fREF BIT RATE ÷ 40 DivFactor (1, 2, 4) C1 R1 UP C2 C3 LC VCO 5.65GHz TO 12.4GHz ÷2 DOWN ÷80 R3 ALC CAL CAL CONTROL BITS 11675-011 FO CAL 3.2mA Figure 38. SERDES PLL Synthesizer Block Diagram Including VCO Divider Block Clock and Data Recovery Equalization The deserializer is equipped with a CDR circuit. Instead of recovering the clock from the JESD204B serial lanes, the CDR recovers the clocks from the SERDES PLL. The 2.825 GHz to 6.2 GHz output from the SERDES PLL, shown in Figure 38, is the input to the CDR. To compensate for signal integrity distortions for each PHY channel due to PCB trace length and impedance, the AD9144 employs an easy to use, low power equalizer on each JESD204B channel. The AD9144 equalizers can compensate for insertion losses far greater than required by the JESD204B specification. The equalizers have two modes of operation that are determined by the EQ_POWER_MODE register setting in Register 0x268[7:6]. In low power mode (Register 0x268[7:6] = 2b’01) and operating at the maximum lane rate of 10 Gbps, the equalizer can compensate for up to 12 dB of insertion loss. In normal mode (Register 0x268[7:6] = 2b’00), the equalizer can compensate for up to 17.5 dB of insertion loss. This performance is shown in Figure 39 as an overlay to the JESD204B specification for insertion loss. Figure 39 shows the equalization performance at 10.0 Gbps, near the maximum baud rate for the AD9144. A CDR sampling mode must be selected to generate the lane rate clock inside the device. If the desired lane rate is greater than 5.65 GHz, half rate CDR operation must be used. If the desired lane rate is less than 5.65 GHz, disable half rate operation. If the lane rate is less than 2.825 GHz, disable half rate and enable 2× oversampling to recover the appropriate lane rate clock. Table 40 gives a breakdown of CDR sampling settings that must be set dependent on the LaneRate. Table 40. CDR Operating Modes LaneRate (Gbps) 1.44 to 3.1 2.88 to 6.2 5.75 to 12.4 ENHALFRATE, Register 0x230[5] 0 0 1 CDR_OVERSAMP, Register 0x230[1] 1 0 0 The CDR circuit synchronizes the phase used to sample the data on each serial lane independently. This independent phase adjustment per serial interface ensures accurate data sampling and eases the implementation of multiple serial interfaces on a PCB. After configuring the CDR circuit, reset it and then release the reset by writing 1 and then 0 to Register 0x206[0]. Power-Down Unused PHYs Note that any unused and enabled lanes consume extra power unnecessarily. Each lane that is not being used (SERDINx±) must be powered off by writing a 1 to the corresponding bit of PHY_PD (Register 0x201). Figure 40 and Figure 41 are provided as points of reference for hardware designers and show the insertion loss for various lengths of well laid out stripline and microstrip transmission lines. See the Hardware Considerations section for specific layout recommendations for the JESD204B channel. Low power mode is recommended if the insertion loss of the JESD204B PCB channels is less than that of the most lossy supported channel for lower power mode (shown in Figure 39). If the insertion loss is greater than that, but still less than that of the most lossy supported channel for normal mode (shown in Figure 39), use normal mode. At 10 Gbps operation, the EQ in normal mode consumes about 4 mW more power per lane used than in low power EQ mode. Note that either mode can be used in conjunction with transmitter preemphasis to ensure functionality and/or to optimize for power. Rev. C | Page 38 of 126 Data Sheet AD9144 DATA LINK LAYER 0 JESD204B SPEC ALLOWED CHANNEL LOSS 2 EXAMPLE OF JESD204B COMPLIANT CHANNE L INSERTION LOSS (dB) 4 6 AD9144 ALLOWED CHANNEL LOSS (LOW POWER MODE) 8 EXAMPLE OF AD9144 COMPATIBLE CHANNEL (LOW POWER MODE) 10 12 14 EXAMPLE OF AD9144 COMPATIBLE CHANNEL (NORMAL MODE) AD9144 ALLOWED CHANNEL LOSS (NORMAL MODE) 16 The data link layer of the AD9144 JESD204B interface accepts the deserialized data from the PHYs and deframes and descrambles them so that data octets are presented to the transport layer to be put into DAC samples. Figure 42 shows the link mode block diagrams for single-link and dual-link configurations and the interaction between the physical layer and logical layer. The logical lanes and DACs can only be configured in sequential order; for example in Mode 10, when in single-link mode, the AD9144 only uses Logical Lane 0 and DAC0, and in dual-link mode, only uses Logical Lane 0, Logical Lane 1 and DAC0, DAC1. See the Mode Configuration Maps section for further details on each of the mode configurations supported. The architecture of the data link layer is shown in Figure 43. The data link layer consists of a synchronization FIFO for each lane, a crossbar switch, a deframer, and descrambler. 18 20 22 2.5 5.0 11675-339 24 7.5 FREQUENCY (GHz) Figure 39. Insertion Loss Allowed 0 The AD9144 can operate as a single-link or dual-link high speed JESD204B serial data interface. When operating in duallink mode, configure both links with the same JESD204B parameters because they share a common device clock and system reference. All eight lanes of the JESD204B interface handle link layer communications such as code group synchronization, frame alignment, and frame synchronization. –5 ATTENUATION (dB) –10 –15 –20 STRIPLINE = 6” STRIPLINE = 10” STRIPLINE = 15” STRIPLINE = 20” STRIPLINE = 25” STRIPLINE = 30” –25 –30 –40 0 1 2 3 4 5 6 7 8 9 10 FREQUENCY (GHz) 11675-010 –35 Figure 40. Insertion Loss of 50 Ω Striplines on FR4 0 –5 –15 –20 6” MICROSTRIP 10” MICROSTRIP 15” MICROSTRIP 20” MICROSTRIP 25” MICROSTRIP 30” MICROSTRIP –25 –30 –35 –40 0 1 2 3 4 5 6 7 8 9 FREQUENCY (GHz) 10 11675-011 ATTENUATION (dB) –10 The AD9144 decodes 8-bit/10-bit control characters, allowing marking of the start and end of the frame and alignment between serial lanes. Each AD9144 serial interface link can issue a synchronization request by setting its SYNCOUT0±/SYNCOUT1± signal low. The synchronization protocol follows Section 4.9 of the JESD204B standard. When a stream of four consecutive /K/ symbols is received, the AD9144 deactivates the synchronization request by setting the SYNCOUT0±/SYNCOUT1± signal high at the next internal LMFC rising edge. Then, it waits for the transmitter to issue an ILAS. During the ILAS sequence, all lanes are aligned using the /A/ to /R/ character transition as described in the JESD204B Serial Link Establishment section. Elastic buffers hold early arriving lane data until the alignment character of the latest lane arrives. At this point, the buffers for all lanes are released and all lanes are aligned (see Figure 44). Figure 41. Insertion Loss of 50 Ω Microstrips on FR4 Rev. C | Page 39 of 126 AD9144 Data Sheet PHYSICAL LAYER (PHY) LOGICAL LAYER CROSSBAR QBD SERDIN0±/PHYSICAL LANE 0 LOGICAL LANE 0/LINK 0 LANE 0 SERDIN1±/PHYSICAL LANE 1 LOGICAL LANE 1/LINK 0 LANE 1 DAC CORE SINGLE-LINK MODE DAC0 LOGICAL LANE 2/LINK 0 LANE 2 SERDIN2±/PHYSICAL LANE 2 SERDIN3±/PHYSICAL LANE 3 SERDIN4±/PHYSICAL LANE 4 SERDIN5±/PHYSICAL LANE 5 CROSSBAR REGISTER 0x308 TO REGISTER 0x30B DAC1 LOGICAL LANE 3/LINK 0 LANE 3 QUAD-BYTE DEFRAMER (QBD0) LOGICAL LANE 4/LINK 0 LANE 4 DAC2 LOGICAL LANE 5/LINK 0 LANE 5 SERDIN6±/PHYSICAL LANE 6 LOGICAL LANE 6/LINK 0 LANE 6 SERDIN7±/PHYSICAL LANE 7 LOGICAL LANE 7/LINK 0 LANE 7 DAC3 LOGICAL LANES PHYSICAL LANES SERDIN0±/PHYSICAL LANE 0 LOGICAL LANE 0/LINK 0 LANE 0 SERDIN1±/PHYSICAL LANE 1 LOGICAL LANE 1/LINK 0 LANE 1 SERDIN2±/PHYSICAL LANE 2 LOGICAL LANE 2/LINK 0 LANE 2 CROSSBAR SERDIN3±/PHYSICAL LANE 3 SERDIN4±/PHYSICAL LANE 4 SERDIN5±/PHYSICAL LANE 5 REGISTER 0x308 TO REGISTER 0x30B QUAD-BYTE DEFRAMER 0 (QBD0) DAC1 LOGICAL LANE 3/LINK 0 LANE 3 LOGICAL LANE 4/LINK 1 LANE 0 DAC2 LOGICAL LANE 5/LINK 1 LANE 1 SERDIN6±/PHYSICAL LANE 6 LOGICAL LANE 6/LINK 1 LANE 2 SERDIN7±/PHYSICAL LANE 7 LOGICAL LANE 7/LINK 1 LANE 3 QUAD-BYTE DEFRAMER 1 (QBD1) DAC3 11675-442 LOGICAL LANES PHYSICAL LANES Figure 42. Link Mode Functional Diagram DATA LINK LAYER SYNCOUTx± LANE 0 DATA CLOCK SERDIN0 FIFO CROSS BAR SWITCH LANE 7 DESERIALIZED AND DESCRAMBLED DATA SYSREF SERDIN7 FIFO LANE0 OCTETS LANE7 OCTETS SYSTEM CLOCK PHASE DETECT 11675-012 LANE 7 DATA CLOCK DESCRAMBLE QUAD-BYTE DEFRAMER QBD LANE 0 DESERIALIZED AND DESCRAMBLED DATA 10-BIT/8-BIT DECODE DUAL-LINK MODE DAC0 PCLK SPI CONTROL Figure 43. Data Link Layer Block Diagram Rev. C | Page 40 of 126 Data Sheet AD9144 L RECEIVE LANES (EARLIEST ARRIVAL) K K K R D D D D A R Q C L RECEIVE LANES (LATEST ARRIVAL) K K K K K K K R D D C D D A R Q C D D A R D D C D D A R D D 0 CHARACTER ELASTIC BUFFER DELAY OF LATEST ARRIVAL 4 CHARACTER ELASTIC BUFFER DELAY OF EARLIEST ARRIVAL L ALIGNED RECEIVE LANES K K K K K K K R D D D D A R Q C C 11675-013 K = K28.5 CODE GROUP SYNCHRONIZATION COMMA CHARACTER A = K28.3 LANE ALIGNMENT SYMBOL F = K28.7 FRAME ALIGNMENT SYMBOL R = K28.0 START OF MULTIFRAME Q = K28.4 START OF LINK CONFIGURATION DATA C = JESD204B LINK CONFIGURATION PARAMETERS D = Dx.y DATA SYMBOL D D A R D D Figure 44. Lane Alignment During ILAS JESD204B Serial Link Establishment A brief summary of the high speed serial link establishment process for Subclass 1 is provided. See Section 5.3.3 of the JESD204B specifications document for complete details. After the last /A/ character of the last ILAS, multiframe data begins streaming. The receiver adjusts the position of the /A/ character such that it aligns with the internal LMFC of the receiver at this point. Step 1: Code Group Synchronization Step 3: Data Streaming Each receiver must locate K (K28.5) characters in its input data stream. After four consecutive K characters are detected on all link lanes, the receiver block deasserts the SYNCOUTx± signal to the transmitter block at the receiver local multiframe clock (LMFC) edge. In this phase, data is streamed from the transmitter block to the receiver block. The transmitter captures the change in the SYNCOUTx± signal, and at a future transmitter LMFC rising edge, starts the initial lane alignment sequence (ILAS). Optionally, data can be scrambled. Scrambling does not start until the very first octet following the ILAS. The receiver block processes and monitors the data it receives for errors, including: The main purposes of this phase are to align all the lanes of the link and to verify the parameters of the link.      Before the link is established, write each of the link parameters to the receiver device to designate how data is sent to the receiver block. If any of these errors exist, they are reported back to the transmitter in one of a few ways (see the JESD204B Error Monitoring section for details). The ILAS consists of four or more multiframes. The last character of each multiframe is a multiframe alignment character, /A/. The first, third, and fourth multiframes are populated with predetermined data values. Note that Section 8.2 of the JESD204B specifications document describes the data ramp that is expected during ILAS. By default, the AD9144 does not require this ramp. Register 0x47E[0] can be set high to require the data ramp. The deframer uses the final /A/ of each lane to align the ends of the multiframes within the receiver. The second multiframe contains an R (K28.0), Q (K28.4), and then data corresponding to the link parameters. Additional multiframes can be added to the ILAS if needed by the receiver. By default, the AD9144 uses four multiframes in the ILAS (this can be changed in Register 0x478). If using Subclass 1, exactly four multiframes must be used.  Step 2: Initial Lane Alignment Sequence   Bad running disparity (8-bit/10-bit error) Not in table (8-bit/10-bit error) Unexpected control character Bad ILAS Interlane skew error (through character replacement) SYNCOUTx± signal assertion: resynchronization (SYNCOUTx± signal pulled low) is requested at each error for the last two errors. For the first three errors, an optional resynchronization request can be asserted when the error counter reaches a set error threshold. For the first three errors, each multiframe with an error in it causes a small pulse on SYNCOUTx±. Errors can optionally trigger an IRQ event, which can be sent to the transmitter. Various test modes for verifying the link integrity can be found in the JESD204B Test Modes section. Rev. C | Page 41 of 126 AD9144 Data Sheet Lane FIFO The FIFOs in front of the crossbar switch and deframer synchronize the samples sent on the high speed serial data interface with the deframer clock by adjusting the phase of the incoming data. The FIFO absorbs timing variations between the data source and the deframer; this allows up to two PClock cycles of drift from the transmitter. The FIFO_STATUS_REG_0 register and FIFO_STATUS_REG_1 register (Register 0x30C and Register 0x30D, respectively) can be monitored to identify whether the FIFOs are full or empty. Lane FIFO IRQ An aggregate lane FIFO error bit is also available as an IRQ event. Use Register 0x01F[1] to enable the FIFO error bit, and then use Register 0x023[1] to read back its status and reset the IRQ signal. See the Interrupt Request Operation section for more information. Crossbar Switch Register 0x308 to Register 0x30B allow arbitrary mapping of physical lanes (SERDINx±) to logical lanes used by the SERDES deframers. Table 41. Crossbar Registers Address 0x308 0x308 0x309 0x309 0x30A 0x30A 0x30B 0x30B Bits [2:0] [5:3] [2:0] [5:3] [2:0] [5:3] [2:0] [5:3] In single-link mode, Deframer 0 is used exclusively and Deframer 1 remains inactive. In dual-link mode, both QBDs are active and must be configured separately using the LINK_PAGE bit (Register 0x300[2]) to select which link is being configured. The LINK_MODE bit (Register 0x300[3]) is 1 for dual-link, or 0 for single-link. Each deframer uses the JESD204B parameters that the user has programmed into the register map to identify how the data has been packed and how to unpack it. The JESD204B parameters are discussed in detail in the Transport Layer section; many of the parameters are also needed in the transport layer to convert JESD204B frames into samples. Descrambler The AD9144 provides an optional descrambler block using a self synchronous descrambler with a polynomial: 1 + x14 + x15. Enabling data scrambling reduces spectral peaks that are produced when the same data octets repeat from frame to frame. It also makes the spectrum data independent so that possible frequency-selective effects on the electrical interface do not cause data-dependent errors. Descrambling of the data is enabled by setting the SCR bit (Register 0x453[7]) to 1. Syncing LMFC Signals Logical Lane LOGICAL_LANE0_SRC LOGICAL_LANE1_SRC LOGICAL_LANE2_SRC LOGICAL_LANE3_SRC LOGICAL_LANE4_SRC LOGICAL_LANE5_SRC LOGICAL_LANE6_SRC LOGICAL_LANE7_SRC The first step in guaranteeing synchronization across links and devices begins with syncing the LMFC signals. Each DAC dual (DAC Dual A: DAC0/DAC1 and DAC Dual B: DAC2/DAC3) has its own LMFC signal. In Subclass 0, the LMFC signals for each of the two links are synchronized to an internal processing clock. In Subclass 1, all LMFC signals (for all duals and devices) are synchronized to an external SYSREF signal. All LMFC sync registers are paged as described in the Dual Paging section. SYSREF Signal Write each LOGICAL_LANEy_SRC with the number (x) of the desired physical lane (SERDINx±) from which to obtain data. By default, all logical lanes use the corresponding physical lane as their data source. For example, by default LOGICAL_ LANE0_SRC = 0; therefore, Logical Lane 0 obtains data from Physical Lane 0 (SERDIN0±). If instead the user wants to use SERDIN4± as the source for Logical Lane 0, the user must write LOGICAL_LANE0_SRC = 4. Lane Inversion Register 0x334 allows inversion of desired logical lanes, which can be used to ease routing of the SERDINx± signals. For each Logical Lane x, set Bit x of Register 0x334 to 1 to invert it. Deframers The AD9144 consists of two quad-byte deframers (QBDs). Each deframer takes in the 8-bit/10-bit encoded data from the deserializer (via the crossbar switch), decodes it, and descrambles it into JESD204B frames before passing it to the transport layer to be converted to DAC samples. The deframer processes four symbols (or octets) per processing clock (PClock) cycle. The SYSREF signal is a differential source synchronous input that synchronizes the LMFC signals in both the transmitter and receiver in a JESD204B Subclass 1 system to achieve deterministic latency. The SYSREF signal is an active high signal that is sampled by the device clock rising edge. It is best practice that the device clock and SYSREF signals be generated by the same source, such as the AD9516-1 clock generator, so that the phase alignment between the signals is fixed. When designing for optimum deterministic latency operation, consider the timing distribution skew of the SYSREF signal in a multipoint link system (multichip). The AD9144 supports a single pulse or step, or a periodic SYSREF± signal. The periodicity can be continuous, strobed, or gapped periodic. The SYSREF± signal can always be dc-coupled (with a common-mode voltage of 0 V to 2 V). When dc-coupled, a small amount of common-mode current ( 4/SYSREF Freq. In addition, the edge rate must be sufficiently fast—at least 1.3 V/ns is recommended per Table 5—to meet the SYSREF vs. DAC clock keep out window (KOW) requirements. It is possible to use ac-coupled mode without meeting the frequency to time-constant constraint mentioned by using SYSREF hysteresis (Register 0x081 and Register 0x082). However, this increases the DAC clock KOW (Table 5 does not apply) by an amount depending on SYSREF frequency, level of hysteresis, capacitor choice, and edge rate. 1.2V 3kΩ SYSREF– 3kΩ ~600mV 11675-015 SYSREF+ Figure 45. SYSREF± Input Circuit Sync Processing Modes Overview The AD9144 supports various LMFC sync processing modes. These modes are one-shot, continuous, windowed continuous, and monitor modes. All sync processing modes perform a phase check to see that the LMFC is phase aligned to an alignment edge. In Subclass 1, the SYSREF pulse acts as the alignment edge; in Subclass 0, an internal processing clock acts as the alignment edge. If the signals are not in phase, a clock rotation occurs to align the signals. The sync modes are described in the following sections. See the Sync Procedure section for details on the procedure for syncing the LMFC signals. One-Shot Sync Mode (SYNCMODE = 0x1) In one-shot sync mode, a phase check occurs on only the first alignment edge that is received after the sync machine is armed. If the phase error is larger than a specified window error tolerance, a phase adjustment occurs. Though an LMFC synchronization occurs only once, the SYSREF signal can still be continuous. Continuous Sync Mode (SYNCMODE = 0x2) Continuous mode must only be used in Subclass 1 with a periodic SYSREF± signal. In continuous mode, a phase check/alignment occurs on every alignment edge. occurs on every alignment edge in continuous mode. The one caveat to the previous statement is that when a phase rotation cycle is underway, subsequent alignment edges are ignored until the logic lane is ready again. The maximum acceptable phase error (in DAC clock cycles) between the alignment edge and the LMFC edge is set in the error window tolerance register. If continuous sync mode is used with a nonzero error window tolerance, a phase check occurs on every SYSREF pulse, but an alignment occurs only if the phase error is greater than the specified error window tolerance. If the jitter of the SYSREF± signal violates the KOW specification given in Table 5 and therefore causes phase error uncertainty, the error tolerance can be increased to avoid constant clock rotations. Note that this means the latency is less deterministic by the size of the window. If the error window tolerance must be set above 3, Subclass 0 with a one-shot sync is recommended. For debug purposes, SYNCARM (Register 0x03A[6]) can be used to inform the user that alignment edges are being received in continuous mode. Because the SYNCARM bit is self cleared after an alignment edge is received, the user can arm the sync (SYNCARM (Register 0x03A[6]) = 1), and then read back SYNCARM. If SYNCARM = 0, the alignment edges are being received and phase checks are occurring. Arming the sync machine in this mode does not affect the operation of the device. One-Shot then Monitor Sync Mode (SYNCMODE = 0x9) In one-shot then monitor mode, the user can monitor the phase error in real time. Use this sync mode with a periodic SYSREF± signal. A phase check and alignment occurs on the first alignment edge received after the sync machine is armed. On all subsequent alignment edges the phase is monitored and reported, but no clock phase adjustment occurs. The phase error can be monitored on the SYNC_CURRERR_L register (Register 0x03C[3:0]). Immediately after an alignment occurs, CURRERR = 0 indicates that there is no difference between the alignment edge and the LMFC edge. On every subsequent alignment edge, the phase is checked. If the alignment is lost, the phase error is reported in the SYNC_ CURRERR_L register in DAC clock cycles. If the phase error is beyond the selected window tolerance (Register 0x034[2:0]), one bit of Register 0x03D[7:6] is set high depending on whether the phase error is on the low or high side. When an alignment occurs, snapshots of the last phase error (Register 0x03C[3:0]) and the corresponding error flags (Register 0x03D[7:6]) are placed into readable registers for reference (Register 0x038 and Register 0x039, respectively). Continuous mode differs from one-shot mode in two ways. First, no SPI cycle is required to arm the device; the alignment edge seen after continuous mode is enabled results in a phase check. Second, a phase check (and when necessary, clock rotation) Rev. C | Page 43 of 126 AD9144 Data Sheet Sync Procedure LMFC Sync IRQ The procedure for enabling the sync is as follows: The sync status bits (SYNCLOCK, SYNCROTATE, SYNCTRIP, and SYNCWLIM) are available as IRQ events. 1. 2. 3. 4. 5. 6. 7. Set Register 0x008 to 0x03 to sync the LMFC for both duals (DAC0/DAC1 and DAC2/DAC3). Set the desired sync processing mode. The sync processing mode settings are listed in Table 42. For Subclass 1, set the error window according to the uncertainty of the SYSREF± signal relative to the DAC clock and the tolerance of the application for deterministic latency uncertainty. Sync window tolerance settings are given in Table 43. Enable sync by writing SYNCENABLE (Register 0x03A[7] = 1). If in one-shot mode, arm the sync machine by writing SYNCARM (Register 0x03A[6] = 1). If in Subclass 1, ensure that at least one SYSREF pulse is sent to the device. Check the status by reading the following bit fields: a) SYNC_BUSY (Register 0x03B[7]) = 0 to indicate that the sync logic is no longer busy. b) SYNC_LOCK (Register 0x03B[3]) = 1 to indicate that the signals are aligned. This bit updates on every phase check. c) SYNC_WLIM (Register 0x03B[1]) = 0 to indicate that the phase error is not beyond the specified error window. This bit updates on every phase check. d) SYNC_ROTATE (Register 0x03B[2]) = 1 if the phases were not aligned before the sync and an alignment occurred; this indicates that a clock alignment occurred. This bit is sticky and can be cleared only by writing to the SYNCCLRSTKY control bit (Register 0x03A[5]). e) SYNC_TRIP (Register 0x03B[0]) = 1 to indicate alignment edge received and phase check occurred. This bit is sticky and can be cleared only by writing to the SYNCCLRSTKY control bit (Register 0x03A[5]). Table 42. Sync Processing Modes Sync Processing Mode One-shot Continuous One-shot then monitor SYNCMODE (Register 0x03A[3:0]) 0x01 0x02 0x09 Table 43. Sync Window Tolerance Sync Error Window Tolerance ±½ DAC clock cycles ±1 DAC clock cycles ±2 DAC clock cycles ±3 DAC clock cycles Use Register 0x021[3:0] to enable the sync status bits for DAC Dual A (DAC0 and DAC1), and then use Register 0x025[3:0] to read back their statuses and reset the IRQ signals. Use Register 0x022[3:0] to enable the sync status bits for DAC Dual B (DAC2 and DAC3), and then use Register 0x026[3:0] read back their statuses and reset the IRQ signals. See the Interrupt Request Operation section for more information. Deterministic Latency JESD204B systems contain various clock domains distributed throughout each system. Data traversing from one clock domain to a different clock domain can lead to ambiguous delays in the JESD204B link. These ambiguities lead to nonrepeatable latencies across the link from power cycle to power cycle with each new link establishment. Section 6 of the JESD204B specification addresses the issue of deterministic latency with mechanisms defined as Subclass 1 and Subclass 2. The AD9144 supports JESD204B Subclass 0 and Subclass 1 operation, but not Subclass 2. Write the subclass to Register 0x301[2:0] and once per link to Register 0x458[7:5]. Subclass 0 This mode does not require any signal on the SYSREF± pins, which can be left disconnected. Subclass 0 still requires that all lanes arrive within the same LMFC cycle, and the dual DACs must be synchronized to each other. Minor Subclass 0 Caveats Because the AD9144 requires an ILAS, the nonmultiple converter single lane (NMCDA-SL) case from the JESD204A specification is only supported when using the optional ILAS. Error reporting using SYNCOUTx± is not supported when using Subclass 0 with F = 1. Subclass 1 This mode gives deterministic latency and allows links to be synced to within ½ of a DAC clock period. It requires an external SYSREF± signal that is accurately phase aligned to the DAC clock. ERRWINDOW (Register 0x034[2:0]) 0x00 0x01 0x02 0x03 Rev. C | Page 44 of 126 Data Sheet AD9144 Deterministic Latency Requirements Because the LMFC is periodic, this can account for any amount of fixed delay. As a result, the LMFC period must only be larger than the variation in the link delays, and the AD9144 can achieve proper performance with a smaller total latency. Figure 46 and Figure 47 show a case where the link delay is larger than an LMFC period. Note that it can be accommodated by delaying LMFCRx. Several key factors are required for achieving deterministic latency in a JESD204B Subclass 1 system. POWER CYCLE VARIANCE LMFC ILAS ALIGNED DATA DATA LATE ARRIVING LMFC REFERENCE EARLY ARRIVING LMFC REFERENCE Link Delay Figure 46. Link Delay > LMFC Period Example The link delay of a JESD204B system is the sum of fixed and variable delays from the transmitter, channel, and receiver as shown in Figure 48. POWER CYCLE VARIANCE LMFC For proper functioning, all lanes on a link must be read during the same LMFC period. Section 6.1 of the JESD204B specification states that the LMFC period must be larger than the maximum link delay. For the AD9144, this is not necessarily the case; instead, the AD9144 uses a local LMFC for each link (LMFCRx) that can be delayed from the SYSREF aligned LMFC. ILAS ALIGNED DATA DATA LMFCRX LMFC REFERENCE FOR ALL POWER CYCLES LMFC_DELAY FRAME CLOCK Figure 47. LMFC_DELAY to Compensate for Link Delay > LMFC LINK DELAY = DELAYFIXED + DELAYVARIABLE LOGIC DEVICE (JESD204B Tx) CHANNEL JESD204B Rx DSP DAC POWER CYCLE VARIANCE LMFC DATA AT Tx INPUT ALIGNED DATA AT Rx OUTPUT 11675-018 • ILAS DATA ILAS DATA FIXED DELAY VARIABLE DELAY Figure 48. JESD204B Link Delay = Fixed Delay + Variable Delay Rev. C | Page 45 of 126 11675-019 • SYSREF± signal distribution skew within the system must be less than the desired uncertainty. SYSREF± setup and hold time requirements must be met for each device in the system. The total latency variation across all lanes, links, and devices must be ≤10 PClock periods. This includes both variable delays and the variation in fixed delays from lane to lane, link to link, and device to device in the system. 11675-017 • AD9144 Data Sheet 1. The method for setting the LMFCDel and LMFCVar is described in the Link Delay Setup section. Setting LMFCDel appropriately ensures that all the corresponding data samples arrive in the same LMFC period. Then LMFCVar is written into the receive buffer delay (RBD) to absorb all link delay variation. This ensures that all data samples have arrived before reading. By setting these to fixed values across runs and devices, deterministic latency is achieved. 2. The RBD described in the JESD204B specification takes values from 1 to K frame clock cycles, while the RBD of the AD9144 takes values from 0 to 10 PClock cycles. As a result, up to 10 PClock cycles of total delay variation can be absorbed. Because LMFCVar is in PClock cycles and LMFCDel is in frame clock cycles, a conversion between these two units is needed. The PClockFactor, or number of frame clock cycles per PClock cycle, is equal to 4/F. For more information on this relationship, see the Clock Relationships section. Two examples follow that show how to determine LMFCVar and LMFCDel. After they are calculated, write LMFCDel into both Register 0x304 and Register 0x305 for all devices in the system, and write LMFCVar to both Register 0x306 and Register 0x307 for all devices in the system. 3. 4. 5. Link Delay Setup Example, with Known Delays All the known system delays can be used to calculate LMFCVar and LMFCDel, as described in the Link Delay Setup section. The example shown in Figure 49 is demonstrated in the following steps according to the procedure outlined in the Link Delay Setup section. Note that this example is in Subclass 1 to achieve deterministic latency, which has a PClockFactor (4/F) of 2 frameclock cycles per PClock cycle, and uses K = 32 (frames/multiframe). Because PCBFixed JESD_K Unsupported Window Limit. Unsupported SYSREF window limit Unsupported M/L/S/F Selection. This JESD combination is not supported Unsupported K Values. 16 and 32 are supported. K value unsupported Unsupported Subclass Value. 0 and 1 are supported. Unsupported subclass value Unsupported Interpolation Rate Factor. 1, 2, 4, 8 are supported. Unsupported interpolation rate factor Reserved. LMFC Sync Error Window. The error window allows the SYSREF sample phase to vary within the confines of the window without triggering a clock adjustment. This is useful if SYSREF cannot be guaranteed to always arrive in the same period of the device clock associated with the target phase. Error window tolerance = ± ERRWINDOW Reserved. LMFC Sync Last Alignment Error. 4-bit twos complement value that represents the phase error (in number of DAC clock cycles) when the clocks were last adjusted. LMFC Sync Last Error Under Flag. Last phase error was beyond lower window tolerance boundary LMFC Sync Last Error Over Flag. Last phase error was beyond upper window tolerance boundary Reserved. LMFC Sync Logic Enable. Enable sync logic Disable sync logic LMFC Sync Arming Strobe. Sync one-shot armed LMFC Sync Sticky Bit Clear. On a rising edge, this bit clears SYNC_ROTATE and SYNC_TRIP. LMFC Sync Clear Last Error. On a rising edge, this bit clears LASTERROR, LASTUNDER, LASTOVER. LMFC Sync Mode. Sync one-shot mode Sync continuous mode Sync monitor only mode Sync one-shot, then monitor Rev. C | Page 101 of 126 Reset 0x0 Access R 0x0 0x0 R R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 0x0 R R/W 0x0 R R 0x0 R 0x0 R 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W AD9144 Address 0x03B Name SYNC_STATUS Data Sheet Bit No. 7 Bit Name SYNC_BUSY [6:4] 3 RESERVED SYNC_LOCK 2 SYNC_ROTATE Settings 1 1 1 1 SYNC_WLIM 1 0 SYNC_TRIP 1 0x03C SYNC_CURRERR_L [7:4] [3:0] RESERVED CURRERROR 0x03D SYNC_CURRERR_H 7 CURRUNDER 1 6 CURROVER 1 [5:0] [7:2] [1:0] RESERVED RESERVED DACFSC_0[9:8] DACGAIN0_0 DACGAIN1_1 [7:0] [7:2] [1:0] DACFSC_0[7:0] RESERVED DACFSC_1[9:8] 0x043 0x044 DACGAIN1_0 DACGAIN2_1 [7:0] [7:2] [1:0] DACFSC_1[7:0] RESERVED DACFSC_2[9:8] 0x045 DACGAIN2_0 [7:0] DACFSC_2[7:0] 0x040 DACGAIN0_1 0x041 0x042 Description LMFC Sync Machine Busy. Sync logic SM is busy Reserved. LMFC Sync Alignment Locked. Sync logic aligned within window LMFC Sync Rotated. Sync logic rotated with SYSREF (sticky) LMFC Sync Alignment Limit Range. Phase error outside window threshold LMFC Sync Tripped After Arming. Sync received SYSREF pulse (sticky) Reserved. LMFC Sync Alignment Error. 4-bit twos complement value that represents the phase error in number of DAC clock cycles (that is, number of DAC clocks between LMFC edge and SYSREF edge). When an adjustment of the clocks is made on any given SYSREF, the value of the phase error is placed into SYNC_ LASTERR, and SYNC_CURRERR is forced to 0. LMFC Sync Current Error Under Flag. Current phase error is beyond lower window tolerance boundary LMFC Sync Current Error Over Flag. Current phase error is beyond upper window tolerance boundary Reserved. Reserved. 2 MSBs of I-Channel DAC Gain Dual A. A 10bit twos complement value that is mapped to analog full-scale current for DAC 0 as shown: 01111111111 = 27.0 mA 0000000000 = 20.48 mA 1000000000 = 13.9 mA 8 LSBs of I-Channel DAC Gain Dual A. Reserved. 2 MSBs of Q-Channel DAC Gain Dual A. A 10bit twos complement value that is mapped to analog full-scale current for DAC 1 as shown in Register 0x040. 01111111111 = 27.0 mA 0000000000 = 20.48 mA 1000000000 = 13.9 mA 8 LSBs of Q-Channel DAC Gain Dual A. Reserved. 2 MSBs of I-Channel DAC Gain Dual B. A 10bit twos complement value that is mapped to analog full-scale current for DAC as shown in Register 0x040. 01111111111 = 27.0 mA 0000000000 = 20.48 mA 1000000000 = 13.9 mA 8 LSBs of I-Channel DAC Gain Dual B. Rev. C | Page 102 of 126 Reset 0x0 Access R 0x0 0x0 R R 0x0 R 0x0 R 0x0 R 0x0 0x0 R R 0x0 R 0x0 R 0x0 0x0 0x0 R R R/W 0x0 0x0 0x0 R/W R R/W 0x0 0x0 0x0 R/W R R/W 0x0 R/W Data Sheet AD9144 Address 0x046 Name DACGAIN3_1 Bit No. [7:2] [1:0] Bit Name RESERVED DACFSC_3[9:8] Settings 0x047 0x050 DACGAIN3_0 NCOALIGN_MODE [7:0] 7 DACFSC_3[7:0] NCO_ALIGN_ARM 6 5 RESERVED NCO_ALIGN_ MTCH Description Reserved. 2 MSBs of Q-Channel DAC Gain Dual B. A 10bit twos complement value that is mapped to analog full-scale current for DAC 3 as shown in Register 0x40. 01111111111 = 27.0 mA 0000000000 = 20.48 mA 1000000000 = 13.9 mA 8 LSBs of Q-Channel DAC Gain Dual B. Arm NCO Align. On a rising edge, arms the NCO align operation. Reserved. NCO Align Data Match. 1 0 4 NCO_ALIGN_PASS 1 0 3 NCO_ALIGN_FAIL 1 0 2 [1:0] RESERVED NCO_ALIGN_ MODE 00 10 01 0x051 0x052 0x053 0x054 0x060 NCOKEY_ILSB NCOKEY_IMSB NCOKEY_QLSB NCOKEY_QMSB PDP_THRES0 [7:0] [7:0] [7:0] [7:0] [7:0] NCOKEYI[7:0] NCOKEYI[15:8] NCOKEYQ[7:0] NCOKEYQ[15:8] PDP_THRESHOLD[7:0] 0x061 PDP_THRES1 [7:5] [4:0] 0x062 PDP_AVG_TIME 7 [6:4] [3:0] RESERVED PDP_ THRESHOLD[12:8] PDP_ENABLE RESERVED PDP_AVG_TIME 0x063 PDP_POWER0 [7:0] PDP_POWER[7:0] 0x064 PDP_POWER1 [7:5] [4:0] RESERVED PDP_POWER[12:8] 1 Key NCO align data match If finished, NCO not aligned on data match NCO Align Pass. NCO align takes effect Clear not taken effect yet NCO Align Fail. NCO reset during rotate Not finished yet Reserved. NCO Align Mode. NCO align disabled NCO align on data key NCO align on SYSREF NCO Data Key for I Channel. NCO Data Key for I Channel. NCO Data Key for Q Channel. NCO Data Key for Q Channel. PDP_THRESHOLD is the average power threshold for comparison. If the moving average of signal power crosses this threshold, PDP_PROTECT is set high. Reserved. See Register 0x60. Enable average power calculation. Reserved. Can be set from 0-10. Averages across 2(9 + PDP_AVG_TIME) IQ sample pairs. If PDP_POWER has not gone over PDP_ THRESHOLD, PDP_POWER reads back the moving average of the signal power (I2 + Q2). If PDP_THRESHOLD is crossed, PDP_POWER will hold the max value until its corresponding IRQ is cleared (0x025[7 or 0x026[7]). Only 6 data MSBs are used in calculating power. Reserved. See Register 0x063. Rev. C | Page 103 of 126 Reset 0x0 0x0 Access R R/W 0x0 0x0 R/W R/W 0x0 0x0 R R 0x0 R 0x0 R 0x0 0x0 R R/W 0x0 0x0 0x0 0x0 0x0 R/W R/W R/W R/W R/W 0x0 0x0 R R/W 0x0 0x0 0x0 R/W R R/W 0x0 R 0x0 0x0 R R AD9144 Address 0x080 0x081 Name CLKCFG0 SYSREF_ACTRL0 Data Sheet Bit No. 7 Bit Name PD_CLK01 Settings 6 PD_CLK23 5 PD_CLK_DIG 4 PD_SERDES_PCLK 3 PD_CLK_REC [2:0] [7:5] 4 RESERVED RESERVED PD_SYSREF 3 HYS_ON 2 SYSREF_RISE 0 1 0x082 0x083 0x084 SYSREF_ACTRL1 DACPLLCNTRL DACPLLSTATUS [1:0] HYS_CNTRL1 [7:0] 7 HYS_CNTRL0 RECAL_DACPLL [6:5] 4 RESERVED ENABLE_DACPLL [3:0] 7 RESERVED DACPLL_ OVERRANGE_H 6 DACPLL_ OVERRANGE_L 5 DACPLL_CAL_ VALID [4:2] 1 RESERVED DACPLL_LOCK 0 RESERVED Description Power-Down Clock for Dual A. This bit disables the digital and analog clocks for Dual A. Power-Down Clock for Dual B. This bit disables the digital and analog clocks for Dual B. Power-Down Clocks to all DACs. This bit disables the digital and analog clocks for both duals. This includes all reference clocks, PCLK, DAC clocks, and digital clocks. Serdes PLL Clock Power-Down. This bit disables the reference clock to the SERDES PLL, which is needed to have an operational serial interface. Clock Receiver Power-Down. This bit powers down the analog DAC clock receiver block. With this bit set, clocks are not passed to internal nets. Reserved. Reserved. Power-Down SYSREF Buffer. This bit powers down the SYSREF receiver. For Subclass 1 operation to work, this buffer must be enabled. Hysteresis Enabled. This bit enables the programmable hysteresis control for the SYSREF receiver. Using hysteresis gives some noise resistance, but delays the SYSREF± edge an amount depending on HYS_CNTRL and the SYSREF± edge rate. The SYSREF± KOW is not guaranteed when using hysteresis. Select DAC Clock Edge to Sample SYSREF. Use falling edge of DAC clock to sample SYSREF for alignment Use rising edge of DAC clock to sample SYSREF for alignment Hysteresis Control Bits[9:8]. HYS_CNTRL is a 10-bit thermometer-coded number. Each bit set adds 10 mV of differential hysteresis to the SYSREF receiver. Hysteresis Control Bits[7:0]. Recalibrate DAC PLL. On a rising edge of this bit, recalibrate the DAC PLL. Reserved. Synthesizer Enable. This bit enables and calibrates the DAC PLL. Reserved. DAC PLL High Overrange. This bit indicates that the DAC PLL hit the upper edge of its operating band. Recalibrate. DAC PLL Low Overrange. This bit indicates that the DAC PLL hit the lower edge of its operating band. Recalibrate. DAC PLL Calibration Valid. This bit indicates that the DAC PLL has been successfully calibrated. Reserved. DAC PLL Lock Bit. This bit is set high by the PLL when it has achieved lock. Reserved. Rev. C | Page 104 of 126 Reset 0x1 Access R/W 0x1 R/W 0x1 R/W 0x1 R/W 0x1 R/W 0x0 0x0 0x1 R R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x0 R/W R/W 0x0 0x0 R R/W 0x0 0x0 R R 0x0 R 0x0 R 0x0 0x0 R R 0x0 R Data Sheet AD9144 Address 0x085 Name DACINTEGERWORD0 Bit No. [7:0] Bit Name B_COUNT 0x087 DACLOOPFILT1 [7:4] LF_C2_WORD [3:0] LF_C1_WORD [7:4] LF_R1_WORD [3:0] LF_C3_WORD 7 LF_BYPASS_R3 6 LF_BYPASS_R1 5 LF_BYPASS_C2 4 LF_BYPASS_C1 [3:0] LF_R3_WORD 0x088 0x089 DACLOOPFILT2 DACLOOPFILT3 0x08A DACCPCNTRL [7:6] [5:0] RESERVED CP_CURRENT 0x08B DACLOGENCNTRL [7:2] [1:0] RESERVED LO_DIV_MODE Settings 01 10 11 Description Integer Division Word. This bit controls the integer feedback divider for the DAC PLL. Determine the frequency of the DAC clock by the following equations (see the DAC PLL Fixed Register Writes section for more details): fDAC = fREF/(REF_DIVRATE) × 2 × B_COUNT fVCO = fREF/(REF_DIVRATE) × 2 × B_COUNT × LO_DIV_MODE Minimum value is 6. C2 Control Word. Set this control to 0x6 for optimal performance. C1 Control Word. Set this control to 0x2 for optimal performance. R1 Control Word. Set this control to 0xC for optimal performance. C3 Control Word. Set this control to 0x9 for optimal performance. Bypass R3 Resistor. When this bit is set, bypass the R3 capacitor (set to 0 pF) when R3_WORD is set to 0. Set this control to 0x0 for optimal performance. Bypass R1 Resistor. When this bit is set, bypass the R1 capacitor (set to 0 pF) when R1_WORD is set to 0. Set this control to 0x0 for optimal performance. Bypass C2 Capacitor. When this bit is set, bypass the C2 capacitor (set to 0 pF) when C2_WORD is set to 0. Set this control to 0x0 for optimal performance. Bypass C1 Capacitor. When this bit is set, bypass the C1 capacitor (set to 0 pF) when C1_WORD is set to 0. Set this control to 0x0 for optimal performance. R3 Control Word. Set this control to 0xE for optimal performance. Reserved. Charge Pump Current Control. Set this control to 0x12 for optimal performance. Reserved. This range controls the RF clock divider between the VCO and DAC clock rates. The options are 4×, 8×, or 16× division. Choose the LO_DIV_MODE so that 6 GHz < fVCO < 12 GHz (see the DAC PLL Fixed Register Writes section for more details): DAC clock = VCO/4 DAC clock = VCO/8 DAC clock = VCO/16 Rev. C | Page 105 of 126 Reset 0x8 Access R/W 0x8 R/W 0x8 R/W 0x8 R/W 0x8 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x8 R/W 0x0 0x20 R R/W 0x0 0x2 R R/W AD9144 Address 0x08C Name DACLDOCNTRL1 Data Sheet Bit No. [7:3] [2:0] Bit Name RESERVED REF_DIV_MODE Settings 000 001 010 011 100 0x08D DACLDOCNTRL2 [7:0] DAC_LDO 0x0E2 CAL_CTRL_GLOBAL [7:2] 1 RESERVED CAL_START_AVG 0 CAL_EN_AVG [7:4] RESERVED 3 CAL_CLK_EN 1 0x0E7 CAL_CLKDIV 1 0 0x0E8 CAL_PAGE [2:0] [7:4] [3:0] RESERVED RESERVED CAL_PAGE 0x0E9 CAL_CTRL 7 CAL_FIN 6 CAL_ACTIVE 1 1 Description Reserved. Reference Clock Division Ratio. This field controls the amount of division that is done to the input clock at the CLK+/CLK− pins before it is presented to the PLL as a reference clock. The reference clock frequency must be between 35 MHz and 80 MHz, but the CLK+/CLK− input frequency can range from 35 MHz to 1 GHz. The user sets this division to achieve a 35 MHz to 80 MHz PLL reference frequency. For more details see the DAC PLL Fixed Register Writes section. 1 2 4 8 16 DAC PLL LDO setting. This register must be written to 0x7B for optimal performance. Reserved. Averaged Calibration Start. On rising edge, calibrate the DACs. Only use if calibrating all DACs. Averaged Calibration Enable. Set prior to starting calibration with CAL_START_AVG. While this bit is set, calibration can be performed, and the results are applied. Enable averaged calibration Must write the default value for proper operation. Enable Self Calibration Clock. Enable calibration clock Disable calibration clock Reserved. Reserved. DAC Calibration Paging. Selects which of the DACs are being accessed for calibration or calibration readback. This paging affects Register 0x0E9 and Register 0x0ED. Calibration: any number of DACs can be accessed simultaneously to write and calibrate. Write a 1 to Bit x to include DAC x. Readback: only one DAC at a time can be accessed when reading back CAL_CTRL (Register 0x0E9). Write a 1 to Bit x to read from DAC x (the other bits must be 0). Calibration finished. This bit is high when the calibration has completed. If the calibration completes and either CAL_ERRHI or CAL_ ERRLO is high, then the calibration cannot be considered valid and are considered a timeout event. Calibration ran and is finished Calibration Active. This bit is high while the calibration is in progress. Calibration is running Rev. C | Page 106 of 126 Reset 0x0 0x1 Access R R/W 0x2B R/W 0x0 0x0 R R/W 0x0 R/W 0x3 R/W 0x0 R/W 0x0 0x0 0xF R R R/W 0x0 R 0x0 R Data Sheet Address Name AD9144 Bit No. 5 Bit Name CAL_ERRHI 4 CAL_ERRLO [3:2] 1 RESERVED CAL_START Settings 1 1 0 1 0 CAL_EN 0 1 0x0ED CAL_INIT [7:0] CAL_INIT 0x110 DATA_FORMAT 7 BINARY_FORMAT 0 1 0x111 DATAPATH_CTRL [6:0] 7 RESERVED INVSINC_ENABLE 1 0 6 5 RESERVED DIG_GAIN_ENABLE 1 0 4 PHASE_ADJ_ ENABLE 1 0 [3:2] MODULATION_TYPE 00 01 10 11 1 SEL_SIDEBAND 0 I_TO_Q Description SAR Data Error: Too High. This bit is set at the end of a calibration cycle if any of the calibration DACs has overranged to the high side. This typically means that the algorithm adjusts the calibration preset of the calibration DACs and runs another cycle. Data saturated high SAR Data Error: Too Low. This bit is set at the end of a calibration cycle if any of the calibration DACs has overranged to the low side. This typically means that the algorithm adjusts the calibration preset of the calibration DACs and runs another cycle. Data saturated low Reserved. Calibration Start. The rising edge of this bit kicks off a calibration sequence for the DACs that have been selected in the CAL_INDX register. Normal operation Start calibration state machine Calibration Enable. Enable the calibration DAC of the converter. Enable to calibration engine and machines. Prepare for a calibration start. For calibration coefficients to be applied to the calibrated DACs, this bit must be high. Do not use calibration DACs Use calibration DACs Initialize Calibration. Must be written to 0xA2 before starting calibration or averaged calibration. Binary or Twos Complementary Format on the Data Bus. Input data is twos complement Input data is offset binary Reserved. Enable Inverse Sinc Filter. Enable inverse sinc filter Disable inverse sinc filter Reserved. Enable Digital Gain. Enable digital gain function Disable digital gain function Enable Phase Compensation. Enable phase adjust compensation Disable phase adjust compensation Selects Type Of Modulation Operation. No modulation Fine modulation (uses FTW) fS/4 coarse modulation fS/8 coarse modulation Spectrum Inversion Control. Can only be used with fine modulation. This causes the negative sideband to be selected and is equivalent to changing the sign of FTW. Send I Data into Q DAC datapath. Occurs at the end of the digital datapath prior to entering DACs. Rev. C | Page 107 of 126 Reset 0x0 Access R 0x0 R 0x0 0x0 R R/W 0x0 R/W 0xA6 R/W 0x0 R/W 0x0 0x1 R R/W 0x0 0x1 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W AD9144 Address 0x112 Name INTERP_MODE Data Sheet Bit No. [7:3] [2:0] Bit Name RESERVED INTERP_MODE Settings 000 001 011 100 0x113 NCO_FTW_UPDATE [7:2] 1 RESERVED FTW_UPDATE_ACK 0 FTW_UPDATE_REQ 0x114 0x115 0x116 0x117 0x118 0x119 0x11A FTW0 FTW1 FTW2 FTW3 FTW4 FTW5 NCO_PHASE_ OFFSET0 [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] FTW[7:0] FTW[15:8] FTW[23:16] FTW[31:24] FTW[39:32] FTW[47:40] NCO_PHASE_ OFFSET[7:0] 0x11B [7:0] 0x11C NCO_PHASE_ OFFSET1 PHASE_ADJ0 [7:0] NCO_PHASE_ OFFSET[15:8] PHASE_ADJ[7:0] 0x11D PHASE_ADJ1 0x11F TXEN_SM_0 [7:5] [4:0] [7:6] RESERVED PHASE_ADJ[12:8] FALL_COUNTERS [5:4] RISE_COUNTERS 3 2 RESERVED PROTECT_OUT_ INVERT 0 1 [1:0] RESERVED Description Reserved. Interpolation Mode. 1× mode 2× mode 4× mode 8× mode Reserved. Frequency tuning word update acknowledge. This readback is high when an FTW has been updated. Frequency tuning word update request from SPI. Unlike most registers, those relating to fine NCO modulation (Register 0x114 to Register 0x11B) are not updated immediately upon writing to them. Once the desired FTW and phase offset values are written, set this bit. These registers update on the rising edge of this bit. It is only after this update that the internal state matches Register 0x114 to Register 0x11B. Confirmation that this update has occurred can be made by reading back bit 1 of this register and ensuring it is set high for the update acknowledge. NCO Frequency Tuning Word. NCO Frequency Tuning Word. NCO Frequency Tuning Word. NCO Frequency Tuning Word. NCO Frequency Tuning Word. NCO Frequency Tuning Word. 8 LSBs of NCO Phase Offset. NCO_PHASE_OFFSET changes the phase of both I and Q data, and is only functional when using NCO fine modulation. It is a 16bit twos complement number ranging from −180 to+180 degrees in steps of .0055°. 8 MSBs of NCO Phase Offset. 8 LSBs of Phase Compensation Word. Phase compensation changes the phase between the I and Q data. PHASE_ADJ is a 13-bit twos complement value. The control ranges from −14° to +14° with 0.0035° resolution steps. Reserved. 5 MSBs of Phase Compensation Word. Fall Counters. The number of counters to use to delay TX_PROTECT fall from TXENx falling edge. Must be set to 1 or 2. Rise Counters. The number of counters to use to delay TX_PROTECT rise from TXENx rising edge. Reserved. PROTECT_OUTx Invert. PROTECT_OUTx is high when output is valid. Suitable for enabling downstream components during transmission PROTECT_OUTx is high when output is invalid. Suitable for disabling downstream components when not transmitting Must write the default value for proper operation. Rev. C | Page 108 of 126 Reset 0x0 0x1 Access R R/W 0x0 0x0 R R 0x0 R/W 0x0 0x0 0x0 0x0 0x0 0x10 0x0 R/W R/W R/W R/W R/W R/W R/W 0x0 R/W 0x0 R/W 0x0 0x0 0x2 R R/W R/W 0x0 R/W 0x0 0x0 R R/W 0x3 R/W Data Sheet AD9144 Address 0x121 Name TXEN_RISE_ COUNT_0 Bit No. [7:0] Bit Name RISE_COUNT_0 0x122 TXEN_RISE_ COUNT_1 [7:0] RISE_COUNT_1 0x123 TXEN_FALL_ COUNT_0 [7:0] FALL_COUNT_0 0x124 TXEN_FALL_ COUNT_1 [7:0] FALL_COUNT_1 0x12D DEVICE_CONFIG_ REG_0 DIE_TEMP_CTRL0 [7:0] DEVICE_CONFIG_0 [7:1] RESERVED 0 AUXADC_ENABLE 0x12F Settings 0 1 0x132 0x133 0x134 DIE_TEMP0 DIE_TEMP1 DIE_TEMP_UPDATE [7:0] [7:0] [7:1] 0 0x135 DC_OFFSET_CTRL [7:1] 0 DIE_TEMP[7:0] DIE_TEMP[15:8] RESERVED DIE_TEMP_ UPDATE RESERVED DC_OFFSET_ON 0x136 IPATH_DC_OFFSET_ 1PART0 [7:0] LSB_OFFSET_I[7:0] 0x137 IPATH_DC_OFFSET_ 1PART1 [7:0] LSB_OFFSET_I[15:8] 0x138 QPATH_DC_OFFSET_ 1PART0 [7:0] LSB_OFFSET_ Q[7:0] 0x139 QPATH_DC_OFFSET_ 1PART1 [7:0] LSB_OFFSET_ Q[15:8] 0x13A IPATH_DC_OFFSET_ 2PART [7:5] RESERVED [4:0] SIXTEENTH_ OFFSET_I [7:5] RESERVED [4:0] SIXTEENTH_ OFFSET_Q 1 x 0x13B QPATH_DC_OFFSET_ 2PART x 0x13C IDAC_DIG_GAIN0 [7:0] IDAC_DIG_ GAIN[7:0] 0x13D IDAC_DIG_GAIN1 [7:4] [3:0] RESERVED IDAC_DIG_ GAIN[11:8] Description First counter used to delay TX_PROTECT rise from TXENx rising edge. Delays by 32 × RISE_COUNT_0 DAC clock cycles. Second counter used to delay TX_PROTECT rise from TXENx rising edge. Delays by 32 × RISE_COUNT_1 DAC clock cycles. First counter used to delay TX_PROTECT fall from TXENx falling edge. Delays by 32 × FALL_COUNT_0 DAC clock cycles. Must be set to a minimum of 0x12. Second counter used to delay TX_PROTECT fall from TXENx falling edge. Delays by 32 × FALL_COUNT_1 DAC clock cycles. Must be set to 0x8B for proper digital datapath configuration. Must write the default value for proper operation. Enables the AUX ADC Block. AUX ADC disable AUX ADC enable Aux ADC Readback Value. Aux ADC Readback Value. Reserved. Die Temperature Update. On a rising edge, a new temperature code is generated. Reserved. DC Offset On. Enables dc offset module 8 LSBs of IPath DC Offset. LSB_OFFSET_I is a 16-bit twos complement number that is added to incoming data. 8 MSBs of IPath DC Offset. LSB_OFFSET_I is a 16-bit twos complement number that is added to incoming I data. 8 LSBs of QPath DC Offset. LSB_OFFSET_Q is a 16-bit twos complement number that is added to incoming Q data. 8 MSBs of QPath DC Offset. LSB_OFFSET_Q is a 16-bit twos complement number that is added to incoming Q data. Reserved. Reset 0xF Access R/W 0x0 R/W 0xFF R/W 0xFF R/W 0x46 R/W 0x10 R/W 0x0 R/W 0x0 0x0 0x0 0x0 R R R R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R SIXTEENTH_OFFSET_I is a 5-bit twos complement number in 16ths of an LSB that is added to incoming I data. x/16 LSB DC offset Reserved. 0x0 R/W 0x0 R SIXTEENTH_OFFSET_Q is a 5-bit twos complement number in 16ths of an LSB that is added to incoming Q data. x/16 LSB DC offset 8 LSBs of I DAC Digital Gain. IDAC_DIG_GAIN is the digital gain of the IDAC. The digital gain is a multiplier from 0 to 4095/2048 in steps of 1/2048. Reserved. 4 MSBs of I DAC Digital Gain 0x0 R/W 0xEA R/W 0x0 0xA R R/W Rev. C | Page 109 of 126 AD9144 Data Sheet Address 0x13E Name QDAC_DIG_GAIN0 Bit No. [7:0] Bit Name QDAC_DIG_ GAIN[7:0] Settings 0x13F QDAC_DIG_GAIN1 [7:4] [3:0] 0x140 GAIN_RAMP_UP_ STEP0 [7:0] RESERVED QDAC_DIG_ GAIN[11:8] GAIN_RAMP_UP_ STEP[7:0] Description 8 LSBs of Q DAC Digital Gain. QDAC_DIG_GAIN is the digital gain of the QDAC. The digital gain is a multiplier from 0 to 4095/2048 in steps of 1/2048. Reserved. 4 MSBs of Q DAC Digital Gain. 0x0 0xFFF 0x141 0x142 GAIN_RAMP_UP_ STEP1 GAIN_RAMP_DOWN_ STEP0 [7:4] RESERVED [3:0] GAIN_RAMP_UP_ STEP[11:8] GAIN_RAMP_ DOWN_STEP[7:0] [7:0] 0 0xFFF 0x143 0x146 0x147 GAIN_RAMP_ DOWN_STEP1 DEVICE_CONFIG_ REG_1 BSM_STAT [7:4] RESERVED [3:0] [7:0] GAIN_RAMP_ DOWN_STEP[11:8] DEVICE_CONFIG_1 [7:6] SOFTBLANKRB 00 01 10 11 0x14B PRBS [5:0] 7 RESERVED PRBS_GOOD_Q 0 1 6 PRBS_GOOD_I 0 1 [5:3] 2 RESERVED PRBS_MODE 0 1 1 PRBS_RESET 0 1 0 PRBS_EN 0 1 0x14C 0x14D 0x1B0 PRBS_ERROR_I PRBS_ERROR_Q DACPLLT0 [7:0] [7:0] [7:0] PRBS_COUNT_I PRBS_COUNT_Q DAC_PLL_PWR Reset 0xEA Access R/W 0x0 0xA R R/W 8 LSBs of Gain Ramp Up Step. GAIN_RAMP_UP_STEP controls the amplitude step size of the BSM’s ramping feature when the gain is being ramped to its assigned value. Smallest ramp up step size Largest ramp up step size Reserved. 0x4 R/W 0x0 R 4 MSBs of Gain Ramp Up Step. See Register 0x140 for description. 8 LSBs of Gain Ramp Down Step. GAIN_RAMP_DOWN_STEP controls the amplitude step size of the BSM’s ramping feature when the gain is being ramped to zero. Smallest ramp down step size Largest ramp down step size Reserved. 0x0 R/W 0x9 R/W 0x0 R 4 MSBs of Gain Ramp Down Step. See Register 0x142 for description. Must be set to 0x01 for proper digital datapath configuration. Blanking State. Data is fully blanked Ramping from data process to full blanking Ramping from fully blanked to data process Data is being processed Reserved. Good Data Indicator Imaginary Channel. Incorrect sequence detected Correct PRBS sequence detected Good Data Indicator Real Channel. Incorrect sequence detected Correct PRBS sequence detected Reserved. Polynomial Select 7-bit: x7 + x6 + 1 15-bit: x15 + x14 + 1 Reset Error Counters. Normal operation Reset counters Enable PRBS Checker. Disable Enable Error Count Value Real Channel. Error Count Value Imaginary Channel. DAC PLL PD settings. This register must be written to 0x00 for optimal performance. 0x0 R/W 0x0 R/W 0x0 R 0x0 0x0 R R 0x0 R 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 0x0 0xFA R R R/W Rev. C | Page 110 of 126 Data Sheet Address 0x1B5 Name DACPLLT5 AD9144 Bit No. [7:4] Bit Name RESERVED [3:0] VCO_VAR 0x1BC DACPLLTC [7:0] DAC_PLL_VCO_ CTRL 0x1BE DACPLLTE [7:0] DAC_PLL_VCO_ PWR 0x1BF DACPLLTF [7:0] DAC_PLL_VCOCAL 0x1C0 DACPLLT10 [7:0] 0x1C1 DACPLLT11 [7:0] DAC_PLL_LOCK_ CNTR DAC_PLL_CP2 0x1C4 DACPLLT17 [7:0] DAC_PLL_VAR1 0x1C5 DACPLLT18 [7:0] DAC_PLL_VAR2 0x200 MASTER_PD [7:1] 0 RESERVED SPI_PD_MASTER 0x201 PHY_PD [7:0] SPI_PD_PHY 0x203 GENERIC_PD [7:2] 1 RESERVED SPI_SYNC1_PD Description Must write the default value for proper operation. Varactor KVO Setting. See Table 83 for optimal settings based on the fVCO being used. DAC PLL Charge Pump settings. This register must be written to 0x24 for optimal performance. Reserved. Temperature Coefficient for VCO Bias. See Table 83 for optimal settings based on the fVCO being used. VCO Bias Control. See Table 83 for optimal settings based on the fVCO being used. DAC PLL VCO control settings. This register must be written to 0x0D for optimal performance. DAC PLL VCO power control settings. This register must be written to 0x02 for optimal performance. DAC PLL VCO calibration settings. This register must be written to 0x8E for optimal performance. This register must be written to 0x2A for optimal performance. This register must be written to0x2A for optimal performance. DAC PLL Varactor setting. Must be set to 0x7E for proper DAC PLL configuration. DAC PLL Varactor setting. See Table 83 for optimal settings based on the fVCO being used. Reserved. Power Down the Entire JESD Receiver Analog (All Eight Channels Plus Bias). SPI Override to Power Down the Individual PHYs. Set Bit x to power down the corresponding SERDINx± PHY Reserved. Power down LVDS buffer for SYNCOUT0±. 0 SPI_SYNC2_PD Power down LVDS buffer for SYNCOUT1±. 0x0 R/W 0x206 CDR_RESET [7:1] 0 RESERVED SPI_CDR_RESETN Reserved. Resets the Digital Control Logic for All PHYs. Hold CDR in reset Enable CDR Reserved. 0x0 0x1 R R/W 0x0 R Enables Half-Rate CDR Operation. Set to 1 when 5.75 Gbps ≤ lane rate ≤ 12.4 Gbps. Must write the default value for proper operation. Enables Oversampling of the Input Data. Set to 1 when 1.44 Gbps ≤ lane rate ≤ 3.1 Gbps. Reserved. Must be set to 0xFF for proper JESD interface configuration. 0x1 R/W 0x2 R/W 0x0 R/W 0x0 0x0 R R/W 0x1B9 DACPLLT9 [7:0] DAC_PLL_CP1 0x1BB DACPLLTB [7:5] [4:3] RESERVED VCO_BIAS_TCF [2:0] VCO_BIAS_REF Settings 0 1 0x230 0x232 CDR_OPERATING_ MODE_REG_0 DEVICE_CONFIG_ REG_3 [7:6] RESERVED 5 ENHALFRATE [4:2] RESERVED 1 CDR_OVERSAMP 0 [7:0] RESERVED DEVICE_CONFIG_3 Rev. C | Page 111 of 126 Reset 0x8 Access R/W 0x3 R/W 0x34 R/W 0x0 0x1 R R/W 0x4 R/W 0x00 R/W 0x00 R/W 0x8D R/W 0x2E R/W 0x24 R/W 0x33 R/W 0x08 R/W 0x0 0x1 R R/W 0x0 R/W 0x0 0x0 R R/W AD9144 Address 0x268 Name EQ_BIAS_REG Data Sheet Bit No. [7:6] Bit Name EQ_POWER_ MODE Settings 00 01 0x280 0x281 SERDESPLL_ ENABLE_CNTRL PLL_STATUS [5:0] RESERVED [7:3] RESERVED 2 RECAL_SERDESPLL 1 0 RESERVED ENABLE_ SERDESPLL RESERVED SERDES_PLL_ OVERRANGE_H [7:6] 5 4 SERDES_PLL_ OVERRANGE_L 3 SERDES_PLL_CAL_ VALID_RB [2:1] 0 0x284 LOOP_FILTER_1 [7:0] RESERVED SERDES_PLL_ LOCK_RB LOOP_FILTER_1 0x285 LOOP_FILTER_2 [7:0] LOOP_FILTER_2 0x286 LOOP_FILTER_3 [7:0] LOOP_FILTER_3 0x287 SERDES_PLL_CP1 [7:0] SERDES_PLL_CP1 0x289 REF_CLK_DIVIDER_ LDO [7:3] RESERVED 2 DEVICE_CONFIG_4 [1:0] SERDES_PLL_DIV_ MODE 00 01 10 0x28A VCO_LDO [7:0] SERDES_PLL_ VCO_LDO 0x28B SERDES_PLL_PD1 [7:0] SERDES_PLL_PD1 0x290 SERDESPLL_VAR1 [7:0] SERDES_PLL_VAR1 Description Control the Equalizer Power/Insertion Loss Capability. Normal mode Low power mode Must write the default value for proper operation. Reserved. Reset 0x1 Access R/W 0x22 R/W 0x0 R Recalibrate SERDES PLL. On a rising edge, recalibrate the SERDES PLL. Reserved. Enable the SERDES PLL. Setting this bit enables and calibrates the SERDES PLL. Reserved. SERDES PLL High Overrange. This bit indicates that the SERDES PLL hit the lower edge of its operating band. Recalibrate. SERDES PLL Low Overrange. This bit indicates that the SERDES PLL hit the lower edge of its operating band. Recalibrate. SERDES PLL Calibration Valid. This bit indicates that the SERDES PLL has been successfully calibrated. Reserved. SERDES PLL Lock. This bit is set high by the PLL when it has achieved lock. SERDES PLL loop filter setting. This register must be written to 0x62 for optimal performance. SERDES PLL loop filter setting. This register must be written to 0xC9 for optimal performance. SERDES PLL loop filter setting. This register must be written to 0x0E for optimal performance. SERDES PLL charge pump setting. This register must be written to 0x12 for optimal performance. Reserved. 0x0 R/W 0x0 0x0 R R/W 0x0 0x0 R R 0x0 R 0x0 R 0x0 0x0 R R 0x77 R/W 0x87 R/W 0x08 R/W 0x3F R/W 0x0 R 0x0 R/W 0x0 R/W 0x2B R/W 0x7F R/W 0x83 R/W Must be set to 1 for proper SERDES PLL configuration. SERDES PLL Reference Clock Division Factor. This field controls the division of the SERDES PLL reference clock before it is fed into the SERDES PLL Phase Frequency Detector (PFD). It must be set so fREF/DivFactor is between 35 MHz and 80 MHz. Divide by 4 for 5.75 Gbps to 12.4 Gbps lane rate Divide by 2 for 2.88 Gbps to 6.2 Gbps lane rate Divide by 1 for 1.44 Gbps to 3.1 Gbps lane rate SERDES PLL VCO LDO setting. This register must be written to 0x7B for optimal performance. SERDES PLL PD setting. This register must be written to 0x00 for optimal performance. SERDES PLL Varactor setting. This register must be written to 0x89 for optimal performance. Rev. C | Page 112 of 126 Data Sheet AD9144 Address 0x294 Name SERDES_PLL_CP2 Bit No. [7:0] Bit Name SERDES_PLL_CP2 0x296 SERDESPLL_VCO1 [7:0] 0x297 SERDESPLL_VCO2 [7:0] 0x299 SERDES_PLL_PD2 [7:0] SERDES_PLL_ VCO1 SERDES_PLL_ VCO2 SERDES_PLL_PD2 0x29A SERDESPLL_VAR2 [7:0] SERDES_PLL_VAR2 0x29C SERDES_PLL_CP3 [7:0] SERDES_PLL_CP3 0x29F SERDESPLL_VAR3 [7:0] SERDES_PLL_VAR3 0x2A0 SERDESPLL_VAR4 [7:0] SERDES_PLL_VAR4 0x2A4 DEVICE_CONFIG_ REG_8 SYNCOUTB_SWING [7:0] DEVICE_CONFIG_8 [7:1] 0 RESERVED SYNCOUTB_ SWING_MD 0x2A5 Settings 0 1 0x2A7 TERM_BLK1_ CTRLREG0 [7:1] 0 RESERVED RCAL_TERMBLK1 0x2AA DEVICE_CONFIG_ REG_9 DEVICE_CONFIG_ REG_10 TERM_BLK2_ CTRLREG0 [7:0] [7:1] DEVICE_CONFIG_ 9 DEVICE_CONFIG_ 10 RESERVED 0 RCAL_TERMBLK2 [7:0] DEVICE_CONFIG_ 11 DEVICE_CONFIG_ 12 RESERVED CHECKSUM_MODE 0x2AB 0x2AE 0x2B1 0x2B2 0x300 DEVICE_CONFIG_ REG_11 DEVICE_CONFIG_ REG_12 GENERAL_JRX_ CTRL_0 [7:0] [7:0] 7 6 0 1 [5:4] RESERVED Description SERDES PLL Charge Pump setting. This register must be set to 0x24 for optimal performance. SERDES PLL VCO setting. This register must be set to 0x03 for optimal performance. SERDES PLL VCO setting. This register must be set to 0x0D for optimal performance. SERDES PLL PD setting. This register must be set to 0x02 for optimal performance. SERDES PLL Varactor setting. This register must be set to 0x8E for optimal performance. SERDES PLL Charge Pump setting. Must be set to 0x2A for proper SERDES PLL configuration. SERDES PLL varactor setting. Must be set to 0x78 for proper SERDES PLL configuration. SERDES PLL varactor setting. This register must be set to 0x06 for optimal performance. Must be set to 0xFF for proper clock configuration. Reserved. SYNCOUTx± Swing Mode. Sets the output differential swing mode for the SYNCOUTx± pins. See Table 8 for details. Normal Swing Mode High Swing Mode Reserved. Termination Calibration. The rising edge of this bit calibrates PHY0, PHY1, PHY6, and PHY7 terminations to 50 Ω. Must be set to 0xB7 for proper JESD interface termination configuration. Must be set to 0x87 for proper JESD interface termination configuration. Reserved. Terminal Calibration. The rising edge of this bit calibrates PHY2, PHY3, PHY4 and PHY5 terminations to 50 Ω. Must be set to 0xB7 for proper JESD interface termination configuration. Must be set to 0x87 for proper JESD interface termination configuration. Reserved. Checksum Mode. This bit controls the locally generated JESD204B link parameter checksum method. The value is stored in the FCMP registers (Register 0x40E, Register 0x416, Register 0x41E, Register 0x426, Register 0x42E, Register 0x436, Register 0x43E, and Register 0x446). Checksum is calculated by summing the individual fields in the link configuration table as defined in Section 8.3, Table 20 of the JESD204B standard Checksum is calculated by summing the registers containing the packed link configuration fields (Σ[0x450:0x45A] modulo 256). Reserved. Rev. C | Page 113 of 126 Reset 0xB0 Access R/W 0x0C R/W 0x00 R/W 0x00 R/W 0xFE R/W 0x17 R/W 0x33 R/W 0x08 R/W 0x4B R/W 0x0 0x0 R R/W 0x0 0x0 R R/W 0xC3 R/W 0x93 R/W 0x0 R 0x0 R/W 0xC3 R/W 0x93 R/W 0x0 0x0 R R/W 0x0 R AD9144 Address Name Data Sheet Bit No. 3 Bit Name LINK_MODE Settings 0 1 2 LINK_PAGE 0 1 [1:0] LINK_EN 0b00 0b01 0b10 0b11 0x301 GENERAL_JRX_CTRL_1 [7:3] [2:0] RESERVED SUBCLASSV_ LOCAL 000 001 0x302 DYN_LINK_LATENCY_0 [7:5] [4:0] RESERVED DYN_LINK_ LATENCY_0 0x303 DYN_LINK_LATENCY_1 [7:5] [4:0] RESERVED DYN_LINK_ LATENCY_1 0x304 LMFC_DELAY_0 [7:5] [4:0] RESERVED LMFC_DELAY_0 0x305 LMFC_DELAY_1 [7:5] [4:0] RESERVED LMFC_DELAY_1 0x306 LMFC_VAR_0 [7:5] [4:0] RESERVED LMFC_VAR_0 0x307 LMFC_VAR_1 [7:5] [4:0] RESERVED LMFC_VAR_1 Description Link Mode. This register selects either singlelink or dual-link mode. Single-link mode Dual-link mode Link Paging. Selects which link’s register map is used. This paging affects Registers 0x401 to 0x47E. Use Link 0 register map Use Link 1 register map Link Enable. These bits bring up the JESD204B receiver digital circuitry: Bit 0 for Link 0 and Bit 1 for Link 1. Enable the link only after the following has occurred: all JESD204B parameters are set, the DAC PLL is enabled and locked (Register 0x084[1] = 1), and the JESD204B PHY is enabled (Register 0x200 = 0x00) and calibrated (Register 0x281[2] = 0). Disable both JESD Link 1 and JESD Link 0 Disable JESD Link 1, enable JESD Link 0 Enable JESD Link 1, disable JESD Link 0 Enable both JESD Link 1 and JESD Link 0 Reserved. JESD204B Subclass. Subclass 0 Subclass 1 Reserved. Dynamic Link Latency: Link 0. Latency between the LMFCRx for link 0 and the last arriving LMFC boundary in units of PCLK cycles. See the Deterministic Latency section. Reserved. Dynamic Link Latency: Link 1. Latency between the LMFCRx for link 1 and the last arriving LMFC boundary in units of PCLK cycles. See the Deterministic Latency section. Reserved. LMFC Delay: Link 0 Delay from the LMFC to LMFCRx for Link 0. In units of frame clock cycles for subclass 1 and PCLK cycles for subclass 0. See the Deterministic Latency section. Reserved. LMFC Delay: Link 1. Delay from the LMFC to LMFCRx for Link 1. In units of frame clock cycles for subclass 1 and PCLK cycles for subclass 0. See the Deterministic Latency section. Reserved. Variable Delay Buffer: Link 0. Sets when data is read from a buffer to be consistent across links and power cycles. In units of PCLK cycles. See the Deterministic Latency section. This setting must not be more than 10. Reserved. Variable Delay Buffer: Link 1. Sets when data is read from a buffer to be consistent across links and power cycles. In units of PCLK cycles. See the Deterministic Latency section. This setting must not be more than 10. Rev. C | Page 114 of 126 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 0x1 R R/W 0x0 0x0 R R 0x0 0x0 R R 0x0 0x0 R R/W 0x0 0x0 R R/W 0x0 0x6 R R/W 0x0 0x6 R R/W Data Sheet Address 0x308 Name XBAR_LN_0_1 AD9144 Bit No. [7:6] [5:3] Bit Name RESERVED LOGICAL_LANE1_ SRC [2:0] LOGICAL_LANE0_ SRC [7:6] [5:3] RESERVED LOGICAL_LANE3_ SRC [2:0] LOGICAL_LANE2_ SRC [7:6] [5:3] RESERVED LOGICAL_LANE5_ SRC [2:0] LOGICAL_LANE4_ SRC [7:6] [5:3] RESERVED LOGICAL_LANE7_ SRC [2:0] LOGICAL_LANE6_ SRC Settings x x 0x309 XBAR_LN_2_3 x x 0x30A XBAR_LN_4_5 x x 0x30B XBAR_LN_6_7 x x 0x30C FIFO_STATUS_REG_0 [7:0] LANE_FIFO_FULL 0x30D FIFO_STATUS_REG_1 [7:0] LANE_FIFO_EMPTY 0x312 SYNCB_GEN_1 [7:6] [5:4] RESERVED SYNCB_ERR _DUR 0 1 2 0x314 SERDES_SPI_REG [3:0] [7:0] 0x315 PHY_PRBS_TEST_EN [7:0] RESERVED SERDES_SPI_ CONFIG PHY_TEST_EN Description Reserved. Logical Lane 1 Source. Selects a physical lane to be mapped onto Logical Lane 1. Data is from SERDINx Logical Lane 0 Source. Selects a physical lane to be mapped onto Logical Lane 0. Data is from SERDINx Reserved. Logical Lane 3 Source. Selects a physical lane to be mapped onto Logical Lane 3. Data is from SERDINx Logical Lane 2 source. Selects a physical lane to be mapped onto Logical Lane 2. Data is from SERDINx Reserved. Logical Lane 5 Source. Selects a physical lane to be mapped onto Logical Lane 5. Data is from SERDINx Logical Lane 4 Source. Selects a physical lane to be mapped onto Logical Lane 4. Data is from SERDINx Reserved. Logical Lane 7 Source. Selects a physical lane to be mapped onto Logical Lane 7. Data is from SERDINx Logical Lane 6 Source. Selects a physical lane to be mapped onto Logical Lane 6. Data is from SERDINx FIFO Full Flags for Each Logical Lane. A full FIFO indicates an error in the JESD204B configuration or with a system clock. If the FIFO for Lane x is full, Bit x in this register will be high. FIFO Empty Flags for Each Logical Lane. An empty FIFO indicates an error in the JESD204B configuration or with a system clock. If the FIFO for Logical Lane x is empty, Bit x in this register will be high. Reserved. Duration of SYNCOUTx± Low for Error. The duration applies to both SYNCOUT0 and SYNCOUT1. A sync error is asserted at the end of a multiframe whenever one or more disparity, not in table or unexpected control character errors are encountered. ½ PCLK cycle 1 PCLK cycle 2 PCLK cycles Reserved. SERDES SPI Configuration. Must be written to 0x01 as part of the Physical Layer setup step. PHY Test Enable. Enables the PHY BER test. Set Bit x to enable the PHY test for Lane x. Rev. C | Page 115 of 126 Reset 0x0 0x1 Access R R/W 0x0 R/W 0x0 0x3 R R/W 0x2 R/W 0x0 0x5 R R/W 0x4 R/W 0x0 0x7 R R/W 0x6 R/W 0x0 R 0x0 R 0x0 R/W 0x0 0x0 R/W R/W 0x0 R/W AD9144 Address 0x316 Name PHY_PRBS_TEST_CTRL Data Sheet Bit No. 7 [6:4] Bit Name RESERVED PHY_SRC_ERR_CNT [3:2] PHY_PRBS_PAT_SEL Settings x 00 01 10 1 PHY_TEST_START 0 1 0 PHY_TEST_RESET 0 1 0x317 0x318 0x319 0x31A 0x31B 0x31C 0x31D 0x32C PHY_PRBS_TEST_ THRESHOLD_LOBITS PHY_PRBS_TEST_ THRESHOLD_ MIDBITS PHY_PRBS_TEST_ THRESHOLD_HIBITS PHY_PRBS_TEST_ ERRCNT_LOBITS PHY_PRBS_TEST_ ERRCNT_MIDBITS PHY_PRBS_TEST_ ERRCNT_HIBITS PHY_PRBS_TEST_ STATUS SHORT_TPL_TEST_0 [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] PHY_PRBS_ THRESHOLD[7:0] PHY_PRBS_ THRESHOLD[15:8] PHY_PRBS_ THRESHOLD[23:16] PHY_PRBS_ERR_ CNT[7:0] PHY_PRBS_ERR_ CNT[15:8] PHY_PRBS_ERR_ CNT[23:16] PHY_PRBS_PASS [7:6] [5:4] RESERVED SHORT_TPL_SP_ SEL [3:2] SHORT_TPL_DAC_ SEL 1 SHORT_TPL_TEST_ RESET x x 0 1 0 SHORT_TPL_TEST_ EN 0 1 0x32D SHORT_TPL_TEST_1 [7:0] SHORT_TPL_REF_ SP_LSB Description Reserved. PHY Error Count Source. Selects which PHY errors are being reported in Register 0x31A to Register 0x31C. Report Lane x error count PHY PRBS Pattern Select. Selects the PRBS pattern for PHY BER test. PRBS7 PRBS15 PRBS31 PHY PRBS Test Start. Starts and stops the PHY PRBS test. Test stopped Test in progress PHY PRBS Test Reset. Resets the PHY PRBS test state machine and error counters. Enable PHY PRBS test state machine Hold PHY PRBS test state machine in reset 8 LSBs of PHY PRBS Error Threshold. Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 8 ISBs of PHY PRBS Error Threshold. 0x0 R/W 8 MSBs of PHY PRBS Error Threshold. 0x0 R/W 8 LSBs of PHY PRBS Error Count. Reported PHY BERT error count from lane selected using Register 0x316[6:4]. 8 ISBs of PHY PRBS Error Count. 0x0 R 0x0 R 8 MSBs of PHY PRBS Error Count. 0x0 R PHY PRBS Test Pass/Fail. Bit x corresponds to PHY PRBS pass/fail for Physical Lane x. The bit is set to 1 while the error count for Physical Lane x is less than PHY_PRBS_THRESHOLD. Reserved. Short Transport Layer Sample Select. Selects which sample to check from the DAC selected via Bits[3:2]. Sample x Short Transport Layer Test DAC Select. Selects which DAC to sample. Sample from DAC x Short Transport Layer Test Reset. Resets the result of short transport layer test. Not reset Reset Short Transport Layer Test Enable. See the Subclass 0 section for details on how to perform this test. Disable Enable Short Transport Layer Test Reference, Sample LSB. This is the lower eight bits of the expected DAC sample. It is used to compare with the received DAC sample at the output of the JESD204B receiver. 0xFF R 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Rev. C | Page 116 of 126 Data Sheet AD9144 Address 0x32E Name SHORT_TPL_TEST_2 Bit No. [7:0] Bit Name SHORT_TPL_REF_ SP_MSB 0x32F SHORT_TPL_TEST_3 [7:1] 0 RESERVED SHORT_TPL_FAIL Settings 0 1 [7:0] 0x400 DEVICE_CONFIG_ REG_13 JESD_BIT_INVERSE_ CTRL DID_REG 0x401 BID_REG 0x333 0x334 0x402 0x403 LID0_REG SCR_L_REG [7:0] DEVICE_CONFIG_ 13 JESD_BIT_INVERSE [7:0] DID_RD [7:4] ADJCNT_RD [3:0] BID_RD 7 6 RESERVED ADJDIR_RD 5 PHADJ_RD [4:0] LID0_RD 7 SCR_RD 0 1 [6:5] [4:0] RESERVED L-1_RD 0 1 3 0x404 F_REG [7:0] F-1_RD 0 1 3 Description Short Transport Layer Test Reference, Sample MSB. This is the upper eight bits of the expected DAC sample. It is used to compare with the received DAC sample at the output of the JESD204B receiver. Reserved. Short Transport Layer Test Fail. This bit shows whether the selected DAC sample matches the reference sample. If they match, it is a test pass, otherwise it is a test fail. Test pass Test fail Must be set to 0x01 for proper JESD interface configuration. Logical Lane Invert. Set Bit x high to invert the JESD deserialized data on Logical Lane x. Device Identification Number. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. Adjustment Resolution to DAC LMFC. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. Must be 0. Bank Identification: Extension to DID. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. Reserved. Direction to Adjust DAC LMFC. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. Must be 0. Phase Adjustment Request to DAC Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. Must be 0. Lane Identification for Lane 0. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. Transmit Scrambling Status. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. Scrambling is disabled Scrambling is enabled Reserved. Number of Lanes per Converter Device. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. One lane per converter Two lanes per converter Four lanes per converter Number of Octets per Frame. Settings of 1, 2 and 4 octets per frame are valid. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. (One octet per frame) per lane (Two octets per frame) per lane (Four octets per frame) per lane Rev. C | Page 117 of 126 Reset 0x0 Access R/W 0x0 0x0 R R 00 R/W 0x0 R/W 0x0 R 0x0 R 0x0 R 0x0 0x0 R R 0x0 R 0x0 R 0x0 R 0x0 0x0 R R 0x0 R AD9144 Address 0x405 Name K_REG Data Sheet Bit No. [7:5] [4:0] Bit Name RESERVED K-1_RD Settings 0x0F 0x1F 0x406 M_REG [7:0] M-1_RD 0 1 3 0x407 CS_N_REG [7:6] CS_RD 5 [4:0] RESERVED N-1_RD [7:5] SUBCLASSV_RD [4:0] NP-1_RD [7:5] JESDV_RD 0x0F 0x408 NP_REG 0x0F 0x409 S_REG 000 001 [4:0] S-1_RD 0 1 0x40A HD_CF_REG 7 HD_RD 0 1 0x40B RES1_REG [6:5] [4:0] RESERVED CF_RD [7:0] RES1_RD Description Reserved. Number of Frames per Multiframe. Settings of 16 or 32 are valid. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. 16 frames per multiframe 32 frames per multiframe Number of converters per device. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. Must be 0, 1, or 3. One converter per device Two converters per device Four converters per device Number of Control Bits per Sample. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. CS must be 0. Reserved. Converter Resolution. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. Converter resolution must be 16. Converter resolution of 16 Device Subclass Version. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. Total Number of Bits per Sample. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. Must be 16 bits per sample. 16 bits per sample. JESD204 Version. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. JESD204A JESD204B Number of Samples per Converter per Frame Cycle. Settings of one and two are valid. See Table 35 and Table 36. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. One sample per converter per frame Two samples per converter per frame High Density Format. See Section 5.1.3 of the JESD294B standard. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. Low density mode High density mode: link information received on Lane 0 as specified in Section 8.3 of JESD204B Reserved. Number of Control Words per Frame Clock Period per Link. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. Bits[4:0] must be 0. Reserved Field 1. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. Rev. C | Page 118 of 126 Reset 0x0 0x0 Access R R 0x0 R 0x0 R 0x0 0x0 R R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 0x0 R R 0x0 R Data Sheet AD9144 Address 0x40C Name RES2_REG Bit No. [7:0] Bit Name RES2_RD 0x40D CHECKSUM_REG [7:0] FCHK0_RD 0x40E COMPSUM0_REG [7:0] FCMP0_RD 0x412 LID1_REG [7:5] [4:0] RESERVED LID1_RD 0x415 CHECKSUM1_REG [7:0] FCHK1_RD 0x416 COMPSUM1_REG [7:0] FCMP1_RD 0x41A LID2_REG 0x41D 0x41E CHECKSUM2_REG COMPSUM2_REG [7:5] [4:0] [7:0] [7:0] RESERVED LID2_RD FCHK2_RD FCMP2_RD 0x422 LID3_REG 0x425 0x426 CHECKSUM3_REG COMPSUM3_REG [7:5] [4:0] [7:0] [7:0] RESERVED LID3_RD FCHK3_RD FCMP3_RD 0x42A LID4_REG 0x42D 0x42E CHECKSUM4_REG COMPSUM4_REG [7:5] [4:0] [7:0] [7:0] RESERVED LID4_RD FCHK4_RD FCMP4_RD 0x432 LID5_REG 0x435 0x436 CHECKSUM5_REG COMPSUM5_REG [7:5] [4:0] [7:0] [7:0] RESERVED LID5_RD FCHK5_RD FCMP5_RD 0x43A LID6_REG 0x43D 0x43E CHECKSUM6_REG COMPSUM6_REG [7:5] [4:0] [7:0] [7:0] RESERVED LID6_RD FCHK6_RD FCMP6_RD 0x442 LID7_REG 0x445 0x446 CHECKSUM7_REG COMPSUM7_REG [7:5] [4:0] [7:0] [7:0] RESERVED LID7_RD FCHK7_RD FCMP7_RD 0x450 ILS_DID [7:0] DID Settings Description Reserved Field 2. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. Checksum for Link Lane 0. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. Computed Checksum for Link Lane 0. The JESD204B receiver computes the checksum of the link information received on Lane 0 as specified in Section 8.3 of JESD204B. The computation method is set by the CHECKSUM_MODE bit (Address 0x300[6]) and must match the likewise calculated checksum in Register 0x40D. Reserved. Lane Identification for Link Lane 1.Link information received on Lane 0 as specified in section 8.3 of JESD204B. Checksum for Link Lane 1. Link information received on Lane 0 as specified in Section 8.3 of JESD204B. Computed Checksum for Link Lane 1. See the description for Register 0x40E. Reserved. Lane Identification for Link Lane 2. Checksum for Link Lane 2. Computed Checksum for Link Lane 2 (see the description for Register 0x40E). Reserved. Lane Identification for Link Lane 3. Checksum for Link Lane 3. Computed Checksum for Link Lane 3 (see the description for Register 0x40E). Reserved. Lane Identification for Link Lane 4. Checksum for Link Lane 4. Computed Checksum for Link Lane 4 (see the description for Register 0x40E). Reserved. Lane Identification for Link Lane 5. Checksum for Link Lane 5. Computed Checksum for Link Lane 5 (see the description for Register 0x40E). Reserved. Lane Identification for Link Lane 6. Checksum for Link Lane 6. Computed Checksum for Link Lane 6 (see the description for Register 0x40E). Reserved. Lane Identification for Link Lane 7. Checksum for Link Lane 7. Computed Checksum for Link Lane 7 (see the description for Register 0x40E). Device Identification Number. Link information received on Link Lane 0 as specified in Section 8.3 of JESD204B. Must be set to value read in Register 0x400. Rev. C | Page 119 of 126 Reset 0x0 Access R 0x0 R 0x0 R 0x0 0x0 R R 0x0 R 0x0 R 0x0 0x0 0x0 0x0 R R R R 0x0 0x0 0x0 0x0 R R R R 0x0 0x0 0x0 0x0 R R R R 0x0 0x0 0x0 0x0 R R R R 0x0 0x0 0x0 0x0 R R R R 0x0 0x0 0x0 0x0 R R R R 0x0 R/W AD9144 Address 0x451 0x452 0x453 Name ILS_BID ILS_LID0 ILS_SCR_L Data Sheet Bit No. [7:4] Bit Name ADJCNT [3:0] BID 7 6 5 RESERVED ADJDIR PHADJ [4:0] LID0 7 SCR Settings 0 1 [6:5] [4:0] RESERVED L-1 0 1 3 7 0x454 ILS_F [7:0] F-1 0 1 3 0x455 ILS_K [7:5] [4:0] RESERVED K-1 0x0F 0x1F 0x456 ILS_M [7:0] M-1 0 1 3 0x457 ILS_CS_N [7:6] CS 5 [4:0] RESERVED N-1 [7:5] SUBCLASSV 0 0xF 0x458 ILS_NP 0 1 [4:0] NP-1 [7:5] JESDV 0xF 0x459 ILS_S 000 001 [4:0] S-1 0 1 Description Adjustment Resolution to DAC LMFC Must be set to 0. Bank Identification: Extension to DID Must be set to value read in Register 0x401[3:0]. Reserved. Direction to Adjust DAC LMFC. Must be set to 0. Phase Adjustment Request to DAC. Must be set to 0. Lane Identification for Link Lane 0. Must be set to the value read in Register 0x402[4:0]. Receiver Descrambling Enable. Descrambling is disabled Descrambling is enabled Reserved. Number of Lanes per Converter Device. See Table 35 and Table 36. One lane per converter Two lanes per converter Four lanes per converter Eight lanes per converter (single link only) Number of Octets per Lane per Frame. Settings of 1, 2, and 4 (octets per lane) per frame are valid. See Table 35 and Table 36. (One octet per lane) per frame (Two octets per lane) per frame (Four octets per lane) per frame Reserved. Number of Frames per Multiframe. Settings of 16 or 32 are valid. Must be set to 32 when F = 1 (Register 0x476). 16 frames per multiframe 32 frames per multiframe Number of Converters per Device. See Table 35 and Table 36. One converter per link Two converters per link Four converters per link (single link only) Number of Control Bits per Sample. Must be set to 0. Control bits are not supported. Zero control bits per sample Reserved. Converter Resolution. Must be set to 16 bits of resolution. Converter resolution of 16. Device Subclass Version. Subclass 0 Subclass 1 Total Number of Bits per Sample. Must be set to 16 bits per sample. 16 bits per sample. JESD204 Version. JESD204A JESD204B Number of Samples per Converter per Frame Cycle. Settings of one and two are valid. See Table 35 and Table 36. One sample per converter per frame Two samples per converter per frame Rev. C | Page 120 of 126 Reset 0x0 Access R/W 0x0 R/W 0x0 0x0 0x0 R R/W R/W 0x0 R/W 0x1 R/W 0x0 0x3 R R/W 0x0 R/W 0x0 0x1F R R/W 0x1 R/W 0x0 R/W 0x0 0xF R R/W 0x1 R/W 0xF R/W 0x1 R/W 0x0 R/W Data Sheet Address 0x45A Name ILS_HD_CF AD9144 Bit No. 7 Bit Name HD Settings 0 1 [6:5] [4:0] RESERVED CF 0x45B 0x45C 0x45D ILS_RES1 ILS_RES2 ILS_CHECKSUM [7:0] [7:0] [7:0] RES1 RES2 FCHK0 0x46B ERRCNTRMON_RB [7:0] READERRORCNTR 0x46B ERRCNTRMON 7 [6:4] RESERVED LANESEL [3:2] [1:0] RESERVED CNTRSEL x 00 01 10 0x46C 0x46D LANEDESKEW BADDISPARITY_RB [7:0] [7:0] LANEDESKEW BADDIS 0x46D BADDISPARITY 7 RST_IRQ_DIS 6 DISABLE_ERR_ CNTR_DIS 5 RST_ERR_CNTR_DIS [4:3] [2:0] RESERVED LANE_ADDR_DIS 0x46E NIT_RB [7:0] NIT 0x46E NIT_W 7 RST_IRQ_NIT 6 DISABLE_ERR_ CNTR_NIT 5 RST_ERR_CNTR_NIT [4:3] [2:0] RESERVED LANE_ADDR_NIT Description High Density Format. If F = 1, HD must be set to 1. Otherwise, HD must be set to 0. See Section 5.1.3 of JESD204B standard. Low density mode High density mode Reserved. Number of Control Words per Frame Clock Period per Link. Must be set to 0. Control bits are not supported. Reserved Field 1. Reserved Field 2. Checksum for Link Lane 0. Calculated checksum. Calculation depends on 0x300[6]. Read JESD204B Error Counter. After selecting the lane and error counter by writing to LANESEL and CNTRSEL (both in this same register), the selected error counter is read back here. Reserved. Link Lane select for JESD204B error counter. Selects the lane whose errors are read back in this register. Selects Link Lane x Reserved. JESD204B Error Counter Select. Selects the type of error that are read back in this register. BADDISCNTR: bad running disparity counter NITCNTR: not in table error counter UCCCNTR: Unexpected control character counter Lane Deskew. Setting Bit x deskews Link Lane x Bad Disparity Character Error (BADDIS). Bit x is set when the bad disparity error count for Link Lane x reaches the threshold in Register 0x47C. BADDIS IRQ Reset. Reset BADDIS IRQ for lane selected via Bits[2:0] by writing 1 to this bit. BADDIS Error Counter Disable. Disable the BADDIS error counter for lane selected via Bits[2:0] by writing 1 to this bit. BADDIS Error Counter Reset. Reset BADDIS error counter for lane selected via Bits[2:0] by writing 1 to this bit. Reserved. Link Lane Address for Functions Described in Bits[7:5]. Not in table Character Error (NIT). Bit x is set when the NIT error count for Link Lane x reaches the threshold in Register 0x47C. IRQ Reset. Reset IRQ for lane selected via Bits[2:0] by writing 1 to this bit. Disable Error Counter. Disable the error counter for lane selected via Bits[2:0] by writing 1 to this bit. Reset Error Counter. Reset error counter for lane selected via Bits[2:0] by writing 1 to this bit. Reserved. Link Lane Address for Functions Described in Bits[7:5]. Rev. C | Page 121 of 126 Reset 0x1 Access R/W 0x0 0x0 R R/W 0x0 0x0 0x45 R/W R/W R/W 0x0 R 0x0 0x0 R W 0x0 0x0 R W 0xF 0x0 R/W R 0x0 W 0x0 W 0x0 W 0x0 0x0 R W 0x0 R 0x0 W 0x0 W 0x0 W 0x0 0x0 R W AD9144 Data Sheet Address 0x46F Name UNEXPECTEDCONTROL_RB Bit No. [7:0] Bit Name UCC 0x46F UNEXPECTEDCONTROL_W 7 RST_IRQ_UCC 6 DISABLE_ERR_ CNTR_UCC 5 [4:3] [2:0] RST_ERR_CNTR_ UCC RESERVED LANE_ADDR_UCC [7:0] CODEGRPSYNC 0x470 CODEGRPSYNCFLG Settings 0 1 0x471 FRAMESYNCFLG [7:0] FRAMESYNC 0 1 0x472 GOODCHKSUMFLG [7:0] GOODCHECKSUM 0 1 0x473 INITLANESYNCFLG [7:0] INITIALLANESYNC 0x476 CTRLREG1 [7:0] F 1 2 4 0x477 CTRLREG2 7 ILAS_MODE 1 0 [6:4] 3 0x478 KVAL [2:0] [7:0] RESERVED THRESHOLD_ MASK_EN RESERVED KSYNC x Description Unexpected Control Character Error (UCC). Bit x is set when the UCC error count for Link Lane x reaches the threshold in Register 0x47C. IRQ Reset. Reset IRQ for lane selected via Bits[2:0] by writing 1 to this bit. Disable Error Counter. Disable the error counter for lane selected via Bits[2:0] by writing 1 to this bit. Reset Error Counter. Reset error counter for lane selected via Bits[2:0] by writing 1 to this bit. Reserved. Link Lane Address for Functions Described in Bits[7:5]. Code Group Sync Flag (from Each Instantiated Lane). Writing 1 to Bit 7 resets the IRQ. The associated IRQ flag is located in Register 0x47A[0]. A loss of CODEGRPSYNC triggers sync request assertion. See the SYNCOUT and SYSREF Signals section and the Deterministic Latency section. Synchronization is lost Synchronization is achieved Frame Sync Flag (from Each Instantiated Lane). This register indicates the live status for each lane. Writing 1 to Bit 7 resets the IRQ. A loss of frame sync automatically initiates a synchronization sequence. Synchronization is lost Synchronization is achieved Good Checksum Flag (from Each Instantiated Lane). Writing 1 to Bit 7 resets the IRQ. The associated IRQ flag is located in Register 0x47A[2]. Last computed checksum is not correct Last computed checksum is correct Initial Lane Sync Flag (from Each Instantiated Lane). Writing 1 to Bit 7 resets the IRQ. The associated IRQ flag is located in Register 0x47A[3]. Loss of synchronization is also reported on SYNCOUT1± or SYNCOUT0±. See the SYNCOUT and SYSREF± Signal section and the Deterministic Latency section. Number of Octets per Frame. Settings of 1, 2, and 4 are valid. See Table 35 and Table 36. One octet per frame Two octets per frame Four octets per frame ILAS Test Mode. Defined in Section 5.3.3.8 of JESD204B specification. JESD204B receiver is constantly receiving ILAS frames Normal link operation Reserved. Threshold Mask Enable. Set this bit if using SYNC_ASSERTION_MASK (Register 0x47B[7:5]). Reserved. Number of K Multiframes During ILAS (Divided by Four). Sets the number of multiframes to send initial lane alignment sequence. Cannot be set to 0. 4x multiframes during ILAS Rev. C | Page 122 of 126 Reset 0x0 Access R 0x0 W 0x0 W 0x0 W 0x0 0x0 R W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x1 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 0x1 R R/W Data Sheet Address 0x47A Name IRQVECTOR_MASK AD9144 Bit No. 7 Bit Name BADDIS_MASK Settings 1 6 NIT_MASK 1 5 UCC_MASK 1 4 3 2 1 0 0x47A IRQVECTOR_FLAG 7 RESERVED INITIALLANESYNC_ MASK 1 BADCHECKSUM_ MASK 1 FRAMESYNC_ MASK 1 CODEGRPSYNC_ MASK 1 BADDIS_FLAG 1 6 NIT_FLAG 1 5 UCC_FLAG 1 4 3 2 1 0 RESERVED INITIALLANESYNC_ FLAG 1 BADCHECKSUM_ FLAG 1 FRAMESYNC_ FLAG 1 CODEGRPSYNC_ FLAG 1 Description Bad Disparity Mask. If the bad disparity count reaches ERRORTHRESH on any lane, IRQ is pulled low. Not in table Mask. If the not in table character count reaches ERRORTHRESH on any lane, IRQ is pulled low. Unexpected Control Character Mask. If the unexpected control character count reaches ERRORTHRESH on any lane, IRQ is pulled low. Reserved. Initial Lane Sync Mask. If initial lane sync (0x473) fails on any lane, IRQ is pulled low. Bad Checksum Mask. If there is a bad checksum (0x472) on any lane, IRQ is pulled low. Frame Sync Mask If frame sync (0x471) fails on any lane, IRQ is pulled low. Code Group Sync Machine Mask. If code group sync (0x470) fails on any lane, IRQ is pulled low. Bad Disparity Error Count. Bad disparity character count reached ERRORTHRESH (0x47C) on at least one lane. Read Register 0x46D to determine which lanes are in error. Not in table Error Count Not in table character count reached ERRORTHRESH (0x47C) on at least one lane. Read Register 0x46E to determine which lanes are in error. Unexpected Control Character Error Count Unexpected control character count reached ERRORTHRESH (0x47C) on at least one lane. Read Register 0x46F to determine which lanes are in error. Reserved. Initial Lane Sync Flag. Initial lane sync failed on at least one lane. Read Register 0x473 to determine which lanes are in error Bad Checksum Flag. Bad checksum on at least one lane. Read Register 0x472 to determine which lanes are in error. Frame Sync Flag. Frame sync failed on at least one lane. Read Register 0x471 to determine which lanes are in error. Code Group Sync Flag. Code group sync failed on at least one lane. Read Register 0x470 to determine which lanes are in error Rev. C | Page 123 of 126 Reset 0x0 Access W 0x0 W 0x0 W 0x0 0x0 R W 0x0 W 0x0 W 0x0 W 0x0 R 0x0 R 0x0 R 0x0 0x0 R R 0x0 R 0x0 R 0x0 R AD9144 Address 0x47B Name SYNCASSERTIONMASK Data Sheet Bit No. 7 Bit Name BADDIS_S Settings 1 6 NIT_S 1 5 UCC_S 1 4 CMM 1 3 CMM_ENABLE 1 0 0x47C ERRORTHRES [2:0] [7:0] RESERVED ETH 0x47D LANEENABLE [7:0] LANE_ENA 0x47E RAMP_ENA [7:1] 0 RESERVED ENA_RAMP_ CHECK 0 1 0x520 DIG_TEST0 [7:2] RESERVED 0x521 DC_TEST_VALUEI0 1 0 [7:0] 0x522 DC_TEST_VALUEI1 [7:0] 0x523 DC_TEST_VALUEQ0 [7:0] 0x524 DC_TEST_VALUEQ1 [7:0] DC_TEST_MODE RESERVED DC_TEST_ VALUEI[7:0] DC_TEST_ VALUEI [15:8] DC_TEST_ VALUEQ[7:0] DC_TEST_ VALUEQ[15:8] Description Bad Disparity Error on Sync. Asserts a sync request on SYNCOUTx± when the bad disparity character count reaches the threshold in Register 0x47C Not in table Error on Sync. Asserts a sync request on SYNCOUTx± when the not in table character count reaches the threshold in Register 0x47C Unexpected Control Character Error on Sync. Asserts a sync request on SYNCOUTx± when the unexpected control character count reaches the threshold in Register 0x47C Configuration Mismatch IRQ. If CMM_ENABLE is high, this bit latches on a rising edge and pull IRQ low. When latched, write a 1 to clear this bit. If CMM_ENABLE is low, this bit is non-functional. Link Lane 0 configuration registers (Register 0x450 to Register 0x45D) do not match the JESD204B transmit settings (Register 0x400 to Register 0x40D) Configuration Mismatch IRQ Enable. Enables IRQ generation if a configuration mismatch is detected Configuration mismatch IRQ disabled Reserved. Error Threshold. Bad disparity, not in table, and unexpected control character errors are counted and compared to the error threshold value. When the count reaches the threshold, either an IRQ is generated or the SYNCOUTx± signal is asserted per the mask register settings, or both. Function is performed in all lanes. Lane Enable. Setting Bit x enables Link Lane x. This register must be programmed before receiving the code group pattern for proper operation. Reserved. Enable Ramp Checking at the Beginning of ILAS. Disable ramp checking at beginning of ILAS; ILAS data need not be a ramp Enable ramp checking; ILAS data needs to be a ramp starting at 00-01-02; otherwise, the ramp ILAS fails and the device does not start up Must write default value for proper operation. DC Test Mode Reserved. DC Value LSB of DC Test Mode for I DAC. Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x1 R/W 0x0 0xFF R R/W 0xF R/W 0x0 0x0 R W 0x7 R/W 0x0 0x0 0x0 R/W R/W R/W DC value MSB of DC Test Mode for I DAC. 0x0 R/W DC value LSB of DC Test Mode for Q DAC. 0x0 R/W DC value MSB of DC Test Mode for Q DAC. 0x0 R/W Rev. C | Page 124 of 126 Data Sheet AD9144 OUTLINE DIMENSIONS 12.10 12.00 SQ 11.90 0.28 0.23 0.18 0.60 MAX 0.60 MAX 88 67 66 PIN 1 INDICATOR 1 PIN 1 INDICATOR 11.85 11.75 SQ 11.65 0.50 BSC 0.50 0.40 0.30 22 23 45 44 TOP VIEW BOTTOM VIEW 10.50 REF 0.70 0.65 0.60 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.045 0.025 0.005 COPLANARITY 0.08 0.20 REF SEATING PLANE 08-10-2012-A 12° MAX 0.90 0.85 0.80 7.55 7.40 SQ 7.25 EXPOSED PAD COMPLIANT TO JEDEC STANDARDS MO-220-VRRD Figure 88. 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 12 mm × 12 mm Body, Very Thin Quad (CP-88-6) Dimensions shown in millimeters 12.10 12.00 SQ 11.90 0.30 0.25 0.20 0.60 MAX 0.60 MAX 67 88 66 1 PIN 1 INDICATOR PIN 1 INDICATOR 0.50 BSC 7.55 7.40 SQ 7.25 EXPOSED PAD 0.65 0.55 0.45 22 44 TOP VIEW 0.90 0.85 0.80 PKG-004598 SEATING PLANE 12° MAX SIDE VIEW 0.190~0.245 REF 0.70 0.65 0.60 0.50 0.40 0.30 45 0.045 0.025 0.005 COPLANARITY 0.08 23 BOTTOM VIEW 10.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220 Figure 89. 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ] (Variable Lead Length) 12 mm × 12 mm Body, Very Thin Quad (CP-88-9) Dimensions shown in millimeters Rev. C | Page 125 of 126 1.00 0.90 0.80 0.80 0.70 0.60 11-09-2018-B 11.85 11.75 SQ 11.65 AD9144 Data Sheet ORDERING GUIDE Model 1 AD9144BCPZ AD9144BCPZRL AD9144BCPAZ AD9144BCPAZRL AD9144-FMC-EBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 88-Lead LFCSP_VQ 88-Lead LFCSP_VQ 88-Lead LFCSP_VQ (Variable Lead Length) 88-Lead LFCSP_VQ (Variable Lead Length) FMC Evaluation Board Z = RoHS Compliant Part. ©2014–2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11675-0-4/19(C) Rev. C | Page 126 of 126 Package Option CP-88-6 CP-88-6 CP-88-9 CP-88-9