16-Bit, 12 GSPS,
RF DAC and Digital Upconverter
AD9163
Data Sheet
FEATURES
The wide bandwidth of up to 1 GHz and the complex NCO and
digital upconverter enable dual band and triple band direct RF
synthesis of wireless infrastructure signals, eliminating costly
analog upconverters.
DAC update rate up to 12 GSPS (minimum)
Direct RF synthesis at 6 GSPS (minimum)
DC to 3 GHz in nonreturn-to-zero (NRZ) mode
DC to 6 GHz in 2× NRZ mode
1.5 GHz to 7.5 GHz in Mix-Mode
Selectable interpolation
6×, 8×, 12×, 16×, 24×
Excellent dynamic performance
Wide analog bandwidth capability combines with high dynamic
range to support DOCSIS 3.1 cable infrastructure compliance
from the minimum of one carrier up to 1 GHz of signal bandwidth,
making it ideal for cable multiple dwelling unit (MDU) applications.
A 2× interpolator filter (FIR85) enables the AD9163 to be configured for lower data rates and converter clocking to reduce the
overall system power and ease the filtering requirements. In
Mix-Mode™ operation, the AD9163 can reconstruct RF carriers
in the second and third Nyquist zones up to 7.5 GHz while still
maintaining exceptional dynamic range. The output current can
be programmed from 8 mA to 38.76 mA. The AD9163 data
interface consists of up to eight JESD204B serializer/deserializer
(SERDES) lanes that are programmable in terms of lane speed
and number of lanes to enable application flexibility.
APPLICATIONS
Broadband communications systems
DOCSIS 3.1 cable modem termination system (CMTS)/
video on demand (VOD)/edge quadrature amplitude
modulation (EQAM)
Wireless communications infrastructure
MC-GSM, W-CDMA, LTE, LTE-A, point to point
GENERAL DESCRIPTION
A serial peripheral interface (SPI) configures the AD9163 and
monitors the status of all the registers. The AD9163 is offered in
a 169-ball, 11 mm × 11 mm, 0.8 mm pitch CSP_BGA package.
The AD91631 is a high performance, 16-bit digital-to-analog
converter (DAC) that supports data rates to 6 GSPS. The DAC
core is based on a quad-switch architecture coupled with a 2×
interpolator filter that enables an effective DAC update rate of
up to 12 GSPS in some modes. The high dynamic range and
bandwidth makes this DAC ideally suited for the most demanding
high speed radio frequency (RF) DAC applications.
PRODUCT HIGHLIGHTS
Superior RF performance and deep interpolation rates enable
use of the AD9163 in many wireless infrastructure applications,
including MC-GSM, W-CDMA, LTE, and LTE-A.
3.
1.
2.
High dynamic range and signal reconstruction bandwidth
supports RF signal synthesis of up to 7.5 GHz.
Up to eight lanes JESD204B SERDES interface, flexible in
terms of number of lanes and lane speed.
Bandwidth and dynamic range to meet multiband wireless
communications standards with margin.
FUNCTIONAL BLOCK DIAGRAM
RESET
SDIO
SDO
CS
SCLK
ISET VREF
IRQ
VREF
AD9163
SPI
NRZ RZ MIX
SERDIN0±
INV
SINC
NCO
SYSREF±
HB
2×
HB
3×
HB
2×,
4×,
8×
TO JESD
TO DATAPATH
TX_ENABLE
DAC
CORE
OUTPUT±
CLOCK
DISTRIBUTION
CLK±
14415-001
HB
2×
JESD
DATA
LATCH
SERDIN7±
SYNCOUT±
Figure 1.
1
Protected by U.S. Patents 6,842,132 and 7,796,971.
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2016–2019 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD9163
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
JESD204B Serial Data Interface .................................................... 31
Applications ....................................................................................... 1
JESD204B Overview .................................................................. 31
General Description ......................................................................... 1
Physical Layer ............................................................................. 32
Product Highlights ........................................................................... 1
Data Link Layer .......................................................................... 35
Functional Block Diagram .............................................................. 1
Transport Layer .......................................................................... 43
Revision History ............................................................................... 3
JESD204B Test Modes ............................................................... 45
Specifications..................................................................................... 4
JESD204B Error Monitoring..................................................... 47
DC Specifications ......................................................................... 4
Hardware Considerations ......................................................... 49
DAC Input Clock Overclocking Specifications ........................ 5
Main Digital Datapath ................................................................... 50
Power Supply DC Specifications ................................................ 5
Data Format ................................................................................ 50
Serial Port and CMOS Pin Specifications ................................. 6
Interpolation Filters ................................................................... 50
JESD204B Serial Interface Speed Specifications ...................... 7
Digital Modulation ..................................................................... 53
SYSREF± to DAC Clock Timing Specifications ....................... 7
Inverse Sinc ................................................................................. 55
Digital Input Data Timing Specifications ................................. 8
Downstream Protection ............................................................ 55
JESD204B Interface Electrical Specifications ........................... 8
Datapath PRBS ........................................................................... 56
AC Specifications.......................................................................... 9
Datapath PRBS IRQ ................................................................... 56
Absolute Maximum Ratings.......................................................... 10
Interrupt Request Operation ........................................................ 58
Reflow Profile .............................................................................. 10
Interrupt Service Routine .......................................................... 58
Thermal Management ............................................................... 10
Applications Information .............................................................. 59
Thermal Resistance .................................................................... 10
Hardware Considerations ......................................................... 59
ESD Caution ................................................................................ 10
Analog Interface Considerations .................................................. 62
Pin Configuration and Function Descriptions ........................... 11
Analog Modes of Operation ..................................................... 62
Typical Performance Characteristics ........................................... 13
Clock Input.................................................................................. 63
Static Linearity ............................................................................ 13
Shuffle Mode ............................................................................... 64
AC Performance (NRZ Mode) ................................................. 14
DLL............................................................................................... 64
AC (Mix-Mode) .......................................................................... 19
Voltage Reference ....................................................................... 64
DOCSIS Performance (NRZ Mode) ........................................ 22
Temperature Sensor ................................................................... 65
Terminology .................................................................................... 27
Analog Outputs .......................................................................... 65
Theory of Operation ...................................................................... 28
Start-Up Sequence .......................................................................... 67
Serial Port Operation ..................................................................... 29
Register Summary .......................................................................... 69
Serial Data Format ..................................................................... 29
Register Details ............................................................................... 76
Serial Port Pin Descriptions ...................................................... 29
Outline Dimensions ..................................................................... 126
Serial Port Options ..................................................................... 29
Ordering Guide ........................................................................ 126
Rev. D | Page 2 of 126
Data Sheet
AD9163
REVISION HISTORY
5/2019—Rev. C to Rev. D
Changes to INPUTS (SDIO, SCLK, CS, RESET, EX_ENABLE)
Parameters, Table 4 ........................................................................... 6
Changes to Table 10 and Thermal Resistance Section ...............10
Change to Transport Layer Testing Section.................................46
Changes to Data Format Section...................................................50
Deleted Table 36; Renumbered Sequentially ...............................55
Changes to Changing the NCO Frequency Section ...................55
Deleted Endnote 2, Table 36 ..........................................................56
Changes to Peak DAC Output Power Capability Section ..........65
Change to Register 0x280, Table 41 ..............................................68
Changes to Table 43 ........................................................................69
Changes to Table 44 ........................................................................76
Updated Outline Dimensions ......................................................126
7/2017—Rev. B to Rev. C
Changes to Table 44 ........................................................................74
Changes to Table 45 ......................................................................118
5/2017—Rev. A to Rev. B
Changes to Start-Up Sequence Section ........................................67
2/2017—Rev. 0 to Rev. A
Change to Endnote 1, Table 1 .......................................................... 4
Added Temperature Sensor Parameter, Table 1 ............................ 4
Change to OUTPUT± to VNEG_N1P2 Parameter, Table 10 ...... 10
Changes to Figure 99 ...................................................................... 38
Changes to Link Delay Setup Example, With Known Delays
Section .............................................................................................. 40
Changes to Link Delay Setup Example, Without Known Delays
Section .............................................................................................. 41
Changes to Table 23 ........................................................................ 43
Changed 4× Six-Lane (L = 3, M = 2, F = 4, S = 3) to 4× Three-Lane
(L = 3, M = 2, F = 4, S = 3), Table 29 ............................................ 46
Added Datapath PRBS Section and Datapath PRBS
IRQ Section ....................................................................................... 56
Moved Figure 133............................................................................ 64
Added Temperature Sensor Section ............................................. 65
Changes to Equivalent DAC Output and Transfer Function
Section .............................................................................................. 65
Changes to Output Stage Configuration Section and Figure 140
Caption ............................................................................................. 66
Added Register 0x132 Row to Register 0x135 Row, Table 44 ........ 70
Added Register 0x132 Row to Register 0x135 Row, Table 45 ........ 84
Change to Register 0x230............................................................... 86
7/2016—Revision 0: Initial Version
Rev. D | Page 3 of 126
AD9163
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
VDD25_DAC = 2.5 V, VDD12A = VDD12_CLK = 1.2 V, VNEG_N1P2 = −1.2 V, DVDD = 1.2 V, IOVDD = 2.5 V, VDD_1P2 =
DVDD_1P2 = PLL_LDO_VDD12 = 1.2 V, SYNC_VDD_3P3 = 3.3 V, DAC output full-scale current (IOUTFS) = 40 mA, and TA = −40°C to
+85°C, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
DAC Update Rate
Minimum
Maximum
Adjusted 4
ACCURACY
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
ANALOG OUTPUTS
Gain Error (with Internal
Reference)
Full-Scale Output Current
Minimum
Maximum
DAC CLOCK INPUT (CLK+, CLK−)
Differential Input Power
Common-Mode Voltage
Input Impedance1
TEMPERATURE DRIFT
Gain
Reference Voltage
TEMPERATURE SENSOR
Accuracy
REFERENCE
Internal Reference Voltage
ANALOG SUPPLY VOLTAGES
VDD25_DAC
VDD12A2
VDD12_CLK2
VNEG_N1P2
DIGITAL SUPPLY VOLTAGES
DVDD
IOVDD3
SERDES SUPPLY VOLTAGES
VDD_1P2
VTT_1P2
DVDD_1P2
PLL_LDO_VDD12
PLL_CLK_VDD12
SYNC_VDD_3P3
BIAS_VDD_1P2
Test Conditions/Comments
Min
16
Typ
Max
Unit
Bit
VDDx 1 = 1.3 V ± 2% 2
VDDx1 = 1.3 V ± 2%2, FIR85 3 2× interpolator enabled
VDDx1 = 1.3 V ± 2%2
6
12
1
1.5
6.4
12.8
1.0667
GSPS
GSPS
GSPS
GSPS
±2.7
±1.7
LSB
LSB
−1.7
%
RSET = 9.76 kΩ
RSET = 9.76 kΩ
7.37
35.8
8
38.76
8.57
41.3
mA
mA
RLOAD = 90 Ω differential on chip
AC-coupled
3 GSPS input clock
−20
0
0.6
90
+10
dBm
V
Ω
After single point calibration (see the Temperature Sensor section)
Can connect to VDD_1P2
Can connect to PLL_LDO_VDD12
Can connect to VDD_1P2
105
75
ppm/°C
ppm/°C
±5
%
1.19
V
2.375
1.14
1.14
−1.26
2.5
1.2
1.2
−1.2
2.625
1.326
1.326
−1.14
V
V
V
V
1.14
1.71
1.2
2.5
1.326
3.465
V
V
1.14
1.14
1.14
1.14
1.14
3.135
1.14
1.2
1.2
1.2
1.2
1.2
3.3
1.2
1.326
1.326
1.326
1.326
1.326
3.465
1.326
V
V
V
V
V
V
V
See the Clock Input section for more details.
For the lowest noise performance, use a separate power supply filter network for the VDD12_CLK and the VDD12A pins.
3
IOVDD can range from 1.8 V to 3.3 V, with ±5% tolerance.
4
The adjusted DAC update rate is calculated as fDAC divided by the minimum required interpolation factor. For the AD9163, the minimum interpolation factor is 6. Therefore, with
fDAC = 6 GSPS, fDAC adjusted = 1 GSPS. When FIR85 is enabled, which puts the device into 2× NRZ mode, fDAC = 2 × (DAC clock input frequency), and the minimum interpolation
increases to 12× (interpolation value). Thus, for the AD9163, with FIR85 enabled and DAC clock = 6 GSPS, fDAC = 12 GSPS, minimum interpolation = 12×, and the adjusted DAC
update rate = 1 GSPS.
1
2
Rev. D | Page 4 of 126
Data Sheet
AD9163
DAC INPUT CLOCK OVERCLOCKING SPECIFICATIONS
VDD25_DAC = 2.5 V, VDD12A = VDD12_CLK = 1.2 V, VNEG_N1P2 = −1.2 V, DVDD = 1.2 V, IOVDD = 2.5 V, VDD_1P2 =
DVDD_1P2 = PLL_LDO_VDD12 = 1.2 V, SYNC_VDD_3P3 = 3.3 V, IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted.
Maximum guaranteed speed using the temperatures and voltages conditions as shown in Table 2, where VDDx is VDD12_CLK, DVDD,
VDD_1P2, DVDD_1P2, and PLL_LDO_VDD12. Any DAC clock speed over 5.1 GSPS requires a maximum junction temperature of
105°C to avoid damage to the device. See Table 10 for details on maximum junction temperature permitted for certain clock speeds.
Table 2.
Parameter 1
MAXIMUM DAC UPDATE RATE
VDDx = 1.2 V ± 5%
VDDx = 1.2 V ± 2%
VDDx = 1.3 V ± 2%
1
Test Conditions/Comments
Min
TJMAX = 25°C
TJMAX = 85°C
TJMAX = 105°C
TJMAX = 25°C
TJMAX = 85°C
TJMAX = 105°C
TJMAX = 25°C
TJMAX = 85°C
TJMAX = 105°C
6.0
5.6
5.4
6.1
5.8
5.6
6.4
6.2
6.0
Typ
Max
Unit
GSPS
GSPS
GSPS
GSPS
GSPS
GSPS
GSPS
GSPS
GSPS
TJMAX is the maximum junction temperature.
POWER SUPPLY DC SPECIFICATIONS
IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted. FIR85 is the finite impulse response with 85 dB digital attenuation.
Table 3.
Parameter
8 LANES, 6× INTERPOLATION (80%), 3 GSPS
Analog Supply Currents
VDD25_DAC = 2.5 V
VDD12A = 1.2 V
VDD12_CLK = 1.2 V
VNEG_N1P2 = −1.2 V
Digital Supply Currents
DVDD = 1.2 V
IOVDD = 2.5 V
SERDES Supply Currents
VDD_1P2 = 1.2 V
DVDD_1P2 = 1.2 V
PLL_LDO_VDD12 = 1.2 V
SYNC_VDD_3P3 = 3.3 V
8 LANES, 8× INTERPOLATION (80%), 5 GSPS
Analog Supply Currents
VDD25_DAC = 2.5 V
VDD12A = 1.2 V
VDD12_CLK = 1.2 V
VNEG_N1P2 = −1.2 V
Digital Supply Currents
DVDD = 1.2 V
IOVDD = 2.5 V
SERDES Supply Currents
VDD_1P2 = 1.2 V
DVDD_1P2 = 1.2 V
PLL_LDO_VDD12 = 1.2 V
SYNC_VDD_3P3 = 3.3 V
Test Conditions/Comments
NCO on, FIR85 on
Min
Includes VTT_1P2, BIAS_VDD_1P2
Connected to PLL_CLK_VDD12
Typ
Max
Unit
93.8
3.7
228.7
−120.7
mA
µA
mA
mA
598.4
2.5
mA
mA
443.4
72.3
81.8
9.4
mA
mA
mA
mA
NCO on, FIR85 off (unless otherwise noted)
94
80
341
−112
100
150
435
mA
µA
mA
mA
NCO on, FIR85 off
495
2.5
878
2.7
mA
mA
Includes VTT_1P2, BIAS_VDD_1P2
477
89
81
9.3
681
130
112
11
mA
mA
mA
mA
−119
Connected to PLL_CLK_VDD12
Rev. D | Page 5 of 126
AD9163
Data Sheet
Parameter
POWER DISSIPATION
3 GSPS
2× NRZ Mode, 6×, FIR85 Enabled, NCO On
NRZ Mode, 24×, FIR85 Disabled, NCO On
5 GSPS
NRZ Mode, 8×, FIR85 Disabled, NCO On
NRZ Mode, 16×, FIR85 Disabled, NCO On
2× NRZ Mode, 6×, FIR85 Enabled, NCO On
Test Conditions/Comments
Min
Typ
Max
Unit
Using 80%, 3× filter, eight-lane JESD204B
Using 80%, 2× filter, one-lane JESD204B
2.1
1.3
W
W
Using 80%, 2× filter, eight-lane JESD204B
Using 80%, 2× filter, eight-lane JESD204B
Using 80%, 3× filter, eight-lane JESD204B
2.18
2.09
2.65
W
W
W
SERIAL PORT AND CMOS PIN SPECIFICATIONS
VDD25_DAC = 2.5 V, VDD12A = VDD12_CLK = 1.2 V, VNEG_N1P2 = −1.2 V, DVDD = 1.2 V, IOVDD = 2.5 V, VDD_1P2 =
DVDD_1P2 = PLL_LDO_VDD12 = 1.2 V, SYNC_VDD_3P3 = 3.3 V, IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted.
Table 4.
Parameter
WRITE OPERATION
Maximum SCLK Clock Rate
SCLK Clock High
SCLK Clock Low
SDIO to SCLK Setup Time
SCLK to SDIO Hold Time
CS to SCLK Setup Time
SCLK to CS Hold Time
READ OPERATION
SCLK Clock Rate
SCLK Clock High
SCLK Clock Low
SDIO to SCLK Setup Time
SCLK to SDIO Hold Time
CS to SCLK Setup Time
SCLK to SDIO (or SDO) Data Valid Time
CS to SDIO (or SDO) Output Valid to High-Z
INPUTS (SDIO, SCLK, CS, RESET, TX_ENABLE)
Voltage Input
High
Low
Current Input
High
Low
OUTPUTS (SDIO, SDO)
Voltage Output
High
Low
Current Output
High
Low
Symbol
fSCLK, 1/tSCLK
tPWH
tPWL
tDS
tDH
tS
tH
Test Comments/Conditions
See Figure 89
SCLK = 20 MHz
SCLK = 20 MHz
Min
100
3.5
4
4
1
9
9
Typ
Max
Unit
MHz
ns
ns
ns
ns
ns
ns
2
0.5
1
0.5
See Figure 88
fSCLK, 1/tSCLK
tPWH
tPWL
tDS
tDH
tS
tDV
20
Not shown in Figure 88 or
Figure 89
VIH
VIL
1.8 V ≤ IOVDD ≤ 3.3 V
1.8 V ≤ IOVDD ≤ 3.3 V
IIH
IIL
VOH
VOL
17
45
MHz
ns
ns
ns
ns
ns
ns
ns
0.3 × IOVDD
V
V
20
20
10
5
10
0.7 × IOVDD
75
−150
1.8 V ≤ IOVDD ≤ 3.3 V
1.8 V ≤ IOVDD ≤ 3.3 V
IOH
IOL
0.8 × IOVDD
0.2 × IOVDD
4
4
Rev. D | Page 6 of 126
µA
µA
V
V
mA
mA
Data Sheet
AD9163
JESD204B SERIAL INTERFACE SPEED SPECIFICATIONS
VDD25_DAC = 2.5 V, VDD12A = VDD12_CLK = 1.2 V, VNEG_N1P2 = −1.2 V, DVDD = 1.2 V, IOVDD = 2.5 V, VDD_1P2 =
DVDD_1P2 = PLL_LDO_VDD12 = 1.2 V, SYNC_VDD_3P3 = 3.3 V, IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted.
Table 5.
Parameter
SERIAL INTERFACE SPEED
Half Rate
Full Rate
Oversampling
2× Oversampling
Test Conditions/Comments
Guaranteed operating range
Min
Typ
6
3
1.5
0.750
Max
Unit
12.5
6.25
3.125
1.5625
Gbps
Gbps
Gbps
Gbps
SYSREF± TO DAC CLOCK TIMING SPECIFICATIONS
VDD25_DAC = 2.5 V, VDD12A = VDD12_CLK = 1.2 V, VNEG_N1P2 = −1.2 V, DVDD = 1.2 V, IOVDD = 2.5 V, VDD_1P2 =
DVDD_1P2 = PLL_LDO_VDD12 = 1.2 V, SYNC_VDD_3P3 = 3.3 V, IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted.
Table 6.
Parameter 1
SYSREF± DIFFERENTIAL SWING = 1.0 V
Minimum Setup Time, tSYSS
Minimum Hold Time, tSYSH
AC-coupled
DC-coupled, common-mode voltage = 0 V
DC-coupled, common-mode voltage = 1.25 V
AC-coupled
DC-coupled, common-mode voltage = 0 V
DC-coupled, common-mode voltage = 1.25 V
Min
Typ
Max
Unit
65
45
68
19
5
51
117
77
129
63
37
114
ps
ps
ps
ps
ps
ps
The SYSREF± pulse must be at least four DAC clock edges wide plus the setup and hold times in Table 6. For more information, see the Sync Processing Modes
Overview section.
tSYSS
tSYSH
SYSREF+
CLK+
MIN 4 DAC CLOCK EDGES
Figure 2. SYSREF± to DAC Clock Timing Diagram (Only SYSREF+ and CLK+ Shown)
Rev. D | Page 7 of 126
14415-002
1
Test Conditions/Comments
AD9163
Data Sheet
DIGITAL INPUT DATA TIMING SPECIFICATIONS
VDD25_DAC = 2.5 V, VDD12A = VDD12_CLK = 1.2 V, VNEG_N1P2 = −1.2 V, DVDD = 1.2 V, IOVDD = 2.5 V, VDD_1P2 =
DVDD_1P2 = PLL_LDO_VDD12 = 1.2 V, SYNC_VDD_3P3 = 3.3 V, IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted.
Table 7.
Parameter
LATENCY 1
Interface
Interpolation
Power-Up Time
DETERMINISTIC LATENCY
Fixed
Variable
SYSREF± to LOCAL MULTIFRAME
CLOCKS (LMFC) DELAY
Test Conditions/Comments
Min
From DAC output off to enabled
Typ
Max
Unit
1
See Table 32
10
PCLK 2 cycle
ns
12
2
PCLK2 cycles
PCLK2 cycles
DAC clock cycles
4
Total latency (or pipeline delay) through the device is calculated as follows:
Total Latency = Interface Latency + Fixed Latency + Variable Latency + Pipeline Delay
See Table 32 for examples of the pipeline delay per block.
2
PCLK is the internal processing clock for the AD9163 and equals the lane rate ÷ 40.
1
JESD204B INTERFACE ELECTRICAL SPECIFICATIONS
VDD25_DAC = 2.5 V, VDD12A = VDD12_CLK = 1.2 V, VNEG_N1P2 = −1.2 V, DVDD = 1.2 V, IOVDD = 2.5 V, VDD_1P2 = DVDD_1P2 =
PLL_LDO_VDD12 = 1.2 V, SYNC_VDD_3P3 = 3.3 V, IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted. VTT is the termination
voltage.
Table 8.
Parameter
JESD204B DATA INPUTS
Input Leakage Current
Logic High
Logic Low
Unit Interval
Common-Mode Voltage
Differential Voltage
VTT Source Impedance
Differential Impedance
Differential Return Loss
Common-Mode Return Loss
SYSREF± INPUT
Differential Impedance
DIFFERENTIAL OUTPUTS (SYNCOUT±) 2
Output Differential Voltage
Output Offset Voltage
1
2
Symbol
Test Conditions/Comments
Min
TA = 25°C
Input level = 1.2 V ± 0.25 V,
VTT = 1.2 V
Input level = 0 V
UI
VRCM
R_VDIFF
ZTT
ZRDIFF
RLRDIF
RLRCM
AC-coupled, VTT = VDD_1P21
At dc
At dc
80
Rev. D | Page 8 of 126
100
8
6
1333
+1.85
1050
30
120
121
420
1.2
Unit
µA
−4
80
−0.05
110
350
1.15
As measured on the input side of the ac coupling capacitor.
IEEE Standard 1596.3 LVDS compatible.
Max
10
169-ball CSP_BGA
Driving 100 Ω differential load
VOD
VOS
Typ
µA
ps
V
mV
Ω
Ω
dB
dB
Ω
450
1.27
mV
V
Data Sheet
AD9163
AC SPECIFICATIONS
VDD25_DAC = 2.5 V, VDD12A = VDD12_CLK = 1.2 V, VNEG_N1P2 = −1.2 V, DVDD = 1.2 V, IOVDD = 2.5 V, VDD_1P2 =
DVDD_1P2 = PLL_LDO_VDD12 = 1.2 V, SYNC_VDD_3P3 = 3.3 V, IOUTFS = 40 mA, TA = 25°C, unless otherwise noted.
Table 9. AC Specifications
Parameter
SPURIOUS-FREE DYNAMIC RANGE (SFDR) 1
Single Tone, fDAC = 5000 MSPS
fOUT = 70 MHz
fOUT = 500 MHz
fOUT = 1000 MHz
fOUT = 2000 MHz
fOUT = 4000 MHz
Single Tone, fDAC = 5000 MSPS
fOUT = 70 MHz
fOUT = 500 MHz
fOUT = 1000 MHz
fOUT = 2000 MHz
fOUT = 4000 MHz
DOCSIS
fOUT = 70 MHz
fOUT = 70 MHz
fOUT = 70 MHz
fOUT = 950 MHz
fOUT = 950 MHz
fOUT = 950 MHz
Wireless Infrastructure
fOUT = 960 MHz
fOUT = 1990 MHz
ADJACENT CHANNEL POWER
fOUT = 877 MHz
fOUT = 877 MHz
fOUT = 1887 MHz
fOUT = 1980 MHz
INTERMODULATION DISTORTION
fOUT = 900 MHz
fOUT = 900 MHz
fOUT = 1800 MHz
fOUT = 1800 MHz
NOISE SPECTRAL DENSITY (NSD)
Single Tone, fDAC = 5000 MSPS
fOUT = 550 MHz
fOUT = 960 MHz
fOUT = 1990 MHz
SINGLE SIDEBAND (SSB) PHASE NOISE AT OFFSET
1 kHz
10 kHz
100 kHz
1 MHz
10 MHz
1
Test Conditions/Comments
Min
FIR85 enabled
−6 dBFS, shuffle enabled
FIR85 enabled
fDAC = 3076 MSPS
Single carrier
Four carriers
Eight carriers
Single carrier
Four carriers
Eight carriers
fDAC = 5000 MSPS
Two-carrier GSM signal at −9 dBFS;
across 925 MHz to 960 MHz band
Two-carrier GSM signal at −9 dBFS;
across 1930 MHz to 1990 MHz band
fDAC = 5000 MSPS
One carrier, first adjacent channel
Two carriers, first adjacent channel
One carrier, first adjacent channel
Four carriers, first adjacent channel
fDAC = 5000 MSPS, two-tone test
0 dBFS
−6 dBFS, shuffle enabled
0 dBFS
−6 dBFS, shuffle enabled
Typ
Max
Unit
−82
−75
−65
−70
−60
dBc
dBc
dBc
dBc
dBc
−75
−75
−70
−75
−65
dBc
dBc
dBc
dBc
dBc
−70
−70
−67
−70
−68
−64
dBc
dBc
dBc
dBc
dBc
dBc
−85
dBc
−81
dBc
−79
−76
−74
−70
dBc
dBc
dBc
dBc
−80
−80
−68
−78
dBc
dBc
dBc
dBc
−168
−167
−164
dBm/Hz
dBm/Hz
dBm/Hz
−119
−125
−135
−144
−156
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fOUT = 3800 MHz, fDAC = 4000 MSPS
See the Clock Input section for more details on optimizing SFDR and reducing the image of the fundamental with clock input tuning.
Rev. D | Page 9 of 126
AD9163
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 10.
SYSREF±
CLK± to Ground
RESET, IRQ, CS, SCLK, SDIO,
SDO to Ground
Junction Temperature1
fDAC = 6 GSPS
fDAC ≤ 5.1 GSPS
Ambient Operating
Temperature Range (TA)
Storage Temperature Range
VDD12A, VDD12_CLK, DVDD,
VDD_1P2, VTT_1P2,
DVDD_1P2, PLL_LDO_VDD12,
PLL_CLK_VDD12,
BIAS_VDD_1P2 to Ground
VDD25_DAC to Ground
VNEG_N1P2 to Ground
IOVDD, SYNC_VDD_3P3 to
Ground
1
Rating
−0.3 V to VDD25_DAC + 0.3 V
−0.3 V to SYNC_VDD_3P3 + 0.3 V
Figure 3 shows the profile view of the device mounted to a user
printed circuit board (PCB) and a heat sink (typically the
aluminum case) to keep the junction (exposed die) below the
maximum junction temperature in Table 10.
−0.3 V to VDD25_DAC −
(VNEG_N1P2) + 0.2 V
GND − 0.5 V to +2.5 V
−0.3 V to VDD12_CLK + 0.3 V
−0.3 V to IOVDD + 0.3 V
CUSTOMER CASE (HEAT SINK)
CUSTOMER THERMAL FILLER
SILICON (DIE)
IC PROFILE
PACKAGE SUBSTRATE
14415-700
Parameter
ISET, VREF to VBG_NEG
SERDINx±, VTT_1P2,
SYNCOUT±
OUTPUT± to VNEG_N1P2
CUSTOMER PCB
105°C
110°C
−40°C to +85°C
Figure 3. Typical Thermal Management Solution
THERMAL RESISTANCE
Typical θJA and θJC values are specified for a 4-layer JEDEC 2S2P
high effective thermal conductivity test board for balled
surface-mount packages. θJA is obtained in still air conditions
(JESD51-2). Airflow increases heat dissipation, effectively reducing
θJA. θJC is obtained with the test case temperature monitored at
the bottom of the package.
−65°C to +150°C
−0.3 V to +1.326 V
−0.3 V to +2.625 V
−1.26 V to +0.3 V
−0.3 V to +3.465 V
θJA =
Some operating modes of the device may cause the device to approach or
exceed the maximum junction temperature during operation at supported
ambient temperatures. Removal of heat from the device may require
additional measures such as active airflow, heat sinks, or other measures.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
REFLOW PROFILE
The AD9163 reflow profile is in accordance with the JEDEC
JESD204B criteria for Pb-free devices. The maximum reflow
temperature is 260°C.
THERMAL MANAGEMENT
The AD9163 is a high power device that can dissipate nearly
3 W depending on the user application and configuration.
Because of the power dissipation, the AD9163 uses an exposed
die package to give the customer the most effective method of
controlling the die temperature. The exposed die allows cooling
of the die directly.
θJC =
TJ − TA
P
TJ − TC
P
where:
θJA is the natural convection junction-to-ambient air thermal
resistance measured in a one-cubic foot sealed enclosure.
TJ is the die junction temperature.
TA is the ambient temperature in a still air environment.
P is the total power (heat) dissipated in the chip.
θJC is the junction-to-case thermal resistance. (In the case of the
AD9163, this is measured at the top of the package on the bare
die.)
TC is the package case temperature. (In the case of the AD9163,
the temperature is measured on the bare die.)
Table 11. Thermal Resistance
Package Type
BC-169-2
ESD CAUTION
Rev. D | Page 10 of 126
θJA
14.6
θJC
0.02
Unit
°C/W
Data Sheet
AD9163
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
A
VSS
VNEG_N1P2
VDD25_DAC
VNEG_N1P2
VDD25_DAC
OUTPUT–
OUTPUT+
VDD25_DAC
VNEG_N1P2
VDD25_DAC
VSS
ISET
VREF
A
B
CLK+
VSS
VSS
VDD25_DAC
VNEG_N1P2
VDD25_DAC
VDD25_DAC
VNEG_N1P2
VDD25_DAC
VDD12A
VDD12A
VDD25_DAC
VNEG_N1P2
B
C
CLK–
VSS
VSS
VSS
VDD25_DAC
VNEG_N1P2
VNEG_N1P2
VDD25_DAC
VBG_NEG
VSS
VSS
VSS
VSS
C
D
VSS
VDD12_CLK
VDD12_CLK
VDD12_CLK
VDD12_CLK
VSS
VSS
VDD12_CLK
VDD12_CLK
VDD12_CLK
VDD12_CLK
VDD12_CLK
VDD12_CLK
D
E
VDD12_CLK
VSS
VSS
VSS
DVDD
DVDD
VSS
DVDD
DVDD
VSS
VSS
VSS
VSS
E
F
SYSREF+
SYSREF–
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CS
VSS
F
G
VSS
VSS
TX_ENABLE
IRQ
DVDD
DVDD
DVDD
DVDD
DVDD
SDIO
SDO
VSS
VSS
G
H
SERDIN7+
SERDIN7–
VDD_1P2
RESET
IOVDD
DVDD_1P2
VSS
DVDD_1P2
IOVDD
SCLK
VDD_1P2
SERDIN0–
SERDIN0+
H
J
VSS
VSS
VDD_1P2
DNC
DNC
VSS
VSS
VSS
SYNCOUT–
SYNCOUT+
VDD_1P2
VSS
VSS
J
K
SERDIN6+
SERDIN6–
VTT_1P2
SYNC_
VDD_3P3
DNC
VSS
PLL_CLK_
VDD12
PLL_LDO_
VDD12
DNC
SYNC_
VDD_3P3
VTT_1P2
SERDIN1–
SERDIN1+
K
L
VSS
VSS
VDD_1P2
VDD_1P2
VDD_1P2
VSS
DNC
VSS
VDD_1P2
VDD_1P2
VDD_1P2
VSS
VSS
L
M
VSS
VSS
SERDIN5+
VSS
SERDIN4+
VSS
PLL_LDO_
BYPASS
VSS
SERDIN3+
VSS
SERDIN2+
VSS
VSS
M
VSS
SERDIN5–
VSS
SERDIN4–
VSS
VSS
VSS
SERDIN3–
VSS
SERDIN2–
VSS
BIAS_
VDD_1P2
N
2
3
4
5
6
7
8
9
10
11
12
13
1
–1.2V ANALOG SUPPLY
2.5V ANALOG SUPPLY
1.2V DAC SUPPLY
GROUND
1.2V DAC CLK SUPPLY
SERDES INPUT
SERDES 3.3V VCO SUPPLY
SERDES 1.2V SUPPLY
DAC RF SIGNALS
SYSREF±/SYNCOUT±
CMOS I/O
IOVDD
DNC = DO NOT CONNECT.
REFERENCE
14415-004
N BIAS_VDD_1P2
Figure 4. 169-Ball CSP_BGA Pin Configuration
Table 12. 169-Ball CSP_BGA Pin Function Descriptions
Pin No.
A1, A11, B2, B3, C2, C3, C4, C10, C11, C12, C13, D1, D6, D7, E2, E3,
E4, E7, E10, E11, E12, E13, F3, F4, F5, F6, F7, F8, F9, F10, F11, F13,
G1, G2, G12, G13, H7, J1, J2, J6, J7, J8, J12, J13, K6, L1, L2, L6, L8,
L12, L13, M1, M2, M4, M6, M8, M10, M12, M13, N2, N4, N6, N7,
N8, N10, N12
A2, A4, A9, B5, B8, B13, C6, C7
A3, A5, A8, A10, B4, B6, B7, B9, B12, C5, C8
A6
A7
A12
Mnemonic
VSS
Description
Supply Return. Connect these pins to ground.
VNEG_N1P2
VDD25_DAC
OUTPUT−
OUTPUT+
ISET
A13
VREF
B1, C1
B10, B11
C9
CLK+, CLK−
VDD12A
VBG_NEG
D2, D3, D4, D5, D8, D9, D10, D11, D12, D13, E1
E5, E6, E8, E9, G5, G6, G7, G8, G9
VDD12_CLK
DVDD
−1.2 V Analog Supply Voltage.
2.5 V Analog Supply Voltage.
DAC Negative Current Output.
DAC Positive Current Output.
Reference Current. Connect this pin to
VNEG_N1P2 with a 9.6 kΩ resistor.
1.2 V Reference Input/Output. Connect this pin
to VSS with a 1 µF capacitor.
Positive and Negative DAC Clock Inputs.
1.2 V Analog Supply Voltage.
−1.2 V Reference. Connect this pin to
VNEG_N1P2 with a 0.1 µF capacitor.
1.2 V Clock Supply Voltage.
1.2 V Digital Supply Voltage.
Rev. D | Page 11 of 126
AD9163
Data Sheet
Pin No.
F1, F2
Mnemonic
SYSREF+, SYSREF−
F12
CS
G3
TX_ENABLE
G4
IRQ
G10
SDIO
G11
SDO
H10
SCLK
H3, H11, J3, J11, L3, L4, L5, L9, L10, L11
H4
VDD_1P2
RESET
H5, H9
IOVDD
H6, H8
H1, H2
DVDD_1P2
SERDIN7+,
SERDIN7−
SERDIN6+,
SERDIN6−
SERDIN5+,
SERDIN5−
SERDIN4+,
SERDIN4−
SERDIN3+,
SERDIN3−
SERDIN2+,
SERDIN2−
SERDIN1−,
SERDIN1+
SERDIN0−,
SERDIN0+
DNC
SYNCOUT−,
SYNCOUT+
VTT_1P2
SYNC_VDD_3P3
PLL_CLK_VDD12
PLL_LDO_VDD12
PLL_LDO_BYPASS
BIAS_VDD_1P2
K1, K2
M3, N3
M5, N5
M9, N9
M11, N11
K12, K13
H12, H13
J4, J5, K5, K9, L7
J9, J10
K3, K11
K4, K10
K7
K8
M7
N1, N13
Rev. D | Page 12 of 126
Description
System Reference Positive and Negative Inputs.
These pins are self biased for ac coupling. They
can be ac-coupled or dc-coupled.
Serial Port Chip Select Bar (Active Low) Input.
CMOS levels on this pin are determined with
respect to IOVDD.
Transmit Enable Input. This pin can be used
instead of the DAC output bias power-down bits
in Register 0x040, Bits[1:0] to enable the DAC
output. CMOS levels are determined with
respect to IOVDD.
Interrupt Request Output (Active Low, Open
Drain).
Serial Port Data Input/Output. CMOS levels on
this pin are determined with respect to IOVDD.
Serial Port Data Output. CMOS levels on this pin
are determined with respect to IOVDD.
Serial Port Data Clock. CMOS levels on this pin
are determined with respect to IOVDD.
1.2 V SERDES Digital Supply.
Reset Bar (Active Low) Input. CMOS levels on this
pin are determined with respect to IOVDD.
Supply Voltage for CMOS Input/Output and SPI.
Operational for 1.8 V to 3.3 V (see Table 1 for
details).
1.2 V SERDES Digital Supply Voltage.
SERDES Lane 7 Positive and Negative Inputs.
SERDES Lane 6 Positive and Negative Inputs.
SERDES Lane 5 Positive and Negative Inputs.
SERDES Lane 4 Positive and Negative Inputs.
SERDES Lane 3 Positive and Negative Inputs.
SERDES Lane 2 Positive and Negative Inputs.
SERDES Lane 1 Negative and Positive Inputs.
SERDES Lane 0 Negative and Positive Inputs.
Do Not Connect. Do not connect to these pins.
Negative and Positive LVDS Sync (Active Low)
Output Signals.
1.2 V SERDES VTT Digital Supply Voltage.
3.3 V SERDES Sync Supply Voltage.
1.2 V SERDES PLL Clock Supply Voltage.
1.2 V SERDES PLL Supply.
1.2 V SERDES PLL Supply Voltage Bypass.
1.2 V SERDES Supply Voltage.
Data Sheet
AD9163
TYPICAL PERFORMANCE CHARACTERISTICS
STATIC LINEARITY
IOUTFS = 40 mA, nominal supplies, TA = 25°C, unless otherwise noted.
4
15
2
10
5
–2
DNL (LSB)
INL (LSB)
0
0
–4
–6
–8
–5
0
10000
20000
30000
40000
50000
60000
CODE
–12
14415-005
–10
0
10000
20000
30000
40000
50000
60000
CODE
Figure 5. INL, IOUTFS = 20 mA
14415-008
–10
Figure 8. DNL, IOUTFS = 20 mA
15
4
2
10
5
DNL (LSB)
INL (LSB)
0
0
–2
–4
–6
–8
–5
0
10000
20000
30000
40000
50000
60000
CODE
–12
14415-006
–10
0
10000
20000
30000
40000
50000
60000
50000
60000
CODE
Figure 6. INL, IOUTFS = 30 mA
14415-009
–10
Figure 9. DNL, IOUTFS = 30 mA
4
15
2
0
DNL (LSB)
5
0
–2
–4
–6
–8
–5
–10
0
10000
20000
30000
40000
CODE
50000
60000
Figure 7. INL, IOUTFS = 40 mA
–12
0
10000
20000
30000
40000
CODE
Figure 10. DNL, IOUTFS = 40 mA
Rev. D | Page 13 of 126
14415-010
–10
14415-007
INL (LSB)
10
AD9163
Data Sheet
AC PERFORMANCE (NRZ MODE)
0
0
–20
–20
MAGNITUDE (dBm)
–40
–60
–40
–60
1000
2000
3000
4000
5000
FREQUENCY (MHz)
14415-011
0
0
0
0
–20
–20
MAGNITUDE (dBm)
4000
5000
–40
–60
–40
–60
0
1000
2000
3000
4000
5000
FREQUENCY (MHz)
14415-012
–80
Figure 12. Single-Tone Spectrum at fOUT = 70 MHz (FIR85 Enabled)
–40
0
3000
2000
4000
5000
FREQUENCY (MHz)
Figure 15. Single-Tone Spectrum at fOUT = 2000 MHz (FIR85 Enabled)
–40
fDAC = 2500MHz
fDAC = 3000MHz
fDAC = 5000MHz
fDAC = 6000MHz
–50
1000
14415-015
MAGNITUDE (dBm)
3000
Figure 14. Single-Tone Spectrum at fOUT = 2000 MHz
–80
–50
fDAC = 2500MHz
fDAC = 3000MHz
fDAC = 5000MHz
fDAC = 6000MHz
–60
IMD (dBc)
–60
–70
–70
–80
–80
–90
–90
0
500
1000
1500
2000
fOUT (MHz)
2500
3000
14415-013
SFDR (dBc)
2000
FREQUENCY (MHz)
Figure 11. Single-Tone Spectrum at fOUT = 70 MHz
–100
1000
14415-014
–80
–80
–100
0
500
1000
1500
2000
fOUT (MHz)
Figure 16. IMD vs. fOUT over fDAC
Figure 13. SFDR vs. fOUT over fDAC
Rev. D | Page 14 of 126
2500
3000
14415-016
MAGNITUDE (dBm)
IOUTFS = 40 mA, fDAC = 5.0 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
Data Sheet
AD9163
IOUTFS = 40 mA, fDAC = 5.0 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
–40
SHUFFLE FALSE
SHUFFLE TRUE
–50
–60
–70
–80
–80
–90
–90
500
1000
1500
2000
2500
fOUT (MHz)
–100
0
SHUFFLE FALSE
SHUFFLE TRUE
SFDR (dBc)
–70
–80
–90
–90
500
1000
1500
2000
2500
fOUT (MHz)
–100
0
–50
1500
2000
2500
IOUTFS = 20mA
IOUTFS = 30mA
IOUTFS = 40mA
–60
IMD (dBc)
–70
–70
–80
–80
–90
–90
500
1000
1500
fOUT (MHz)
2000
2500
14415-019
IN-BAND THIRD HARMONIC (dBc)
–40
–60
–100
0
1000
Figure 21. SFDR vs. fOUT over DAC IOUTFS
SHUFFLE FALSE
SHUFFLE TRUE
DIGITAL SCALE = 0dB
DIGITAL SCALE = –6dB
DIGITAL SCALE = –12dB
DIGITAL SCALE = –18dB
500
fOUT (MHz)
Figure 18. SFDR for In-Band Second Harmonic vs. fOUT over Digital Scale
–50
2500
IOUTFS = 20mA
IOUTFS = 30mA
IOUTFS = 40mA
–70
–80
–40
2500
–60
–60
–100
0
2000
–50
14415-018
IN-BAND SECOND HARMONIC (dBc)
–50
1500
Figure 20. IMD vs. fOUT over Digital Scale
–40
DIGITAL SCALE = 0dB
DIGITAL SCALE = –6dB
DIGITAL SCALE = –12dB
DIGITAL SCALE = –18dB
1000
fOUT (MHz)
Figure 17. SFDR vs. fOUT over Digital Scale
–40
500
14415-020
IMD (dBc)
–70
14415-017
SFDR (dBc)
–60
–100
0
SHUFFLE FALSE
SHUFFLE TRUE
DIGITAL SCALE = 0dB
DIGITAL SCALE = –6dB
DIGITAL SCALE = –12dB
DIGITAL SCALE = –18dB
14415-021
–50
DIGITAL SCALE = 0dB
DIGITAL SCALE = –6dB
DIGITAL SCALE = –12dB
DIGITAL SCALE = –18dB
14415-022
–40
Figure 19. SFDR for In-Band Third Harmonic vs. fOUT over Digital Scale
Rev. D | Page 15 of 126
–100
0
500
1000
1500
2000
fOUT (MHz)
Figure 22. IMD vs. fOUT over DAC IOUTFS
AD9163
Data Sheet
IOUTFS = 40 mA, fDAC = 5.0 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
–150
–40
fDAC = 2500MHz
fDAC = 3000MHz
fDAC = 5000MHz
fDAC = 6000MHz
TEMPERATURE = –40°C
TEMPERATURE = +25°C
TEMPERATURE = +85°C
–50
W-CDMA NSD (dBm/Hz)
–155
–70
–80
–160
–165
500
1000
1500
2000
2500
fOUT (MHz)
–175
400
14415-023
–100
0
–150
W-CDMA NSD (dBm/Hz)
–165
1400
1600
1800
2000
–160
–165
–170
–170
600
800
1000
1200
1400
1600
1800
2000
fOUT (MHz)
–175
400
800
600
1000
1200
1400
1600
1800
2000
fOUT (MHz)
Figure 27. W-CDMA NSD Measured at 10% Offset from fOUT vs. fOUT over fDAC
Figure 24. Single-Tone NSD Measured at 70 MHz vs. fOUT over fDAC
–40
–150
TEMPERATURE = –40°C
TEMPERATURE = +25°C
TEMPERATURE = +85°C
fDAC = 2500MHz
fDAC = 3000MHz
fDAC = 5000MHz
fDAC = 6000MHz
–50
–60
IMD (dBc)
–160
–165
–70
–80
–170
600
800
1000
1200
1400
fOUT (MHz)
1600
1800
2000
Figure 25. Single-Tone NSD Measured at 10% Offset from fOUT vs. fOUT over fDAC
Rev. D | Page 16 of 126
–100
0
500
1000
150 0
200 0
fOUT (MHz)
Figure 28. IMD vs. fOUT over Temperature
2500
14415-026
–175
400
–90
14415-224
SINGLE-TONE NSD (dBm/Hz)
1200
fDAC = 2500MHz
fDAC = 3000MHz
fDAC = 5000MHz
fDAC = 6000MHz
–155
14415-024
SINGLE-TONE NSD (dBm/Hz)
fDAC = 2500MHz
fDAC = 3000MHz
fDAC = 5000MHz
fDAC = 6000MHz
–160
–155
1000
Figure 26. W-CDMA NSD Measured at 70 MHz vs. fOUT over fDAC
–150
–175
400
800
fOUT (MHz)
Figure 23. SFDR vs. fOUT over Temperature
–155
600
14415-225
–170
–90
14415-225
SFDR (dBc)
–60
Data Sheet
AD9163
IOUTFS = 40 mA, fDAC = 5.0 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
–150
TEMPERATURE = –40°C
TEMPERATURE = +25°C
TEMPERATURE = +90°C
–155
W-CDMA NSD (dBm/Hz)
–160
–165
–170
800
1000
1200
1400
1600
1800
2000
600
800
1000
1200
1400
1600
1800
2000
fOUT (MHz)
Figure 32. W-CDMA NSD Measured at 70 MHz vs. fOUT over Temperature
–150
TEMPERATURE = –40°C
TEMPERATURE = +25°C
TEMPERATURE = +90°C
–155
TEMPERATURE = –40°C
TEMPERATURE = +25°C
TEMPERATURE = +90°C
W-CDMA NSD (dBm/Hz)
–155
–160
–165
–170
–160
–165
600
800
1000
1200
1400
1600
1800
fOUT (MHz)
2000
–175
400
800
1000
1200
1400
1600
1800
fOUT (MHz)
2000
Figure 33. W-CDMA NSD Measured at 10% Offset from fOUT vs. fOUT over
Temperature
14415-029
Figure 30. Single-Tone NSD Measured at 10% Offset from fOUT vs. fOUT over
Temperature
600
14415-331
–170
14415-227
SINGLE-TONE NSD (dBm/Hz)
–175
400
14415-028
600
Figure 29. Single-Tone NSD Measured at 70 MHz vs. fOUT over Temperature
–175
400
–165
–170
fOUT (MHz)
–150
–160
Figure 31. Single-Carrier W-CDMA at 877.5 MHz
14415-032
–175
400
TEMPERATURE = –40°C
TEMPERATURE = +25°C
TEMPERATURE = +90°C
–155
14415-027
SINGLE-TONE NSD (dBm/Hz)
–150
Figure 34. Two-Carrier W-CDMA at 875 MHz
Rev. D | Page 17 of 126
AD9163
Data Sheet
IOUTFS = 40 mA, fDAC = 5.0 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
–60
FIRST ACLR
SECOND ACLR
–65
–70
–70
ACLR (dBc)
–65
–75
–80
–80
–85
–85
1000
1200
1400
1600
1800
2000
2200
fOUT (MHz)
Figure 35. Single-Carrier, W-CDMA Adjacent Channel Leakage Ratio (ACLR)
vs. fOUT (First ACLR, Second ACLR)
–60
–65
–90
800
–60
–65
1800
2000
2200
THIRD ACLR
FOURTH ACLR
FIFTH ACLR
ACLR (dBc)
–75
–80
–80
–85
–85
1000
1200
1400
1600
1800
2000
2200
Figure 36. Single-Carrier, W-CDMA ACLR vs. fOUT (Third ACLR, Fourth ACLR,
Fifth ACLR)
–60
–90
800
14415-031
1200
1400
1600
1800
70MHz
900MHz
1800MHz
3900MHz
CLOCK SOURCE
SSB PHASE NOISE (dBc/Hz)
–80
–120
–140
–160
2200
Figure 39. Two-Carrier, W-CDMA ACLR vs. fOUT (Third ACLR, Fourth ACLR,
Fifth ACLR)
–60
–100
2000
fOUT (MHz)
70MHz
900MHz
1800MHz
3900MHz
CLOCK SOURCE
–80
1000
–100
–120
–140
10
100
1k
10k
100k
1M
10M
100M
OFFSET OVER fOUT (Hz)
14415-035
–160
–180
Figure 37. SSB Phase Noise vs. Offset over fOUT, fDAC = 4000 MSPS
(Two Different DAC Clock Sources Used for Best Composite Curve)
10
100
1k
10k
100k
1M
10M
100M
OFFSET OVER fOUT (Hz)
Figure 40. SSB Phase Noise vs. Offset over fOUT, fDAC = 6000 MSPS
Rev. D | Page 18 of 126
14415-036
ACLR (dBc)
1600
–70
fOUT (MHz)
SSB PHASE NOISE (dBc/Hz)
1400
Figure 38. Two-Carrier, W-CDMA ACLR vs. fOUT (First ACLR, Second ACLR)
THIRD ACLR
FOURTH ACLR
FIFTH ACLR
–75
–180
1200
fOUT (MHz)
–70
–90
800
1000
14415-034
–90
800
FIRST ACLR
SECOND ACLR
14415-033
–75
14415-030
ACLR (dBc)
–60
Data Sheet
AD9163
AC (MIX-MODE)
0
0
–20
–20
MAGNITUDE (dBm)
–40
–60
–40
–60
2000
1000
3000
4000
5000
FREQUENCY (MHz)
14415-038
0
0
0
0
–20
–20
MAGNITUDE (dBm)
4000
5000
–40
–60
–40
–60
–80
2000
3000
4000
5000
FREQUENCY (MHz)
14415-039
1000
0
Figure 42. Single-Tone Spectrum at fOUT = 2350 MHz (FIR85 Enabled)
0
3000
4000
5000
Figure 45. Single-Tone Spectrum at fOUT = 4000 MHz (FIR85 Enabled)
–155
–155
W-CDMA NSD (dBm/Hz)
–150
–165
2000
FREQUENCY (MHz)
–150
–160
1000
14415-042
MAGNITUDE (dBm)
3000
Figure 44. Single-Tone Spectrum at fOUT = 4000 MHz
–80
–160
–165
–170
–170
3000
4000
5000
6000
fOUT (MHz)
7000
14415-040
SINGLE-TONE NSD (dBm/Hz)
2000
FREQUENCY (MHz)
Figure 41. Single-Tone Spectrum at fOUT = 2350 MHz
–175
1000
14415-041
–80
–80
–175
3000
4000
5000
6000
fOUT (MHz)
Figure 46. W-CDMA NSD vs. fOUT
Figure 43. Single-Tone NSD vs. fOUT
Rev. D | Page 19 of 126
7000
14415-599
MAGNITUDE (dBm)
IOUTFS = 40 mA, fDAC = 5.0 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
AD9163
Data Sheet
IOUTFS = 40 mA, fDAC = 5.0 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
–40
–50
–50
–60
–60
SFDR (dBc)
–70
–80
4000
3000
SHUFFLE FALSE
SHUFFLE TRUE
5000
6000
7000
8000
fOUT (MHz)
–100
2000
3000
–50
DIGITAL SCALE
DIGITAL SCALE
DIGITAL SCALE
DIGITAL SCALE
=
=
=
=
–40
–50
IMD (dBc)
–70
–80
–90
–90
3000
4000
5000
7000
6000
8000
fOUT (MHz)
–100
2000
3000
–40
fDAC = 2500MHz
fDAC = 3000MHz
fDAC = 5000MHz
fDAC = 6000MHz
–50
6000
7000
9000
fDAC = 2500MHz
fDAC = 3000MHz
fDAC = 5000MHz
fDAC = 6000MHz
IMD (dBc)
–60
–70
–70
–80
–80
–90
–90
2000
3000
4000
5000
6000
7000
fOUT (MHz)
8000
9000
14415-046
SFDR (dBc)
5000
Figure 51. IMD vs. fOUT over DAC IOUTFS
–60
–100
1000
4000
fOUT (MHz)
Figure 48. IMD vs. fOUT over Digital Scale
–50
8000
IOUTFS = 20mA
IOUTFS = 30mA
IOUTFS = 40mA
–70
–80
–40
8000
–60
14415-045
IMD (dBc)
–60
–100
2000
7000
6000
Figure 50. SFDR vs. fOUT over DAC IOUTFS
SHUFFLE FALSE
SHUFFLE TRUE
0dB
–6dB
–12dB
–18dB
5000
fOUT (MHz)
Figure 47. SFDR vs. fOUT over Digital Scale
–40
4000
14415-047
–90
DIGITAL SCALE = 0dB
DIGITAL SCALE = –6dB
DIGITAL SCALE = –12dB
DIGITAL SCALE = –18dB
14415-048
–100
2000
–70
–80
14415-044
–90
IOUTFS = 20mA
IOUTFS = 30mA
IOUTFS = 40mA
14415-049
SFDR (dBc)
–40
–100
1000
Figure 49. SFDR vs. fOUT over fDAC
2000
3000
4000
5000
6000
7000
fOUT (MHz)
Figure 52. IMD vs. fOUT over fDAC
Rev. D | Page 20 of 126
8000
Data Sheet
AD9163
14415-051
14415-053
IOUTFS = 40 mA, fDAC = 5.0 GSPS, nominal supplies, TA = 25°C, unless otherwise noted.
Figure 53. Single-Carrier W-CDMA at 1887.5 MHz
–60
–65
–70
–70
ACLR (dBc)
–65
–75
–80
–85
–85
2800
3000
3200
3400
3600
3800
fOUT (MHz)
Figure 54. Single-Carrier, W-CDMA ACLR vs. fOUT (First ACLR, Second ACLR)
–65
–90
2600
3000
3200
3400
3600
3800
fOUT (MHz)
Figure 57. Four-Carrier, W-CDMA ACLR vs. fOUT (First ACLR, Second ACLR)
–60
THIRD ACLR
FOURTH ACLR
FIFTH ACL
–65
–70
THIRD ACLR
FOURTH ACLR
FIFTH ACL
ACLR (dBc)
–70
–75
–75
–80
–80
–85
–85
2800
3000
3200
fOUT (MHz)
3400
3600
3800
–90
2600
14415-055
–90
2600
2800
Figure 55. Single-Carrier, W-CDMA ACLR vs. fOUT (Third ACLR, Fourth ACLR,
Fifth ACLR)
2800
3000
3200
fOUT (MHz)
3400
3600
3800
14415-057
–60
ACLR (dBc)
–75
–80
–90
2600
FIRST ACLR
SECOND ACLR
14415-056
FIRST ACLR
SECOND ACLR
14415-054
ACLR (dBc)
–60
Figure 56. Four-Carrier W-CDMA at 1980 MHz
Figure 58. Four-Carrier, W-CDMA ACLR vs. fOUT (Third ACLR, Fourth ACLR,
Fifth ACLR)
Rev. D | Page 21 of 126
AD9163
Data Sheet
DOCSIS PERFORMANCE (NRZ MODE)
0
–10
–10
–20
–20
–30
–40
–50
–60
–30
–40
–50
–60
–70
–70
–80
–80
–90
500
1000
1500
2000
2500
3000
FREQUENCY (MHz)
–90
0
–10
–20
–20
–30
–30
MAGNITUDE (dBc)
–10
–40
–50
–60
–80
–90
2500
3000
FREQUENCY (MHz)
–90
0
500
1000
1500
2000
2500
3000
FREQUENCY (MHz)
Figure 60. Four Carriers at 70 MHz Output
Figure 63. Four Carriers at 70 MHz Output (Shuffle On)
0
0
–10
–10
–20
–20
MAGNITUDE (dBc)
–30
–40
–50
–60
–70
–30
–40
–50
–60
–70
–80
0
500
1000
1500
2000
2500
FREQUENCY (MHz)
3000
Figure 61. Eight Carriers at 70 MHz Output
–90
0
500
1000
1500
2000
2500
3000
FREQUENCY (MHz)
Figure 64. Eight Carriers at 70 MHz Output (Shuffle On)
Rev. D | Page 22 of 126
14415-363
–80
–90
14415-060
MAGNITUDE (dBc)
3000
–60
–80
2000
2500
–50
–70
1500
2000
–40
–70
14415-059
MAGNITUDE (dBc)
0
1000
1500
Figure 62. Single Carrier at 70 MHz Output (Shuffle On)
0
500
1000
FREQUENCY (MHz)
Figure 59. Single Carrier at 70 MHz Output
0
500
14415-362
0
14415-361
MAGNITUDE (dBc)
0
14415-058
MAGNITUDE (dBc)
IOUTFS = 40 mA, fDAC = 3.076 GSPS, nominal supplies, FIR85 enabled, TA = 25°C, unless otherwise noted.
Data Sheet
AD9163
0
–10
–10
–20
–20
–30
–40
–50
–60
–30
–40
–50
–60
–70
–70
–80
–80
500
1000
1500
2000
2500
3000
FREQUENCY (MHz)
–90
–10
–20
–20
MAGNITUDE (dBc)
–10
–30
–40
–50
–60
2500
3000
FREQUENCY (MHz)
–90
0
–10
–20
–20
MAGNITUDE (dBc)
–10
–30
–40
–50
–60
2500
FREQUENCY (MHz)
3000
–60
–80
2000
2500
–50
–80
1500
2000
–40
–70
1000
1500
–30
–70
3000
14415-063
MAGNITUDE (dBc)
0
500
1000
Figure 69. Four Carriers at 950 MHz Output (Shuffle On)
0
0
500
FREQUENCY (MHz)
Figure 66. Four Carriers at 950 MHz Output
–90
3000
–60
–80
2000
2500
–50
–80
1500
2000
–40
–70
1000
1500
–30
–70
14415-062
MAGNITUDE (dBc)
0
500
1000
Figure 68. Single Carrier at 950 MHz Output (Shuffle On)
0
0
500
FREQUENCY (MHz)
Figure 65. Single Carrier at 950 MHz Output
–90
0
14415-365
0
–90
0
500
1000
1500
2000
2500
3000
FREQUENCY (MHz)
Figure 70. Eight Carriers at 950 MHz Output (Shuffle On)
Figure 67. Eight Carriers at 950 MHz Output
Rev. D | Page 23 of 126
14415-366
–90
14415-364
MAGNITUDE (dBc)
0
14415-061
MAGNITUDE (dBc)
IOUTFS = 40 mA, fDAC = 3.076 GSPS, nominal supplies, FIR85 enabled, TA = 25°C, unless otherwise noted.
AD9163
Data Sheet
IOUTFS = 40 mA, fDAC = 3.076 GSPS, nominal supplies, FIR85 enabled, TA = 25°C, unless otherwise noted.
–40
–60
–70
–80
0
200
400
600
800
1000
1200
1400
fOUT (MHz)
Figure 71. In-Band Second Harmonic vs. fOUT Performance for One DOCSIS Carrier
0
200
400
600
800
1000
1200
1400
fOUT (MHz)
Figure 74. In-Band Third Harmonic vs. fOUT Performance for One DOCSIS Carrier
–80
0
200
400
600
800
1000
1200
1400
Figure 72. In-Band Second Harmonic vs. fOUT Performance for Four DOCSIS
Carriers
–50
–60
–70
–80
–90
0
200
400
600
800
1000
1200
1400
fOUT (MHz)
14415-068
IN-BAND THIRD HARMONIC (dBc)
–70
14415-065
IN-BAND SECOND HARMONIC (dBc)
–60
fOUT (MHz)
Figure 75. In-Band Third Harmonic vs. fOUT Performance for Four DOCSIS Carriers
–40
–40
IN-BAND THIRD HARMONIC (dBc)
–50
–60
–70
–80
0
200
400
600
800
fOUT (MHz)
1000
1200
1400
Figure 73. In-Band Second Harmonic vs. fOUT Performance for Eight DOCSIS
Carriers
–50
–60
–70
–80
–90
14415-066
IN-BAND SECOND HARMONIC (dBc)
–80
–40
–50
–90
–70
–90
–40
–90
–60
0
200
400
600
800
fOUT (MHz)
1000
1200
1400
14415-069
–90
–50
14415-067
IN-BAND THIRD HARMONIC (dBc)
–50
14415-064
IN-BAND SECOND HARMONIC (dBc)
–40
Figure 76. In-Band Third Harmonic vs. fOUT Performance for Eight DOCSIS Carriers
Rev. D | Page 24 of 126
Data Sheet
AD9163
IOUTFS = 40 mA, fDAC = 3.076 GSPS, nominal supplies, FIR85 enabled, TA = 25°C, unless otherwise noted.
–40
–60
–70
–80
–60
–70
200
400
600
800
1000
1200
1400
–90
0
200
–40
ACPR (dBc)
–70
1000
1200
1400
1200
1400
Y-AXIS: FIRST ACPR
Y-AXIS: SECOND ACPR
Y-AXIS: THIRD ACPR
Y-AXIS: FOURTH ACPR
Y-AXIS: FIFTH ACPR
–50
–60
800
Figure 80. 16-Carrier ACPR vs. fOUT
Y-AXIS: FIRST ACPR
Y-AXIS: SECOND ACPR
Y-AXIS: THIRD ACPR
Y-AXIS: FOURTH ACPR
Y-AXIS: FIFTH ACPR
–50
600
fOUT (MHz)
Figure 77. Single-Carrier Adjacent Channel Power Ratio (ACPR) vs. fOUT
–40
400
14415-073
0
fOUT (MHz)
ACPR (dBc)
FIRST ACPR
SECOND ACPR
THIRD ACPR
FOURTH ACPR
FIFTH ACPR
–80
14415-070
–90
Y-AXIS:
Y-AXIS:
Y-AXIS:
Y-AXIS:
Y-AXIS:
–50
ACPR (dBc)
–50
ACPR (dBc)
–40
Y-AXIS: FIRST ACPR
Y-AXIS: SECOND ACPR
Y-AXIS: THIRD ACPR
Y-AXIS: FOURTH ACPR
Y-AXIS: FIFTH ACPR
–60
–70
–80
0
200
400
600
800
1000
1200
1400
fOUT (MHz)
–90
0
200
Y-AXIS:
Y-AXIS:
Y-AXIS:
Y-AXIS:
Y-AXIS:
800
1000
Figure 81. 32-Carrier ACPR vs. fOUT
0
FIRST ACPR
SECOND ACPR
THIRD ACPR
FOURTH ACPR
FIFTH ACPR
–10
MAGNITUDE (dBc)
–20
–60
–70
–80
–30
–40
–50
–60
–70
0
200
400
600
800
1000
fOUT (MHz)
1200
1400
–90
0
500
1000
1500
2000
2500
FREQUENCY (MHz)
Figure 82. 194-Carrier, Sinc Enabled, FIR85 Enabled
Figure 79. Eight-Carrier ACPR vs. fOUT
Rev. D | Page 25 of 126
3000
14415-075
–80
–90
14415-072
ACPR (dBc)
–50
600
fOUT (MHz)
Figure 78. Four-Carrier ACPR vs. fOUT
–40
400
14415-074
–90
14415-071
–80
AD9163
Data Sheet
IOUTFS = 40 mA, fDAC = 3.076 GSPS, nominal supplies, FIR85 enabled, TA = 25°C, unless otherwise noted.
–40
–25
–35
–50
ACLR IN GAP CHANNEL (dBc)
–55
–65
–75
–85
–95
–105
–60
–70
–80
–90
–125
CENTER 77MHz
RES BW 10kHz
VBW 1.kHz
SPAN 60.0MHz
SWEEP 6.041s (1001pts)
–100
Figure 83. Gap Channel ACLR at 77 MHz
0
200
400
600
800
1000
1200
fGAP (fOUT = fGAP) (MHz)
Figure 84. ACLR in Gap Channel vs. fGAP
Rev. D | Page 26 of 126
1400
14415-077
–115
14415-076
MAGNITUDE (dBm)
–45
Data Sheet
AD9163
TERMINOLOGY
Integral Nonlinearity (INL)
INL is the maximum deviation of the actual analog output from
the ideal output, determined by a straight line drawn from zero
scale to full scale.
Differential Nonlinearity (DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Offset Error
Offset error is the deviation of the output current from the ideal
of 0 mA. For OUTPUT+, 0 mA output is expected when all
inputs are set to 0. For OUTPUT−, 0 mA output is expected
when all inputs are set to 1.
Gain Error
Gain error is the difference between the actual and ideal output
span. The actual span is determined by the difference between
the output when the input is at its minimum code and the
output when the input is at its maximum code.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either TMIN or TMAX. For offset
and gain drift, the drift is reported in ppm of full-scale range
(FSR) per degree Celsius. For reference drift, the drift is reported
in ppm per degree Celsius.
Settling Time
Settling time is the time required for the output to reach and
remain within a specified error band around its final value,
measured from the start of the output transition.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels, between the peak amplitude
of the output signal and the peak spurious signal within the dc
to Nyquist frequency of the DAC. Typically, energy in this band
is rejected by the interpolation filters. This specification,
therefore, defines how well the interpolation filters work and
the effect of other parasitic coupling paths on the DAC output.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in decibels.
Interpolation Filter
If the digital inputs to the DAC are sampled at a multiple rate of
the interpolation rate (fDATA), a digital filter can be constructed that
has a sharp transition band near fDATA/2. Images that typically
appear around the output data rate (fDAC) can be greatly
suppressed.
Adjacent Channel Leakage Ratio (ACLR)
ACLR is the ratio in decibels relative to the carrier (dBc)
between the measured power within a channel relative to its
adjacent channel.
Adjusted DAC Update Rate
The adjusted DAC update rate is the DAC update rate divided
by the smallest interpolating factor. For clarity on DACs with
multiple interpolating factors, the adjusted DAC update rate for
each interpolating factor may be given.
Physical Lane
Physical Lane x refers to SERDINx±.
Logical Lane
Logical Lane x refers to physical lanes after optionally being
remapped by the crossbar block (Register 0x308 to Register 0x30B).
Link Lane
Link Lane x refers to logical lanes considered in the link.
Rev. D | Page 27 of 126
AD9163
Data Sheet
THEORY OF OPERATION
The AD9163 is a 16-bit single RF DAC and digital upconverter
with a SERDES interface. Figure 1 shows a detailed functional
block diagram of the AD9163. Eight high speed serial lanes
carry data at a maximum speed of 12.5 Gbps, and either a 5 GSPS
real input or a 2.5 GSPS complex input data rate to the DAC.
Compared to either LVDS or CMOS interfaces, the SERDES
interface simplifies pin count, board layout, and input clock
requirements to the device.
The clock for the input data is derived from the DAC clock, or
device clock (required by the JESD204B specification). This
device clock is sourced with a high fidelity direct external DAC
sampling clock. The performance of the DAC can be optimized by
using on-chip adjustments to the clock input, accessible through
the SPI port. The device can be configured to operate in one-lane,
two-lane, three-lane, four-lane, six-lane, or eight-lane modes,
depending on the required input data rate.
The digital datapath of the AD9163 offers several interpolation
modes (6×, 8×, 12×, 16×, and 24×) through either an initial
half-band (2×) or third-band (3×) filter with programmable
80% or 90% bandwidth, and three subsequent half-band filters
(all 90%) with a maximum DAC sample rate of 6 GSPS. An
inverse sinc filter is provided to compensate for sinc related rolloff. An additional half-band filter, FIR85, takes advantage of the
quad-switch architecture to interpolate on the falling edge of
the clock, and effectively double the DAC update rate in 2×
NRZ mode. A 48-bit programmable modulus NCO is provided
to enable digital frequency shifts of signals with near infinite
precision. The NCO can be operated with digital data from the
SERDES interface and digital datapath. The 100 MHz speed of
the SPI write interface enables rapid updating of the frequency
tuning word of the NCO.
The AD9163 DAC core provides a fully differential current output
with a nominal full-scale current of 38.76 mA. The full-scale
output current, IOUTFS, is user adjustable from 8 mA to 38.76 mA,
typically. The differential current outputs are complementary.
The DAC uses the patented quad-switch architecture, which
enables DAC decoder options to extend the output frequency
range into the second and third Nyquist zones with Mix-Mode,
return to zero (RZ) mode, and 2× NRZ mode (with FIR85
enabled). Mix-Mode can be used to access 1.5 GHz to around
7.5 GHz. In the interpolation modes, the output can range from
0 Hz to 6 GHz in 2× NRZ mode using the NCO to shift a signal
of up to 1.8 GHz instantaneous bandwidth to the desired fOUT.
The AD9163 is capable of multichip synchronization that can both
synchronize multiple DACs and establish a constant and
deterministic latency (latency locking) path for the DACs. The
latency for each of the DACs remains constant to within several
DAC clock cycles from link establishment to link establishment.
An external alignment (SYSREF±) signal makes the AD9163
Subclass 1 compliant. Several modes of SYSREF± signal
handling are available for use in the system.
An SPI configures the various functional blocks and monitors
their statuses. The various functional blocks and the data
interface must be set up in a specific sequence for proper operation
(see the Start-Up Sequence section). Simple SPI initialization
routines set up the JESD204B link and are included in the
evaluation board package. This data sheet describes the various
blocks of the AD9163 in greater detail. Descriptions of the
JESD204B interface, control parameters, and various registers to
set up and monitor the device are provided. The recommended
start-up routine reliably sets up the data link.
Rev. D | Page 28 of 126
Data Sheet
AD9163
SERIAL PORT OPERATION
The serial port is a flexible, synchronous serial communications
port that allows easy interfacing with many industry-standard
microcontrollers and microprocessors. The serial input/output
(I/O) is compatible with most synchronous transfer formats,
including both the Motorola SPI and Intel® SSR protocols. The
interface allows read/write access to all registers that configure
the AD9163. MSB first or LSB first transfer formats are supported.
The serial port interface can be configured as a 4-wire interface
or a 3-wire interface in which the input and output share a singlepin I/O (SDIO).
CS F12
The serial clock pin synchronizes data to and from the device
and runs the internal state machines. The maximum frequency
of SCLK is 100 MHz. All data input is registered on the rising
edge of SCLK. All data is driven out on the falling edge of SCLK.
SPI
PORT
14415-078
SCLK H10
Figure 85. Serial Port Interface Pins
There are two phases to a communication cycle with the AD9163.
Phase 1 is the instruction cycle (the writing of an instruction
byte into the device), coincident with the first 16 SCLK rising
edges. The instruction word provides the serial port controller
with information regarding the data transfer cycle, Phase 2 of
the communication cycle. The Phase 1 instruction word defines
whether the upcoming data transfer is a read or write, along with
the starting register address for the following data transfer.
A logic high on the CS pin followed by a logic low resets the
serial port timing to the initial state of the instruction cycle.
From this state, the next 16 rising SCLK edges represent the
instruction bits of the current I/O operation.
The remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the device and
the system controller. Phase 2 of the communication cycle is a
transfer of one or more data bytes. Eight × N SCLK cycles are
needed to transfer N bytes during the transfer cycle. Registers
change immediately upon writing to the last bit of each transfer
byte, except for the frequency tuning word (FTW) and numerically
controlled oscillator (NCO) phase offsets, which change only when
the frequency tuning word FTW_LOAD_REQ bit is set.
SERIAL DATA FORMAT
The instruction byte contains the information shown in Table 13.
Table 13. Serial Port Instruction Word
I15 (MSB)
R/W
SERIAL PORT PIN DESCRIPTIONS
Serial Clock (SCLK)
SDO G11
SDIO G10
A14 to A0, Bit I14 to Bit I0 of the instruction word, determine
the register that is accessed during the data transfer portion of
the communication cycle. For multibyte transfers, A[14:0] is the
starting address. The remaining register addresses are generated
by the device based on the address increment bit. If the address
increment bits are set high (Register 0x000, Bit 5 and Bit 2),
multibyte SPI writes start on A[14:0] and increment by 1 every
eight bits sent/received. If the address increment bits are set to
0, the address decrements by 1 every eight bits.
I[14:0]
A[14:0]
R/W, Bit 15 of the instruction word, determines whether a read
or a write data transfer occurs after the instruction word write.
Logic 1 indicates a read operation, and Logic 0 indicates a write
operation.
Chip Select (CS)
An active low input starts and gates a communication cycle.
CS allows more than one device to be used on the same serial
communications lines. The SDIO pin goes to a high impedance
state when this input is high. During the communication cycle,
the chip select must stay low.
Serial Data I/O (SDIO)
This pin is a bidirectional data line. In 4-wire mode, this pin
acts as the data input and SDO acts as the data output.
SERIAL PORT OPTIONS
The serial port can support both MSB first and LSB first data
formats. This functionality is controlled by the LSB first bit
(Register 0x000, Bit 6 and Bit 1). The default is MSB first (LSB
bit = 0).
When the LSB first bits = 0 (MSB first), the instruction and data
bits must be written from MSB to LSB. R/W is followed by
A[14:0] as the instruction word, and D[7:0] is the data-word.
When the LSB first bits = 1 (LSB first), the opposite is true.
A[0:14] is followed by R/W, which is subsequently followed by
D[0:7].
The serial port supports a 3-wire or 4-wire interface. When the
SDO active bits = 1 (Register 0x000, Bit 4 and Bit 3), a 4-wire
interface with a separate input pin (SDIO) and output pin (SDO) is
used. When the SDO active bits = 0, the SDO pin is unused and
the SDIO pin is used for both the input and the output.
Multibyte data transfers can be performed as well by holding
the CS pin low for multiple data transfer cycles (eight SCLKs)
after the first data transfer word following the instruction cycle.
The first eight SCLKs following the instruction cycle read from
or write to the register provided in the instruction cycle. For
each additional eight SCLK cycles, the address is either incremented or decremented and the read/write occurs on the new
register.
Rev. D | Page 29 of 126
AD9163
Data Sheet
To prevent confusion and to ensure consistency between devices,
the chip tests the first nibble following the address phase, ignoring
the second nibble. This test is completed independently from the
LSB first bits and ensures that there are extra clock cycles following
the soft reset bits (Register 0x000, Bit 0 and Bit 7). This test of
the first nibble only applies when writing to Register 0x000.
INSTRUCTION CYCLE
INSTRUCTION CYCLE
SDIO
A0
A1
A12 A13 A14 R/W D00 D10 D20
A2
D4N D5N D6N D7N
Figure 87. Serial Register Interface Timing, LSB First, Register 0x000, Bit 5 and
Bit 2 = 1
CS
SCLK
tDV
CS
DATA BIT n
DATA BIT n – 1
Figure 88. Timing Diagram for Serial Port Register Read
R/W A14 A13
A3
A2 A1
A0 D7N D6N D5N
14415-079
SCLK
SDIO
D30 D20 D10 D00
Figure 86. Serial Register Interface Timing, MSB First, Register 0x000, Bit 5
and Bit 2 = 0
tS
tH
CS
tPWH
tPWL
SDIO
tDH
INSTRUCTION BIT 15 INSTRUCTION BIT 14
INSTRUCTION BIT 0
Figure 89. Timing Diagram for Serial Port Register Write
Rev. D | Page 30 of 126
14415-082
SCLK
tDS
14415-080
SCLK
SDIO
DATA TRANSFER CYCLE
DATA TRANSFER CYCLE
CS
14415-081
The direction of the address can be set using ADDRINC or
ADDRINC_M (Register 0x000, Bit 5 and Bit 2). When ADDRINC
or ADDRINC_M is 1, the multicycle addresses are incremented.
When ADDRINC or ADDRINC_M is 0, the addresses are decremented. A new write cycle can always be initiated by bringing
CS high and then low again.
Data Sheet
AD9163
JESD204B SERIAL DATA INTERFACE
JESD204B OVERVIEW
The AD9163 has eight JESD204B data ports that receive data.
The eight JESD204B ports can be configured as part of a single
JESD204B link that uses a single system reference (SYSREF±) and
device clock (CLK±).
The JESD204B serial interface hardware consists of three layers:
the physical layer, the data link layer, and the transport layer.
These sections of the hardware are described in subsequent
sections, including information for configuring every aspect of
the interface. Figure 90 shows the communication layers
implemented in the AD9163 serial data interface to recover the
clock and deserialize, descramble, and deframe the data before it
is sent to the digital signal processing section of the device.
The physical layer establishes a reliable channel between the
transmitter (Tx) and the receiver (Rx), the data link layer is
responsible for unpacking the data into octets and descrambling
the data. The transport layer receives the descrambled
JESD204B frames and converts them to DAC samples.
A number of JESD204B parameters (L, F, K, M, N, NP, S, HD)
define how the data is packed and tell the device how to turn
the serial data into samples. These parameters are defined in
detail in the Transport Layer section. The AD9163 also has a
descrambling option (see the Descrambler section for more
information).
The various combinations of JESD204B parameters that are
supported depend solely on the number of lanes. Thus, a
unique set of parameters can be determined by selecting the
lane count to be used. In addition, the interpolation rate and
number of lanes can be used to define the rest of the configuration needed to set up the AD9163. The interpolation rate and
the number of lanes are selected in Register 0x110.
The AD9163 has a single DAC output; however, for the purposes
of the complex signal processing on chip, the converter count is
defined as M = 2 whenever interpolation is used.
For a particular application, the number of converters to use
(M) and the DataRate variable are known. The LaneRate
variable and number of lanes (L) can be traded off as follows:
DataRate = (DACRate)/(InterpolationFactor)
LaneRate = (20 × DataRate × M)/L
where LaneRate must be between 750 Mbps and 12.5 Gbps.
Achieving and recovering synchronization of the lanes is very
important. To simplify the interface to the transmitter, the
AD9163 designate a master synchronization signal for each
JESD204B link. The SYNCOUT± pin is used as the master signal
for all lanes. If any lane in a link loses synchronization, a
resynchronization request is sent to the transmitter via the
synchronization signal of the link. The transmitter stops sending
data and instead sends synchronization characters to all lanes in
that link until resynchronization is achieved.
SYNCOUT±
PHYSICAL
LAYER
SERDIN7±
DATA LINK
LAYER
TRANSPORT
LAYER
QBD/
DESCRAMBLER
FRAME TO
SAMPLES
I DATA[15:0]
DESERIALIZER
TO DAC
DSP BLOCK
Q DATA[15:0]
DESERIALIZER
14415-083
SERDIN0±
SYSREF±
Figure 90. Functional Block Diagram of Serial Link Receiver
Table 14. Single-Link JESD204B Operating Modes
Parameter
L (Lane Count)
M (Converter Count)
F (Octets per Frame per Lane)
S (Samples per Converter per Frame)
1
1
2
4
1
Rev. D | Page 31 of 126
2
2
2
2
1
Number of Lanes (L)
3
4
6
3
4
6
2
2
2
4
1
2
3
1
3
8
8
2
1
2
AD9163
Data Sheet
Table 15. Data Structure per Lane for JESD204B Operating Modes 1
JESD204B Parameters
L = 8, M = 2, F = 1, S = 2
L = 6, M = 2, F = 2, S = 3
L = 4, M = 2, F = 1, S = 1
L = 3, M = 2, F = 4, S = 3
L = 2, M = 2, F = 2, S = 1
L = 1, M = 2, F = 4, S = 1
1
Lane No.
Lane 0
Lane 1
Lane 2
Lane 3
Lane 4
Lane 5
Lane 6
Lane 7
Lane 0
Lane 1
Lane 2
Lane 3
Lane 4
Lane 5
Lane 0
Lane 1
Lane 2
Lane 3
Lane 0
Lane 1
Lane 2
Lane 0
Lane 1
Lane 0
Frame 0
M0S0[15:8]
M0S0[7:0]
M0S1[15:8]
M0S1[7:0]
M1S0[15:8]
M1S0[7:0]
M1S1[15:8]
M1S1[7:0]
M0S0[15:8]
M0S1[15:8]
M0S2[15:8]
M1S0[15:8]
M1S1[15:8]
M1S2[15:8]
M0S0[15:8]
M0S0[7:0]
M1S0[15:8]
M1S0[7:0]
M0S0[15:8]
M0S2[15:8]
M1S1[15:8]
M0S0[15:8]
M1S0[15:8]
M0S0[15:8]
Frame 1
Frame 2
Frame 3
M0S1[15:8]
M1S0[15:8]
M1S2[15:8]
M0S1[7:0]
M1S0[7:0]
M1S2[7:0]
M1S0[15:8]
M1S0[7:0]
M0S0[7:0]
M0S1[7:0]
M0S2[7:0]
M1S0[7:0]
M1S1[7:0]
M1S2[7:0]
M0S0[7:0]
M0S2[7:0]
M1S1[7:0]
M0S0[7:0]
M1S0[7:0]
M0S0[7:0]
Mx is the converter number and Sy is the sample number. For example, M0S0 means Converter 0, Sample 0. Blank cells are not applicable.
PHYSICAL LAYER
The physical layer of the JESD204B interface, hereafter referred
to as the deserializer, has eight identical channels. Each channel
consists of the terminators, an equalizer, a clock and data recovery
(CDR) circuit, and the 1:40 demux function (see Figure 91).
DESERIALIZER
SERDINx±
TERMINATION
EQUALIZER
CDR
1:40
The AD9163 autocalibrates the input termination to 50 Ω.
Before running the termination calibration, Register 0x2A7 and
Register 0x2AE must be written as described in Table 16 to
guarantee proper calibration. The termination calibration begins
when Register 0x2A7, Bit 0 and Register 0x2AE, Bit 0 transition
from low to high. Register 0x2A7 controls autocalibration for
PHY 0, PHY 1, PHY 6, and PHY 7. Register 0x2AE controls
autocalibration for PHY 2, PHY 3, PHY 4, and PHY 5.
The PHY termination autocalibration routine is as shown in
Table 16.
14415-084
SPI
CONTROL
Table 16. PHY Termination Autocalibration Routine
Address
0x2A7
Value
0x01
JESD204B data is input to the AD9163 via the SERDINx± 1.2 V
differential input pins as per the JESD204B specification.
0x2AE
0x01
Interface Power-Up and Input Termination
The input termination voltage of the DAC is sourced externally
via the VTT_1P2 pins (K3 and K11). Set VTT, the termination
voltage, by connecting it to VDD_1P2. It is recommended that
the JESD204B inputs be ac-coupled to the JESD204B transmit
device using 100 nF capacitors.
FROM SERDES PLL
Figure 91. Deserializer Block Diagram
Before using the JESD204B interface, it must be powered up by
setting Register 0x200, Bit 0 = 0. In addition, each physical lane
(PHY) that is not being used (SERDINx±) must be powered
down. To do so, set the corresponding Bit x for Physical Lane x in
Register 0x201 to 0 if the physical lane is being used, and to 1 if it is
not being used.
Rev. D | Page 32 of 126
Description
Autotune PHY 0, PHY 1, PHY 6, and
PHY 7 terminations
Autotune PHY 2, PHY 3, PHY 4, and
PHY 5 terminations
Data Sheet
AD9163
The calibration code of the termination can be read from
Bits[3:0] in Register 0x2AC (PHY 0, PHY 1, PHY 6, PHY 7)
and Register 0x2B3 (PHY 2, PHY 3, PHY 4, PHY 5). If needed,
the termination values can be adjusted or set using several
registers. The TERM_BLKx_CTRLREG1 registers (Register 0x2A8
and Register 0x2AF), can override the autocalibrated value. When
set to 0xXXX0XXXX, the termination block autocalibrates,
which is the normal, default setting. When set to 0xXXX1XXXX,
the autocalibration value is overwritten with the value in Bits[3:1]
of Register 0x2A8 and Register 0x2AF. Individual offsets from the
autocalibration value for each lane can be programmed in Bits[3:0]
of Register 0x2BB to Register 0x2C2. The value is a signed magnitude, with Bit 3 as the sign bit. The total range of the termination
resistor value is about 94 Ω to 120 Ω, with approximately 3.5%
increments across the range (for example, smaller steps at the
bottom of the range than at the top).
Receiver Eye Mask
The AD9163 complies with the JESD204B specification
regarding the receiver eye mask and is capable of capturing data
that complies with this mask. Figure 92 shows the receiver eye
mask normalized to the data rate interval with a 600 mV VTT
swing. See the JESD204B specification for more information
regarding the eye mask and permitted receiver eye opening.
LV-OIF-11G-SR RECEIVER EYE MASK
PCLK Factor = FrameRate/PCLK Rate = 4/F
where:
M is the JESD204B parameter for converters per link.
L is the JESD204B parameter for lanes per link.
F is the JESD204B parameter for octets per frame per lane.
SERDES PLL
Functional Overview of the SERDES PLL
The independent SERDES PLL uses integer N techniques to
achieve clock synthesis. The entire SERDES PLL is integrated
on chip, including the VCO and the loop filter. The SERDES
PLL VCO operates over the range of 6 GHz to 12.5 GHz.
In the SERDES PLL, a VCO divider block divides the VCO
clock by 2 to generate a 3 GHz to 6.25 GHz quadrature clock for
the deserializer cores. This clock is the input to the clock and
data recovery block that is described in the Clock and Data
Recovery section.
The reference clock to the SERDES PLL is always running at a
frequency, fREF, that is equal to 1/40 of the lane rate (PCLK Rate).
This clock is divided by a DivFactor value (set by SERDES_PLL_
DIV_FACTOR) to deliver a clock to the phase frequency detector
(PFD) block that is between 35 MHz and 80 MHz. Table 17
includes the respective SERDES_PLL_DIV_FACTOR register
settings for each of the desired PLL_REF_CLK_RATE options
available.
AMPLITUDE (mV)
525
Table 17. SERDES PLL Divider Settings
Lane Rate
(Gbps)
0.750 to 1.5625
1.5 to 3.125
3 to 6.25
6 to 12.5
55
0
–55
–525
0.35
0.5
0.65
1.00
TIME (UI)
SERDES_PLL_DIV_FACTOR
Register 0x289, Bits[1:0]
0b10 = ÷1
0b10 = ÷1
0b01 = ÷2
0b00 = ÷4
Register 0x280 controls the synthesizer enable and recalibration.
14415-085
0
PLL_REF_CLK_RATE,
Register 0x084, Bits[5:4]
0b01 = 2×
0b00 = 1×
0b00 = 1×
0b00 = 1×
Figure 92. Receiver Eye Mask for 600 mV VTT Swing
Clock Relationships
The following clocks rates are used throughout the rest of the
JESD204B section. The relationship between any of the clocks
can be derived from the following equations:
DataRate = (DACRate)/(InterpolationFactor)
LaneRate = (20 × DataRate × M)/L
ByteRate = LaneRate/10
This relationship comes from 8-bit/10-bit encoding, where each
byte is represented by 10 bits.
To enable the SERDES PLL, first set the PLL divider register (see
Table 17). Then enable the SERDES PLL by writing Register 0x280,
Bit 0 = 1. If a recalibration is needed, write Register 0x280, Bit 2 =
0b1 and then reset the bit to 0b0. The rising edge of the bit causes a
recalibration to begin.
Confirm that the SERDES PLL is working by reading
Register 0x281. If Register 0x281, Bit 0 = 1, the SERDES PLL
has locked. If Register 0x281, Bit 3 = 1, the SERDES PLL was
successfully calibrated. If Register 0x281, Bit 4 or Bit 5 is high, the
PLL reaches the lower or upper end of its calibration band and
must be recalibrated by writing 0 and then 1 to Register 0x280,
Bit 2.
PCLK Rate = ByteRate/4
The processing clock is used for a quad-byte decoder.
FrameRate = ByteRate/F
where F is defined as octets per frame per lane.
Rev. D | Page 33 of 126
AD9163
Data Sheet
Clock and Data Recovery
Equalization
The deserializer is equipped with a CDR circuit. Instead of
recovering the clock from the JESD204B serial lanes, the CDR
recovers the clocks from the SERDES PLL. The 3 GHz to
6.25 GHz output from the SERDES PLL, shown in Figure 94, is
the input to the CDR.
To compensate for signal integrity distortions for each PHY
channel due to PCB trace length and impedance, the AD9163
employs an easy to use, low power equalizer on each JESD204B
channel. The AD9163 equalizers can compensate for insertion
losses far greater than required by the JESD204B specification.
The equalizers have two modes of operation that are determined by
the EQ_POWER_MODE register setting in Register 0x268,
Bits[7:6]. In low power mode (Register 0x268, Bits[7:6] = 2b’01)
and operating at the maximum lane rate of 12.5 Gbps, the
equalizer can compensate for up to 11.5 dB of insertion loss. In
normal mode (Register 0x268, Bits[7:6] = 2b’00), the equalizer
can compensate for up to 17.2 dB of insertion loss. This
performance is shown in Figure 93 as an overlay to the JESD204B
specification for insertion loss. Figure 93 shows the equalization
performance at 12.5 Gbps, near the maximum baud rate for the
AD9163.
SPI_ENHALFRATE
Register 0x230, Bit 5
0 (full rate)
0 (full rate)
0 (full rate)
1 (half rate)
SPI_DIVISION_RATE,
Register 0x230,
Bits[2:1]
10b (divide by 4)
01b (divide by 2)
00b (no divide)
00b (no divide)
0
JESD204B SPEC ALLOWED
CHANNEL LOSS
2
4
6
The CDR circuit synchronizes the phase used to sample the data on
each serial lane independently. This independent phase adjustment
per serial interface ensures accurate data sampling and eases the
implementation of multiple serial interfaces on a PCB.
10
AD9163 ALLOWED
CHANNEL LOSS
(LOW POWER MODE)
12
AD9163 ALLOWED
CHANNEL LOSS
(NORMAL MODE)
14
16
EXAMPLE OF
AD9163
COMPATIBLE
CHANNEL
(NORMAL MODE)
20
22
24
3.125
Power-Down Unused PHYs
6.250
9.375
FREQUENCY (GHz)
Figure 93. Insertion Loss Allowed
Note that any unused and enabled lanes consume extra power
unnecessarily. Each lane that is not being used (SERDINx±)
must be powered off by writing a 1 to the corresponding bit of
PHY_PD (Register 0x201).
MODE
HALF RATE
FULL RATE, NO DIV
FULL RATE, DIV 2
FULL RATE, DIV 4
INTERPOLATION
JESD LANES
REG 0x110
÷4
EXAMPLE OF
AD9163
COMPATIBLE
CHANNEL (LOW
POWER MODE)
8
18
After configuring the CDR circuit, reset it and then release the
reset by writing 1 and then 0 to Register 0x206, Bit 0.
DAC CLOCK
(5GHz)
EXAMPLE OF
JESD204B
COMPLIANT
CHANNEL
PCLK
GENERATOR
CDR OVERSAMP
REG 0x289
PLL REF CLOCK
VALID RANGE
35MHz TO 80MHz
÷4, ÷2,
OR ÷1
DIVIDE (N)
20
40
80
160
ENABLE HALF RATE
DIVISION RATE
REG 0x230
SAMPLE CLOCK
I, Q TO CDR
VALID RANGE
3GHz TO 6.25GHz
CP
LF
PLL_REF_CLK_RATE
1×, 2×, 4×
REG 0x084
÷2
CDR
÷N
÷8
÷6 TO ÷127,
DEFAULT: 10
Figure 94. SERDES PLL Synthesizer Block Diagram Including VCO Divider Block
Rev. D | Page 34 of 126
JESD LANE CLOCK
(SAME RATE AS PCLK)
14415-086
Lane Rate
(Gbps)
0.750 to 1.5625
1.5 to 3.125
3 to 6.25
6 to 12.5
14415-087
Table 18. CDR Operating Modes
INSERTION LOSS (dB)
A CDR sampling mode must be selected to generate the lane
rate clock inside the device. If the desired lane rate is greater
than 6.25 GHz, half rate CDR operation must be used. If the
desired lane rate is less than 6.25 GHz, disable half rate operation.
If the lane rate is less than 3 GHz, disable full rate and enable 2×
oversampling to recover the appropriate lane rate clock. Table 18
gives a breakdown of CDR sampling settings that must be set
depending on the lane rate value.
Data Sheet
AD9163
Figure 95 and Figure 96 are provided as points of reference for
hardware designers and show the insertion loss for various
lengths of well laid out stripline and microstrip transmission
lines, respectively. See the Hardware Considerations section for
specific layout recommendations for the JESD204B channel.
Low power mode is recommended if the insertion loss of the
JESD204B PCB channels is less than that of the most lossy
supported channel for low power mode (shown in Figure 93). If
the insertion loss is greater than that, but still less than that of
the most lossy supported channel for normal mode (shown in
Figure 93), use normal mode. At 12.5 Gbps operation, the
equalizer in normal mode consumes about 4 mW more power
per lane used than in low power equalizer mode. Note that either
mode can be used in conjunction with transmitter preemphasis
to ensure functionality and/or optimize for power.
0
–5
–15
–20
–25
STRIPLINE
STRIPLINE
STRIPLINE
STRIPLINE
STRIPLINE
STRIPLINE
–30
–35
=
=
=
=
=
=
6"
10"
15"
20"
25"
30"
–40
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (GHz)
14415-088
ATTENUATION (dB)
–10
DATA LINK LAYER
The data link layer of the AD9163 JESD204B interface accepts
the deserialized data from the PHYs and deframes and descrambles
them so that data octets are presented to the transport layer to be
put into DAC samples. The architecture of the data link layer is
shown in Figure 97. The data link layer consists of a
synchronization FIFO for each lane, a crossbar switch, a deframer,
and a descrambler.
The AD9163 can operate as a single-link high speed JESD204B
serial data interface. All eight lanes of the JESD204B interface
handle link layer communications such as code group synchronization (CGS), frame alignment, and frame synchronization.
The AD9163 decodes 8-bit/10-bit control characters, allowing
marking of the start and end of the frame and alignment
between serial lanes. Each AD9163 serial interface link can issue
a synchronization request by setting its SYNCOUT± signal low.
The synchronization protocol follows Section 4.9 of the JESD204B
standard. When a stream of four consecutive /K/ symbols is
received, the AD9163 deactivates the synchronization request
by setting the SYNCOUT± signal high at the next internal
LMFC rising edge. Then, the AD9163 waits for the transmitter
to issue an initial lane alignment sequence (ILAS). During the
ILAS, all lanes are aligned using the /A/ to /R/ character transition
as described in the JESD204B Serial Link Establishment section.
Elastic buffers hold early arriving lane data until the alignment
character of the latest lane arrives. At this point, the buffers for
all lanes are released and all lanes are aligned (see Figure 98).
Figure 95. Insertion Loss of 50 Ω Striplines on FR4
0
–5
–15
–20
–25
6" MICROSTRIP
10" MICROSTRIP
15" MICROSTRIP
20" MICROSTRIP
25" MICROSTRIP
30" MICROSTRIP
–30
–35
–40
0
1
2
3
4
5
6
7
8
9
FREQUENCY (GHz)
10
14415-089
ATTENUATION (dB)
–10
Figure 96. Insertion Loss of 50 Ω Microstrips on FR4
Rev. D | Page 35 of 126
AD9163
Data Sheet
DATA LINK LAYER
SYNCOUTx±
LANE 7 DATA CLOCK
SYSREF±
CROSSBAR
SWITCH
SERDIN7±
FIFO
LANE 0 OCTETS
LANE 7 OCTETS
SYSTEM CLOCK
PHASE DETECT
14415-090
LANE 7 DESERIALIZED
AND DESCRAMBLED DATA
SERDIN0±
FIFO
DESCRAMBLE
LANE 0 DATA CLOCK
QUAD-BYTE
DEFRAMER
QBD
8-BIT/10-BIT DECODE
LANE 0 DESERIALIZED
AND DESCRAMBLED DATA
PCLK
SPI CONTROL
Figure 97. Data Link Layer Block Diagram
L RECEIVE LANES
(EARLIEST ARRIVAL) K K K R D D
D D A R Q C
L RECEIVE LANES
(LATEST ARRIVAL) K K K K K K K R D D
C
D D A R Q C
D D A R D D
C
D D A R D D
0 CHARACTER ELASTIC BUFFER DELAY OF LATEST ARRIVAL
4 CHARACTER ELASTIC BUFFER DELAY OF EARLIEST ARRIVAL
L ALIGNED
RECEIVE LANES K K K K K K K R D D
D D A R Q C
D D A R D D
14415-091
K = K28.5 CODE GROUP SYNCHRONIZATION COMMA CHARACTER
A = K28.3 LANE ALIGNMENT SYMBOL
F = K28.7 FRAME ALIGNMENT SYMBOL
R = K28.0 START OF MULTIFRAME
Q = K28.4 START OF LINK CONFIGURATION DATA
C = JESD204x LINK CONFIGURATION PARAMETERS
D = Dx.y DATA SYMBOL
C
Figure 98. Lane Alignment During ILAS
JESD204B Serial Link Establishment
A brief summary of the high speed serial link establishment
process for Subclass 1 is provided. See Section 5.3.3 of the
JESD204B specifications document for complete details.
Step 1: Code Group Synchronization
Each receiver must locate /K/ (K28.5) characters in its input
data stream. After four consecutive /K/ characters are detected
on all link lanes, the receiver block deasserts the SYNCOUT±
signal to the transmitter block at the receiver LMFC edge.
The transmitter captures the change in the SYNCOUT± signal
and at a future transmitter LMFC rising edge starts the ILAS.
Step 2: Initial Lane Alignment Sequence
The main purposes of this phase are to align all the lanes of the
link and to verify the parameters of the link.
Before the link is established, write each of the link parameters
to the receiver device to designate how data is sent to the
receiver block.
The ILAS consists of four or more multiframes. The last character
of each multiframe is a multiframe alignment character, /A/.
The first, third, and fourth multiframes are populated with
predetermined data values. Note that Section 8.2 of the JESD204B
specifications document describes the data ramp that is expected
during ILAS. The AD9163 does not require this ramp. The
deframer uses the final /A/ of each lane to align the ends of the
multiframes within the receiver. The second multiframe contains
an /R/ (K.28.0), /Q/ (K.28.4), and then data corresponding to
the link parameters. Additional multiframes can be added to
the ILAS if needed by the receiver. By default, the AD9163 uses
four multiframes in the ILAS (this can be changed in Register
0x478). If using Subclass 1, exactly four multiframes must be used.
After the last /A/ character of the last ILAS, multiframe data
begins streaming. The receiver adjusts the position of the /A/
Rev. D | Page 36 of 126
Data Sheet
AD9163
Table 19. Crossbar Registers
character such that it aligns with the internal LMFC of the
receiver at this point.
Step 3: Data Streaming
In this phase, data is streamed from the transmitter block to the
receiver block.
Optionally, data can be scrambled. Scrambling does not start
until the very first octet following the ILAS.
The receiver block processes and monitors the data it receives
for errors, including the following:
•
•
•
•
•
Bad running disparity (8-bit/10-bit error)
Not in table (8-bit/10-bit error)
Unexpected control character
Bad ILAS
Interlane skew error (through character replacement)
•
•
Bits
[2:0]
[5:3]
[2:0]
[5:3]
[2:0]
[5:3]
[2:0]
[5:3]
Logical Lane
SRC_LANE0
SRC_LANE1
SRC_LANE2
SRC_LANE3
SRC_LANE4
SRC_LANE5
SRC_LANE6
SRC_LANE7
Write each SRC_LANEy with the number (x) of the desired
physical lane (SERDINx±) from which to obtain data. By
default, all logical lanes use the corresponding physical lane as
their data source. For example, by default, SRC_LANE0 = 0;
therefore, Logical Lane 0 obtains data from Physical Lane 0
(SERDIN0±). To use SERDIN4± as the source for Logical Lane 0
instead, the user must write SRC_LANE0 = 4.
If any of these errors exist, they are reported back to the
transmitter in one of the following ways (see the JESD204B
Error Monitoring section for details):
•
Address
0x308
0x308
0x309
0x309
0x30A
0x30A
0x30B
0x30B
Lane Inversion
SYNCOUT± signal assertion: resynchronization
(SYNCOUT± signal pulled low) is requested at each error
for the last two errors. For the first three errors, an optional
resynchronization request can be asserted when the error
counter reaches a set error threshold.
For the first three errors, each multiframe with an error in
it causes a small pulse on SYNCOUT±.
Errors can optionally trigger an interrupt request (IRQ)
event, which can be sent to the transmitter.
For more information about the various test modes for
verifying the link integrity, see the JESD204B Test Modes
section.
Lane First In/First Out (FIFO)
The FIFOs in front of the crossbar switch and deframer synchronize the samples sent on the high speed serial data interface
with the deframer clock by adjusting the phase of the incoming
data. The FIFO absorbs timing variations between the data
source and the deframer; this allows up to two PCLK cycles of
drift from the transmitter. The FIFO_STATUS_REG_0 register
and FIFO_STATUS_REG_1 register (Register 0x30C and
Register 0x30D, respectively) can be monitored to identify
whether the FIFOs are full or empty.
Lane FIFO IRQ
An aggregate lane FIFO error bit is also available as an IRQ
event. Use Register 0x020, Bit 2 to enable the FIFO error bit,
and then use Register 0x024, Bit 2 to read back its status and
reset the IRQ signal. See the Interrupt Request Operation
section for more information.
Register 0x334 allows inversion of desired logical lanes, which
can be used to ease routing of the SERDINx± signals. For each
Logical Lane x, set Bit x of Register 0x334 to 1 to invert it.
Deframer
The AD9163 consists of one quad-byte deframer (QBD). The
deframer accepts the 8-bit/10-bit encoded data from the
deserializer (via the crossbar switch), decodes it, and descrambles it
into JESD204B frames before passing it to the transport layer to be
converted to DAC samples. The deframer processes four symbols
(or octets) per processing clock (PCLK) cycle.
The deframer uses the JESD204B parameters that the user has
programmed into the register map to identify how the data is
packed, and unpacks it. The JESD204B parameters are
described in detail in the Transport Layer section; many of the
parameters are also needed in the transport layer to convert
JESD204B frames into samples.
Descrambler
The AD9163 provides an optional descrambler block using a
self synchronous descrambler with the following polynomial:
1 + x14 + x15.
Enabling data scrambling reduces spectral peaks that are
produced when the same data octets repeat from frame to
frame. It also makes the spectrum data independent so that
possible frequency selective effects on the electrical interface do
not cause data dependent errors. Descrambling of the data is
enabled by setting the SCR bit (Register 0x453, Bit 7) to 1.
Crossbar Switch
Register 0x308 to Register 0x30B allow arbitrary mapping of
physical lanes (SERDINx±) to logical lanes used by the SERDES
deframers.
Rev. D | Page 37 of 126
AD9163
Data Sheet
Syncing LMFC Signals
The first step in guaranteeing synchronization across links and
devices begins with syncing the LMFC signals. In Subclass 0,
the LMFC signal is synchronized to an internal processing
clock. In Subclass 1, LMFC signals are synchronized to an
external SYSREF± signal.
SYSREF± Signal
The SYSREF± signal is a differential source synchronous input that
synchronizes the LMFC signals in both the transmitter and receiver
in a JESD204B Subclass 1 system to achieve deterministic latency.
The SYSREF± signal is a rising edge sensitive signal that is
sampled by the device clock rising edge. It is best practice that the
device clock and SYSREF± signals be generated by the same
source, such as the HMC7044 clock generator, so that the phase
alignment between the signals is fixed. When designing for
optimum deterministic latency operation, consider the timing
distribution skew of the SYSREF± signal in a multipoint link
system (multichip).
The AD9163 supports a periodic SYSREF± signal. The periodicity
can be continuous, strobed, or gapped periodic. The SYSREF±
signal can always be dc-coupled (with a common-mode voltage
of 0 V to 1.25 V). When dc-coupled, a small amount of commonmode current ( 4/SYSREF± frequency. In
addition, the edge rate must be sufficiently fast to meet the
SYSREF± vs. DAC clock keep out window (KOW)
requirements.
It is possible to use ac-coupled mode without meeting the
frequency to time constant constraints (τ = RC and τ > 4/SYSREF±
frequency) by using SYSREF± hysteresis (Register 0x088 and
Register 0x089). However, using hystereis increases the DAC
clock KOW (Table 6 does not apply) by an amount depending
on the SYSREF± frequency, level of hysteresis, capacitor choice,
and edge rate.
SYSREF+
50Ω
The SYSREF± signal is sampled by a divide by 4 version of the
DAC clock. After SYSREF± is sampled, the phase of the DAC
clock/4 used to sample SYSREF± is stored in Register 0x037,
Bits[7:0] and Register 0x038, Bits[3:0] as a thermometer code. This
offset can be used by the SERDES data transmitter (for example,
FPGA) to align multiple DACs by accounting for this clock offset
when transmitting data. See the Sync Procedure section for details
on the procedure for syncing the LMFC signals.
One-Shot Sync Mode (SYNC_MODE = Register 0x03A,
Bits[1:0] = 0b10)
In one-shot sync mode, a phase check occurs on only the first
alignment edge that is received after the sync machine is armed.
After the phase is aligned on the first edge, the AD9163 transitions
to monitor mode. Though an LMFC synchronization occurs only
once, the SYSREF± signal can still be continuous. In this case,
the phase is monitored and reported, but no clock phase
adjustment occurs.
Continuous Sync Mode (SYNC_MODE = Register 0x03A,
Bits[1:0] = 0b01)
Continuous mode must be used in Subclass 1 only with a periodic
SYSREF± signal. In continuous mode, a phase check/alignment
occurs on every alignment edge.
Continuous mode differs from one-shot mode in two ways.
First, no SPI cycle is required to arm the device; the alignment
edge seen after continuous mode is enabled results in a phase
check. Second, a phase check occurs on every alignment edge in
continuous mode.
Monitor Sync Mode (SYNC_MODE = Register 0x03A,
Bits[1:0]) = 0b00)
In monitor mode, the user can monitor the phase error in real time.
Use this sync mode with a periodic SYSREF± signal. The phase is
monitored and reported, but no clock phase adjustment occurs.
When an alignment request (SYSREF± edge) occurs, snapshots
of the last phase error are placed into readable registers for
reference (Register 0x037 and Register 0x038, Bits[3:0]), and the
IRQ_SYSREF_JITTER interrupt is set, if appropriate.
Sync Procedure
3kΩ
The procedure for enabling the sync is as follows:
19kΩ
1.
19kΩ
3kΩ
14415-147
50Ω
SYSREF–
All sync processing modes perform a phase check to confirm that
the LMFC is phase aligned to an alignment edge. In Subclass 1, the
SYSREF± rising edge acts as the alignment edge; in Subclass 0, an
internal processing clock acts as the alignment edge.
2.
Figure 99. SYSREF± Input Circuit
Sync Processing Modes Overview
3.
The AD9163 supports several LMFC sync processing modes.
These modes are one-shot, continuous, and monitor modes.
Rev. D | Page 38 of 126
Set up the DAC; the SERDES PLL locks it, and enables the
CDR (see the Start-Up Sequence section).
Set Register 0x039 (SYSREF± jitter window). A minimum
of 4 DAC clock cycles is recommended. See Table 21 for
settings.
Optionally, read back the SYSREF± count to check whether
the SYSREF± pulses are being received.
Data Sheet
AD9163
a.
4.
5.
6.
7.
8.
9.
Set Register 0x036 = 0. Writing anything to
SYSREF_COUNT resets the count.
b. Set Register 0x034 = 0. Writing anything to
SYNC_LMFC_STAT0 saves the data for readback and
registers the count.
c. Read SYSREF_COUNT from the value from
Register 0x036.
Perform a one-shot sync.
a. Set Register 0x03A = 0x00. Clear one-shot mode if
already enabled.
b. Set Register 0x03A = 0x02. Enable one-shot sync
mode. The state machine enters monitor mode after a
sync occurs.
Optionally, read back the sync SYNC_LMFC_STATx
registers to verify that sync completed correctly.
a. Set Register 0x034 = 0. Register 0x034 must be written
to read the value.
b. Read Register 0x035 and Register 0x034 to find the
value of SYNC_LMFC_STATx. It is recommended to
set SYNC_LMFC_STATx to 0 but it can be set to 4, or
a LMFC period in DAC clocks – 4, due to jitter.
Optionally, read back the sync SYSREF_PHASEx register
to identify which phase of the divide by 4 was used to
sample SYSREF±. Read Register 0x038 and Register 0x037
as thermometer code. The MSBs of Register 0x037,
Bits[7:4], normally show the thermometer code value.
Turn the link on (Register 0x300, Bit 0 = 1).
Read back Register 0x302 (dynamic link latency).
Repeat the reestablishment of the link several times (Step 1
to Step 7) and note the dynamic link latency values. Based
on the values, program the LMFC delay (Register 0x304) and
the LMFC variable (Register 0x306), and then restart the link.
JESD204B systems contain various clock domains distributed
throughout its system. Data traversing from one clock domain
to a different clock domain can lead to ambiguous delays in the
JESD204B link. These ambiguities lead to nonrepeatable latencies
across the link from power cycle to power cycle with each new
link establishment. Section 6 of the JESD204B specification
addresses the issue of deterministic latency with mechanisms
defined as Subclass 1 and Subclass 2.
The AD9163 supports JESD204B Subclass 0 and Subclass 1
operation, but not Subclass 2. Write the subclass to Register 0x458,
Bits[7:5].
Subclass 0
This mode gives deterministic latency to within 32 DAC clock
cycles. It does not require any signal on the SYSREF± pins,
which can be left disconnected.
Subclass 0 still requires that all lanes arrive within the same LMFC
cycle and the dual DACs must be synchronized to each other.
Subclass 1
This mode gives deterministic latency and allows the link to be
synced to within four DAC clock periods. It requires an external
SYSREF± signal that is accurately phase aligned to the DAC clock.
Deterministic Latency Requirements
Several key factors are required for achieving deterministic
latency in a JESD204B Subclass 1 system.
•
•
•
Table 20. Sync Processing Modes
Sync Processing
Mode
No synchronization
One shot
Continuous
Deterministic Latency
SYNC_MODE (Register 0x03A, Bits[1:0])
0b00
0b10
0b01
Table 21. SYSREF± Jitter Window Tolerance
SYSREF± Jitter Window
Tolerance (DAC Clock Cycles)
±½
±4
±8
±12
±16
±20
+24
±28
1
SYSREF_JITTER_WINDOW
(Register 0x039, Bits[5:0])1
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
The two least significant digits are ignored because the SYSREF± signal is
sampled with a divide by 4 version of the DAC clock. As a result, the jitter
window is set by this divide by 4 clock rather than the DAC clock. It is
recommended that at least a four-DAC clock SYSREF± jitter window be chosen.
Rev. D | Page 39 of 126
SYSREF± signal distribution skew within the system must
be less than the desired uncertainty.
SYSREF± setup and hold time requirements must be met
for each device in the system.
The total latency variation across all lanes, links, and
devices must be ≤10 PCLK periods, which includes both
variable delays and the variation in fixed delays from lane
to lane, link to link, and device to device in the system.
AD9163
Data Sheet
LINK DELAY = DELAYFIXED + DELAYVARIABLE
LOGIC DEVICE
(JESD204B Tx)
CHANNEL
JESD204B Rx
DSP
DAC
POWER CYCLE
VARIANCE
LMFC
ILAS
DATA
ALIGNED DATA
AT Rx OUTPUT
ILAS
DATA
FIXED DELAY
VARIABLE
DELAY
14415-095
DATA AT
Tx INPUT
Figure 100. JESD204B Link Delay = Fixed Delay + Variable Delay
Link Delay
Setting LMFCDel appropriately ensures that all the corresponding
data samples arrive in the same LMFC period. Then LMFCVar
is written into the receive buffer delay (RBD) to absorb all link
delay variation. This write ensures that all data samples have
arrived before reading. By setting these to fixed values across
runs and devices, deterministic latency is achieved.
The link delay of a JESD204B system is the sum of the fixed and
variable delays from the transmitter, channel, and receiver as
shown in Figure 100.
For proper functioning, all lanes on a link must be read during
the same LMFC period. Section 6.1 of the JESD204B specification states that the LMFC period must be larger than the maximum
link delay. For the AD9163, this is not necessarily the case;
instead, the AD9163 uses a local LMFC for each link (LMFCRx)
that can be delayed from the SYSREF± aligned LMFC. Because
the LMFC is periodic, this delay can account for any amount of
fixed delay. As a result, the LMFC period must only be larger
than the variation in the link delays, and the AD9163 can achieve
proper performance with a smaller total latency. Figure 101 and
Figure 102 show a case where the link delay is greater than an
LMFC period. Note that it can be accommodated by delaying
LMFCRx.
The RBD described in the JESD204B specification takes values
from 1 frame clock cycle to K frame clock cycles, and the RBD
of the AD9163 takes values from 0 PCLK cycle to 10 PCLK
cycles. As a result, up to 10 PCLK cycles of total delay variation
can be absorbed. LMFCVar and LMFCDel are both in PCLK
cycles. The PCLK factor, or number of frame clock cycles per
PCLK cycle, is equal to 4/F. For more information on this
relationship, see the Clock Relationships section.
Two examples follow that show how to determine LMFCVar
and LMFCDel. After they are calculated, write LMFCDel into
Register 0x304 for all devices in the system, and write LMFCVar
to Register 0x306 for all devices in the system.
POWER CYCLE
VARIANCE
Link Delay Setup Example, With Known Delays
LMFC
ILAS
DATA
EARLY ARRIVING
LMFC REFERENCE
All the known system delays can be used to calculate LMFCVar
and LMFCDel.
14415-093
ALIGNED DATA
LATE ARRIVING
LMFC REFERENCE
The example shown in Figure 103 is demonstrated in the
following steps. Note that this example is in Subclass 1 to
achieve deterministic latency, which has a PCLK factor (4/F) of
2 frame clock cycles per PCLK cycle, and uses K = 32
(frames/multiframe). Because PCBFixed LMFC Period Example
POWER CYCLE
VARIANCE
LMFC
ALIGNED DATA
ILAS
DATA
LMFCRX
LMFC REFERENCE FOR ALL POWER CYCLES
FRAME CLOCK
14415-094
1.
LMFC_DELAY
2.
Figure 102. LMFC_DELAY_x to Compensate for Link Delay > LMFC
The method to select the LMFCDel (Register 0x304) and
LMFCVar (Register 0x306) variables is described in the Link
Delay Setup Example, With Known Delays section.
Rev. D | Page 40 of 126
Find the receiver delays using Table 7.
RxFixed = 12 PCLK cycles
RxVar = 2 PCLK cycles
Find the transmitter delays. The equivalent table in the
example JESD204B core (implemented on a GTH or GTX
gigabit transceiver on a Virtex-6 FPGA) states that the
delay is 56 ± 2 byte clock cycles.
Data Sheet
4.
5.
6.
7.
8.
Because the PCLK Rate = ByteRate/4 as described in the
Clock Relationships section, the transmitter delays in
PCLK cycles are calculated as follows:
TxFixed = 54/4 = 13.5 PCLK cycles
TxVar = 4/4 = 1 PCLK cycle
Calculate MinDelayLane as follows:
MinDelayLane = floor(RxFixed + TxFixed + PCBFixed)
= floor(12 + 13.5 + 0)
= floor(25.5)
MinDelayLane = 25
Calculate MaxDelayLane as follows:
MaxDelayLane = ceiling(RxFixed + RxVar + TxFixed +
TxVar + PCBFixed))
= ceiling(12 + 2 + 13.5 + 1 + 0)
= ceiling(28.5)
MaxDelayLane = 29
Calculate LMFCVar as follows:
LMFCVar = (MaxDelay + 1) − (MinDelay − 1)
= (29 + 1) − (25 − 1) = 30 − 24
LMFCVar = 6 PCLK cycles
Calculate LMFCDel as follows:
LMFCDel = (MinDelay − 1) % (K/PClockFactor)
= (30 − 1) % (32/2)
= 29 % 16
LMFCDel = 13 PCLK cycles
Write LMFCDel to Register 0x304 for all devices in the
system. Write LMFCVar to Register 0x306 for all devices in
the system.
Link Delay Setup Example, Without Known Delay
If the system delays are not known, the AD9163 can read back
the link latency between LMFCRX for each link and the
SYSREF± aligned LMFC. This information is then used to
calculate LMFCVar and LMFCDel.
Figure 105 shows how DYN_LINK_LATENCY_0 (Register 0x302)
provides a readback showing the delay (in PCLK cycles)
between LMFCRX and the transition from ILAS to the first data
sample. By repeatedly power cycling and taking this measurement,
the minimum and maximum delays across power cycles can be
determined and used to calculate LMFCVar and LMFCDel.
In Figure 105, for Link A, Link B, and Link C, the system
containing the AD9163 (including the transmitter) is power
cycled and configured 20 times. The AD9163 is configured as
described in the Sync Procedure section. Because the purpose
of this exercise is to determine LMFCDel and LMFCVar, the
LMFCDel value is programmed to 0 and the
DYN_LINK_LATENCY_0 value is read from Register 0x302.
The variation in the link latency over the 20 runs is shown in
Figure 105, described as follows:
•
•
•
Link A gives readbacks of 6, 7, 0, and 1. Note that the set of
recorded delay values rolls over the edge of a multiframe at
the boundary of K/PCLK factor = 8. Add the number of
PCLK cycles per multiframe = 8 to the readback values of 0
and 1 because they rolled over the edge of the multiframe.
Delay values range from 6 to 9.
Link B gives delay values from 5 to 7.
Link C gives delay values from 4 to 7.
LMFC
PCLK
FRAME CLOCK
DATA AT Tx FRAMER
ALIGNED LANE DATA
AT Rx DEFRAMER OUTPUT
ILAS
DATA
ILAS
Tx VAR
DELAY
Rx VAR
DELAY
DATA
PCB FIXED
DELAY
LMFCRX
LMFC DELAY = 26 FRAME CLOCK CYCLES
TOTAL FIXED LATENCY = 30 PCLK CYCLES
Figure 103. LMFC Delay Calculation Example
Rev. D | Page 41 of 126
TOTAL VARIABLE
LATENCY = 4
PCLK CYCLES
14415-096
3.
AD9163
AD9163
Data Sheet
The example shown in Figure 105 is demonstrated in the
following steps. Note that this example is in Subclass 1 to
achieve deterministic latency, which has a PCLK factor
(FrameRate ÷ PCLK Rate) of 4 and uses K = 32; therefore PCLK
cycles per multiframe = 8.
3.
5.
SYSREF±
LMFCRX
ILAS
ALIGNED DATA
DATA
DYN_LINK_LATENCY
Figure 104. DYN_LINK_LATENCY_x Illustration
LMFC
PCLK
FRAME CLOCK
DYN_LINK_LATENCY_CNT
0
1
2
ALIGNED DATA (LINK A)
ALIGNED DATA (LINK B)
ALIGNED DATA (LINK C)
3
4
5
6
7
0
1
2
3
ILAS
4
5
6
7
DATA
DATA
ILAS
ILAS
DATA
LMFCRX
DETERMINISTICALLY
DELAYED DATA
ILAS
LMFC_DELAY = 6
(FRAME CLOCK CYCLES)
DATA
LMFC_VAR = 7
(PCLK CYCLES)
Figure 105. Multilink Synchronization Settings, Derived Method Example
Rev. D | Page 42 of 126
14415-098
2.
Calculate the minimum of all delay measurements across
all power cycles, links, and devices as follows:
MinDelay = min(all Delay values) = 4
Calculate the maximum of all delay measurements across
all power cycles, links, and devices as follows:
MaxDelay = max(all Delay values) = 9
Calculate the total delay variation (with guard band) across
all power cycles, links, and devices as follows:
14415-097
1.
4.
LMFCVar = (MaxDelay + 1) − (MinDelay − 1)
= (9 + 1) − (4 − 1) = 10 − 3 = 7 PCLK cycles
Calculate the minimum delay in PCLK cycles (with guard
band) across all power cycles, links, and devices as follows:
LMFCDel
= (MinDelay − 1) % (K/PCLK Factor)
= (4 − 1) % 32/4
= 3 % 8 = 3 PCLK cycles
Write LMFCDel to Register 0x304 for all devices in the
system. Write LMFCVar to Register 0x306 for all devices in
the system.
Data Sheet
AD9163
TRANSPORT LAYER
TRANSPORT LAYER
(QBD)
LANE 0 OCTETS
DAC A_I0[15:0]
DELAY
BUFFER 0
F2S_0
DAC A_Q0[15:0]
LANE 3 OCTETS
PCLK_0
SPI CONTROL
LANE 4 OCTETS
DAC B_I0[15:0]
PCLK_0
TO
PCLK_1
FIFO
DELAY
BUFFER 1
F2S_1
DAC B_Q0[15:0]
14415-099
LANE 7 OCTETS
PCLK_1
SPI CONTROL
Figure 106. Transport Layer Block Diagram
The transport layer receives the descrambled JESD204B frames
and converts them to DAC samples based on the programmed
JESD204B parameters shown in Table 22. The device parameters
are defined in Table 23.
Table 22. JESD204B Transport Layer Parameters
Parameter
F
K
L
M
S
Description
Number of octets per frame per lane: 1, 2, or 4
Number of frames per multiframe: K = 32
Number of lanes per converter device (per link), as
follows: 4 or 8
Number of converters per device (per link), as follows:
2 (2 is used for the AD9163)
Number of samples per converter, per frame: 1 or 2
Table 23. JESD204B Device Parameters
Parameter
CF
CS
HD
N
Nʹ (or NP)
Description
Number of control words per device clock per link.
Not supported, must be 0.
Number of control bits per conversion sample. Not
supported, must be 0.
High density user data format. Used when samples
must be split across lanes. Set to 1 always, even
when F does not equal 1. Otherwise, a link
configuration error triggers and the IRQ_ILAS flag
is set.
Converter resolution = 16.
Total number of bits per sample = 16.
Certain combinations of these parameters are supported by the
AD9163. See Table 26 for a list of supported interpolation rates
and the number of lanes that is supported for each rate. Table 26
lists the JESD204B parameters for each of the interpolation and
number of lanes configuration, and gives an example lane rate for a
5 GHz DAC clock. Table 25 lists JESD204B parameters that have
fixed values. A value of yes in Table 24 means the interpolation rate
is supported for the number of lanes. A blank cell means it is not
supported.
Table 24. Interpolation Rates and Number of Lanes
Interpolation
6×
8×
12×
16×
24×
8
Yes
Yes
Yes
Yes
Yes
6
Yes
Yes
Yes
Yes
Yes
4
Yes
Yes
Yes
Yes
Yes
3
Yes
Yes
Yes
Yes
Yes
2
1
Yes
Yes
Yes
Yes
Yes
Yes
Table 25. JESD204B Parameters with Fixed Values
Parameter
K
N
NP
CF
HD
CS
Rev. D | Page 43 of 126
Value
32
16
16
0
1
0
AD9163
Data Sheet
Table 26. JESD204B Parameters for Interpolation Rate and Number of Lanes
Interpolation
Rate
6
6
6
6
8
8
8
8
8
12
12
12
12
12
16
16
16
16
16
16
24
24
24
24
24
24
No. of
Lanes
3
4
6
8
2
3
4
6
8
2
3
4
6
8
1
2
3
4
6
8
1
2
3
4
6
8
M
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
F
4
1
2
1
2
4
1
2
1
2
4
1
2
1
4
2
4
1
2
1
4
2
4
1
2
1
S
3
1
3
2
1
3
1
3
2
1
3
1
3
2
1
1
3
1
3
2
1
1
3
1
3
2
PCLK Period
(DAC Clocks)
18
24
36
48
16
24
32
48
64
24
36
48
72
96
16
32
48
64
96
128
24
48
72
96
144
192
LMFC Period
(DAC Clocks)
576
192
576
384
256
768
256
768
512
384
1152
384
1152
768
512
512
1536
512
1536
1024
768
768
2304
768
2304
1536
Rev. D | Page 44 of 126
Lane Rate at 5 GHz DAC Clock
(GHz)
11.11
8.33
5.55
4.16
12.5
8.33
6.25
4.16
3.12
8.33
5.55
4.16
2.77
2.08
12.5
6.25
4.16
3.12
2.08
1.56
8.33
4.16
2.77
2.08
1.38
1.04
Data Sheet
AD9163
Configuration Parameters
The AD9163 modes refer to the link configuration parameters
for L, K, M, N, NP, S, and F. Table 27 provides the description
and addresses for these settings.
Table 27. Configuration Parameters
JESD204B
Setting
L−1
F−1
Description
Number of lanes minus 1.
M−1
Number of ((octets per frame) per
lane) minus 1.
Number of frames per multiframe
minus 1.
Number of converters minus 1.
N−1
Converter bit resolution minus 1.
NP − 1
Bit packing per sample minus 1.
S−1
Number of ((samples per
converter) per frame) minus 1.
High density format. Set to 1 if F =
1. Leave at 0 if F ≠ 1.
Device ID. Match the device ID
sent by the transmitter.
Bank ID. Match the bank ID sent by
the transmitter.
Lane ID for Lane 0. Match the Lane
ID sent by the transmitter on
Logical Lane 0.
JESD204x version. Match the
version sent by the transmitter
(0x0 = JESD204A, 0x1 = JESD204B).
K−1
HD
DID
BID
LID0
JESDV
counts for failing lanes are reported for one JESD204B lane at a
time. The process for performing PRBS testing on the AD9163
is as follows:
1.
2.
Address
Register 0x453,
Bits[4:0]
Register 0x454,
Bits[7:0]
Register 0x455,
Bits[4:0]
Register 0x456,
Bits[7:0]
Register 0x457,
Bits[4:0]
Register 0x458,
Bits[4:0]
Register 0x459,
Bits[4:0]
Register 0x45A,
Bit 7
Register 0x450,
Bits[7:0]
Register 0x451,
Bits[7:0]
Register 0x452,
Bits[4:0]
Register 0x459,
Bits[7:5]
Data Flow Through the JESD204B Receiver
The link configuration parameters determine how the serial bits
on the JESD204B receiver interface are deframed and passed on
to the DACs as data samples.
Deskewing and Enabling Logical Lanes
After proper configuration, the logical lanes are automatically
deskewed. All logical lanes are enabled or not based on the lane
number setting in Register 0x110, Bits[7:4]. The physical lanes
are all powered up by default.
To disable power to physical lanes that are not being used, set Bit x
in Register 0x201 to 1 to disable Physical Lane x, and keep it at 0
to enable it.
JESD204B TEST MODES
PHY PRBS Testing
The JESD204B receiver on the AD9163 includes a PRBS pattern
checker on the back end of its physical layer. This functionality
enables bit error rate (BER) testing of each physical lane of the
JESD204B link. The PHY PRBS pattern checker does not
require that the JESD204B link be established. It can synchronize
with a PRBS7, PRBS15, or PRBS31 data pattern. PRBS pattern
verification can be done on multiple lanes at once. The error
3.
4.
5.
6.
7.
8.
9.
Start sending a PRBS7, PRBS15, or PRBS31 pattern from
the JESD204B transmitter.
Select and write the appropriate PRBS pattern to
Register 0x316, Bits[3:2], as shown in Table 28.
Enable the PHY test for all lanes being tested by writing to
PHY_TEST_EN (Register 0x315). Each bit of Register 0x315
enables the PRBS test for the corresponding lane. For example,
writing a 1 to Bit 0 enables the PRBS test for Physical Lane 0.
Toggle PHY_TEST_RESET (Register 0x316, Bit 0) from 0
to 1 then back to 0.
Set PHY_PRBS_TEST_THRESHOLD_xBITS (Bits[23:0],
Register 0x319 to Register 0x317) as desired.
Write a 0 and then a 1 to PHY_TEST_START (Register 0x316,
Bit 1). The rising edge of PHY_TEST_START starts the test.
a. (Optional) In some cases, it may be necessary to
repeat Step 4 at this point. Toggle PHY_TEST_RESET
(Register 0x316, Bit 0) from 0 to 1, then back to 0.
Wait 500 ms.
Stop the test by writing PHY_TEST_START
(Register 0x316, Bit 1) = 0.
Read the PRBS test results.
a. Each bit of PHY_PRBS_PASS (Register 0x31D)
corresponds to one SERDES lane (0 = fail, 1 = pass).
The number of PRBS errors seen on each failing lane can be
read by writing the lane number to check (0 to 7) in PHY_SRC_
ERR_CNT (Register 0x316, Bits[6:4]) and reading the PHY_PRBS_
ERR_COUNT (Register 0x31C to Register 0x31A). The maximum
error count is 224 − 1. If all bits of Register 0x31C to Register 0x31A
are high, the maximum error count on the selected lane is
exceeded.
Table 28. PHY PRBS Pattern Selection
PHY_PRBS_PAT_SEL Setting
(Register 0x316, Bits[3:2])
0b00 (default)
0b01
0b10
PRBS Pattern
PRBS7
PRBS15
PRBS31
Transport Layer Testing
The JESD204B receiver in the AD9163 supports the short
transport layer (STPL) test as described in the JESD204B
standard. This test can be used to verify the data mapping
between the JESD204B transmitter and receiver. To perform
this test, this function must be implemented in the logic device
and enabled there. Before running the test on the receiver side,
the link must be established and running without errors.
The STPL test ensures that each sample from each converter is
mapped appropriately according to the number of converters
(M) and the number of samples per converter (S). As specified
in the JESD204B standard, the converter manufacturer specifies
what test samples are transmitted. Each sample must have a
Rev. D | Page 45 of 126
AD9163
Data Sheet
unique value. For example, if M = 2 and S = 2, four unique
samples are transmitted repeatedly until the test is stopped. The
expected sample must be programmed into the device and the
expected sample is compared to the received sample one sample
at a time until all are tested. The process for performing this test
on the AD9163 is described as follows:
7.
1.
2.
3.
9.
4.
5.
6.
Synchronize the JESD204B link.
Enable the STPL test at the JESD204B Tx.
Depending on JESD204B case, there may be up to two
DACs, and each frame may contain up to four DAC
samples. Configure the SHORT_TPL_REF_SP_MSB bits
(Register 0x32E) and SHORT_TPL_REF_SP_LSB bits
(Register 0x32D) to match one of the samples for one
converter within one frame.
Set SHORT_TPL_SP_SEL (Register 0x32C, Bits[7:4]) to
select the sample within one frame for the selected
converter according to Table 29.
Set SHORT_TPL_TEST_EN (Register 0x32C, Bit 0) to 1.
Set SHORT_TPL_TEST_RESET (Register 0x32C, Bit 1) to
1, then back to 0.
8.
Wait for the desired time. The desired time is calculated as
1/(sample rate × BER). For example, given a bit error rate
of BER = 1 × 10−10 and a sample rate = 1 GSPS, the desired
time = 10 sec.
Read the test result at SHORT_TPL_FAIL (Register 0x32F,
Bit 0).
Choose another sample for the same or another converter
to continue with the test, until all samples for both
converters from one frame are verified. (Note that the
converter count is M = 2 for all interpolator modes on the
AD9163 to enable complex signal processing.)
Consult Table 29 for a guide to the test sample alignment. Note
that the sample order for 1×, eight-lane mode has Sample 1 and
Sample 2 swapped. Also, the STPL test for the three-lane and
six-lane options is not functional and always fails.
Table 29. Short TPL Test Samples Assignment1
JESD204x Mode
6× Eight-Lane (L = 8, M = 2, F = 1, S = 2)
8× Eight-Lane (L = 8, M = 2, F = 1, S = 2)
12× Eight-Lane e (L = 8, M = 2, F = 1, S = 2)
16× Eight-Lane (L = 8, M = 2, F = 1, S = 2)
24× Eight-Lane (L = 8, M = 2, F = 1, S = 2)
6× Six-Lane (L = 6, M = 2, F = 2, S = 3)
8× Six-Lane (L = 6, M = 2, F = 2, S = 3)
12× Six-Lane (L = 6, M = 2, F = 2, S = 3)
16× Six-Lane (L = 6, M = 2, F = 2, S = 3)
24× Six-Lane (L = 6, M = 2, F = 2, S = 3)
4× Three-Lane (L = 3, M = 2, F = 4, S = 3)
6× Three-Lane (L = 3, M = 2, F = 4, S = 3)
8× Three-Lane (L = 3, M = 2, F = 4, S = 3)
12× Three-Lane (L = 3, M = 2, F = 4, S = 3)
16× Three-Lane (L = 3, M = 2, F = 4, S = 3)
24× Three-Lane (L = 3, M = 2, F = 4, S = 3)
6× Four-Lane (L = 4, M = 2, F = 1, S = 1)
8× Four-Lane (L = 4, M = 2, F = 1, S = 1)
12× Four-Lane (L = 4, M = 2, F = 1, S = 1)
16× Four-Lane (L = 4, M = 2, F = 1, S = 1)
24× Four-Lane (L = 4, M = 2, F = 1, S = 1)
8× Two-Lane (L = 2, M = 2, F = 2, S = 1)
12× Two-Lane (L = 2, M = 2, F = 2, S = 1)
16× Two-Lane (L = 2, M = 2, F = 2, S = 1)
24× Two-Lane (L = 2, M = 2, F = 2, S = 1)
16× One-Lane (L = 1, M = 2, F = 4, S = 1)
24× One-Lane (L = 1, M = 2, F = 4, S = 1)
1
Required Samples from JESD204x Tx
Send four samples: M0S0, M0S1, M1S0,
M1S1, and repeat
Samples Assignment
SP0: M0S0, SP4: M0S0, SP8: M0S0, SP12: M0S0
SP1: M1S0, SP5: M1S0, SP9: M1S0, SP13: M1S0
SP2: M0S1, SP6: M0S1, SP10: M0S1, SP14: M0S1
SP3: M1S1, SP7: M1S1, SP11: M1S1, SP15: M1S1
Send six samples: M0S0, M0S1, M0S2,
M1S0, M1S1, M1S2, and repeat
Test hardware is not functional; STPL always fails
Send two samples: M0S0, M1S0, repeat
SP0: M0S0, SP4: M0S0, SP8: M0S0, SP12: M0S0
SP1: M1S0, SP5: M1S0, SP9: M1S0, SP13: M1S0
SP2: M0S0, SP6: M0S0, SP10: M0S0, SP14: M0S0
SP3: M1S0, SP7: M1S0, SP11: M1S0, SP15: M1S0
Mx is the converter number and Sy is the sample number. For example, M0S0 means Converter 0, Sample 0. SPx is the sample pattern word number. For example, SP0
means Sample Pattern Word 0.
Rev. D | Page 46 of 126
Data Sheet
AD9163
Repeated CGS and ILAS Test
As per Section 5.3.3.8.2 of the JESD204B specification, the
AD9163 can check that a constant stream of /K28.5/ characters
is being received, or that CGS followed by a constant stream of
ILAS is being received.
To run a repeated CGS test, send a constant stream of /K28.5/
characters to the AD9163 SERDES inputs. Next, set up the
device and enable the links. Ensure that the /K28.5/ characters are
being received by verifying that SYNCOUT± is deasserted and
that CGS has passed for all enabled link lanes by reading
Register 0x470.
To run the CGS followed by a repeated ILAS sequence test,
follow the procedure to set up the links, but before performing
the last write (enabling the links), enable the ILAS test mode by
writing a 1 to Register 0x477, Bit 7. Then, enable the links. When
the device recognizes four CGS characters on each lane, it
deasserts the SYNCOUT±. At this point, the transmitter starts
sending a repeated ILAS sequence.
Read Register 0x473 to verify that initial lane synchronization has
passed for all enabled link lanes.
JESD204B ERROR MONITORING
on a per lane and per error type basis. Each error type and lane
has a register dedicated to it. To check the error count, the
following steps must be performed:
1.
2.
3.
Choose and enable which errors to monitor by selecting
them in Register 0x480, Bits[5:3] to Register 0x487,
Bits[5:3]. Unexpected K (UEK) character, BDE, and NIT
error monitoring can be selected for each lane by writing a
1 to the appropriate bit, as described in the register map.
These bits are enabled by default.
The corresponding error counter reset bits are in
Register 0x480, Bits[2:0] to Register 0x487, Bits[2:0].
Write a 0 to the corresponding bit to reset that error
counter.
Registers 0x488, Bits[2:0] to Register 0x48F, Bits[2:0] have
the terminal count hold indicator for each error counter. If
this flag is enabled, when the terminal error count of 0xFF
is reached, the counter ceases counting and holds that
value until reset. Otherwise, it wraps to 0x00 and continues
counting. Select the desired behavior and program the
corresponding register bits per lane.
Check for Error Count Over Threshold
To check for the error count over threshold, follow these steps:
Disparity, Not in Table, and Unexpected Control (K)
Character Errors
1.
As per Section 7.6 of the JESD204B specification, the AD9163
can detect disparity errors, not in table (NIT) errors, and
unexpected control character errors, and can optionally issue a
sync request and reinitialize the link when errors occur.
Note that the disparity error counter counts all characters with
invalid disparity, regardless of whether they are in the 8-bit/10-bit
decoding table. This is a minor deviation from the JESD204B
specification, which only counts disparity errors when they are
in the 8-bit/10-bit decoding table.
Several other interpretations of the JESD204B specification are
noted in this section. When three NIT errors are injected to one
lane and QUAL_RDERR (Register 0x476, Bit 4) = 1, the readback
values of the bad disparity error (BDE) count register is 1.
Reporting of disparity errors that occur at the same character
position of an NIT error is disabled. No such disabling is performed for the disparity errors in the characters after an NIT
error. Therefore, it is expected behavior that an NIT error may
result in a BDE error.
A resync is triggered when four NIT errors are injected with
Register 0x476, Bit 4 = 1. When this bit is set, the error counter
does not distinguish between a concurrent invalid symbol with
the wrong running disparity but is in the 8-bit/10-bit decoding
table, and an NIT error. Thus, a resync can be triggered when
four NIT errors are injected because they are not distinguished
from disparity errors.
2.
3.
Define the error counter threshold. The error counter
threshold can be set to a user defined value in Register 0x47C,
or left to the default value of 0xFF. When the error threshold is
reached, an IRQ is generated or SYNCOUT± is asserted or
both, depending on the mask register settings. This one error
threshold is used for all three types of errors (UEK, NIT,
and BDE).
Set the SYNC_ASSERT_MASK bits. The SYNCOUT±
assertion behavior is set in Register 0x47D, Bits[2:0]. By
default, when any error counter of any lane is equal to the
threshold, it asserts SYNCOUT± (Register 0x47D, Bits[2:0] =
0b111).
Read the error count reached indicator. Each error counter
has a terminal count reached indicator, per lane. This indicator is set to 1 when the terminal count of an error counter
for a particular lane has been reached. These status bits are
located in Register 0x490, Bits[2:0] to Register 0x497, Bits[2:0].
These registers also indicate whether a particular lane is
active by setting Bit 3 = 0b1.
Error Counter and IRQ Control
For error counter and IRQ control, follow these steps:
1.
Checking Error Counts
The error count can be checked for disparity errors, NIT errors,
and unexpected control character errors. The error counts are
Rev. D | Page 47 of 126
Enable the JESD204B interrupts. The interrupts for the UEK,
NIT, and BDE error counters are in Register 0x4B8, Bits[7:5].
There are other interrupts to monitor when bringing up the
link, such as lane deskewing, initial lane sync, good check
sum, frame sync, code group sync (Register 0x4B8, Bits[4:0],
and configuration mismatch (Register 0x4B9, Bit 0). These
bits are off by default but can be enabled by writing 0b1 to the
corresponding bit.
AD9163
2.
3.
Data Sheet
Read the JESD204B interrupt status. The interrupt status
bits are in Register 0x4BA, Bits[7:0] and Register 0x4BB,
Bit 0, with the status bit position corresponding to the
enable bit position.
It is recommended to enable all interrupts that are planned
to be used prior to bringing up the JESD204B link. When
the link is up, the interrupts can be reset and then used to
monitor the link status.
2.
3.
4.
Monitoring Errors via SYNCOUT±
When one or more disparity, NIT, or unexpected control
character errors occur, the error is reported on the SYNCOUT±
pin as per Section 7.6 of the JESD204B specification. The
JESD204B specification states that the SYNCOUT± signal is
asserted for exactly two frame periods when an error occurs. For
the AD9163, the width of theSYNCOUT± pulse can be
programmed to ½, 1, or 2 PCLK cycles. The settings to achieve a
SYNCOUT± pulse of two frame clock cycles are given in Table 30.
Table 31. Sync Assertion Mask (SYNC_ASSERT_MASK)
Addr.
0x47D
Table 30. Setting SYNCOUT± Error Pulse Duration
F
1
2
4
1
PCLK Factor
(Frames/PCLK)
4
2
1
SYNC_ERR_DUR (Register 0x312,
Bits[7:4]) Setting1
0 (default)
1
2
These register settings assert the SYNCOUT± signal for two frame clock cycle
pulse widths.
Unexpected Control Character, NIT, Disparity IRQs
For UEK character, NIT, and disparity errors, error count over
the threshold events are available as IRQ events. Enable these
events by writing to Register 0x4B8, Bits[7:5]. The IRQ event
status can be read at Register 0x4BA, Bits[7:5] after the IRQs are
enabled.
See the Error Counter and IRQ Control section for information
on resetting the IRQ. See the Interrupt Request Operation
section for more information on IRQs.
Errors Requiring Reinitializing
A link reinitialization automatically occurs when four invalid
disparity characters are received as per Section 7.1 of the
JESD204B specification. When a link reinitialization occurs, the
resync request is five frames and nine octets long.
The user can optionally reinitialize the link when the error
count for disparity errors, NIT errors, or UEK character errors
reaches a programmable error threshold. The process to enable
the reinitialization feature for certain error types is as follows:
1.
Enable the sync assertion mask for each type of error by
writing to SYNC_ASSERT_MASK (Register 0x47D,
Bits[2:0]) according to Table 31.
Program the desired error counter threshold into
ERRORTHRES (Register 0x47C).
For each error type enabled in the SYNC_ASSERT_MASK
register, if the error counter on any lane reaches the
programmed threshold, SYNCOUT± falls, issuing a sync
request. Note that all error counts are reset when a link
reinitialization occurs. The IRQ does not reset and must be
reset manually.
Bit No.
2
Bit Name
BDE
1
NIT
0
UEK
Description
Set to 1 to assert SYNCOUT± if
the disparity error count
reaches the threshold
Set to 1 to assert SYNCOUT± if
the NIT error count reaches
the threshold
Set to 1 to assert SYNCOUT± if
the UEK character error
count reaches the threshold
CGS, Frame Sync, Checksum, and ILAS Monitoring
Register 0x470 to Register 0x473 can be monitored to verify
that each stage of the JESD204B link establishment has
occurred.
Bit x of CODE_GRP_SYNC (Register 0x470) is high if Link
Lane x received at least four K28.5 characters and passed code
group synchronization.
Bit x of FRAME_SYNC (Register 0x471) is high if Link Lane x
completed initial frame synchronization.
Bit x of GOOD_CHECKSUM (Register 0x472) is high if the
checksum sent over the lane matches the sum of the JESD204B
parameters sent over the lane during ILAS for Link Lane x. The
parameters can be added either by summing the individual fields
in registers or summing the packed register. If Register 0x300,
Bit 6 = 0 (default), the calculated checksums are the lower eight
bits of the sum of the following fields: DID, BID, LID, SCR, L − 1,
F − 1, K − 1, M − 1, N − 1, SUBCLASSV, NP − 1, JESDV, S − 1,
and HD. If Register 0x300, Bit 6 = 1, the calculated checksums
are the lower eight bits of the sum of Register 0x400 to
Register 0x40C and LID.
Bit x of INIT_LANE_SYNC (Register 0x473) is high if Link
Lane x passed the initial lane alignment sequence.
Choose and enable which errors to monitor by selecting
them in Register 0x480, Bits[5:3] to Register 0x487,
Bits[5:3]. UEK, BDE, and NIT error monitoring can be
selected for each lane by writing a 1 to the appropriate bit,
as described in Table 44. These are enabled by default.
Rev. D | Page 48 of 126
Data Sheet
AD9163
CGS, Frame Sync, Checksum, and ILAS IRQs
Fail signals for CGS, frame sync, checksum, and ILAS are available
as IRQ events. Enable them by writing to Register 0x4B8,
Bits[3:0]. The IRQ event status can be read at Register 0x4BA,
Bits[3:0] after the IRQs are enabled. Write a 1 to Register 0x4BA,
Bit 0 to reset the CGS IRQ. Write a 1 to Register 0x4BA, Bit 1 to
reset the frame sync IRQ. Write a 1 to Register 0x4BA, Bit 2 to
reset the checksum IRQ. Write a 1 to Register 0x4BA, Bit 3 to
reset the ILAS IRQ.
to read back its status and reset the IRQ signal. See the Interrupt
Request Operation section for more information.
The configuration mismatch event flag is high when the link
configuration settings (in Register 0x450 to Register 0x45D) do
not match the JESD204B transmitted settings (Register 0x400 to
Register 0x40D).
See the Interrupt Request Operation section for more
information.
This function is different from the good checksum flags in
Register 0x472. The good checksum flags ensure that the transmitted checksum matches a calculated checksum based on the
transmitted settings. The configuration mismatch event ensures
that the transmitted settings match the configured settings.
Configuration Mismatch IRQ
HARDWARE CONSIDERATIONS
The AD9163 has a configuration mismatch flag that is available as
an IRQ event. Use Register 0x4B9, Bit 0 to enable the mismatch
flag (it is enabled by default), and then use Register 0x4BB, Bit 0
See the Applications Information section for information on
hardware considerations.
Rev. D | Page 49 of 126
AD9163
Data Sheet
14415-104
MAIN DIGITAL DATAPATH
Figure 107. Block Diagram of the Main Digital Datapath
The block diagram in Figure 107 shows the functionality of the
main digital datapath. The digital processing includes an input
interpolation block with the choice of bypass (1×), 2×, or 3×
interpolation, three additional 2× half-band interpolation
filters, a final 2× NRZ mode interpolator filter, FIR85, that can
be bypassed, and a quadrature modulator that consists of a
48-bit NCO and an inverse sinc block.
All of the interpolation filters accept in-phase (I) and quadrature
(Q) data streams as a complex data stream. Similarly, the
quadrature modulator and inverse sinc function also accept
input data as a complex data stream. Thus, any use of the digital
datapath functions requires the input data to be a complex data
stream.
In bypass mode (1× interpolation), the input data stream is
expected to be real data.
Table 32. Pipeline Delay (Latency) for Various DAC Blocks
Mode
6×
8×
12×
16×
24×
1
FIR85
On
No
No
No
No
No
Filter
Bandwidth
80%
80%
80%
80%
80%
Inverse
Sinc
No
No
No
No
No
NCO
No
No
No
No
No
Pipeline Delay1
(fDAC Clocks)
332
602
674
1188
1272
The pipeline delay given is a representative number, and may vary by a cycle
or two based on the internal handoff timing conditions at startup.
The pipeline delay changes based on the digital datapath
functions that are selected. See Table 32 for examples of the
pipeline delay per block. These delays are in addition to the
JESD204B latency.
INTERPOLATION FILTERS
The main digital path contains five half-band interpolation
filters, plus a final half-band interpolation filter that is used in
2× NRZ mode. The filters are cascaded as shown in Figure 107.
The first pair of filters is a 2× (HB2) or 3× (HB3) filter. Each of
these filters has two options for bandwidth, 80% or 90%. The
80% filters are lower power than the 90%. The filters default to
the lower power 80% bandwidth. To select the filter bandwidth
as 90%, program the FILT_BW bit in the DATAPATH_CFG
register to 1 (Register 0x111, Bit 4 = 0b1).
Following the first pair of filters is a series of 2× half-band
filters, each of which halves the usable bandwidth of the
previous one. HB4 has 45%, HB5 has 22.5%, and HB6 has
11.25% of the fDATA bandwidth.
The final half-band filter, FIR85, is used in the 2× NRZ mode. It
is clocked at the 2 × fDAC rate and has a usable bandwidth of 45%
of the fDAC rate. The FIR85 filter is a complex filter, and therefore
the bandwidth is centered at 0 Hz. The FIR85 filter is used in
conjunction with the complex interpolation modes to push the
DAC update rate higher and move images further from the
desired signal.
Table 33 shows how to select each available interpolation mode,
their usable bandwidths, and their maximum data rates. Calculate
the available signal bandwidth as the interpolator filter bandwidth,
BWFILT, multiplied by fDAC/InterpolationFactor, as follows:
BWSIGNAL = BWFILT × (fDAC/InterpolationFactor)
Filter Performance
DATA FORMAT
The input data format for all modes on the AD9163 is 16-bit,
twos complement. The digital datapath and the DAC decoder
operate in twos complement format.
To avoid the NCO frequency leakage, the digital codes fed into
the DAC must be balanced around zero code (number of
positive codes must be equal to the number of negative codes).
That is, input DC offset must be removed from the input digital
code. If not, the leakage can become apparent when using the
NCO to shift a signal that is above or below 0 Hz when
synthesized. The NCO frequency is seen as a small spur at the
NCO FTW.
The interpolation filters interpolate between existing data in
such a way that they minimize changes in the incoming data
while suppressing the creation of interpolation images. This
datapath is shown for each filter in Figure 108.
The usable bandwidth (as shown in Table 33) is defined as the
frequency band over which the filters have a pass-band ripple of
less than ±0.001 dB and an image rejection of greater than
85 dB. A conceptual drawing that shows the relative bandwidth
of each of the filters is shown in Figure 108. The maximum pass
band amplitude of all filters is the same; they are different in the
illustration to improve understanding.
Rev. D | Page 50 of 126
Data Sheet
AD9163
Filter Performance Beyond Specified Bandwidth
6×
8×
12×
16×
24×
FIR85
–1500
–1000
–500
0
500
1000
1500
FREQUENCY (MHz)
14415-105
FILTER RESPONSE
Some of the interpolation filters are specified to 0.4 × fDATA (with
a pass band). The filters can be used slightly beyond this ratio at
the expense of increased pass-band ripple and decreased
interpolation image rejection.
Figure 108. All Band Responses of Interpolation Filters
Table 33. Interpolation Modes and Usable Bandwidth
Interpolation Mode
6×
8×
12×
16×
24×
2× NRZ (Register 0x111, Bit 0 = 1)
INTERP_MODE, Register 0x110, Bits[3:0]
0x04
0x05
0x06
0x07
0x08
Any combination 2
Available Signal Bandwidth (BW)1
BW × fDATA/2
BW × fDATA/2
BW × fDATA/2
BW × fDATA/2
BW × fDATA/2
0.45 × fDAC 3
Maximum fDATA (MHz)
fDAC/6
fDAC/8
fDAC/12
fDAC/16
fDAC/24
fDAC (real) or fDAC/2
(complex)3
The data rate (fDATA) for all interpolator modes is a complex data rate, meaning each of I data and Q data run at that rate. Available signal bandwidth is the data rate
multiplied by the bandwidth of the initial 2× or 3× interpolator filters, which can be set to BW = 80% or BW = 90%. This bandwidth is centered at 0 Hz.
The 2× NRZ filter, FIR85, can be used with any of the interpolator combinations.
3
The bandwidth of the FIR85 filter is centered at 0 Hz.
1
2
Rev. D | Page 51 of 126
Data Sheet
90
0
20
70
–0.2
60
–0.3
50
–0.4
40
–0.5
30
–20
–80
–120
42
43
44
45
BANDWIDTH (% fDATA )
–160
0
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Figure 112. 3× Third-Band 80% Filter Response
20
0
–20
MAGNITUDE (dB)
Most of the filters are specified to 0.45 × fDATA (with pass band).
Figure 110 to Figure 117 show the filter response for each of the
interpolator filters on the AD9163.
0.2
NORMALIZED FREQUENCY (Rad/Sample)
Figure 109. Interpolation Filter Performance Beyond Specified Bandwidth for
the 80% Filters
Figure 109 shows the performance of the interpolation filters
beyond 0.4 × fDATA. The ripple increases much slower than the
image rejection decreases. This means that if the application can
tolerate degraded image rejection from the interpolation filters,
more bandwidth can be used.
0.1
14415-160
–140
–0.6
41
–60
–100
IMAGE REJECTION
PASS-BAND RIPPLE
20
40
–40
MAGNITUDE (dB)
–0.1
MAXIMUM PASS-BAND RIPPLE (dB)
0
80
14415-106
–40
–60
–80
–100
–120
20
–140
–160
MAGNITUDE (dB)
–20
0
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
NORMALIZED FREQUENCY (Rad/Sample)
–40
Figure 113. 3× Third-Band 90% Filter Response
–60
20
–80
0
–20
–140
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
NORMALIZED FREQUENCY (Rad/Sample)
14415-158
–120
MAGNITUDE (dB)
–100
–40
–60
–80
–100
Figure 110. First 2× Half-Band 80% Filter Response
–120
20
–140
0
–160
–20
MAGNITUDE (dB)
0.1
14415-161
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
NORMALIZED FREQUENCY (Rad/Sample)
–40
Figure 114. Second 2× Half-Band 45% Filter Response
–60
–80
–100
–140
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
NORMALIZED FREQUENCY (Rad/Sample)
1.0
14415-159
–120
Figure 111. First 2× Half-Band 90% Filter Response
Rev. D | Page 52 of 126
1.0
14415-162
MINIMUM INTERPOLATION IMAGE REJECTION (dB)
AD9163
Data Sheet
AD9163
DIGITAL MODULATION
20
The AD9163 has digital modulation features to modulate the
baseband quadrature signal to the desired DAC output
frequency.
0
MAGNITUDE (dB)
–20
–40
The AD9163 is equipped with several NCO modes. The default
NCO is a 48-bit, integer NCO. The A/B ratio of the dual
modulus NCO allows the output frequency to be synthesized
with very fine precision. NCO mode is selected as shown in
Table 34.
–60
–80
–100
–120
Table 34. Modulation Mode Selection
–160
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
14415-163
–140
1.0
0.9
NORMALIZED FREQUENCY (Rad/Sample)
Figure 115. Third 2× Half-Band 22.5% Filter Response
20
MAGNITUDE (dB)
0
–20
48-Bit Dual Modulus NCO
–40
This modulation mode uses an NCO, a phase shifter, and a
complex modulator to modulate the signal by a programmable
carrier signal as shown in Figure 118. This configuration allows
output signals to be placed anywhere in the output spectrum
with very fine frequency resolution.
–60
–80
–100
–140
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
NORMALIZED FREQUENCY (Rad/Sample)
14415-164
–120
Figure 116. Fourth 2× Half-Band 11.25% Filter Response
20
The NCO produces a quadrature carrier to translate the input
signal to a new center frequency. A quadrature carrier is a pair of
sinusoidal waveforms of the same frequency, offset 90° from
each other. The frequency of the quadrature carrier is set via a
FTW. The quadrature carrier is mixed with the I and Q data and
then summed into the I and Q datapaths, as shown in Figure 118.
Integer NCO Mode
0
The main 48-bit NCO can be used as an integer NCO by using
the following formula to create the frequency tuning word
(FTW):
–20
MAGNITUDE (dB)
Modulation Mode
None
48-Bit Integer NCO
48-Bit Dual Modulus NCO
Modulation Type
Register 0x111, Register 0x111,
Bit 6
Bit 2
0b0
0b0
0b1
0b0
0b1
0b1
–40
–60
−fDAC/2 ≤ fCARRIER < +fDAC/2
–80
FTW = (fCARRIER/fDAC) × 248
where FTW is a 48-bit, twos complement number.
–120
When in 2× NRZ mode (FIR85 enabled with Register 0x111,
Bit 0 = 1), the frequency tuning word is calculated as
–140
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
NORMALIZED FREQUENCY (Rad/Sample)
1.0
14415-165
–100
0 ≤ fCARRIER < fDAC
FTW = (fCARRIER/fDAC) × 248
Figure 117. FIR85 2× Half-Band 45% Filter Response
where FTW is a 48-bit binary number.
This method of calculation causes fCARRIER values in the second
Nyquist zone to appear to move to fDAC − fCARRIER when flipping
the FIR85 enable bit and not changing the FTW to account for
the change in number format.
Rev. D | Page 53 of 126
AD9163
Data Sheet
require exact rational frequency synthesis. The underlying
function of the programmable modulus technique is to alter the
accumulator modulus.
The intended effect is that a sweep of the NCO from 0 Hz to
fDAC − fDAC/248 appears seamless when the FIR85 enable bit is set
to Register 0x111, Bit 0 = 0b1 prior to fCARRIER/fDAC = 0.5. As can
be seen from examination, the FTWs from 0 to less than fDAC/2
mean the same in either case, but they mean different fCARRIER
values from fDAC/2 to fDAC − fDAC/248. This effect must be considered
when constructing FTW values and using the 2× NRZ mode.
Implementation of the programmable modulus function within
the AD9163 is such that the fraction, M/N, is expressible per
Equation 1. Note that the form of the equation implies a
compound frequency tuning word with X representing the
integer part and A/B representing the fractional part.
The frequency tuning word is set as shown in Table 35.
A
X+
f CARRIER
M
B
=
=
2 48
f DAC
N
Table 35. NCO FTW Registers
Address
0x114
0x115
0x116
0x117
0x118
0x119
Value
FTW[7:0]
FTW[15:8]
FTW[23:16]
FTW[31:24]
FTW[39:32]
FTW[47:40]
Description
8 LSBs of FTW
Next 8 bits of FTW
Next 8 bits of FTW
Next 8 bits of FTW
Next 8 bits of FTW
8 MSBs of FTW
where:
X is programmed in Register 0x114 to Register 0x119.
A is programmed in Register 0x12A to Register 0x12F.
B is programmed in Register 0x124 to Register 0x129.
Programmable Modulus Example
Unlike other registers, the FTW registers are not updated immediately upon writing. Instead, the FTW registers update on the
rising edge of FTW_LOAD_REQ (Register 0x113, Bit 0). After
an update request, FTW_LOAD_ACK (Register 0x113, Bit 1) must
be high to acknowledge that the FTW has updated.
The SEL_SIDEBAND bit (Register 0x111, Bit 1 = 0b1) is a convenience bit that can be set to use the lower sideband modulation
result, which is equivalent to flipping the sign of the FTW.
I DATA
COS(ωn + θ)
ω
π
NCO
θ
SIN(ωn + θ)
OUT_I
OUT_Q
–
+
–1
Q DATA
0
INTERPOLATION
M/N = 250,000,000/2,500,000,000 = 1/10
Therefore, M = 1 and N = 10.
NCO Reset
1
14415-108
SEL_SIDEBAND
Consider the case in which fDAC = 2500 MHz and the desired
value of fCARRIER is 250 MHz. This scenario synthesizes an output
frequency that is not a power of two submultiple of the sample
rate, namely fCARRIER = (1/10) fDAC, which is not possible with a
typical accumulator-based DDS. The frequency ratio, fCARRIER/fDAC,
leads directly to M and N, which are determined by reducing
the fraction (250,000,000/2,500,000,000) to its lowest terms, that is,
After calculation, X = 28147497671065, A = 3, and B = 5.
Programming these values into the registers for X, A, and B (X
is programmed in Register 0x114 to Register 0x119, B is
programmed in Register 0x124 to Register 0x129, and A is
programmed in Register 0x12A to Register 0x12F) causes the
NCO to produce an output frequency of exactly 250 MHz given
a 2500 MHz sampling clock. For more details, refer to the AN-953
Application Note on the Analog Devices, Inc., website.
INTERPOLATION
FTW[47:0]
NCO_PHASE_OFFSET
[15:0]
(1)
Figure 118. NCO Modulator Block Diagram
Modulus NCO Mode
The main 48-bit NCO can also be used in a dual modulus mode
to create fractional frequencies beyond the 48-bit accuracy. The
modulus mode is enabled by programming the MODULUS_EN
bit in the DATAPATH_CFG register to 1 (Register 0x111, Bit 2 =
0b1).
The frequency ratio for the programmable modulus direct
digital synthesis (DDS) is very similar to that of the typical
accumulator-based DDS. The only difference is that N is not
required to be a power of two for the programmable modulus,
but can be an arbitrary integer. In practice, hardware constraints
place limits on the range of values for N. As a result, the
modulus extends the use of the NCO to applications that
Resetting the NCO can be useful when determining the start time
and phase of the NCO. The NCO can be reset by several different methods, including a SPI write, using the TX_ENABLE pin,
or by the SYSREF± signal. Due to internal timing variations
from device to device, these methods achieve an accuracy of
±6 DAC clock cycles.
Program Register 0x800, Bits[7:6] to 0b01 to set the NCO in
phase discontinuous switching mode via a write to the SPI port.
Then, any time the frequency tuning word is updated, the NCO
phase accumulator resets and the NCO begins counting at the
new FTW.
Rev. D | Page 54 of 126
Data Sheet
AD9163
Changing the NCO Frequency
1
The FTW_REQ_MODE bits can be configured to use any of the
FTW words as the automatic update trigger word. This configuration provides convenience when choosing the order in which to
program the FTW registers.
The speed of the SPI port write function is guaranteed, and is a
minimum of 100 MHz (see Table 4). Thus, the NCO FTW can
be updated in as little as 240 ns with a one register write in
automatic update mode.
The NCO only supports phase noncontinuous mode. In this
mode, the phase accumulator is reset by updating the frequency
tuning word of the NCO, making an instantaneous jump to the
new frequency.
INVERSE SINC
The AD9163 provides a digital inverse sinc filter to compensate
the DAC roll-off over frequency. The filter is enabled by setting
the INVSINC_EN bit (Register 0x111, Bit 7) and is disabled by
default.
The inverse sinc (sinc−1) filter is a seven-tap FIR filter. Figure 119
shows the frequency response of sin(x)/x roll-off, the inverse
sinc filter, and the composite response. The composite response
has less than ±0.05 dB pass-band ripple up to a frequency of
0.4 × fDACCLK. When 2× NRZ mode is enabled, the inverse sinc
filter operates to 0.4 × f2×DACCLK.
To provide the necessary peaking at the upper end of the pass
band, the inverse sinc filter shown has an intrinsic insertion loss of
about 3.8 dB.
–1
–2
–3
–4
–5
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
FREQUENCY (× fDAC )
14415-109
To set the automatic FTW update mode, write the appropriate
word to the FTW_REQ_MODE bits (Register 0x113, Bits[6:4]),
choosing the particular FTW word that causes the automatic
update. For example, if relatively coarse frequency steps are
needed, it may be sufficient to write a single word to the MSB
byte of the FTW, and therefore the FTW_REQ_MODE bits can
be programmed to 110 (Register 0x113, Bits[6:4] = 0b110).
Then, each time the most significant byte, FTW5, is written, the
NCO FTW is automatically updated.
SIN(x)/x ROLL-OFF
SINC–1 FILTER RESPONSE
COMPOSITE RESPONSE
0
MAGNITUDE (dB)
In the 48-bit NCO, the mode of updating the frequency tuning
word can be changed from requiring a write to the FTW_LOAD_
REQ bit (Register 0x113, Bit 0) to an automatic update mode. In
the automatic update mode, the FTW is updated as soon as the
chosen FTW word is written.
Figure 119. Responses of Sin(x)/x Roll-Off, the Sinc−1 Filter, and the
Composite of the Two
DOWNSTREAM PROTECTION
The AD9163 has several features designed to protect the power
amplifier (PA) of the system, as well as other downstream
blocks. They consist of a control signal from the LMFC sync
logic and a transmit enable function. The protection mechanism
in each case is the blanking of data that is passed to the DAC
decoder. The differences lie in the location in the datapath and
slight variations of functionality.
The JESD204B serial link has several flags and quality measures
to indicate the serial link is up and running error free. If any of
these measures flags an issue, a signal from the LMFC sync logic is
sent to a mux that stops data from flowing to the DAC decoder
and replaces it with 0s.
There are several transmit enable features, including a TX_
ENABLE register that can be used to squelch data at several
points in the datapath or configure the TX_ENABLE pin to do
likewise.
Transmit Enable
The transmit enable feature can be configured either as a SPI
controlled function or a pin controlled function. It can be used
for several different purposes. The SPI controlled function has
less accurate timing due to its reliance on a microcontroller to
program it; therefore, it is typically used as a preventative measure
at power-up or when configuring the device.
The SPI controlled TX_ENABLE function can be used to zero
the input to the digital datapath or to zero the output from the
digital datapath, as shown in Figure 120. If the input to the
digital datapath is zeroed, any filtering that is selected filters the
0 signal, causing a gradual ramp-down of energy in the digital
datapath. If the digital datapath is bypassed, as in 1÷ mode, the
data at the input to the DAC immediately drops to zero.
Rev. D | Page 55 of 126
AD9163
Data Sheet
The TX_ENABLE pin can be used for more accurate timing
when enabling or disabling the DAC output. The effect of the
TX_ENABLE pin can be configured by the same TX_ENABLE
register (Register 0x03F) as is used for the SPI controlled functions, and it can be made to have the same effects as the SPI
controlled function, namely to zero the input to the digital
datapath or to zero the output from the digital datapath. In
addition, the TX_ENABLE pin can also be configured to ramp
down (or up) the full-scale current of the DAC. The ramp down
reduces the output power of the DAC by about 20 dB from full
scale to the minimum output current.
The TX_ENABLE pin can also be programmed to reset the
NCO phase accumulator. See Table 36 for a description of the
settings available for the TX_ENABLE function.
Table 36. TX_ENABLE Settings
Register
0x03F
Bit 7
Bit 6
Setting
0
1
0
1
Bits[5:4]
Bit 3
Bit 2
Bit 1
N/A1
0
1
0
1
0
1
Bit 0
0
1
1
N/A means not applicable.
Description
SPI control: zero data to the DAC
SPI control: allow data to pass to the
DAC
SPI control: zero data at input to the
datapath
SPI control: allow data to enter the
datapath
Reserved
Use SPI writes to reset the NCO
Use TX_ENABLE to reset the NCO
Use SPI control to zero data to the DAC
Use TX_ENABLE pin to zero data to the
DAC
Use SPI control to zero data at the input
to the datapath
Use TX_ENABLE pin to zero data at
input to the datapath
Use SPI registers to control the full-scale
current
Use TX_ENABLE pin to control the fullscale current
DATAPATH PRBS
The datapath PRBS can verify the AD9163 datapath receives
and correctly decodes data. The datapath PRBS verifies the
JESD204B parameters of the transmitter and receiver match, the
lanes of the receiver are mapped appropriately, the lanes are
appropriately inverted, and, if necessary, the start-up routine is
correctly implemented.
To run the datapath PRBS test, complete the following steps:
1.
Set up the device in the desired operating mode using the
start-up sequence.
2. Send PRBS7 or PRBS15 data.
3. Write Register 0x14, Bit 2 = 0 for PRBS7 or 1 for PRBS15.
4. Write Register 0x14B, Bits[1:0] = 0b11 to enable and reset
the PRBS test.
5. Write Register 0x14B, Bits[1:0] = 0b01 to enable the PRBS
test and release reset.
6. Wait 500 ms.
7. Check the status of the PRBS by checking the IRQ for the I
and Q path PRBS as described in the Datapath PRBS IRQ
section.
8. Read Register 0x14B, Bits [7:6]. Bit 6 is 0 if the I channel
has any errors. Bit 7 is 0 if the Q channel has any errors.
9. Read Register 0x14C to read the error count for the I channel.
10. Read Register 0x14D to read the error count for the Q
channel. The PRBS processes 32 bits at a time, and
compares the 32 new bits to the previous set of 32 bits. It
detects and reports only 1 error in every group of 32 bits;
therefore, the error count partly depends on when the
errors are seen.
For example, see the following sequence:
•
•
•
Bits: 32 good, 31 good, 1 bad; 32 good [2 errors]
Bits: 32 good, 22 good, 10 bad; 32 good [2 errors]
Bits: 32 good, 31 good, 1 bad; 31 good, 1 bad; 32 good
[3 errors]
DATAPATH PRBS IRQ
The PRBS fail signals for the I and Q path are available as IRQ
events. Use Register 0x020, Bits [1:0] to enable the fail signals,
and then use Register 0x024, Bits [1:0] to read back the status
and reset the IRQ signals. See the Interrupt Request Operation
section for more information.
Rev. D | Page 56 of 126
Data Sheet
AD9163
DATA
TO DAC
0
0
MAIN
DIGITAL
PATH
0
FROM LMFC
SYNC LOGIC
FROM REG
0x03F[7]
FROM REG
0x03F[6]
FROM REG
0x03F[2]
FROM REG
0x03F[1]
Figure 120. Downstream Protection Block Diagram
Rev. D | Page 57 of 126
14415-110
TX_ENABLE
TX_ENABLE
AD9163
Data Sheet
INTERRUPT REQUEST OPERATION
The AD9163 provides an interrupt request output signal (IRQ)
on Ball G4 that can be used to notify an external host processor
of significant device events. On assertion of the interrupt, query
the device to determine the precise event that occurred. The
IRQ pin is an open-drain, active low output. Pull the IRQ pin
high, external to the device. This pin can be tied to the interrupt
pins of other devices with open-drain outputs to wire; OR these
pins together.
Figure 121 shows a simplified block diagram of how the IRQ
blocks work. If IRQ_EN is low, the INTERRUPT_SOURCE
signal is set to 0. If IRQ_EN is high, any rising edge of EVENT
causes the INTERRUPT_SOURCE signal to be set high. If any
INTERRUPT_SOURCE signal is high, the IRQ pin is pulled
low. INTERRUPT_SOURCE can be reset to 0 by either an
IRQ_RESET signal or a DEVICE_RESET signal.
Depending on the STATUS_MODE signal, the EVENT_STATUS
bit reads back an event signal or INTERRUPT_SOURCE signal.
The AD9163 has several interrupt register blocks (IRQ) that can
monitor up to 75 events (depending on device configuration).
Certain details vary by IRQ register block as described in Table 37.
Table 38 shows the source registers of the IRQ_EN, IRQ_RESET,
and STATUS_MODE signals in Figure 121, as well as the address
where EVENT_STATUS is read back.
Table 37. IRQ Register Block Details
Register Block
0x020, 0x024
Event
Reported
Per chip
0x4B8 to 0x4BB; 0x470
to 0x473
Per link and
lane
EVENT_STATUS
INTERRUPT_SOURCE if
IRQ is enabled; if not, it
is the event signal
INTERRUPT_SOURCE if
IRQ is enabled; if not, 0
INTERRUPT SERVICE ROUTINE
Interrupt request management starts by selecting the set of event
flags that require host intervention or monitoring. Enable the
events that require host action so that the host is notified when
they occur. For events requiring host intervention upon IRQ
activation, run the following routine to clear an interrupt request:
1.
2.
3.
4.
Read the status of the event flag bits that are being monitored.
Disable the interrupt by writing 0 to IRQ_EN.
Read the event source.
Perform any actions that may be required to clear the cause
of the event. In many cases, no specific actions may be
required.
Verify that the event source is functioning as expected.
Clear the interrupt by writing 1 to IRQ_RESET.
Enable the interrupt by writing 1 to IRQ_EN.
5.
6.
7.
0
1
EVENT_STATUS
STATUS_MODE
IRQ
IRQ_EN
EVENT
INTERRUPT_SOURCE
0
1
IRQ_EN
OTHER
INTERRUPT
SOURCES
IRQ_RESET
14415-111
DEVICE_RESET
Figure 121. Simplified Schematic of IRQ Circuitry
Table 38. IRQ Register Block Address of IRQ Signal Details
Register Block
0x020, 0x024
0x4B8 to 0x4BB
0x470 to 0x473
1
2
IRQ_EN
0x020; R/W per chip
0x4B8, 0x4B9; W per error type
0x470 to 0x473; W per error type
Address of IRQ Signals 1
IRQ_RESET
STATUS_MODE 2
0x024; W per chip
STATUS_MODE = IRQ_EN
0x4BA, 0x4BB; W per error type N/A, STATUS_MODE = 1
0x470 to 0x473; W per link
N/A, STATUS_MODE = 1
R is read; W is write; and R/W is read/write.
N/A means not applicable.
Rev. D | Page 58 of 126
EVENT_STATUS
0x024; R per chip
0x4BA, 0x4BB; R per chip
0x470 to 0x473; R per link
Data Sheet
AD9163
APPLICATIONS INFORMATION
HARDWARE CONSIDERATIONS
Power Sequencing
Power Supply Recommendations
The AD9163 requires power sequencing to avoid damage to the
DAC. A board design with the AD9163 must include a power
sequencer chip, such as the ADM1184, to ensure that the
domains power up in the correct order. The ADM1184 monitors
the level of power domains upon power-up. It sends an enable
signal to the next grouping of power domains. When all power
domains are powered up, a power-good signal is sent to the
system controller to indicate all power supplies are powered up.
All the AD9163 supply domains must remain as noise free as
possible for the best operation. Power supply noise has a
frequency component that affects performance, and is specified in
volts rms terms.
An LC filter on the output of the power supply is recommended
to attenuate the noise, and must be placed as close to the AD9163
as possible. The VDD12_CLK supply is the most noise sensitive
supply on the device, followed by the VDD25_DAC and
VNEG_N1P2 supplies, which are the DAC output rails. It is
highly recommended that the VDD12_CLK be supplied by
itself with an ultralow noise regulator such as the ADM7154 or
ADP1761 to achieve the best phase noise performance possible.
Noisier regulators impose phase noise onto the DAC output.
The VDD12A supply can be connected to the digital DVDD
supply with a separate filter network. All of the SERDES 1.2 V
supplies can be connected to one regulator with separate filter
networks. The IOVDD supply can be connected to the VDD25_
DAC supply with a separate filter network, or can be powered
from a system controller (for example, a microcontroller), 1.8 V
to 3.3 V supply. The power supply sequencing requirement
must be met; therefore, a switch or other solution must be used
when connected to the IOVDD supply with VDD25_DAC.
Take note of the maximum power consumption numbers given
in Table 3 to ensure the power supply design can tolerate temperature and IC process variation extremes. The amount of current
drawn is dependent on the chosen use cases, and specifications
are provided for several use cases to illustrate examples and
contributions from individual blocks, and to assist in calculating
the maximum required current per supply.
Another consideration for the power supply design is peak
current handling capability. The AD9163 draws more current in
the main digital supply when synthesizing a signal with
significant amplitude variations, such as a modulated signal, as
compared to when in idle mode or synthesizing a dc signal.
Therefore, the power supply must be able to supply current
quickly to accommodate burst signals such as GSM, TDMA, or
other signals that have an on/off time domain response. Because
the amount of current variation depends on the signals used, it
is best to perform lab testing first to establish ranges. A typical
difference can be several hundred milliamperes.
The IOVDD, VDD12A, VDD12_CLK, and DVDD domains
must be powered up first. Then, the VNEG_N1P2, VDD_1P2,
PLL_CLK_VDD12, DVDD_1P2, and SYNC_VDD_3P3 can be
powered up. The VDD25_DAC domain must be powered up
last. There is no requirement for a power-down sequence.
Power and Ground Planes
Solid ground planes are recommended to avoid ground loops
and to provide a solid, uninterrupted ground reference for the
high speed transmission lines that require controlled impedances.
It is recommended that power planes be stacked between
ground layers for high frequency filtering. Doing so adds extra
filtering and isolation between power supply domains in
addition to the decoupling capacitors.
Do not use segmented power planes as a reference for controlled
impedances unless the entire length of the controlled impedance
trace traverses across only a single segmented plane. These and
additional guidelines for the topology of high speed transmission
lines are described in the JESD204B Serial Interface Inputs
(SERDIN0± to SERDIN7±) section.
For some applications, where highest performance and higher
output frequencies are required, the choice of PCB materials
significantly impacts results. For example, materials such as
polyimide or materials from the Rogers Corporation can be
used, for example, to improve tolerance to high temperatures
and improve performance. Rogers 4350 material is used for the
top three layers in some of the evaluation board designs:
between the top signal layer and the ground layer below it,
between the ground layer and an internal signal layer, and
between that signal layer and another ground layer.
JESD204B Serial Interface Inputs (SERDIN0± to
SERDIN7±)
When considering the layout of the JESD204B serial interface
transmission lines, there are many factors to consider to
maintain optimal link performance. Among these factors are
insertion loss, return loss, signal skew, and the topology of the
differential traces.
Rev. D | Page 59 of 126
AD9163
Data Sheet
The JESD204B specification limits the amount of insertion loss
allowed in the transmission channel (see Figure 93). The AD9163
equalization circuitry allows significantly more loss in the channel
than is required by the JESD204B specification. It is still important
that the designer of the PCB minimize the amount of insertion
loss by adhering to the following guidelines:
•
•
•
Keep the differential traces short by placing the AD9163 as
near the transmitting logic device as possible and routing
the trace as directly as possible between the devices.
Route the differential pairs on a single plane using a solid
ground plane as a reference. It is recommended to route the
SERDES lanes on the same layer as the AD9163 to avoid vias
being used in the SERDES lanes.
Use a PCB material with a low dielectric constant ( 6 Gbps.
[4:3] RESERVED
Reserved.
0x0
R/W
[2:1] SPI_DIVISION_RATE
Enables oversampling of the input 0x0
data.
R/W
00 No division. Data rate > 3 Gbps.
01 Division by 2. 1.5 Gbps < data rate
≤ 3 Gbps.
10 Division by 4. 750 Mbps < data
rate ≤ 1.5 Gbps.
0
0x250 EQ_CONFIG_PHY_0_1
RESERVED
Reserved.
[7:4] SPI_EQ_CONFIG1
0x0
R/W
0x8
R/W
0x8
R/W
0000 Manual mode (SPI configured
values used).
0001 Boost level = 1.
0010 Boost level = 2.
0011 Boost level = 3.
0100 Boost level = 4.
0101 Boost level = 5.
0110 Boost level = 6.
0111 Boost level = 7.
1000 Boost level = 8.
1001 Boost level = 9.
1010 Boost level = 10.
1011 Boost level = 11.
1100 Boost level = 12.
1101 Boost level = 13.
1110 Boost level = 14.
1111 Boost level = 15.
[3:0] SPI_EQ_CONFIG0
0000 Manual mode (SPI configured
values used).
0001 Boost level = 1.
0010 Boost level = 2.
0011 Boost level = 3.
0100 Boost level = 4.
0101 Boost level = 5.
0110 Boost level = 6.
0111 Boost level = 7.
1000 Boost level = 8.
Rev. D | Page 86 of 126
Data Sheet
Hex.
Addr.
Name
AD9163
Bits Bit Name
Settings
Description
Reset Access
1001 Boost level = 9.
1010 Boost level = 10.
1011 Boost level = 11.
1100 Boost level = 12.
1101 Boost level = 13.
1110 Boost level = 14.
1111 Boost level = 15.
0x251 EQ_CONFIG_PHY_2_3
[7:4] SPI_EQ_CONFIG3
0x8
R/W
0x8
R/W
0x8
R/W
0000 Manual mode (SPI configured
values used).
0001 Boost level = 1.
0010 Boost level = 2.
0011 Boost level = 3.
0100 Boost level = 4.
0101 Boost level = 5.
0110 Boost level = 6.
0111 Boost level = 7.
1000 Boost level = 8.
1001 Boost level = 9.
1010 Boost level = 10.
1011 Boost level = 11.
1100 Boost level = 12.
1101 Boost level = 13.
1110 Boost level = 14.
1111 Boost level = 15.
[3:0] SPI_EQ_CONFIG2
0000 Manual mode (SPI configured
values used).
0001 Boost level = 1.
0010 Boost level = 2.
0011 Boost level = 3.
0100 Boost level = 4.
0101 Boost level = 5.
0110 Boost level = 6.
0111 Boost level = 7.
1000 Boost level = 8.
1001 Boost level = 9.
1010 Boost level = 10.
1011 Boost level = 11.
1100 Boost level = 12.
1101 Boost Level = 13.
1110 Boost level = 14.
1111 Boost level = 15.
0x252 EQ_CONFIG_PHY_4_5
[7:4] SPI_EQ_CONFIG5
0000 Manual mode (SPI configured
values used).
0001 Boost level = 1.
0010 Boost level = 2.
0011 Boost level = 3.
0100 Boost level = 4.
0101 Boost level = 5.
0110 Boost level = 6.
0111 Boost level = 7.
1000 Boost level = 8.
Rev. D | Page 87 of 126
AD9163
Hex.
Addr.
Name
Data Sheet
Bits Bit Name
Settings
Description
Reset Access
1001 Boost level = 9.
1010 Boost level = 10.
1011 Boost level = 11.
1100 Boost level = 12.
1101 Boost level = 13.
1110 Boost level = 14.
1111 Boost level = 15.
[3:0] SPI_EQ_CONFIG4
0x8
R/W
0x8
R/W
0x8
R/W
0000 Manual mode (SPI configured
values used).
0001 Boost level = 1.
0010 Boost level = 2.
0011 Boost level = 3.
0100 Boost level = 4.
0101 Boost level = 5.
0110 Boost level = 6.
0111 Boost level = 7.
1000 Boost level = 8.
1001 Boost level = 9.
1010 Boost level = 10.
1011 Boost level = 11.
1100 Boost level = 12.
1101 Boost level = 13.
1110 Boost level = 14.
1111 Boost level = 15.
0x253 EQ_CONFIG_PHY_6_7
[7:4] SPI_EQ_CONFIG7
0000 Manual mode (SPI configured
values used).
0001 Boost level = 1.
0010 Boost level = 2.
0011 Boost level = 3.
0100 Boost level = 4.
0101 Boost level = 5.
0110 Boost level = 6.
0111 Boost level = 7.
1000 Boost level = 8.
1001 Boost level = 9.
1010 Boost level = 10.
1011 Boost level = 11.
1100 Boost level = 12.
1101 Boost level = 13.
1110 Boost level = 14.
1111 Boost level = 15.
[3:0] SPI_EQ_CONFIG6
0000 Manual mode (SPI configured
values used).
0001 Boost level = 1.
0010 Boost level = 2.
0011 Boost level = 3.
0100 Boost level = 4.
0101 Boost level = 5.
0110 Boost level = 6.
0111 Boost level = 7.
1000 Boost level = 8.
Rev. D | Page 88 of 126
Data Sheet
Hex.
Addr.
Name
AD9163
Bits Bit Name
Settings
Description
Reset Access
1001 Boost level = 9.
1010 Boost level = 10.
1011 Boost level = 11.
1100 Boost level = 12.
1101 Boost level = 13.
1110 Boost level = 14.
1111 Boost level = 15.
0x268 EQ_BIAS_REG
[7:6] EQ_POWER_MODE
Controls the equalizer power
mode/insertion loss capability.
0x1
R/W
00 Normal mode.
01 Low power mode.
0x280 SYNTH_ENABLE_CNTRL
0x281 PLL_STATUS
[5:0] RESERVED
Reserved.
0x4
R/W
[7:3] RESERVED
Reserved.
0x0
R
2
SPI_RECAL_SYNTH
Set this bit high to rerun all of the
0x0
SERDES PLL calibration routines. Set
this bit low again to allow additional
recalibrations. Rising edge causes
the calibration.
R/W
1
RESERVED
Reserved.
0x0
R/W
0
SPI_ENABLE_SYNTH
Enable the SERDES PLL. Setting this
bit turns on all currents and
proceeds to calibrate the PLL. Make
sure reference clock and division
ratios are correct before enabling
this bit.
0x0
R/W
[7:6] RESERVED
Reserved.
0x0
R
5
If set, the SERDES PLL CP output is 0x0
above valid operating range.
R
SPI_CP_OVER_RANGE_HIGH_RB
0 Charge pump output is within
operating range.
1 Charge pump output is above
operating range.
4
SPI_CP_OVER_RANGE_LOW_RB
If set, the SERDES PLL CP output is 0x0
below valid operating range.
R
0 Charge pump output is within
operating range.
1 Charge pump output is below
operating range.
3
SPI_CP_CAL_VALID_RB
This bit tells the user if the charge
pump calibration has completed
and is valid.
0x0
R
0 Charge pump calibration is not
valid.
1 Charge pump calibration is valid.
[2:1] RESERVED
Reserved.
0x0
R
0
If set, the SERDES synthesizer
locked.
0x0
R
SPI_PLL_LOCK_RB
0 PLL is not locked.
1 PLL is locked.
0x289 REF_CLK_DIVIDER_LDO
[7:2] RESERVED
Reserved.
0x0
R
[1:0] SERDES_PLL_DIV_FACTOR
SERDES PLL reference clock
division factor. This field controls
the division of the SERDES PLL
reference clock before it is fed
into the SERDES PLL PFD. It must
be set so that fREF/DivFactor is
between 35 MHz and 80 MHz.
0x0
R/W
00 Divide by 4 for lane rate between
6 Gbps and 12.5 Gbps.
Rev. D | Page 89 of 126
AD9163
Hex.
Addr.
Name
Data Sheet
Bits Bit Name
Settings
Description
Reset Access
01 Divide by 2 for lane rate between
3 Gbps and 6 Gbps.
10 Divide by 1 for lane rate between
1.5 Gbps and 3 Gbps.
0x2A7 TERM_BLK1_CTRLREG0
0x2A8 TERM_BLK1_CTRLREG1
[7:1] RESERVED
Reserved.
0x0
R
0
Rising edge of this bit starts a
termination calibration routine.
0x0
R/W
SPI override for termination value
for PHY 0, PHY 1, PHY 6, and
PHY 7. Value options are as
follows:
0x0
R/W
SPI_I_TUNE_R_CAL_TERMBLK1
[7:0] SPI_I_SERIALIZER_RTRIM_TERMBLK1
XXX0XXXX Automatically calibrate
termination value.
XXX1000X Force 000 as termination value.
XXX1001X Force 001 as termination value.
XXX1010X Force 010 as termination value.
XXX1011X Force 011 as termination value.
XXX1100X Force 100 as termination value.
XXX1101X Force 101 as termination value.
XXX1110X Force 110 as termination value.
XXX1111X Force 111 as termination value.
XXX1000X Force 000 as termination value.
0x2AC TERM_BLK1_RD_REG0
0x2AE TERM_BLK2_CTRLREG0
0x2AF TERM_BLK2_CTRLREG1
[7:4] RESERVED
Reserved.
0x0
R
[3:0] SPI_O_RCAL_CODE_TERMBLK1
Readback of calibration code for
PHY 0, PHY 1, PHY 6, and PHY 7.
0x0
R
[7:1] RESERVED
Reserved.
0x0
R
0
Rising edge of this bit starts a
termination calibration routine.
0x0
R/W
SPI override for termination value
for PHY 2, PHY 3, PHY 4, and
PHY 5. Value options are as
follows:
0x0
R/W
SPI_I_TUNE_R_CAL_TERMBLK2
[7:0] SPI_I_SERIALIZER_RTRIM_TERMBLK2
XXX0XXXX Automatically calibrate
termination value.
XXX1000X Force 000 as termination value.
XXX1001X Force 001 as termination value.
XXX1010X Force 010 as termination value.
XXX1011X Force 011 as termination value.
XXX1100X Force 100 as termination value.
XXX1101X Force 101 as termination value.
XXX1110X Force 110 as termination value.
XXX1111X Force 111 as termination value.
XXX1000X Force 000 as termination value.
0x2B3 TERM_BLK2_RD_REG0
0x2BB TERM_OFFSET_0
0x2BC TERM_OFFSET_1
[7:4] RESERVED
Reserved.
0x0
R
[3:0] SPI_O_RCAL_CODE_TERMBLK2
Readback of calibration code for
PHY 2, PHY 3, PHY 4, and PHY 5.
0x0
R
[7:4] RESERVED
Reserved.
0x0
R
[3:0] TERM_OFFSET_0
Add or subtract from the
termination calibration value of
Physical Lane 0. 4-bit signed
magnitude value that adds to or
subtracts from the termination
value. Bit 3 is the sign bit, and
Bits[2:0] are the magnitude bits.
0x0
R/W
[7:4] RESERVED
Reserved.
0x0
R
Rev. D | Page 90 of 126
Data Sheet
Hex.
Addr.
Name
0x2BD TERM_OFFSET_2
0x2BE TERM_OFFSET_3
0x2BF TERM_OFFSET_4
0x2C0 TERM_OFFSET_5
0x2C1 TERM_OFFSET_6
0x2C2 TERM_OFFSET_7
0x300 GENERAL_JRX_CTRL_0
AD9163
Bits Bit Name
Description
Reset Access
[3:0] TERM_OFFSET_1
Settings
Add or subtract from the
termination calibration value of
Physical Lane 1. 4-bit signed
magnitude value that adds to or
subtracts from the termination
value. Bit 3 is the sign bit, and
Bits[2:0] are the magnitude bits.
0x0
R/W
[7:4] RESERVED
Reserved.
0x0
R
[3:0] TERM_OFFSET_2
Add or subtract from the
termination calibration value of
Physical Lane 2. 4-bit signed
magnitude value that adds to or
subtracts from the termination
value. Bit 3 is the sign bit, and
Bits[2:0] are the magnitude bits.
0x0
R/W
[7:4] RESERVED
Reserved.
0x0
R
[3:0] TERM_OFFSET_3
Add or subtract from the
termination calibration value of
Physical Lane 3. 4-bit signed
magnitude value that adds to or
subtracts from the termination
value. Bit 3 is the sign bit, and
Bits[2:0] are the magnitude bits.
0x0
R/W
[7:4] RESERVED
Reserved.
0x0
R
[3:0] TERM_OFFSET_4
Add or subtract from the
termination calibration value of
Physical Lane 4. 4-bit signed
magnitude value that adds to or
subtracts from the termination
value. Bit 3 is the sign bit, and
Bits[2:0] are the magnitude bits.
0x0
R/W
[7:4] RESERVED
Reserved.
0x0
R
[3:0] TERM_OFFSET_5
Add or subtract from the
termination calibration value of
Physical Lane 5. 4-bit signed
magnitude value that adds to or
subtracts from the termination
value. Bit 3 is the sign bit, and
Bits[2:0] are the magnitude bits.
0x0
R/W
[7:4] RESERVED
Reserved.
0x0
R
[3:0] TERM_OFFSET_6
Add or subtract from the
termination calibration value of
Physical Lane 6. 4-bit signed
magnitude value that adds to or
subtracts from the termination
value. Bit 3 is the sign bit, and
Bits[2:0] are the magnitude bits.
0x0
R/W
[7:4] RESERVED
Reserved.
0x0
R
[3:0] TERM_OFFSET_7
Add or subtract from the
termination calibration value of
Physical Lane 7. 4-bit signed
magnitude value that adds to or
subtracts from the termination
value. Bit 3 is the sign bit, and
Bits[2:0] are the magnitude bits.
0x0
R/W
7
RESERVED
Reserved.
0x0
R
6
CHECKSUM_MODE
JESD204B link parameter
checksum calculation method.
0x0
R/W
0x0
R
0 Checksum is sum of fields.
1 Checksum is sum of octets.
[5:1] RESERVED
Reserved.
Rev. D | Page 91 of 126
AD9163
Hex.
Addr.
Name
Data Sheet
Bits Bit Name
Description
Reset Access
This bit brings up the JESD204B
receiver when all link parameters
are programmed and all clocks
are ready.
0x0
R/W
[7:5] RESERVED
Reserved.
0x0
R
[4:0] DYN_LINK_LATENCY_0
Measurement of the JESD204B
link delay (in PCLK units). Link 0
dynamic link latency. Latency
between current deframer LMFC
and the global LMFC.
0x0
R
[7:5] RESERVED
Reserved.
0x0
R
[4:0] LMFC_DELAY_0
Fixed part of the JESD204B link
0x0
delay (in PCLK units). Delay in frame
clock cycles for global LMFC for Link
0.
R/W
[7:5] RESERVED
Reserved.
0x0
R
[4:0] LMFC_VAR_0
Variable part of the JESD204B link
delay (in PCLK units). Location in Rx
LMFC where JESD204B words are
read out from buffer. This setting
must not be more than 10 PCLKs.
0x1F
R/W
[7:6] RESERVED
Reserved.
0x0
R
[5:3] SRC_LANE1
Select data from SERDIN0±,
SERDIN1±, …, or SERDIN7± for
Logic Lane 1.
0x1
R/W
0x0
R/W
0
0x302 DYN_LINK_LATENCY_0
0x304 LMFC_DELAY_0
0x306 LMFC_VAR_0
0x308 XBAR_LN_0_1
Settings
LINK_EN
000 Data is from SERDIN0±.
001 Data is from SERDIN1±.
010 Data is from SERDIN2±.
011 Data is from SERDIN3±.
100 Data is from SERDIN4±.
101 Data is from SERDIN5±.
110 Data is from SERDIN6±.
111 Data is from SERDIN7±.
[2:0] SRC_LANE0
Select data from SERDIN0±,
SERDIN1±, …, or SERDIN7± for
Logic Lane 0.
000 Data is from SERDIN0±.
001 Data is from SERDIN1±.
010 Data is from SERDIN2±.
011 Data is from SERDIN3±.
100 Data is from SERDIN4±.
101 Data is from SERDIN5±.
110 Data is from SERDIN6±.
111 Data is from SERDIN7±.
0x309 XBAR_LN_2_3
[7:6] RESERVED
Reserved.
0x0
R
[5:3] SRC_LANE3
Select data from SERDIN0±,
SERDIN1±, …, or SERDIN7± for
Logic Lane 3.
0x3
R/W
000 Data is from SERDIN0±.
001 Data is from SERDIN1±.
010 Data is from SERDIN2±.
011 Data is from SERDIN3±.
100 Data is from SERDIN4±.
101 Data is from SERDIN5±.
110 Data is from SERDIN6±.
111 Data is from SERDIN7±.
Rev. D | Page 92 of 126
Data Sheet
Hex.
Addr.
Name
AD9163
Bits Bit Name
Settings
[2:0] SRC_LANE2
Description
Reset Access
Select data from SERDIN0±,
SERDIN1±, …, or SERDIN7± for
Logic Lane 2.
0x2
R/W
000 Data is from SERDIN0±.
001 Data is from SERDIN1±.
010 Data is from SERDIN2±.
011 Data is from SERDIN3±.
100 Data is from SERDIN4±.
101 Data is from SERDIN5±.
110 Data is from SERDIN6±.
111 Data is from SERDIN7±.
0x30A XBAR_LN_4_5
[7:6] RESERVED
Reserved.
0x0
R
[5:3] SRC_LANE5
Select data from SERDIN0±,
SERDIN1±, …, or SERDIN7± for
Logic Lane 5.
0x5
R/W
0x4
R/W
000 Data is from SERDIN0±.
001 Data is from SERDIN1±.
010 Data is from SERDIN2±.
011 Data is from SERDIN3±.
100 Data is from SERDIN4±.
101 Data is from SERDIN5±.
110 Data is from SERDIN6±.
111 Data is from SERDIN7±.
[2:0] SRC_LANE4
Select data from SERDIN0±,
SERDIN1±, …, or SERDIN7± for
Logic Lane 4.
000 Data is from SERDIN0±.
001 Data is from SERDIN1±.
010 Data is from SERDIN2±.
011 Data is from SERDIN3±.
100 Data is from SERDIN4±.
101 Data is from SERDIN5±.
110 Data is from SERDIN6±.
111 Data is from SERDIN7±.
0x30B XBAR_LN_6_7
[7:6] RESERVED
Reserved.
0x0
R
[5:3] SRC_LANE7
Select data from SERDIN0±,
SERDIN1±, …, or SERDIN7± for
Logic Lane 7.
0x7
R/W
0x6
R/W
000 Data is from SERDIN0±.
001 Data is from SERDIN1±.
010 Data is from SERDIN2±.
011 Data is from SERDIN3±.
100 Data is from SERDIN4±.
101 Data is from SERDIN5±.
110 Data is from SERDIN6±.
111 Data is from SERDIN7±.
[2:0] SRC_LANE6
Select data from SERDIN0±,
SERDIN1±, …, or SERDIN7± for
Logic Lane 6.
000 Data is from SERDIN0±.
001 Data is from SERDIN1±.
010 Data is from SERDIN2±.
011 Data is from SERDIN3±.
100 Data is from SERDIN4±.
101 Data is from SERDIN5±.
Rev. D | Page 93 of 126
AD9163
Hex.
Addr.
Name
Data Sheet
Bits Bit Name
Settings
Description
Reset Access
110 Data is from SERDIN6±.
111 Data is from SERDIN7±.
0x30C FIFO_STATUS_REG_0
[7:0] LANE_FIFO_FULL
Bit 0 corresponds to FIFO full flag
for data from SERDIN0±.
0x0
R
0x0
R
Bit 1 corresponds to FIFO full flag
for data from SERDIN1±.
Bit 2 corresponds to FIFO full flag
for data from SERDIN2±.
Bit 3 corresponds to FIFO full flag
for data from SERDIN3±.
Bit 4 corresponds to FIFO full flag
for data from SERDIN4±.
Bit 5 corresponds to FIFO full flag
for data from SERDIN5±.
Bit 6 corresponds to FIFO full flag
for data from SERDIN6±.
Bit 7 corresponds to FIFO full flag
for data from SERDIN7±.
0x30D FIFO_STATUS_REG_1
[7:0] LANE_FIFO_EMPTY
Bit 0 corresponds to FIFO empty
flag for data from SERDIN0±.
Bit 1 corresponds to FIFO empty
flag for data from SERDIN1±.
Bit 2 corresponds to FIFO empty
flag for data from SERDIN2±.
Bit 3 corresponds to FIFO empty
flag for data from SERDIN3±.
Bit 4 corresponds to FIFO empty
flag for data from SERDIN4±.
Bit 5 corresponds to FIFO empty
flag for data from SERDIN5±.
Bit 6 corresponds to FIFO empty
flag for data from SERDIN6±.
Bit 7 corresponds to FIFO empty
flag for data from SERDIN7±.
0x311 SYNC_GEN_0
[7:3] RESERVED
Reserved.
0x0
R
2
Mask EOMF from QBD_0. Assert
SYNCOUT based on loss of
multiframe sync.
0x0
R/W
EOMF_MASK_0
0 Do not assert SYNCOUT on loss of
multiframe.
1 Assert SYNCOUT on loss of
multiframe.
1
RESERVED
Reserved.
0x0
R/W
0
EOF_MASK_0
Mask EOF from QBD_0. Assert
SYNCOUT based on loss of frame
sync.
0x0
R/W
0 Do not assert SYNCOUT on loss of
frame.
1 Assert SYNCOUT on loss of frame.
0x312 SYNC_GEN_1
[7:4] SYNC_ERR_DUR
Duration of SYNCOUT signal low
for purpose of sync error report. 0
means half PCLK cycle. Add an
additional PCLK = 4 octets for
each increment of the value.
0x0
R/W
[3:0] SYNC_SYNCREQ_DUR
Duration of SYNCOUT signal low
for purpose of sync request. 0
means 5 frame + 9 octets. Add an
additional PCLK = 4 octets for
each increment of the value.
0x0
R/W
Rev. D | Page 94 of 126
Data Sheet
Hex.
Addr.
Name
AD9163
Description
Reset Access
0x313 SYNC_GEN_3
Bits Bit Name
[7:0] LMFC_PERIOD
Settings
LMFC period in PCLK cycle. This is
to report the global LMFC period
based on PCLK.
0x0
R
0x315 PHY_PRBS_TEST_EN
[7:0] PHY_TEST_EN
Enable PHY BER by ungating the
clocks.
0x0
R/W
0x0
R
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
Bits[7:0] of the 24-bit threshold
value set the error flag for PHY
PRBS test.
0x0
R/W
0x318 PHY_PRBS_TEST_THRESHOLD_MIDBITS [7:0] PHY_PRBS_THRESHOLD_MIDBITS
Bits[15:8] of the 24-bit threshold
value set the error flag for PHY
PRBS test.
0x0
R/W
0x319 PHY_PRBS_TEST_THRESHOLD_HIBITS
[7:0] PHY_PRBS_THRESHOLD_HIBITS
Bits[23:16] of the 24-bit threshold
value set the error flag for PHY
PRBS test.
0x0
R/W
0x31A PHY_PRBS_TEST_ERRCNT_LOBITS
[7:0] PHY_PRBS_ERR_CNT_LOBITS
Bits[7:0] of the 24-bit reported
PHY BER test error count from
selected lane.
0x0
R
0x31B PHY_PRBS_TEST_ERRCNT_MIDBITS
[7:0] PHY_PRBS_ERR_CNT_MIDBITS
Bits[15:8] of the 24-bit reported
PHY BER test error count from
selected lane.
0x0
R
0x31C PHY_PRBS_TEST_ERRCNT_HIBITS
[7:0] PHY_PRBS_ERR_CNT_HIBITS
Bits[23:16] of the 24-bit reported
PHY BER test error count from
selected lane.
0x0
R
0x31D PHY_PRBS_TEST_STATUS
[7:0] PHY_PRBS_PASS
Each bit is for the corresponding
0xFF
lane. Report PHY BER test pass/fail
for each lane.
R
0x31E
[7:5] RESERVED
Reserved.
0x0
R
[4:2] PHY_GRAB_LANE_SEL
Select which lane to grab data.
0x0
R/W
1 PHY test enable.
0 PHY test disable.
0x316 PHY_PRBS_TEST_CTRL
7
RESERVED
Reserved.
[6:4] PHY_SRC_ERR_CNT
000 Report Lane 0 error count.
001 Report Lane 1 error count.
010 Report Lane 2 error count.
011 Report Lane 3 error count.
100 Report Lane 4 error count.
101 Report Lane 5 error count.
110 Report Lane 6 error count.
111 Report Lane 7 error count.
[3:2] PHY_PRBS_PAT_SEL
Select PRBS pattern for PHY BER
test.
00 PRBS7.
01 PRBS15.
10 PRBS31.
11 Not used.
1
PHY_TEST_START
Start and stop the PHY PRBS test.
0 Test not started.
1 Test started.
0
PHY_TEST_RESET
Reset PHY PRBS test state
machine and error counters.
0 Not reset.
1 Reset.
0x317 PHY_PRBS_TEST_THRESHOLD_LOBITS
PHY_DATA_SNAPSHOT_CTRL
[7:0] PHY_PRBS_THRESHOLD_LOBITS
000 Grab data from Lane 0.
001 Grab data from Lane 1.
010 Grab data from Lane 2.
011 Grab data from Lane 3.
Rev. D | Page 95 of 126
AD9163
Hex.
Addr.
Name
Data Sheet
Bits Bit Name
Settings
Description
Reset Access
100 Grab data from Lane 4.
101 Grab data from Lane 5.
110 Grab data from Lane 6.
111 Grab data from Lane 7.
1
PHY_GRAB_MODE
Use error trigger to grab data.
0x0
R/W
Transition from 0 to 1 causes logic to 0x0
store current receive data from one
lane.
R/W
0 Grab data when
PHY_GRAB_DATA is set.
1 Grab data upon bit error.
0
0x31F
PHY_GRAB_DATA
PHY_SNAPSHOT_DATA_BYTE0
[7:0] PHY_SNAPSHOT_DATA_BYTE0
Current data received represents
PHY_SNAPSHOT_DATA[7:0].
0x0
R
0x320 PHY_SNAPSHOT_DATA_BYTE1
[7:0] PHY_SNAPSHOT_DATA_BYTE1
Current data received represents
PHY_SNAPSHOT_DATA[15:8].
0x0
R
0x321 PHY_SNAPSHOT_DATA_BYTE2
[7:0] PHY_SNAPSHOT_DATA_BYTE2
Current data received represents
PHY_SNAPSHOT_DATA[23:16].
0x0
R
0x322 PHY_SNAPSHOT_DATA_BYTE3
[7:0] PHY_SNAPSHOT_DATA_BYTE3
Current data received represents
PHY_SNAPSHOT_DATA[31:24].
0x0
R
0x323 PHY_SNAPSHOT_DATA_BYTE4
[7:0] PHY_SNAPSHOT_DATA_BYTE4
Current data received represents
PHY_SNAPSHOT_DATA[39:32].
0x0
R
0x32C SHORT_TPL_TEST_0
[7:4] SHORT_TPL_SP_SEL
Short transport layer sample
selection. Select which sample to
check from a specific DAC.
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0000 Sample 0.
0001 Sample 1.
0010 Sample 2.
0011 Sample 3.
0100 Sample 4.
0101 Sample 5.
0110 Sample 6.
0111 Sample 7.
1000 Sample 8.
1001 Sample 9.
1010 Sample 10.
1011 Sample 11.
1100 Sample 12.
1101 Sample 13.
1110 Sample 14.
1111 Sample 15.
[3:2] SHORT_TPL_M_SEL
Short transport layer test DAC
selection. Select which DAC to
check.
00 DAC 0.
01 DAC 1.
10 DAC 2.
11 DAC 3.
1
SHORT_TPL_TEST_RESET
Short transport layer test reset.
Resets the result of short
transport layer test.
0 Not reset.
1 Reset.
0
SHORT_TPL_TEST_EN
Short transport layer test enable.
Enable short transport layer test.
0 Disable.
1 Enable.
Rev. D | Page 96 of 126
Data Sheet
Hex.
Addr.
Name
AD9163
Description
Reset Access
0x32D SHORT_TPL_TEST_1
Bits Bit Name
[7:0] SHORT_TPL_REF_SP_LSB
Settings
Short transport layer reference
sample LSB. This is the lower eight
bits of expected DAC sample. It is
used to compare with the received
DAC sample at the output of
JESD204B Rx.
0x0
R/W
0x32E
SHORT_TPL_TEST_2
[7:0] SHORT_TPL_REF_SP_MSB
Short transport layer test reference
sample MSB. This is the upper eight
bits of expected DAC sample. It is
used to compare with the received
sample at JESD204B Rx output.
0x0
R/W
0x32F
SHORT_TPL_TEST_3
[7:1] RESERVED
Reserved.
0x0
R
0
Short transport layer test fail. This bit 0x0
shows if the selected DAC sample
matches the reference sample. If
they match, the test passes;
otherwise, the test fails.
R
SHORT_TPL_FAIL
0 Test pass.
1 Test fail.
0x334 JESD_BIT_INVERSE_CTRL
[7:0] JESD_BIT_INVERSE
Each bit of this byte inverses the
JESD204B deserialized data from
one specific JESD204B Rx PHY. The
bit order matches the logical lane
order. For example, Bit 0 controls
Lane 0, Bit 1 controls Lane 1.
0x400 DID_REG
[7:0] DID_RD
Received ILAS configuration on
0x0
Lane 0. DID is the device ID number.
Link information received on Lane 0
as specified in Section 8.3 of
JESD204B.
R
0x401 BID_REG
[7:0] BID_RD
Received ILAS configuration on
0x0
Lane 0. BID is the bank ID, extension
to DID. Link information received on
Lane 0 as specified in Section 8.3 of
JESD204B.
R
0x402 LID0_REG
7
RESERVED
Reserved.
0x0
R
6
ADJDIR_RD
Received ILAS configuration on
0x0
Lane 0. ADJDIR is the direction to
adjust the DAC LMFC. Link
information received on Lane 0 as
specified in Section 8.3 of JESD204B.
R
5
PHADJ_RD
Received ILAS configuration on
0x0
Lane 0. PHADJ is the phase
adjustment request to DAC. Link
information received on Lane 0 as
specified in Section 8.3 of JESD204B.
R
[4:0] LL_LID0
Received ILAS LID configuration
0x0
on Lane 0. LID0 is the lane
identification for Lane 0. Link
information received on Lane 0 as
specified in Section 8.3 of
JESD204B.
R
7
Received ILAS configuration on
Lane 0. SCR is the Tx scrambling
status. Link information received
on Lane 0 as specified in
Section 8.3 of JESD204B.
0x0
R
0x0
R
0x403 SCR_L_REG
SCR_RD
0x0
R/W
0 Scrambling is disabled.
1 Scrambling is enabled.
[6:5] RESERVED
Reserved.
Rev. D | Page 97 of 126
AD9163
Hex.
Addr.
Name
Data Sheet
Bits Bit Name
Settings
[4:0] L_RD
Description
Reset Access
Received ILAS configuration on
Lane 0. L is the number of lanes per
converter device. Link information
received on Lane 0 as specified in
Section 8.3 of JESD204B.
0x0
R
Received ILAS configuration on
0x0
Lane 0. F is the number of octets per
frame. Settings of 1, 2, and 4 are
valid (value in register is F − 1). Link
information received on Lane 0 as
specified in Section 8.3 of JESD204B.
R
00000 1 lane per converter device.
00001 2 lanes per converter device.
00011 4 lanes per converter device.
00111 8 lanes per converter device.
0x404 F_REG
[7:0] F_RD
0 1 octet per frame.
1 2 octets per frame.
11 4 octets per frame.
0x405 K_REG
[7:5] RESERVED
Reserved.
0x0
R
[4:0] K_RD
Received ILAS configuration on
0x0
Lane 0. K is the number of frames
per multiframe. Settings of 16 or
32 are valid. On this device, all
modes use K = 32 (value in register
is K − 1). Link information received
on Lane 0 as specified in Section
8.3 of JESD204B.
R
01111 16 frames per multiframe.
11111 32 frames per multiframe.
0x406 M_REG
[7:0] M_RD
Received ILAS configuration on
0x0
Lane 0. M is the number of
converters per device. Link
information received on Lane 0 as
specified in Section 8.3 of
JESD204B. M is 1 for real interface
and 2 for complex interface (value
in register is M − 1).
R
0x407 CS_N_REG
[7:6] CS_RD
Received ILAS configuration on
0x0
Lane 0. CS is the number of
control bits per sample. Link
information received on Lane 0 as
specified in Section 8.3 of
JESD204B. CS is always 0 on this
device.
R
5
0x408 NP_REG
Reserved.
0x0
R
[4:0] N_RD
RESERVED
Received ILAS configuration on
Lane 0. N is the converter resolution. Value in register is N − 1 (for
example, 16 bits = 0b01111).
0x0
R
[7:5] SUBCLASSV_RD
Received ILAS configuration on
Lane 0. SUBCLASSV is the device
subclass version. Link information
received on Lane 0 as specified in
Section 8.3 of JESD204B.
0x0
R
0x0
R
000 Subclass 0.
001 Subclass 1.
[4:0] NP_RD
Received ILAS configuration on
Lane 0. NP is the total number of
bits per sample. Link information
received on Lane 0 as specified in
Section 8.3 of JESD204B. Value in
register is NP − 1, for example,
16 bits per sample = 0b01111.
Rev. D | Page 98 of 126
Data Sheet
Hex.
Addr.
AD9163
Name
Bits Bit Name
0x409 S_REG
[7:5] JESDV_RD
Settings
Description
Reset Access
Received ILAS configuration on
Lane 0. JESDV is the JESD204x
version. Link information received
on Lane 0 as specified in
Section 8.3 of JESD204B.
0x0
R
[4:0] S_RD
Received ILAS configuration on
0x0
Lane 0. S is the number of samples
per converter per frame cycle.
Link information received on Lane
0 as specified in Section 8.3 of
JESD204B. Value in register is S − 1.
R
7
Received ILAS configuration on
0x0
Lane 0. HD is the high density
format. Refer to Section 5.1.3 of
JESD204B standard. Link
information received on Lane 0 as
specified in Section 8.3 of
JESD204B.
R
000 JESD204A.
001 JESD204B.
0x40A HD_CF_REG
HD_RD
0 Low density mode.
1 High density mode.
[6:5] RESERVED
Reserved.
0x0
R
[4:0] CF_RD
Received ILAS configuration on
Lane 0. CF is the number of
control words per frame clock
period per link. Link information
received on Lane 0 as specified in
Section 8.3 of JESD204B. CF is
always 0 on this device.
0x0
R
0x40B RES1_REG
[7:0] RES1_RD
Received ILAS configuration on
0x0
Lane 0. Reserved Field 1. Link
information received on Lane 0 as
specified in Section 8.3 of
JESD204B.
R
0x40C RES2_REG
[7:0] RES2_RD
Received ILAS configuration on
0x0
Lane 0. Reserved Field 2. Link
information received on Lane 0 as
specified in Section 8.3 of
JESD204B.
R
0x40D CHECKSUM0_REG
[7:0] LL_FCHK0
Received checksum during ILAS
on Lane 0. Checksum for Lane 0.
Link information received on
Lane 0 as specified in Section 8.3
of JESD204B.
0x0
R
0x40E
[7:0] LL_FCMP0
Computed checksum on Lane 0.
0x0
Computed checksum for Lane 0.
The JESD204B Rx computes the
checksum of the link information
received on Lane 0 as specified in
Section 8.3 of JESD204B. The
computation method is set by the
CHECKSUM_MODE bit
(Register 0x300, Bit 6) and must
match the likewise calculated
checksum in Register 0x40D.
R
[7:5] RESERVED
Reserved.
0x0
R
[4:0] LL_LID1
Received ILAS LID configuration
on Lane 1. Lane identification for
Lane 1. Link information received
on Lane 0 as specified in
Section 8.3 of JESD204B.
0x0
R
COMPSUM0_REG
0x412 LID1_REG
Rev. D | Page 99 of 126
AD9163
Hex.
Addr.
Name
Data Sheet
Description
Reset Access
0x415 CHECKSUM1_REG
[7:0] LL_FCHK1
Received checksum during ILAS
on lane 1. Checksum for Lane 1.
Link information received on
Lane 0 as specified in Section 8.3
of JESD204B.
0x0
R
0x416 COMPSUM1_REG
[7:0] LL_FCMP1
Computed checksum on Lane 1.
Computed checksum for Lane 1
(see description for Register 0x40E).
0x0
R
0x41A LID2_REG
[7:5] RESERVED
Reserved.
0x0
R
[4:0] LL_LID2
Received ILAS LID configuration
on Lane 2. Lane identification for
Lane 2.
0x0
R
0x41D CHECKSUM2_REG
[7:0] LL_FCHK2
Received checksum during ILAS
on Lane 2. Checksum for Lane 2.
0x0
R
0x41E
[7:0] LL_FCMP2
Computed checksum on Lane 2.
Computed checksum for Lane 2
(see description for Register 0x40E).
0x0
R
[7:5] RESERVED
Reserved.
0x0
R
[4:0] LL_LID3
Received ILAS LID configuration
on Lane 3. Lane identification for
Lane 3.
0x0
R
0x425 CHECKSUM3_REG
[7:0] LL_FCHK3
Received checksum during ILAS
on Lane 3. Checksum for Lane 3.
0x0
R
0x426 COMPSUM3_REG
[7:0] LL_FCMP3
Computed checksum on Lane 3.
Computed checksum for Lane 3
(see description for Register 0x40E).
0x0
R
0x42A LID4_REG
[7:5] RESERVED
Reserved.
0x0
R
[4:0] LL_LID4
Received ILAS LID configuration
on Lane 4. Lane identification for
Lane 4.
0x0
R
0x42D CHECKSUM4_REG
[7:0] LL_FCHK4
Received checksum during ILAS
on Lane 4. Checksum for Lane 4.
0x0
R
0x42E
[7:0] LL_FCMP4
Computed checksum on Lane 4.
Computed checksum for Lane 4
(see description for Register 0x40E).
0x0
R
[7:5] RESERVED
Reserved.
0x0
R
[4:0] LL_LID5
Received ILAS LID configuration
on Lane 5. Lane identification for
Lane 5.
0x0
R
0x435 CHECKSUM5_REG
[7:0] LL_FCHK5
Received checksum during ILAS
on Lane 5. Checksum for Lane 5.
0x0
R
0x436 COMPSUM5_REG
[7:0] LL_FCMP5
Computed checksum on Lane 5.
Computed checksum for Lane 5
(see description for Register 0x40E).
0x0
R
0x43A LID6_REG
[7:5] RESERVED
Reserved.
0x0
R
[4:0] LL_LID6
Received ILAS LID configuration
on Lane 6. Lane identification for
Lane 6.
0x0
R
0x43D CHECKSUM6_REG
[7:0] LL_FCHK6
Received checksum during ILAS
on Lane 6. Checksum for Lane 6.
0x0
R
0x43E
[7:0] LL_FCMP6
Computed checksum on Lane 6.
Computed checksum for Lane 6
(see description for Register 0x40E).
0x0
R
[7:5] RESERVED
Reserved.
0x0
R
[4:0] LL_LID7
Received ILAS LID configuration
on Lane 7. Lane identification for
Lane 7.
0x0
R
0x445 CHECKSUM7_REG
[7:0] LL_FCHK7
Received checksum during ILAS
on Lane 7. Checksum for Lane 7.
0x0
R
0x446 COMPSUM7_REG
[7:0] LL_FCMP7
Computed checksum on Lane 7.
Computed checksum for Lane 7
(see description for Register 0x40E).
0x0
R
COMPSUM2_REG
0x422 LID3_REG
COMPSUM4_REG
0x432 LID5_REG
COMPSUM6_REG
0x442 LID7_REG
Bits Bit Name
Settings
Rev. D | Page 100 of 126
Data Sheet
Hex.
Addr.
Name
AD9163
Bits Bit Name
Settings
Description
Reset Access
0x450 ILS_DID
[7:0] DID
Device (= link) identification
0x0
number. DID is the device ID
number. Link information received
on Lane 0 as specified in Section
8.3 of JESD204B. Must be set to
the value read in Register 0x400.
This signal must only be programmed while the QBD is held in
soft reset (Register 0x475, Bit 3),
and must not be changed during
normal operation.
R/W
0x451 ILS_BID
[7:0] BID
Bank ID, extension to DID. This
signal must only be programmed
while the QBD is held in soft reset
(Register 0x475, Bit 3), and must
not be changed during normal
operation.
0x0
R/W
0x452 ILS_LID0
7
RESERVED
Reserved.
0x0
R
6
ADJDIR
Direction to adjust DAC LMFC
0x0
(Subclass 2 only). ADJDIR is the
direction to adjust DAC LMFC.
Link information received on Lane
0 as specified in Section 8.3 of
JESD204B. This signal must only be
programmed while the QBD is
held in soft reset (Register 0x475,
Bit 3), and must not be changed
during normal operation.
R/W
5
PHADJ
Phase adjustment to DAC
0x0
(Subclass 2 only). PHADJ is the
phase adjustment request to the
DAC. Link information received on
Lane 0 as specified in Section 8.3
of JESD204B. This signal must only
be programmed while the QBD is
held in soft reset (Register 0x475,
Bit 3), and must not be changed
during normal operation.
R/W
[4:0] LID0
Lane identification number
0x0
(within link). LID0 is the lane
identification for Lane 0. Link
information received on Lane 0 as
specified in Section 8.3 of
JESD204B. This signal must only
be programmed while the QBD is
held in soft reset (Register 0x475,
Bit 3), and must not be changed
during normal operation.
R/W
7
Scramble enable. SCR is the Rx
descrambling enable. This signal
must only be programmed while
the QBD is held in soft reset
(Register 0x475, Bit 3), and must
not be changed during normal
operation.
0x1
R/W
0x453 ILS_SCR_L
SCR
0 Descrambling is disabled.
1 Descrambling is enabled.
[6:5] RESERVED
Reserved.
0x0
R
[4:0] L
Number of lanes per converter
(minus 1). L is the number of lanes
per converter device. Settings of
1, 2, 3, 4, 6, and 8 are valid. Refer
to Table 14 and Table 15.
0x7
R
Rev. D | Page 101 of 126
AD9163
Hex.
Addr.
Name
Data Sheet
Bits Bit Name
Settings
Description
Reset Access
0x454 ILS_F
[7:0] F
Number of octets per frame
0x0
(minus 1). This value of F is not
used to soft configure the QBD.
Register CTRLREG1 is used to softconfigure the QBD.
R
0x455 ILS_K
[7:5] RESERVED
Reserved.
R
[4:0] K
Number of frames per multiframe
0x1F
(minus 1). K is the number of frames
per multiframe. On this device, all
modes use K = 32 (value in register
is K − 1). This signal must only be
programmed while the QBD is held
in soft reset (Register 0x475, Bit 3),
and must not be changed during
normal operation.
0x0
R/W
01111 16 frames per multiframe.
11111 32 frames per multiframe.
0x456 ILS_M
[7:0] M
Number of converters per device
(minus 1). M is the number of
converters/device. Settings of 1
and 2 are valid. Refer to Table 14
and Table 15.
0x1
R
0x457 ILS_CS_N
[7:6] CS
Number of control bits per
sample. CS is the number of
control bits per sample. Must be
set to 0. Control bits are not
supported.
0x0
R
5
0x458 ILS_NP
Reserved.
0x0
R
[4:0] N
RESERVED
Converter resolution (minus 1). N
is the converter resolution. Must
be set to 16 (0x0F).
0xF
R
[7:5] SUBCLASSV
Device subclass version. SUBCLASSV 0x0
is the device subclass version. This
signal must only be programmed
while the QBD is held in soft reset
(Register 0x475, Bit 3), and must
not be changed during normal
operation.
R/W
000 Subclass 0.
001 Subclass 1.
010 Subclass 2 (not supported).
0x459 ILS_S
[4:0] NP
Total number of bits per sample
(minus 1). NP is the total number
of bits per sample. Must be set to
16 (0x0F). Refer to Table 14 and
Table 15.
0xF
R
[7:5] JESDV
JESD204x version. JESDV is the
JESD204x version. This signal
must only be programmed while
the QBD is held in soft reset
(Register 0x475, Bit 3), and must
not be changed during normal
operation.
0x0
R/W
0x1
R
000 JESD204A.
001 JESD204B.
[4:0] S
Number of samples per converter
per frame cycle (minus 1). S is the
number of samples per converter
per frame cycle. Settings of 1 and
2 are valid. Refer to Table 14 and
Table 15.
Rev. D | Page 102 of 126
Data Sheet
Hex.
Addr.
Name
0x45A ILS_HD_CF
AD9163
Bits Bit Name
7
Settings
HD
Description
Reset Access
High density format. HD is the
high density mode. Refer to
Section 5.1.3 of JESD204B
standard.
0x1
R
0 Low density mode.
1 High density mode.
[6:5] RESERVED
Reserved.
0x0
R
[4:0] CF
Number of control bits per
sample. CF is the number of
control words per frame clock
period per link. Must be set to 0.
Control bits are not supported.
0x0
R
0x45B ILS_RES1
[7:0] RES1
Reserved. Reserved Field 1. This
signal must only be programmed
while the QBD is held in soft reset
(Register 0x475, Bit 3), and must
not be changed during normal
operation.
0x0
R/W
0x45C ILS_RES2
[7:0] RES2
Reserved. Reserved Field 2. This
signal must only be programmed
while the QBD is held in soft reset
(Register 0x475, Bit 3), and must
not be changed during normal
operation.
0x0
R/W
0x45D ILS_CHECKSUM
[7:0] FCHK0
Link configuration checksum.
0x0
Checksum for Lane 0. The checksum
for the configuration values (not the
whole register content)
programmed into Register 0x450 to
Register 0x45C must be calculated
according to section 8.3 of the
JESD204B specification and written
to this register (SUM(DID,…,SC,
L-1,…CF)%256). This signal must
only be programmed while the
QBD is held in soft reset (Register
0x475, Bit 3), and must not be
changed during normal
operation.
R/W
0x46C LANE_DESKEW
7
Interlane deskew status for Lane 7 0x0
(ignore this output when
NO_ILAS = 1).
R
ILD7
0 Deskew failed.
1 Deskew achieved.
6
ILS6
Initial lane synchronization status
for Lane 6 (ignore this output
when NO_ILAS = 1).
0x0
R
0x0
R
0x0
R
0 Synchronization lost.
1 Synchronization achieved.
5
ILD5
Interlane deskew status for Lane 5
(ignore this output when
NO_ILAS = 1).
0 Deskew failed.
1 Deskew achieved.
4
ILD4
Interlane deskew status for Lane 4
(ignore this output when
NO_ILAS = 1).
0 Deskew failed.
1 Deskew achieved.
Rev. D | Page 103 of 126
AD9163
Hex.
Addr.
Name
Data Sheet
Bits Bit Name
3
Settings
ILD3
Description
Reset Access
Interlane deskew status for Lane 3
0x0
(ignore this output when NO_ILAS =
1).
R
0 Deskew failed.
1 Deskew achieved.
2
ILD2
Interlane deskew status for Lane 2
(ignore this output when
NO_ILAS = 1).
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0 Deskew failed.
1 Deskew achieved.
1
ILD1
Interlane deskew status for Lane 1
(ignore this output when
NO_ILAS = 1).
0 Deskew failed.
1 Deskew achieved.
0
ILD0
Interlane deskew status for Lane 0
(ignore this output when
NO_ILAS = 1).
0 Deskew failed.
1 Deskew achieved.
0x46D BAD_DISPARITY
7
BDE7
Bad disparity error status for Lane 7.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
6
BDE6
Bad disparity error status for Lane 6.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
5
BDE5
Bad disparity errors status for
Lane 5.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
4
BDE4
Bad disparity error status for Lane 4.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
3
BDE3
Bad disparity error status for Lane 3.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
2
BDE2
Bad disparity error status for Lane 2.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
1
BDE1
Bad disparity error status for Lane 1.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
0
BDE0
Bad disparity error status for Lane 0.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
0x46E
NOT_IN_TABLE
7
NIT7
Not in table error status for Lane 7.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
6
NIT6
Not in table error status for Lane 6.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
5
NIT5
Not in table errors status for Lane 5.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
Rev. D | Page 104 of 126
Data Sheet
Hex.
Addr.
Name
AD9163
Bits Bit Name
4
Settings
NIT4
Description
Reset Access
Not in table error status for Lane 4.
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
3
NIT3
Not in table error status for Lane 3.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
2
NIT2
Not in table error status for Lane 2.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
1
NIT1
Not in table error status for Lane 1.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
0
NIT0
Not in table error status for Lane 0.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
0x46F
UNEXPECTED_KCHAR
7
UEK7
Unexpected K character error
status for Lane 7.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
6
UEK6
Unexpected K character error
status for Lane 6.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
5
UEK5
Unexpected K character error
status for Lane 5.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
4
UEK4
Unexpected K character error
status for Lane 4.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
3
UEK3
Unexpected K character error
status for Lane 3.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
2
UEK2
Unexpected K character error
status for Lane 2.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
1
UEK1
Unexpected K character error
status for Lane 1.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
0
UEK0
Unexpected K character error
status for Lane 0.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
0x470 CODE_GRP_SYNC
7
CGS7
Code group sync status for Lane 7.
0 Synchronization lost.
1 Synchronization achieved.
6
CGS6
Code group sync status for Lane 6.
0 Synchronization lost.
1 Synchronization achieved.
Rev. D | Page 105 of 126
AD9163
Hex.
Addr.
Name
Data Sheet
Bits Bit Name
5
Settings
CGS5
Description
Reset Access
Code group sync status for Lane 5.
0x0
R
0x0
R
0x0
R
0x0
R
Code group sync status for Lane 1. 0x0
R
0 Synchronization lost.
1 Synchronization achieved.
4
CGS4
Code group sync status for Lane 4.
0 Synchronization lost.
1 Synchronization achieved.
3
CGS3
Code group sync status for Lane 3.
0 Synchronization lost.
1 Synchronization achieved.
2
CGS2
Code group sync status for Lane 2.
0 Synchronization lost.
1 Synchronization achieved.
1
CGS1
0 Synchronization lost.
1 Synchronization achieved.
0
CGS0
Code group sync status for Lane 0.
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0 Synchronization lost.
1 Synchronization achieved.
0x471 FRAME_SYNC
7
FS7
Frame sync status for Lane 7
(ignore this output when
NO_ILAS = 1).
0 Synchronization lost.
1 Synchronization achieved.
6
FS6
Frame sync status for Lane 6
(ignore this output when
NO_ILAS = 1).
0 Synchronization lost.
1 Synchronization achieved.
5
FS5
Frame sync status for Lane 5
(ignore this output when
NO_ILAS = 1).
0 Synchronization lost.
1 Synchronization achieved.
4
FS4
Frame sync status for Lane 4
(ignore this output when
NO_ILAS = 1).
0 Synchronization lost.
1 Synchronization achieved.
3
FS3
Frame sync status for Lane 3
(ignore this output when
NO_ILAS = 1).
0 Synchronization lost.
1 Synchronization achieved.
2
FS2
Frame sync status for Lane 2
(ignore this output when
NO_ILAS = 1).
0 Synchronization lost.
1 Synchronization achieved.
1
FS1
Frame sync status for Lane 1
(ignore this output when
NO_ILAS = 1).
0 Synchronization lost.
1 Synchronization achieved.
Rev. D | Page 106 of 126
Data Sheet
Hex.
Addr.
Name
AD9163
Bits Bit Name
0
Settings
FS0
Description
Reset Access
Frame sync status for Lane 0
(ignore this output when
NO_ILAS = 1).
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0 Synchronization lost.
1 Synchronization achieved.
0x472 GOOD_CHECKSUM
7
CKS7
Computed checksum status for
Lane 7 (ignore this output when
NO_ILAS = 1).
0 Checksum is incorrect.
1 Checksum is correct.
6
CKS6
Computed checksum status for
Lane 6 (ignore this output when
NO_ILAS = 1).
0 Checksum is incorrect.
1 Checksum is correct.
5
CKS5
Computed checksum status for
Lane 5 (ignore this output when
NO_ILAS = 1).
0 Checksum is incorrect.
1 Checksum is correct.
4
CKS4
Computed checksum status for
Lane 4 (ignore this output when
NO_ILAS = 1).
0 Checksum is incorrect.
1 Checksum is correct.
3
CKS3
Computed checksum status for
Lane 3 (ignore this output when
NO_ILAS = 1).
0 Checksum is incorrect.
1 Checksum is correct.
2
CKS2
Computed checksum status for
Lane 2 (ignore this output when
NO_ILAS = 1).
0 Checksum is incorrect.
1 Checksum is correct.
1
CKS1
Computed checksum status for
Lane 1 (ignore this output when
NO_ILAS = 1).
0 Checksum is incorrect.
1 Checksum is correct.
0
CKS0
Computed checksum status for
Lane 0 (ignore this output when
NO_ILAS = 1).
0 Checksum is incorrect.
1 Checksum is correct.
0x473 INIT_LANE_SYNC
7
ILS7
Initial lane synchronization status
for Lane 7 (ignore this output
when NO_ILAS = 1).
0 Synchronization lost.
1 Synchronization achieved.
6
ILS6
Initial lane synchronization status
for Lane 6 (ignore this output
when NO_ILAS = 1).
0 Synchronization lost.
1 Synchronization achieved.
Rev. D | Page 107 of 126
AD9163
Hex.
Addr.
Name
Data Sheet
Bits Bit Name
Description
Reset Access
Initial lane synchronization status
for Lane 5 (ignore this output
when NO_ILAS = 1).
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R/W
When this input = 1, character
0x0
replacement at the end of
frame/multiframe is disabled. This
signal must only be programmed
while the QBD is held in soft reset
(Register 0x475, Bit 3), and must
not be changed during normal
operation.
R/W
[5:4] RESERVED
Reserved.
0x0
R
3
Soft reset. Active high synchronous
reset. Resets all hardware to poweron state.
0x0
R/W
5
Settings
ILS5
0 Synchronization lost.
1 Synchronization achieved.
4
ILS4
Initial lane synchronization status
for Lane 4 (ignore this output
when NO_ILAS = 1).
0 Synchronization lost.
1 Synchronization achieved.
3
ILS3
Initial lane synchronization status
for Lane 3 (ignore this output
when NO_ILAS = 1).
0 Synchronization lost.
1 Synchronization achieved.
2
ILS2
Initial lane synchronization status
for Lane 2 (ignore this output
when NO_ILAS = 1).
0 Synchronization lost.
1 Synchronization achieved.
1
ILS1
Initial lane synchronization status
for Lane 1 (ignore this output
when NO_ILAS = 1).
0 Synchronization lost.
1 Synchronization achieved.
0
ILS0
Initial lane synchronization status
for Lane 0 (ignore this output
when NO_ILAS = 1).
0 Synchronization lost.
1 Synchronization achieved.
0x475 CTRLREG0
7
RX_DIS
Level input: disable deframer
receiver when this input = 1. This
signal must only be programmed
while the QBD is held in soft reset
(Register 0x475, Bit 3), and must
not be changed during normal
operation.
1 Disable character replacement of
/A/ and /F/ control characters at
the end of received frames and
multiframes.
0 Enables the substitution.
6
CHAR_REPL_DIS
SOFTRST
1 Disables the deframer reception.
0 Enable deframer logic.
2
FORCESYNCREQ
Command from application to
assert a sync request (SYNCOUT).
Active high.
0x0
R/W
1
RESERVED
Reserved.
0x0
R
Rev. D | Page 108 of 126
Data Sheet
Hex.
Addr.
Name
AD9163
Bits Bit Name
Description
Reset Access
When this level input is set, it
enables replacement of frames
received in error. This signal must
only be programmed while the
QBD is held in soft reset (Register
0x475, Bit 3), and must not be
changed during normal
operation.
0x1
R/W
[7:5] RESERVED
Reserved.
0x0
R
4
Error reporting behavior for
0x1
concurrent NIT and RD errors. This
signal must only be programmed
while the QBD is held in soft reset
(Register 0x475, Bit 3), and must
not be changed during normal
operation.
0
0x476 CTRLREG1
Settings
REPL_FRM_ENA
QUAL_RDERR
R/W
0 NIT has no effect on RD error.
1 NIT error masks concurrent RD
error.
3
DEL_SCR
Alternative descrambler enable.
(see JESD204B Section 5.2.4) This
signal must only be programmed
while the QBD is held in soft reset
(Register 0x475, Bit 3), and must
not be changed during normal
operation.
0x0
R/W
Determines the QBD behavior
0x1
after code group sync has been
achieved. This signal must only be
programmed while the QBD is
held in soft reset (Register 0x475,
Bit 3), and must not be changed
during normal operation.
R/W
1 Descrambling begins at Octet 2 of
user data.
0 Descrambling begins at Octet 0 of
user data. This is the common
usage.
2
CGS_SEL
0 After code group sync is achieved,
the QBD asserts SYNCOUT only if
there are sufficient disparity errors
as per the JESD204B standard.
1 After code group sync is achieved,
if a /K/ is followed by any
character other than an /R/ or
another /K/, QBD asserts
SYNCOUT.
1
NO_ILAS
This signal must only be
programmed while the QBD is
held in soft reset (Register 0x475,
Bit 3), and must not be changed
during normal operation.
0x0
R/W
0x0
R/W
1 For single-lane operation, ILAS is
omitted. Code group sync is
followed by user data.
0 Code group sync is followed by
ILAS. For multilane operation,
NO_ILAS must always be set to 0.
0
FCHK_N
Checksum calculation method.
This signal must only be
programmed while the QBD is
held in soft reset (Register 0x475,
Register 3), and must not be
changed during normal
operation.
Rev. D | Page 109 of 126
AD9163
Hex.
Addr.
Name
Data Sheet
Bits Bit Name
Settings
Description
Reset Access
0 Calculate checksum by summing
individual fields (this more closely
matches the definition of the
checksum field in the JESD204B
standard.
1 Calculate checksum by summing
the registers containing the
packed fields (this setting is
provided in case the framer of
another vendor performs the
calculation with this method).
0x477 CTRLREG2
7
ILS_MODE
Data link layer test mode. This
signal must only be programmed
while the QBD is held in soft reset
(Register 0x475, Bit 3), and must
not be changed during normal
operation.
0x0
R/W
0 Normal mode.
1 Code group sync pattern is
followed by a perpetual ILAS
sequence.
6
RESERVED
Reserved.
0x0
R
5
REPDATATEST
Repetitive data test enable, using
JTSPAT pattern. To enable the
test, ILS_MODE must = 0. This
signal must only be programmed
while the QBD is held in soft reset
(Register 0x475, Bit 3), and must
not be changed during normal
operation.
0x0
R/W
4
QUETESTERR
Queue test error mode. This signal 0x0
must only be programmed while
the QBD is held in soft reset
(Register 0x475, Bit 3), and must
not be changed during normal
operation.
R/W
0 Simultaneous errors on multiple
lanes are reported as one error.
1 Detected errors from all lanes are
trapped in a counter and
sequentially signaled on
SYNCOUT.
3
0x478 KVAL
AR_ECNTR
Automatic reset of error counter. 0x0
The error counter that causes
assertion of SYNCOUT is automatically reset to 0 when AR_ECNTR = 1.
All other counters are unaffected.
This signal must only be
programmed while the QBD is
held in soft reset (Register 0x475,
Bit 3), and must not be changed
during normal operation.
R/W
[2:0] RESERVED
Reserved.
0x0
R
[7:0] KSYNC
Number of 4 × K multiframes
during ILS. F is the number of
octets per frame. Settings of 1, 2,
and 4 are valid. Refer to Table 14
and Table 15. This signal must only
be programmed while the QBD is
held in soft reset (Register 0x475,
Bit 3), and must not be changed
during normal operation.
0x1
R/W
Rev. D | Page 110 of 126
Data Sheet
Hex.
Addr.
Name
AD9163
Description
Reset Access
0x47C ERRORTHRES
Bits Bit Name
[7:0] ETH
Settings
Error threshold value. Bad
disparity, NIT disparity, and
unexpected K character errors are
counted and compared to the
error threshold value. When the
count is equal, either an IRQ is
generated or SYNCOUT± is
asserted per the mask register
settings or both. Function is
performed in all lanes. This signal
must only be programmed while
the QBD is held in soft reset
(Register 0x475, Bit 3), and must
not be changed during normal
operation.
0xFF
R/W
0x47D SYNC_ASSERT_MASK
[7:3] RESERVED
Reserved.
0x0
R
SYNCOUT assertion enable mask
for BD, NIT, and UEK error
conditions. Active high, SYNCOUT
assertion enable mask for BD, NIT,
and UEK error conditions,
respectively. When an error
counter, in any lane, has reached
the error threshold count, ETH[7:0],
and the corresponding
SYNC_ASSERT_ MASK bit is set,
SYNCOUT is asserted. The mask
bits are as follows. Note that the
bit sequence is reversed with
respect to the other error count
controls and the error counters.
0x7
R/W
[2:0] SYNC_ASSERT_MASK
Bit 2 = bad disparity error (BDE).
Bit 1 = not in table error (NIT).
Bit 0 = unexpected K (UEK)
character error.
0x480 ECNT_CTRL0
[7:6] RESERVED
Reserved.
0x0
R
[5:3] ECNT_ENA0
Error counter enable for Lane 0.
Counters of each lane are
addressed as follows:
0x7
R/W
Reset error counters for Lane 0,
0x7
active high. Counters of each lane
are addressed as follows:
R/W
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
[2:0] ECNT_RST0
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
0x481 ECNT_CTRL1
[7:6] RESERVED
Reserved.
[5:3] ECNT_ENA1
Error counters enable for Lane 1,
0x7
active high. Counters of each lane
are addressed as follows:
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
Rev. D | Page 111 of 126
0x0
R
R/W
AD9163
Hex.
Addr.
Name
Data Sheet
Bits Bit Name
Settings
[2:0] ECNT_RST1
Description
Reset Access
0x7
Reset error counters for Lane 1,
active high. Counters of each lane
are addressed as follows:
R/W
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
0x482 ECNT_CTRL2
[7:6] RESERVED
Reserved.
[5:3] ECNT_ENA2
0x7
Error counters enable for Lane 2,
active high. Counters of each lane
are addressed as follows:
0x0
R
R/W
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
[2:0] ECNT_RST2
0x7
Reset error counters for Lane 2,
active high. Counters of each lane
are addressed as follows:
R/W
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
0x483 ECNT_CTRL3
[7:6] RESERVED
Reserved.
[5:3] ECNT_ENA3
0x7
Error counters enable for Lane 3,
active high. Counters of each lane
are addressed as follows:
0x0
R
R/W
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
[2:0] ECNT_RST3
Reset error counters for Lane 3,
0x7
active high. Counters of each lane
are addressed as follows:
R/W
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
0x484 ECNT_CTRL4
[7:6] RESERVED
Reserved.
[5:3] ECNT_ENA4
Error counters enable for Lane 4,
0x7
active high. Counters of each lane
are addressed as follows:
0x0
R
R/W
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
[2:0] ECNT_RST4
0x7
Reset error counters for Lane 4,
active high. Counters of each lane
are addressed as follows:
R/W
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
0x485 ECNT_CTRL5
[7:6] RESERVED
Reserved.
[5:3] ECNT_ENA5
0x7
Error counters enable for Lane 5,
active high. Counters of each lane
are addressed as follows:
Bit 2 = unexpected K (UEK)
character error.
Rev. D | Page 112 of 126
0x0
R
R/W
Data Sheet
Hex.
Addr.
Name
AD9163
Bits Bit Name
Settings
Description
Reset Access
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
[2:0] ECNT_RST5
Reset error counters for Lane 5,
0x7
active high. Counters of each lane
are addressed as follows:
R/W
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
0x486 ECNT_CTRL6
[7:6] RESERVED
Reserved.
[5:3] ECNT_ENA6
Error counters enable for Lane 6,
0x7
active high. Counters of each lane
are addressed as follows:
0x0
R
R/W
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
[2:0] ECNT_RST6
Reset error counters for Lane 6,
0x7
active high. Counters of each lane
are addressed as follows:
R/W
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
0x487 ECNT_CTRL7
[7:6] RESERVED
Reserved.
[5:3] ECNT_ENA7
Error counters enable for Lane 7,
0x7
active high. Counters of each lane
are addressed as follows:
0x0
R
R/W
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
[2:0] ECNT_RST7
Reset error counters for Lane 7,
0x7
active high. Counters of each lane
are addressed as follows:
R/W
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
0x488 ECNT_TCH0
[7:3] RESERVED
Reserved.
0x0
R
[2:0] ECNT_TCH0
Terminal count hold enable of
error counters for Lane 0. When
set, the designated counter is to
hold the terminal count value of
0xFF when it is reached until the
counter is reset by the user. Otherwise, the designated counter
rolls over. Counters of each lane
are addressed as follows:
0x7
R/W
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
This signal must only be
programmed while the QBD is
held in soft reset (Register 0x475,
Bit 3), and must not be changed
during normal operation.
Rev. D | Page 113 of 126
AD9163
Hex.
Addr.
Name
0x489 ECNT_TCH1
Data Sheet
Bits Bit Name
Description
Reset Access
[7:3] RESERVED
Settings
Reserved.
0x0
[2:0] ECNT_TCH1
Terminal count hold enable of error 0x7
counters for Lane 1. When set, the
designated counter is to hold the
terminal count value of 0xFF when it
is reached until the counter is reset
by the user. Otherwise, the
designated counter rolls over.
Counters of each lane are addressed
as follows:
R
R/W
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
This signal must only be
programmed while the QBD is
held in soft reset (Register 0x475,
Bit 3), and must not be changed
during normal operation.
0x48A ECNT_TCH2
[7:3] RESERVED
Reserved.
0x0
R
[2:0] ECNT_TCH2
Terminal count hold enable of
error counters for Lane 2. When
set, the designated counter is to
hold the terminal count value of
0xFF when it is reached until the
counter is reset by the user.
Otherwise, the designated counter
rolls over. Counters of each lane are
addressed as follows:
0x7
R/W
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
This signal must only be
programmed while the QBD is
held in soft reset (Register 0x475,
Bit 3), and must not be changed
during normal operation.
0x48B ECNT_TCH3
[7:3] RESERVED
Reserved.
0x0
R
[2:0] ECNT_TCH3
Terminal count hold enable of
error counters for Lane 3. When
set, the designated counter is to
hold the terminal count value of
0xFF when it is reached until the
counter is reset by the user.
Otherwise, the designated counter
rolls over. Counters of each lane are
addressed as follows:
0x7
R/W
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
This signal must only be
programmed while the QBD is
held in soft reset (Register 0x475,
Bit 3), and must not be changed
during normal operation.
Rev. D | Page 114 of 126
Data Sheet
Hex.
Addr.
Name
0x48C ECNT_TCH4
AD9163
Bits Bit Name
Description
Reset Access
[7:3] RESERVED
Settings
Reserved.
0x0
R
[2:0] ECNT_TCH4
Terminal count hold enable of
error counters for Lane 4. When
set, the designated counter is to
hold the terminal count value of
0xFF when it is reached until the
counter is reset by the user.
Otherwise, the designated counter
rolls over. Counters of each lane are
addressed as follows:
0x7
R/W
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
This signal must only be
programmed while the QBD is
held in soft reset (Register 0x475,
Bit 3), and must not be changed
during normal operation.
0x48D ECNT_TCH5
[7:3] RESERVED
Reserved.
0x0
R
[2:0] ECNT_TCH5
Terminal count hold enable of
error counters for Lane 5. When
set, the designated counter is to
hold the terminal count value of
0xFF when it is reached until the
counter is reset by the user.
Otherwise, the designated counter
rolls over. Counters of each lane are
addressed as follows:
0x7
R/W
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
This signal must only be
programmed while the QBD is
held in soft reset (Register 0x475,
Bit 3), and must not be changed
during normal operation.
0x48E
ECNT_TCH6
[7:3] RESERVED
Reserved.
0x0
R
[2:0] ECNT_TCH6
Terminal count hold enable of
error counters for Lane 6. When
set, the designated counter is to
hold the terminal count value of
0xFF when it is reached until the
counter is reset by the user.
Otherwise, the designated
counter rolls over. Counters of
each lane are addressed as
follows:
0x7
R/W
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
This signal must only be
programmed while the QBD is
held in soft reset (Register 0x475,
Bit 3), and must not be changed
during normal operation.
Rev. D | Page 115 of 126
AD9163
Data Sheet
Hex.
Addr.
Name
Bits Bit Name
Description
Reset Access
0x48F
ECNT_TCH7
[7:3] RESERVED
Reserved.
0x0
R
[2:0] ECNT_TCH7
Terminal count hold enable of
error counters for Lane 7. When
set, the designated counter is to
hold the terminal count value of
0xFF when it is reached until the
counter is reset by the user.
Otherwise, the designated
counter rolls over. Counters of
each lane are addressed as
follows:
0x7
R/W
Settings
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
This signal must only be
programmed while the QBD is
held in soft reset (Register 0x475,
Bit 3), and must not be changed
during normal operation.
0x490 ECNT_STAT0
[7:4] RESERVED
Reserved.
0x0
R
3
This output indicates if Lane 0 is
enabled.
0x0
R
Terminal count reached indicator 0x0
of error counters for Lane 0. Set to
1 when the corresponding
counter terminal count value of
0xFF has been reached. Counters
of each lane are addressed as
follows.
R
LANE_ENA0
0 Lane 0 is held in soft reset.
1 Lane 0 is enabled.
[2:0] ECNT_TCR0
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
0x491 ECNT_STAT1
[7:4] RESERVED
Reserved.
0x0
R
3
This output indicates if Lane 1 is
enabled.
0x0
R
Terminal count reached indicator 0x0
of error counters for Lane 1. Set to
1 when the corresponding
counter terminal count value of
0xFF has been reached. Counters
of each lane are addressed as
follows.
R
LANE_ENA1
0 Lane 1 is held in soft reset.
1 Lane 1 is enabled.
[2:0] ECNT_TCR1
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
0x492 ECNT_STAT2
[7:4] RESERVED
Reserved.
0x0
R
3
This output indicates if Lane 2 is
enabled.
0x0
R
LANE_ENA2
0 Lane 2 is held in soft reset.
1 Lane 2 is enabled.
Rev. D | Page 116 of 126
Data Sheet
Hex.
Addr.
Name
AD9163
Bits Bit Name
Settings
[2:0] ECNT_TCR2
Description
Reset Access
Terminal count reached indicator 0x0
of error counters for Lane 2. Set to
1 when the corresponding
counter terminal count value of
0xFF has been reached. Counters
of each lane are addressed as
follows.
R
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
0x493 ECNT_STAT3
[7:4] RESERVED
Reserved.
0x0
R
3
This output indicates if Lane 3 is
enabled.
0x0
R
Terminal count reached indicator 0x0
of error counters for Lane 3. Set to
1 when the corresponding
counter terminal count value of
0xFF has been reached. Counters
of each lane are addressed as
follows:
R
LANE_ENA3
0 Lane 3 is held in soft reset.
1 Lane 3 is enabled.
[2:0] ECNT_TCR3
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
0x494 ECNT_STAT4
[7:4] RESERVED
Reserved.
0x0
R
3
This output indicates if Lane 4 is
enabled.
0x0
R
Terminal count reached indicator 0x0
of error counters for Lane 4. Set to
1 when the corresponding
counter terminal count value of
0xFF has been reached. Counters
of each lane are addressed as
follows:
R
LANE_ENA4
0 Lane 4 is held in soft reset.
1 Lane 4 is enabled.
[2:0] ECNT_TCR4
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
0x495 ECNT_STAT5
[7:4] RESERVED
Reserved.
0x0
R
3
This output indicates if Lane 5 is
enabled.
0x0
R
Terminal count reached indicator 0x0
of error counters for Lane 5. Set to
1 when the corresponding
counter terminal count value of
0xFF has been reached. Counters
of each lane are addressed as
follows:
R
LANE_ENA5
0 Lane 5 is held in soft reset.
1 Lane 5 is enabled.
[2:0] ECNT_TCR5
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
Rev. D | Page 117 of 126
AD9163
Hex.
Addr.
Name
0x496 ECNT_STAT6
Data Sheet
Bits Bit Name
Description
Reset Access
[7:4] RESERVED
Settings
Reserved.
0x0
R
3
This output indicates if Lane 6 is
enabled.
0x0
R
Terminal count reached indicator 0x0
of error counters for Lane 6. Set to
1 when the corresponding
counter terminal count value of
0xFF has been reached. Counters
of each lane are addressed as
follows:
R
LANE_ENA6
0 Lane 6 is held in soft reset.
1 Lane 6 is enabled.
[2:0] ECNT_TCR6
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
0x497 ECNT_STAT7
[7:4] RESERVED
Reserved.
0x0
R
3
This output indicates if Lane 7 is
enabled.
0x0
R
Terminal count reached indicator 0x0
of error counters for Lane 7. Set to
1 when the corresponding
counter terminal count value of
0xFF has been reached. Counters
of each lane are addressed as
follows:
R
LANE_ENA7
0 Lane 7 is held in soft reset.
1 Lane 7 is enabled.
[2:0] ECNT_TCR7
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
0x498 BD_CNT0
[7:0] BD_CNT0
Bad disparity 8-bit error counters
for Lane 0.
0x0
R
0x499 BD_CNT1
[7:0] BD_CNT1
Bad disparity 8-bit error counters
for Lane 1.
0x0
R
0x49A BD_CNT2
[7:0] BD_CNT2
Bad disparity 8-bit error counters
for Lane 2.
0x0
R
0x49B BD_CNT3
[7:0] BD_CNT3
Bad disparity 8-bit error counters
for Lane 3.
0x0
R
0x49C BD_CNT4
[7:0] BD_CNT4
Bad disparity 8-bit error counters
for Lane 4.
0x0
R
0x49D BD_CNT5
[7:0] BD_CNT5
Bad disparity 8-bit error counters
for Lane 5.
0x0
R
0x49E
BD_CNT6
[7:0] BD_CNT6
Bad disparity 8-bit error counters
for Lane 6.
0x0
R
0x49F
BD_CNT7
[7:0] BD_CNT7
Bad disparity 8-bit error counters
for Lane 7.
0x0
R
0x4A0 NIT_CNT0
[7:0] NIT_CNT0
Not in table 8-bit error counters
for Lane 0.
0x0
R
0x4A1 NIT_CNT1
[7:0] NIT_CNT1
Not in table 8-bit error counters
for Lane 1.
0x0
R
0x4A2 NIT_CNT2
[7:0] NIT_CNT2
Not in table 8-bit error counters
for Lane 2.
0x0
R
0x4A3 NIT_CNT3
[7:0] NIT_CNT3
Not in table 8-bit error counters
for Lane 3.
0x0
R
0x4A4 NIT_CNT4
[7:0] NIT_CNT4
Not in table 8-bit error counters
for Lane 4.
0x0
R
Rev. D | Page 118 of 126
Data Sheet
Hex.
Addr.
Name
AD9163
Description
Reset Access
0x4A5 NIT_CNT5
Bits Bit Name
[7:0] NIT_CNT5
Settings
Not in table 8-bit error counters
for Lane 5.
0x0
R
0x4A6 NIT_CNT6
[7:0] NIT_CNT6
Not in table 8-bit error counters
for Lane 6.
0x0
R
0x4A7 NIT_CNT7
[7:0] NIT_CNT7
Not in table 8-bit error counters
for Lane 7.
0x0
R
0x4A8 UEK_CNT0
[7:0] UEK_CNT0
Unexpected K character 8-bit
error counters for Lane 0.
0x0
R
0x4A9 UEK_CNT1
[7:0] UEK_CNT1
Unexpected K character 8-bit
error counters for Lane 1.
0x0
R
0x4AA UEK_CNT2
[7:0] UEK_CNT2
Unexpected K character 8-bit
error counters for Lane 2.
0x0
R
0x4AB UEK_CNT3
[7:0] UEK_CNT3
Unexpected K character 8-bit
error counters for Lane 3.
0x0
R
0x4AC UEK_CNT4
[7:0] UEK_CNT4
Unexpected K character 8-bit
error counters for Lane 4.
0x0
R
0x4AD UEK_CNT5
[7:0] UEK_CNT5
Unexpected K character 8-bit
error counters for Lane 5.
0x0
R
0x4AE UEK_CNT6
[7:0] UEK_CNT6
Unexpected K character 8-bit
error counters for Lane 6.
0x0
R
0x4AF UEK_CNT7
[7:0] UEK_CNT7
Unexpected K character 8-bit
error counters for Lane 7.
0x0
R
0x4B0 LINK_STATUS0
7
Bad disparity errors status for
Lane 0.
0x0
R
0x0
R
0x0
R
Interlane deskew status for Lane 0 0x0
(ignore this output when
NO_ILAS = 1).
R
BDE0
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
6
NIT0
Not in table errors status for
Lane 0.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
5
UEK0
Unexpected K character errors
status for Lane 0.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
4
ILD0
0 Deskew failed.
1 Deskew achieved.
3
ILS0
Initial lane synchronization status
for Lane 0 (ignore this output
when NO_ILAS = 1).
0x0
R
0x0
R
0x0
R
0 Synchronization lost.
1 Synchronization achieved.
2
CKS0
Computed checksum status for
Lane 0 (ignore this output when
NO_ILAS = 1).
0 Checksum is incorrect.
1 Checksum is correct.
1
FS0
Frame sync status for Lane 0
(ignore this output when
NO_ILAS = 1).
0 Synchronization lost.
1 Synchronization achieved.
Rev. D | Page 119 of 126
AD9163
Hex.
Addr.
Name
Data Sheet
Bits Bit Name
0
Settings
CGS0
Description
Reset Access
Code group sync status for Lane 0. 0x0
R
0 Synchronization lost.
1 Synchronization achieved.
0x4B1 LINK_STATUS1
7
BDE1
Bad disparity errors status for
Lane 1.
0x0
R
0x0
R
0x0
R
Interlane deskew status for Lane 1 0x0
(ignore this output when
NO_ILAS = 1).
R
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
6
NIT1
Not in table errors status for
Lane 1.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
5
UEK1
Unexpected K character errors
status for Lane 1.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
4
ILD1
0 Deskew failed.
1 Deskew achieved.
3
ILS1
Initial lane synchronization status
for Lane 1 (ignore this output
when NO_ILAS = 1).
0x0
R
0x0
R
0x0
R
Code group sync status for Lane 1. 0x0
R
0 Synchronization lost.
1 Synchronization achieved.
2
CKS1
Computed checksum status for
Lane 1 (ignore this output when
NO_ILAS = 1).
0 Checksum is incorrect.
1 Checksum is correct.
1
FS1
Frame sync status for Lane 1
(ignore this output when
NO_ILAS = 1).
0 Synchronization lost.
1 Synchronization achieved.
0
CGS1
0 Synchronization lost.
1 Synchronization achieved.
0x4B2 LINK_STATUS2
7
BDE2
Bad disparity errors status for
Lane 2.
0x0
R
0x0
R
0x0
R
Interlane deskew status for Lane 2 0x0
(ignore this output when
NO_ILAS = 1).
R
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
6
NIT2
Not in table errors status for
Lane 2.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
5
UEK2
Unexpected K character errors
status for Lane 2.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
4
ILD2
0 Deskew failed.
1 Deskew achieved.
Rev. D | Page 120 of 126
Data Sheet
Hex.
Addr.
Name
AD9163
Bits Bit Name
3
Settings
ILS2
Description
Reset Access
Initial lane synchronization status
for Lane 2 (ignore this output
when NO_ILAS = 1).
0x0
R
0x0
R
0x0
R
Code group sync status for Lane 2. 0x0
R
0 Synchronization lost.
1 Synchronization achieved.
2
CKS2
Computed checksum status for
Lane 2 (ignore this output when
NO_ILAS = 1).
0 Checksum is incorrect.
1 Checksum is correct.
1
FS2
Frame sync status for Lane 2
(ignore this output when
NO_ILAS = 1).
0 Synchronization lost.
1 Synchronization achieved.
0
CGS2
0 Synchronization lost.
1 Synchronization achieved.
0x4B3 LINK_STATUS3
7
BDE3
Bad disparity errors status for
Lane 3.
0x0
R
0x0
R
0x0
R
Interlane deskew status for Lane 3 0x0
(ignore this output when
NO_ILAS = 1).
R
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
6
NIT3
Not in table errors status for
Lane 3.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
5
UEK3
Unexpected K character errors
status for Lane 3.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
4
ILD3
0 Deskew failed.
1 Deskew achieved.
3
ILS3
Initial lane synchronization status
for Lane 3 (ignore this output
when NO_ILAS = 1).
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0 Synchronization lost.
1 Synchronization achieved.
2
CKS3
Computed checksum status for
Lane 3 (ignore this output when
NO_ILAS = 1).
0 Checksum is incorrect.
1 Checksum is correct.
1
FS3
Frame sync status for Lane 3
(ignore this output when
NO_ILAS = 1).
0 Synchronization lost.
1 Synchronization achieved.
0
CGS3
Code group sync status for Lane 3.
0 Synchronization lost.
1 Synchronization achieved.
0x4B4 LINK_STATUS4
7
BDE4
Bad disparity errors status for
Lane 4.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
Rev. D | Page 121 of 126
AD9163
Hex.
Addr.
Name
Data Sheet
Bits Bit Name
Settings
[2:0] ECNT_RST1
Description
Reset Access
0x7
Reset error counters for Lane 1,
active high. Counters of each lane
are addressed as follows:
R/W
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
0x482 ECNT_CTRL2
[7:6] RESERVED
Reserved.
[5:3] ECNT_ENA2
0x7
Error counters enable for Lane 2,
active high. Counters of each lane
are addressed as follows:
0x0
R
R/W
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
[2:0] ECNT_RST2
0x7
Reset error counters for Lane 2,
active high. Counters of each lane
are addressed as follows:
R/W
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
0x483 ECNT_CTRL3
[7:6] RESERVED
Reserved.
[5:3] ECNT_ENA3
0x7
Error counters enable for Lane 3,
active high. Counters of each lane
are addressed as follows:
0x0
R
R/W
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
[2:0] ECNT_RST3
Reset error counters for Lane 3,
0x7
active high. Counters of each lane
are addressed as follows:
R/W
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
0x484 ECNT_CTRL4
[7:6] RESERVED
Reserved.
[5:3] ECNT_ENA4
Error counters enable for Lane 4,
0x7
active high. Counters of each lane
are addressed as follows:
0x0
R
R/W
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
[2:0] ECNT_RST4
0x7
Reset error counters for Lane 4,
active high. Counters of each lane
are addressed as follows:
R/W
Bit 2 = unexpected K (UEK)
character error.
Bit 1 = not in table error (NIT).
Bit 0 = bad disparity error (BDE).
0x485 ECNT_CTRL5
[7:6] RESERVED
Reserved.
[5:3] ECNT_ENA5
0x7
Error counters enable for Lane 5,
active high. Counters of each lane
are addressed as follows:
Bit 2 = unexpected K (UEK)
character error.
Rev. D | Page 112 of 126
0x0
R
R/W
Data Sheet
Hex.
Addr.
Name
AD9163
Bits Bit Name
1
Settings
FS5
Description
Reset Access
Frame sync status for Lane 5
(ignore this output when
NO_ILAS = 1).
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
Code group sync status for Lane 6. 0x0
R
0 Synchronization lost.
1 Synchronization achieved.
0
CGS5
Code group sync status for Lane 5.
0 Synchronization lost.
1 Synchronization achieved.
0x4B6 LINK_STATUS6
7
BDE6
Bad disparity errors status for
Lane 6.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
6
NIT6
Not in table errors status for Lane 6.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
5
UEK6
Unexpected K character errors
status for Lane 6.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
4
ILD6
Interlane deskew status for Lane 6
(ignore this output when
NO_ILAS = 1).
0 Deskew failed.
1 Deskew achieved.
3
ILS6
Initial lane synchronization status
for Lane 6 (ignore this output
when NO_ILAS = 1).
0 Synchronization lost.
1 Synchronization achieved.
2
CKS6
Computed checksum status for
Lane 6 (ignore this output when
NO_ILAS = 1).
0 Checksum is incorrect.
1 Checksum is correct.
1
FS6
Frame sync status for Lane 6
(ignore this output when
NO_ILAS = 1).
0 Synchronization lost.
1 Synchronization achieved.
0
CGS6
0 Synchronization lost.
1 Synchronization achieved.
0x4B7 LINK_STATUS7
7
BDE7
Bad disparity errors status for
Lane 7.
0x0
R
0x0
R
0x0
R
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
6
NIT7
Not in table errors status for
Lane 7.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
5
UEK7
Unexpected K character errors
status for Lane 7.
0 Error count < ETH[7:0] value.
1 Error count ≥ ETH[7:0] value.
Rev. D | Page 123 of 126
AD9163
Hex.
Addr.
Name
Data Sheet
Bits Bit Name
4
Settings
ILD7
Description
Reset Access
Interlane deskew status for Lane 7 0x0
(ignore this output when
NO_ILAS = 1).
R
0 Deskew failed.
1 Deskew achieved.
3
ILS7
Initial lane synchronization status
for Lane 7 (ignore this output
when NO_ILAS = 1).
0x0
R
0x0
R
0x0
R
0x0
R
0 Synchronization lost.
1 Synchronization achieved.
2
CKS7
Computed checksum status for
Lane 7 (ignore this output when
NO_ILAS = 1).
0 Checksum is incorrect.
1 Checksum is correct.
1
FS7
Frame sync status for Lane 7
(ignore this output when
NO_ILAS = 1).
0 Synchronization lost.
1 Synchronization achieved.
0
CGS7
Code group sync status for Lane 7.
0 Synchronization lost.
1 Synchronization achieved.
0x4B8 JESD_IRQ_ENABLEA
0x4B9 JESD_IRQ_ENABLEB
7
EN_BDE
Bad disparity error counter.
0x0
R/W
6
EN_NIT
Not in table error counter.
0x0
R/W
5
EN_UEK
Unexpected K error counter.
0x0
R/W
4
EN_ILD
Interlane deskew.
0x0
R/W
3
EN_ILS
Initial lane sync.
0x0
R/W
2
EN_CKS
Good checksum. This is an
0x0
interrupt that compares two
checksums: the checksum that
the transmitter sent over the link
during the ILAS, and the
checksum that the receiver
calculated from the ILAS data that
the transmitter sent over the link.
Note that the checksum IRQ never
at any time looks at the checksum
that is programmed over the SPI
into Register 0x45D. The
checksum IRQ only looks at the
data sent by the transmitter, and
never looks at any data
programmed via the SPI.
R/W
1
EN_FS
Frame sync.
0x0
R/W
0
EN_CGS
Code group sync.
0x0
R/W
[7:1] RESERVED
Reserved.
0x0
R
0
Configuration mismatch (checked
0x0
for Lane 0 only). The ILAS IRQ
compares the two sets of ILAS
data that the receiver has: the ILAS
data sent over the JESD204B link by
the transmitter, and the ILAS data
programmed into the receiver via
the SPI (Register 0x450 to Register
0x45D). If the data differs, the IRQ
is triggered. Note that all of the
ILAS data (including the checksum)
is compared.
EN_ILAS
Rev. D | Page 124 of 126
R/W
Data Sheet
Hex.
Addr.
Name
0x4BA JESD_IRQ_STATUSA
0x4BB JESD_IRQ_STATUSB
0x800 HOPF_CTRL
AD9163
Bits Bit Name
Description
Reset Access
7
IRQ_BDE
Settings
Bad disparity error counter.
0x0
R/W
6
IRQ_NIT
Not in table error counter.
0x0
R/W
5
IRQ_UEK
Unexpected K error counter.
0x0
R/W
4
IRQ_ILD
Interlane deskew.
0x0
R/W
3
IRQ_ILS
Initial lane sync.
0x0
R/W
2
IRQ_CKS
Good checksum.
0x0
R/W
1
IRQ_FS
Frame sync.
0x0
R/W
0
IRQ_CGS
Code group sync.
0x0
R/W
[7:1] RESERVED
Reserved.
0x0
R
0
Configuration mismatch (checked 0x0
for Lane 0 only).
R/W
Frequency switch mode.
0x0
R/W
0x0
R
IRQ_ILAS
[7:6] HOPF_MODE
00 Reserved
01 Phase discontinuous switch.
Changes the frequency tuning
word and resets the phase
accumulator.
10 Reserved.
[5:0] RESERVED
Reserved.
Rev. D | Page 125 of 126
AD9163
Data Sheet
OUTLINE DIMENSIONS
11.05
11.00 SQ
10.95
A1 BALL
CORNER
1.285
BSC
A1 BALL
PAD CORNER
13 12 11 10 9 8 7 6 5 4 3 2 1
A
5.935
BSC
B
C
D
E
F
G
H
J
K
L
M
N
9.60
REF SQ
0.80
BSC
TOP VIEW
2.405 BSC
BOTTOM VIEW
0.70
REF
5.890 BSC
DETAIL A
*0.95 MAX
PKG-004675
SEATING
PLANE
0.36
0.31
0.26
DETAIL A
0.45
0.40
0.35
BALL DIAMETER
COPLANARITY
0.12
*COMPLIANT TO JEDEC STANDARDS MO-275-FFAC-1 WITH THE
EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
08-30-2017-B
0.35
0.30
0.25
Figure 141. 169-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-169-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD9163BBCZ
AD9163BBCZRL
AD9163-FMCC-EBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
169-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
169-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
Evaluation Board
Z = RoHS Compliant Part.
©2016–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14415-0-5/19(D)
Rev. D | Page 126 of 126
Package Option
BC-169-2
BC-169-2
工商网监
湘ICP备2023018690号
