Data Sheet
DC to 9 GHz Vector Signal Generator
AD9166
FEATURES
DC-coupled, 50 Ω matched output
Up to 4.3 dBm output power, −9.5 dBm at 9 GHz
DAC core update rate: 12.0 GSPS (guaranteed minimum) in
2× NRZ mode
Wide analog bandwidth
DC to 9.0 GHz in 2× NRZ mode (12.0 GSPS DAC update rate)
1.0 GHz to 8.0 GHz in mix mode (6.0 GSPS DAC update rate)
DC to 4.5 GHz in NRZ mode (6.0 GSPS DAC update rate)
Power dissipation of 4.88 W in 2× NRZ mode (10 GSPS DAC
update rate)
Bypassable datapath interpolation
2×, 3×, 4×, 6×, 8×, 12×, 16×, 24×
Instantaneous (complex) signal bandwidth
2.25 GHz with device clock at 5 GHz (2× interpolation)
1.8 GHz with device clock at 6 GHz (3× interpolation)
Fast frequency hopping
Integrated BiCMOS buffer amplifier
APPLICATIONS
Instrumentation: automated test equipment, electronic test
and measurement, arbitrary waveform generators
Electronic warfare: radars, jammers
Broadband communications systems
Local oscillator drivers
GENERAL DESCRIPTION
The AD91661 is a high performance, wideband, on-chip vector
signal generator composed of a high speed JESD204B serializer/
deserializer (SERDES) interface, a flexible 16-bit digital datapath, a
inphase/quadrature (I/Q) digital-to-analog converter (DAC)
core, and an integrated differential to single-ended output
buffer amplifier, matched to a 50 Ω load up to 10 GHz.
The DAC core is based on a quad-switch architecture, which is
configurable to increase the effective DAC core update rate of
up to 12.8 GSPS from a 6.4 GHz DAC sampling clock, with an
analog output bandwidth of true dc to 9.0 GHz, typically. The
digital datapath includes multiple interpolation filter stages, a
direct digital synthesizer (DDS) block with multiple
numerically controlled oscillators (NCOs) supporting fast
frequency hopping (FFH), and additional FIR85 and inverse
sinc filter stages to allow flexible spectrum planning.
The differential to single-ended buffer eliminates the need for a
wideband balun, and supports the full analog output bandwidth
of the DAC core. DC coupling the output allows baseband wave1
form generation without the need for external bias tees or similar
circuitry, which makes the AD9166 uniquely suited for the most
demanding high speed ultrawideband RF transmit applications.
The various filter stages enable the AD9166 to be configured for
lower data rates, while maintaining higher DAC clock rates to
ease the filtering requirements and reduce the overall system size,
weight, and power.
The data interface receiver consists of up to eight JESD204B
SERDES lanes, each capable of carrying up to 12.5 Gbps. To
enable maximum flexibility, the receiver is fully configurable
according to the data rate, number of SERDES lanes, and lane
mapping required by the JESD204B transmitter.
In 2× nonreturn-to-zero (NRZ) mode of operation (with FIR85
enabled), the AD9166 can reconstruct RF carriers from true dc
to the edge of the third Nyquist zone, or an analog bandwidth of
true dc up to 9 GHz.
In mix mode, the AD9166 can reconstruct RF carriers in the
second and third Nyquist zones while consuming lower power
and maintaining a performance comparable to 2× NRZ mode.
In baseband modes, such as return-to-zero (RZ) and 1× NRZ,
the AD9166 is ideal to reconstruct RF carriers from true dc to
the edge of the first Nyquist zone while consuming lower power
compared to 2× NRZ mode.
The quadrature DDS block can be configured as a digital
upconverter to upconvert I/Q data samples to the desired
location across the spectrum, in all three Nyquist zones.
The DDS also consists of a bank of 32 numerically controlled
oscillators (NCOs), each with its own 32-bit phase accumulator.
When combined with a 100 MHz serial peripheral interface (SPI),
the DDS allows a phase coherent FFH, with a phase settling
time as low as 300 ns.
The AD9166 is configured using a common SPI interface that
monitors the status of all registers. The AD9166 is offered in a
324-ball, 15 mm × 15 mm, 0.8 mm pitch BGA_ED package.
PRODUCT HIGHLIGHTS
1.
2.
3.
High dynamic range and signal reconstruction bandwidth
supports RF signal synthesis of up to 9 GHz.
Fully supports zero IF and other dc-coupled applications.
Up to an eight-lane JESD204B SERDES interface, with
various features to allow flexibility when interfacing to a
JESD204B transmitter.
Protected by U.S. Patents 6,842,132 and 7,796,971.
Rev. 0
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Tel: 781.329.4700
©2020 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD9166
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
JESD204B Overview .................................................................. 29
Applications ....................................................................................... 1
Physical Layer ............................................................................. 31
General Description ......................................................................... 1
Data Link Layer .......................................................................... 34
Product Highlights ........................................................................... 1
Transport Layer .......................................................................... 42
Revision History ............................................................................... 2
JESD204B Test Modes ............................................................... 44
Functional Block Diagram .............................................................. 3
JESD204B Error Monitoring..................................................... 46
Specifications..................................................................................... 4
Hardware Considerations ......................................................... 48
DC Specifications ......................................................................... 4
Main Digital Datapath ................................................................... 49
Power Supply DC Specifications ................................................ 5
Data Format ................................................................................ 49
Device Input Clock Rate and DAC Update Rate Specifications
......................................................................................................... 7
Interpolation Filters ................................................................... 49
JESD204B Interface Specifications ............................................. 8
Inverse Sinc ................................................................................. 55
Input Data Rate and Bandwidth Specifications........................ 9
Downstream Protection ............................................................ 55
Pipeline Delay and Latency Uncertainty Specifications .......... 9
Datapath PRBS ........................................................................... 56
AC Specifications........................................................................ 10
Datapath PRBS IRQ ................................................................... 56
CMOS Pin Specifications .......................................................... 11
Interrupt Request Operation ........................................................ 57
Timing Specifications ................................................................ 12
Interrupt Service Routine .......................................................... 57
Absolute Maximum Ratings.......................................................... 14
Applications Information .............................................................. 58
Reflow Profile .............................................................................. 14
Hardware Considerations ......................................................... 58
Thermal Management ............................................................... 14
Analog Interface Considerations .................................................. 61
Thermal Resistance .................................................................... 14
Analog Modes of Operation ..................................................... 61
ESD Caution ................................................................................ 14
Clock Input.................................................................................. 62
Pin Configuration and Function Descriptions ........................... 15
Shuffle Mode ............................................................................... 63
Typical Performance Characteristics ........................................... 18
Voltage Reference and Full-Scale Current (FSC) ................... 63
AC Performance (2× NRZ (FIR85) Mode) ............................. 18
Analog Output ............................................................................ 64
LTE Performance (2× NRZ (FIR85) Mode) ........................... 23
Temperature Sensors .................................................................. 65
802.11AC Performance (2× NRZ (FIR85) Mode) ................. 24
Start-Up Sequence .......................................................................... 67
Terminology .................................................................................... 25
Register Summary: DAC ............................................................... 70
Theory of Operation ...................................................................... 26
Register Details: DAC Register Map ............................................ 79
Serial Port Operation ..................................................................... 27
Register Summary: Amplifier ..................................................... 135
Data Format ................................................................................ 27
Register Details: Amplifier Register Map .................................. 136
Serial Port Pin Descriptions ...................................................... 27
Outline Dimensions ..................................................................... 138
Serial Port Options ..................................................................... 28
Ordering Guide ........................................................................ 138
Digital Modulation ..................................................................... 52
JESD204B Serial Data Interface .................................................... 29
REVISION HISTORY
7/2020—Revision 0: Initial Version
Rev. 0 | Page 2 of 138
Data Sheet
AD9166
FUNCTIONAL BLOCK DIAGRAM
AD9166
NRZ RZ MIX
SERDIN0±
SERDIN7±
SYNCOUT±
VREF
FIR85
HB
2×
JESD
NCO
INV
SINC
SYSREF±
HB
2×
HB
3×
HB
2×,
4×,
8×
TO JESD
TO DATAPATH
TX_ENABLE
Rev. 0 | Page 3 of 138
DAC
CORE
WIDEBAND
AMP
RFOUT
CLOCK
DISTRIBUTION
NOTES
1. FSC IS FULL-SCALE CURRENT.
2. ICM IS THE INPUT COMMON-MODE CURRENT OF THE BUFFER AMPLIFIER.
Figure 1.
ICM
FSC
CLK±
20810-001
SPI
DATA
LATCH
SDIO
SDO
CS_AMP/CS_DAC
SCLK
VREF
ISET
IRQ
MATCHING
NETWORK
RESET
AD9166
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
DAC_2P5_AN = 2.5 V, DAC_1P2_AN = DAC_1P2_CLK = 1.2 V, DAC_N1P2_AN = −1.2 V, DAC_1P2_DIG = 1.2 V, VDD_IO = 2.5 V,
DAC_1P2_SER = 1.2 V, DAC_3P3_SYNC = 3.3 V, AMP_5V_IN = 5.0 V, AMP_3P3_OUT = 3.3 V, AMP_3P3 = 3.3 V, AMP_N5 = −5.0 V,
DAC output full-scale current (IOUTFS) = 40 mA, and TA = −40°C to +85°C, unless otherwise noted. 50 Ω matched output.
Table 1.
Parameter
RESOLUTION
DAC ANALOG OUTPUT
Power-Up Delay
Gain Error (with Internal Reference)
Full-Scale Output Current (IOUTFS)
Minimum
Maximum
AMPLIFIER ANALOG OUTPUT
Maximum Full-Scale Power
DC
9 GHz
DEVICE CLOCK INPUT (CLK+, CLK−)
Differential Input Power
Common-Mode Voltage
Input Impedance1
Maximum Input Frequency (fCLK)
TEMPERATURE SENSOR
Amplifier Sensor Accuracy2
DAC Sensor Accuracy3
ANALOG SUPPLY VOLTAGES
DAC_2P5_AN
DAC_1P2_AN4
DAC_1P2_CLK4
DAC_N1P2_AN
AMP_5V_IN
AMP_3P3_OUT
AMP_N5
AMP_3P3
DIGITAL SUPPLY VOLTAGES
DAC_1P2_DIG
VDD_IO5
SERDES SUPPLY VOLTAGES
DAC_1P2_SER
DAC_3P3_SYNC
Test Conditions/Comments
Min
16
From DAC output off to enabled
DAC reference current setting resistor (RSET) = 9.76 kΩ
RSET = 9.76 kΩ
7.37
35.8
Typ
Max
Unit
Bits
10
ns
−1.7
%
8
38.76
8.57
41.3
mA
mA
Measured with full-scale output current set to its typical
maximum
4.3
−9.5
FIR85 enabled (2× NRZ)
Load resistance (RLOAD) = 90 Ω differential on chip
AC-coupled
3 GSPS input clock
See Table 3 for more details
−20
0
0.6
90
6400
dBm
dBm
+10
°C
°C
±5
±5
1
2.375
1.14
1.14
−1.26
4.75
3.135
−5.25
3.135
2.5
1.2
1.2
−1.2
5
3.3
−5
3.3
2.625
1.326
1.326
−1.14
5.25
3.465
−4.75
3.465
V
V
V
V
V
V
V
V
1.14
1.71
1.2
2.5
1.326
3.465
V
V
1.14
3.135
1.2
3.3
1.326
3.465
V
V
See the Clock Input section for more details.
The temperature sensor of the amplifier is a more accurate representation of TJ, but requires one-point calibration.
3
Do not use the DAC temperature sensor reading to monitor TJ. Use as a reference only.
4
For the lowest noise performance, use a separate power supply filter network for the DAC_1P2_CLK and the DAC_1P2_AN pins.
5
VDD_IO can range from 1.8 V to 3.3 V, with ±5% tolerance.
2
Rev. 0 | Page 4 of 138
dBm
V
Ω
MHz
Data Sheet
AD9166
POWER SUPPLY DC SPECIFICATIONS
IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted. FIR85 is the finite impulse response with 85 dB digital attenuation.
Table 2.
Parameter
8 LANES, 2× INTERPOLATION (80%), 3 GSPS
Analog Supply Currents
DAC_2P5_AN
DAC_1P2_AN
DAC_1P2_CLK
DAC_N1P2_AN
AMP_5V_IN
AMP_3P3_OUT
AMP_N5
AMP_3P3
Digital Supply Currents
DAC_1P2_DIG
VDD_IO1
DAC_1P2_SER
DAC_3P3_SYNC
8 LANES, 6× INTERPOLATION (80%), 3 GSPS
Analog Supply Currents
DAC_2P5_AN
DAC_1P2_AN
DAC_1P2_CLK
DAC_N1P2_AN
AMP_5V_IN
AMP_3P3_OUT
AMP_N5
AMP_3P3
Digital Supply Currents
DAC_1P2_DIG
VDD_IO1
DAC_1P2_SER
DAC_3P3_SYNC
NCO ONLY MODE, 5 GSPS
Analog Supply Currents
DAC_2P5_AN
DAC_1P2_AN
DAC_1P2_CLK
DAC_N1P2_AN
AMP_5V_IN
AMP_3P3_OUT
AMP_N5
AMP_3P3
Digital Supply Currents
DAC_1P2_DIG
VDD_IO1
DAC_1P2_SER
DAC_3P3_SYNC
8 LANES, 4× INTERPOLATION (80%), 5 GSPS
Analog Supply Currents
DAC_2P5_AN
DAC_1P2_AN
DAC_1P2_CLK
DAC_N1P2_AN
AMP_5V_IN
Test Conditions/Comments
NCO on, FIR85 on
Min
−117
VDD_IO = 2.5 V
Typ
Max
Unit
53.5
1
239
−111.1
169.9
65.1
187.8
21.2
57
111
255
182
70.7
209
23
mA
μA
mA
mA
mA
mA
mA
mA
545
2.5
567.4
9.1
611
2.7
627
11
mA
mA
mA
mA
NCO on, FIR85 on
VDD_IO = 2.5 V
−120
VDD_IO = 2.5 V
53.5
1.4
238.1
−111.1
169.7
65.0
195.1
21.1
mA
μA
mA
mA
mA
mA
mA
mA
632.4
0.025
614.2
9.2
mA
mA
mA
mA
47.6
0
359
−104.9
169.7
65.1
194.9
21.1
63
109
382
182
71
216
23
mA
μA
mA
mA
mA
mA
mA
mA
446.9
2.5
3.0
0.34
493
2.7
8.5
0.44
mA
mA
mA
mA
55.5
0.1
358.9
−120.0
166.8
59
123
382
mA
μA
mA
mA
mA
NCO on, FIR85 off (unless otherwise noted for this test)
−126
Rev. 0 | Page 5 of 138
178
AD9166
Parameter
AMP_3P3_OUT
AMP_N5
AMP_3P3
Digital Supply Currents
VDD_IO1
DAC_1P2_DIG
DAC_1P2_SER
DAC_3P3_SYNC
8 LANES, 4× INTERPOLATION (80%), 5.8 GSPS
Analog Supply Currents
DAC_2P5_AN
DAC_1P2_AN
DAC_1P2_CLK
DAC_N1P2_AN
AMP_5V_IN
AMP_3P3_OUT
AMP_N5
AMP_3P3
Digital Supply Currents
VDD_IO1
DAC_1P2_DIG
DAC_1P2_SER
DAC_3P3_SYNC
8 LANES, 3× INTERPOLATION (80%), 4.5 GSPS
Analog Supply Currents
DAC_2P5_AN
DAC_1P2_AN
DAC_1P2_CLK
DAC_N1P2_AN
AMP_5V_IN
AMP_3P3_OUT
AMP_N5
AMP_3P3
Digital Supply Currents
VDD_IO1
DAC_1P2_DIG
DAC_1P2_SER
DAC_3P3_SYNC
POWER DISSIPATION
Amplifier, Standalone
DAC, Standalone, 3 GSPS
2× NRZ Mode, 6×, FIR85 Enabled, NCO On
NRZ Mode, 24×, FIR85 Disabled, NCO On
DAC, Standalone, 5 GSPS
NRZ Mode, 8×, FIR85 Disabled, NCO On
NRZ Mode, 16×, FIR85 Disabled, NCO On
DAC, Standalone, 10 GSPS
2× NRZ Mode, 6×, FIR85 Enabled, NCO On
Total, Amplifier and DAC, 10 GSPS
1
Data Sheet
Test Conditions/Comments
Min
Typ
65.1
185.9
21.3
Max
71
207
23
Unit
mA
mA
mA
2.5
705.1
749.1
962.7
541.6
9.2
2.7
769
819
1044
586
11
mA
mA
mA
mA
mA
mA
53.5
0
406
−111.1
169.6
65.0
194.5
21.2
57
68
430
182
71
216
23
mA
μA
mA
mA
mA
mA
mA
mA
2.5
1090
575.5
9.0
2.7
1200
622
11
mA
mA
mA
mA
53.5
0
330.5
−111.1
169.7
65.0
195.0
21.2
57
68
352
182
71
216
23
mA
μA
mA
mA
mA
mA
mA
mA
2.5
1025.1
579.4
9.2
1115
626
11
mA
mA
mA
mA
2.33
2.43
W
Using 80%, 3× filter, eight-lane JESD204B
Using 80%, 2× filter, one-lane JESD204B
2.0
1.2
2.21
1.31
W
W
Using 80%, 2× filter, eight-lane JESD204B
Using 80%, 2× filter, eight-lane JESD204B
2.08
1.99
2.30
2.18
W
W
Using 80%, 3× filter, eight-lane JESD204B
Using 80%, 3× filter, eight-lane JESD204B
2.55
4.88
2.85
W
W
VDD_IO = 2.5 V
NCO on, FIR85 off
NCO off, FIR85 on
NCO on, FIR85 on
NCO on, FIR85 on
−117
VDD_IO = 2.5 V
NCO on, FIR85 on
−117
VDD_IO = 2.5 V
VDD_IO can range from 1.8 V to 3.3 V, with ±5% tolerance.
Rev. 0 | Page 6 of 138
Data Sheet
AD9166
DEVICE INPUT CLOCK RATE AND DAC UPDATE RATE SPECIFICATIONS
DAC_2P5_AN = 2.5 V, DAC_1P2_AN = DAC_1P2_CLK = 1.2 V, DAC_N1P2_AN = −1.2 V, DAC_1P2_DIG = 1.2 V, VDD_IO = 2.5 V,
DAC_1P2_SER = 1.2 V, DAC_3P3_SYNC = 3.3 V, AMP_5V_IN = 5.0 V, AMP_3P3_OUT = 3.3 V, AMP_3P3 = 3.3 V, AMP_N5 = −5.0 V,
IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted.
Maximum guaranteed speed using the temperature and voltage conditions shown in Table 3, where DAC_1P2_x includes DAC_1P2_AN,
DAC_1P2_CLK, DAC_1P2_DIG, and DAC_1P2_SER. Any device clock speed over 5.1 GHz requires a maximum junction temperature not
exceeding 105°C to avoid damage to the device. See Table 11 for details on maximum junction temperature permitted for certain clock speeds.
Table 3.
Parameter
MAXIMUM INPUT CLOCK RATE (fCLK)
DAC_1P2_x = 1.2 V ± 5%
DAC_1P2_x = 1.2 V ± 2%
DAC_1P2_x = 1.3 V ± 2%
DAC UPDATE RATE (fDAC)
Minimum
Maximum
Adjusted2
1
2
Test Conditions/Comments1
Min
TJ_DAC_MAX = 25°C
TJ_DAC_MAX = 85°C
TJ_DAC_MAX = 105°C
TJ_DAC_MAX = 25°C
TJ_DAC_MAX = 85°C
TJ_DAC_MAX = 105°C
TJ_DAC_MAX = 25°C
TJ_DAC_MAX = 85°C
T_DAC_MAX = 105°C
6.0
5.6
5.4
6.1
5.8
5.6
6.4
6.2
6.0
DAC_1P2_x = 1.3 V ± 2%
DAC_1P2_x = 1.3 V ± 2%, FIR85 (2× NRZ) enabled
DAC_1P2_x = 1.3 V ± 2%
6
12
6
Typ
Max
Unit
GHz
GHz
GHz
GHz
GHz
GHz
GHz
GHz
GHz
1.5
6.4
12.8
6.4
GSPS
GSPS
GSPS
GSPS
TJ_DAC_MAX is the maximum junction temperature measured using the DAC temperature sensor.
The adjusted DAC update rate is calculated as follows: when FIR85 is disabled, fDAC is divided by the minimum required interpolation factor. For the AD9166, the
minimum interpolation factor is 1. Therefore, with fDAC = 6.0 GSPS, fDAC adjusted = 6.0 GSPS. When FIR85 is enabled, which puts the device into 2× NRZ mode, fDAC = 2 ×
fCLK, and the minimum interpolation is 2× (interpolation value). Thus, for the AD9166, with FIR85 enabled and fCLK = 6 GHz, fDAC = 12.0 GSPS, minimum interpolation = 2×, and the
adjusted DAC update rate = 6.0 GSPS.
Rev. 0 | Page 7 of 138
AD9166
Data Sheet
JESD204B INTERFACE SPECIFICATIONS
DAC_2P5_AN = 2.5 V, DAC_1P2_AN = DAC_1P2_CLK = 1.2 V, DAC_N1P2_AN = −1.2 V, DAC_1P2_DIG = 1.2 V, VDD_IO = 2.5 V,
DAC_1P2_SER = 1.2 V, DAC_3P3_SYNC = 3.3 V, AMP_5V_IN = 5.0 V, AMP_3P3_OUT = 3.3 V, AMP_3P3 = 3.3 V, AMP_N5 = −5.0 V,
IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted. VTT is the termination voltage.
Table 4.
Parameter
SERIAL INTERFACE SPEED
Half Rate
Full Rate
Oversampling
2× Oversampling
JESD204B DATA INPUTS
Input Leakage Current
Logic High
Logic Low
Unit Interval
Common-Mode Voltage
Differential Voltage
VTT Source Impedance
Differential Impedance
Differential Return Loss
Common-Mode Return Loss
SYSREF± INPUT
Differential Impedance
DIFFERENTIAL OUTPUTS (SYNCOUT±)2
Output Differential Voltage
Output Offset Voltage
1
2
Symbol
Test Conditions/Comments
Guaranteed operating range per each lane
Min
Typ
6
3
1.5
0.750
TA = 25°C
Input level = 1.2 V ± 0.25 V, VTT = 1.2 V
Input level = 0 V
UI
VRCM
VDIFF
ZTT
ZRDIFF
RLRDIF
RLRCM
AC-coupled, VTT = DAC_1P2_SER1
At dc
At dc
Max
Unit
12.5
6.25
3.125
1.5625
Gbps
Gbps
Gbps
Gbps
1333
+1.85
1050
30
120
μA
μA
ps
V
mV
Ω
Ω
dB
dB
10
−4
80
−0.05
110
80
100
8
6
121
Ω
Driving 100 Ω differential load
VOD
VOS
350
1.15
As measured on the input side of the ac coupling capacitor.
IEEE Standard 1596.3 LVDS compatible.
Rev. 0 | Page 8 of 138
420
1.2
450
1.27
mV
V
Data Sheet
AD9166
INPUT DATA RATE AND BANDWIDTH SPECIFICATIONS
DAC_2P5_AN = 2.5 V, DAC_1P2_AN = DAC_1P2_CLK = 1.2 V, DAC_N1P2_AN = −1.2 V, DAC_1P2_DIG = 1.2 V, VDD_IO = 2.5 V,
DAC_1P2_SER = 1.2 V, DAC_3P3_SYNC = 3.3 V, AMP_5V_IN = 5.0 V, AMP_3P3_OUT = 3.3 V, AMP_3P3 = 3.3 V, AMP_N5 = −5.0 V,
IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted.
Table 5.
Parameter
INPUT DATA RATE
Complex1
Real
INSTANTANEOUS SIGNAL BANDWIDTH2
Complex
Real
ANALOG BANDWIDTH
2x NRZ (FIR85 Enabled)
Minimum
Maximum
Mix Mode (FIR85 Disabled)
Minimum
Maximum
NRZ (FIR85 Disabled)
Minimum
Maximum3
1
2
3
Test Conditions/Comments
Min
Interpolation > 1×
Interpolation = 1×
0.15
0.3
Typ
fCLK = 5 GHz, interpolation = 2×
fCLK = 6 GHz, interpolation = 3×
fCLK = 5 GHz, interpolation = 1×
Max
Unit
2.5
5.0
GSPS
GSPS
2.25
1.8
2.5
GHz
GHz
GHz
fDAC = 12.0 GSPS
DC
9.0
GHz
GHz
1.0
8.0
GHz
GHz
DC
4.5
GHz
GHz
fDAC = 6.0 GSPS
fDAC = 6.0 GSPS
The complex data rate is the combined rate for both I and Q.
Interpolation filter bandwidth set to 90%.
Limited by the available output power due to sinc roll-off. See Figure 88 for more details.
PIPELINE DELAY AND LATENCY UNCERTAINTY SPECIFICATIONS
DAC_2P5_AN = 2.5 V, DAC_1P2_AN = DAC_1P2_CLK = 1.2 V, DAC_N1P2_AN = −1.2 V, DAC_1P2_DIG = 1.2 V, VDD_IO = 2.5 V,
DAC_1P2_SER = 1.2 V, DAC_3P3_SYNC = 3.3 V, AMP_5V_IN = 5.0 V, AMP_3P3_OUT = 3.3 V, AMP_3P3 = 3.3 V, AMP_N5 = −5.0 V,
IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted.
Table 6.
Parameter1
JESD204B LINK LATENCY
Fixed
Variable
JESD204B TO DATAPATH INTERFACE LATENCY
DATAPATH PIPELINE DELAY3
SYSREF± to LOCAL MULTIFRAME CLOCKS (LMFC) DELAY
DETERMINISTIC LATENCY UNCERTAINTY
JED204B Subclass 0
JED204B Subclass 14
Test Conditions/Comments
NCO only, FIR85 off, inverse sinc off
JED204B Subclass 1
Min
Typ
Max
Unit
12
2
PCLK2 cycles
PCLK2 cycles
PCLK2 cycle
fCLK cycles
fCLK cycles
1
48
4
32
4
1
fCLK cycles
fCLK cycles
The total latency through the device is calculated as follows:
Total Latency = Fixed Latency + Variable Latency + Interface Latency + Datapath Pipeline Delay.
2
PCLK is the internal processing clock for the AD9166 and equals the lane rate ÷ 40.
3
See Table 33 for pipeline delay (latency) values across different datapath configurations.
4
The SYSREF± signal input is sampled at a rate of fCLK/4, which leads to up to 4 fCLK cycles of deterministic latency uncertainty, provided that the setup and hold times for
sampling SYSREF± are met according to Table 10. The deterministic latency uncertainty can be further improved, using Register 0x037 and Register 0x038 to read the
exact clock cycle that was used to sample SYSREF±. See the SYSREF± Signal section for more details.
Rev. 0 | Page 9 of 138
AD9166
Data Sheet
AC SPECIFICATIONS
DAC_2P5_AN = 2.5 V, DAC_1P2_AN = DAC_1P2_CLK = 1.2 V, DAC_N1P2_AN = −1.2 V, DAC_1P2_DIG = 1.2 V, VDD_IO = 2.5 V,
DAC_1P2_SER = 1.2 V, DAC_3P3_SYNC = 3.3 V, AMP_5V_IN = 5.0 V, AMP_3P3_OUT = 3.3 V, AMP_3P3 = 3.3 V, AMP_N5 = −5.0 V.
IOUTFS = 20 mA, digital scale = 0 dBFS, fDAC = 12.0 GSPS, FIR85 enabled, TA = 25°C, unless otherwise noted. fOUT is output frequency.
Table 7.
Parameter
SPURIOUS-FREE DYNAMIC RANGE (SFDR)1
Single Tone
fOUT = 51 MHz
fOUT = 451 MHz
fOUT = 1051 MHz
fOUT = 2051 MHz
fOUT = 4051 MHz
fOUT = 6051 MHz
fOUT = 9051 MHz
Single Tone, IOUTFS = 40 mA
fOUT = 51 MHz
fOUT = 451 MHz
fOUT = 1051 MHz
fOUT = 2051 MHz
fOUT = 4051 MHz
fOUT = 6051 MHz
fOUT = 9051 MHz
ADJACENT CHANNEL LEAKAGE RATIO (ACLR)
Single-Carrier Long-Term Evolution (LTE)
fOUT = 849 MHz
fOUT = 1865 MHz
fOUT = 2150 MHz
fOUT = 2680 MHz
fOUT = 3380 MHz
fOUT = 3680 MHz
Single-Carrier IEEE 802.11AC
fOUT = 5160 MHz
fOUT = 5865 MHz
INTERMODULATION DISTORTION (IMD)
Two-Tone Test
fOUT = 51 MHz
fOUT = 451 MHz
fOUT = 1051 MHz
fOUT = 2051 MHz
fOUT = 4051 MHz
fOUT = 6051 MHz
fOUT = 9051 MHz
Two-Tone Test, IOUTFS = 40 mA
fOUT = 51 MHz
fOUT = 451 MHz
fOUT = 1051 MHz
fOUT = 2051 MHz
fOUT = 4051 MHz
fOUT = 6051 MHz
fOUT = 9051 MHz
Test Conditions/Comments
Min
Typ
Max
Unit
−83
−66
−54
−46
−38
−42
−35
dBc
dBc
dBc
dBc
dBc
dBc
dBc
−69
−55
−43
−33
−25
−29
−20
dBc
dBc
dBc
dBc
dBc
dBc
dBc
−70
−70
−71
−71
−69
−67
dBc
dBc
dBc
dBc
dBc
dBc
−60
−59
dBc
dBc
−78
−65
−59
−51
−37
−55
−43
dBc
dBc
dBc
dBc
dBc
dBc
dBc
−75
−60
−55
−49
−31
−38
−32
dBc
dBc
dBc
dBc
dBc
dBc
dBc
First adjacent channel, −6 dBFS
First adjacent channel
Rev. 0 | Page 10 of 138
Data Sheet
AD9166
Parameter
NOISE SPECTRAL DENSITY (NSD)
fOUT = 537 MHz
fOUT = 1044 MHz
fOUT = 2062 MHz
fOUT = 3791 MHz
fOUT = 4095 MHz
fOUT = 5011 MHz
fOUT = 5926 MHz
SINGLE SIDEBAND PHASE NOISE AT OFFSET
1 kHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
10 MHz Offset
1
Test Conditions/Comments
Single tone, IOUTFS = 40 mA
Min
Typ
Max
Unit
−157
−157
−157
−154
−157
−153
−150
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−110.2
−134.8
−140.4
−149.0
−154.0
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fOUT = 3600 MHz, fDAC = 12,042.24 MSPS
See the Clock Input section for more details on optimizing SFDR and reducing the image of the fundamental with clock input tuning.
CMOS PIN SPECIFICATIONS
DAC_2P5_AN = 2.5 V, DAC_1P2_AN = DAC_1P2_CLK = 1.2 V, DAC_N1P2_AN = −1.2 V, DAC_1P2_DIG = 1.2 V, VDD_IO = 2.5 V,
DAC_1P2_SER = 1.2 V, DAC_3P3_SYNC =3.3 V, AMP_5V_IN = 5.0 V, AMP_3P3_OUT = 3.3 V, AMP_3P3 = 3.3V, AMP_N5 = −5.0 V,
IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted. CS_x refers to CS_AMP and CS_DAC.
Table 8.
Parameter
INPUTS (SDIO, SCLK, CS_x, RESET, TX_ENABLE)
Voltage Input
High
Low
Current Input
High
Low
OUTPUTS (SDIO, SDO)
Voltage Output
High
Low
Current Output
High
Low
Symbol
Test Comments/Conditions
Min
VIH
VIL
1.8 V ≤ VDD_IO ≤ 2.5 V
1.8 V ≤ VDD_IO ≤ 2.5 V
0.7 × VDD_IO
IIH
IIL
VOH
VOL
Typ
Max
Unit
0.3 × VDD_IO
V
V
75
−150
1.8 V ≤ VDD_IO ≤ 3.3 V
1.8 V ≤ VDD_IO ≤ 3.3 V
IOH
IOL
0.8 × VDD_IO
0.2 × VDD_IO
4
4
Rev. 0 | Page 11 of 138
μA
μA
V
V
mA
mA
AD9166
Data Sheet
TIMING SPECIFICATIONS
Serial Port
DAC_2P5_AN = 2.5 V, DAC_1P2_AN = DAC_1P2_CLK = 1.2 V, DAC_N1P2_AN = −1.2 V, DAC_1P2_DIG = 1.2 V, VDD_IO = 2.5 V,
DAC_1P2_SER = 1.2 V, DAC_3P3_SYNC =3.3 V, AMP_5V_IN = 5.0 V, AMP_3P3_OUT = 3.3 V, AMP_3P3 = 3.3V, AMP_N5 = −5.0 V,
IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted. CS_x refers to CS_AMP and CS_DAC.
Table 9.
Parameter
WRITE OPERATION
Maximum SCLK Clock Rate
SCLK Clock High
SCLK Clock Low
SDIO to SCLK Setup Time
SCLK to SDIO Hold Time
CS_x to SCLK Setup Time
SCLK to CS_x Hold Time
READ OPERATION
SCLK Clock Rate
SCLK Clock High
SCLK Clock Low
SDIO to SCLK Setup Time
SCLK to SDIO Hold Time
CS_x to SCLK Setup Time
SCLK to SDIO (or SDO) Data Valid Time
CS_x to SDIO (or SDO) Output Valid to High-Z
Symbol
fSCLK, 1/tSCLK
tPWH
tPWL
tDS
tDH
tS
tH
Test Comments/Conditions
See Figure 47
SCLK = 20 MHz
SCLK = 20 MHz
Min
100
2.1
4.3
2.6
3.5
9
9
Typ
Max
Unit
MHz
ns
ns
ns
ns
ns
ns
2
1.5
2.53
6.7
See Figure 46
fSCLK, 1/tSCLK
tPWH
tPWL
tDS
tDH
tS
tDV
20
Not shown in Figure 46
Not shown in Figure 46
Not shown in Figure 46
Not shown in Figure 46
Not shown in Figure 46
Not shown in Figure 46
Rev. 0 | Page 12 of 138
20
20
10
5
10
12
21
MHz
ns
ns
ns
ns
ns
ns
ns
Data Sheet
AD9166
SYSREF±
DAC_2P5_AN = 2.5 V, DAC_1P2_AN = DAC_1P2_CLK = 1.2 V, DAC_N1P2_AN = −1.2 V, DAC_1P2_DIG = 1.2 V, VDD_IO = 2.5 V,
DAC_1P2_SER = 1.2 V, DAC_3P3_SYNC = 3.3 V, AMP_5V_IN = 5.0 V, AMP_3P3_OUT = 3.3 V, AMP_3P3 = 3.3 V, AMP_N5 = −5.0 V,
IOUTFS = 40 mA, TA = −40°C to +85°C, unless otherwise noted.
Table 10.
Parameter
SYSREF±2
Differential Swing = 1.0 V
Minimum Setup Time, tSYSS
Minimum Hold Time, tSYSH
2
AC-coupled
DC-coupled, common-mode voltage = 0 V
DC-coupled, common-mode voltage = 1.25 V
AC-coupled
DC-coupled, common-mode voltage = 0 V
DC-coupled, common-mode voltage = 1.25 V
Min
Typ
65
45
68
19
5
51
Max1
Unit
ps
ps
ps
ps
ps
ps
The maximum setup and hold times can be inferred from the data sheet for the 11 mm × 11 mm variant of the AD9164, under the assumption that the variations due
to difference in device laminate between the AD9166 and the AD9164 are minimal.
The SYSREF± pulse must have a duration longer than the device sample and hold time, plus four additional device clock cycles. For more information, refer to the
SYSREF± Signal section.
tSYSS
tSYSH
SYSREF+
CLK+
MIN 4 CLOCK EDGES
Figure 2. SYSREF± to Device Clock Timing Diagram (Only SYSREF+ and CLK+ Shown)
Rev. 0 | Page 13 of 138
20810-002
1
Test Conditions/Comments
AD9166
Data Sheet
ABSOLUTE MAXIMUM RATINGS
REFLOW PROFILE
Table 11.
Parameter
Supply Pins
DAC_1P2_AN, DAC_1P2_CLK,
DAC_1P2_DIG, DAC_1P2_SER
to GND
DAC_2P5_AN to GND
DAC_N1P2_AN to GND
VDD_IO, DAC_3P3_SYNC,
AMP_3P3_OUT, AMP_3P3 to
GND
AMP_5V_IN to GND
AMP_N5 to GND
Input/Output Pins
RESET, IRQ, CS_AMP, CS_DAC ,
SCLK, SDIO, SDO to GND
SYNCOUT±
SERDINx±
SYSREF±
CLK± to GND
ISET, VREF to DAC_VBGNEG
Junction Temperature1
DAC Core (TJ_DAC)
fCLK > 5.1 GHz
fCLK ≤ 5.1 GHz
Amplifier (TJ_AMP)
Peak Reflow
Storage Temperature Range
1
The AD9166 reflow profile is in accordance with the JEDEC
JESD204B criteria for Pb-free devices. The maximum reflow
temperature is 260°C.
Rating
−0.3 V to +1.326 V
THERMAL MANAGEMENT
−0.3 V to +2.625 V
−1.26 V to +0.3 V
−0.3 V to +3.465 V
The AD9166 is a high-power device that can dissipate as much as
4.88 W depending on the user application and configuration.
Due to the high power density of the AD9166, thermal
management is required to avoid exceeding the maximum
junction temperatures specified in Table 11, especially at
elevated ambient temperatures in still air.
−0.3 V to +5.25 V
−5.25 V to +0.3 V
THERMAL RESISTANCE
−0.3 V to VDD_IO + 0.3 V
−0.3 V to DAC_3P3_SYNC + 0.3 V
−0.3 V to DAC_1P2_SER + 0.3 V
− 0.5 V to +2.5 V
−0.3 V to DAC_1P2_CLK + 0.3 V
−0.3 V to DAC_2P5_AN + 0.3 V
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJC is
the junction to case thermal resistance.
Table 12. Thermal Resistance
Package Type
BP-324-11
105°C
110°C
105°C
260°C
−65°C to +150°C
1
Some operating modes of the device may cause the device to approach or
exceed the maximum junction temperature during operation at supported
ambient temperatures. Removal of heat from the device may require
additional measures such as active airflow, heat sinks, or other measures.
θJA
25.1
θJC
8.7
Unit
°C/W
Thermal resistance values specified are simulated based on JEDEC
specifications in compliance with JESD51-12.
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. 0 | Page 14 of 138
Data Sheet
AD9166
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
A
GND
GND
GND
GND
GND
GND
GND
GND
RFOUT
GND
GND
GND
GND
GND
GND
GND
GND
GND
B
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AMP_
CS_AMP
VBG
GND
GND
GND
GND
GND
DAC_
N1P2
_AN
DAC_
DAC_
DAC_
DAC_
N1P2 2P5_AN 2P5_AN 2P5_AN
_AN
GND
AMP_
1P8_
BYPASS
GND
DAC_
DAC_
2P5_AN 2P5_AN
GND
ISET
VREF
GND
GND
DAC_
N1P2
_AN
DAC_
N1P2
_AN
DAC_
N1P2
_AN
GND
DAC_
AMP_
DAC_ DAC_
DAC_
DAC_
DAC_
N1P2
1P8_
2P5_AN 2P5_AN 1P2_AN 1P2_AN 2P5_AN _AN
BYPASS
GND
GND
DAC_
N1P2
_AN
DAC_
N1P2
_AN
GND
C
D
E
F
G
GND
GND
CLK+
CLK–
GND
GND
GND
GND
GND
GND
GND
GND
AMP_
3P3
AMP_
N5
AMP_
N5
DAC_
N1P2
_AN
AMP_
3P3
AMP_
3P3_
OUT
AMP_
3P3_ AMP_N5 AMP_N5 AMP_N5 VDD_IO
OUT
DAC_
1P2_
CLK
DAC_
1P2_
CLK
AMP_
5V_
IN
AMP_
5V_
IN
GND
GND
GND
GND
GND
AMP_
5V_
IN
GND
GND
GND
DAC_
1P2_
CLK
DAC_
1P2_
CLK
DAC_
1P2_
CLK
DAC_
N1P2
_AN
DAC_
N1P2
_AN
DAC_
N1P2
_AN
GND
DAC_
1P2_
CLK
DAC_
1P2_
CLK
DAC_
1P2_
CLK
DAC_
1P2_
CLK
GND
GND
GND
GND
DAC_
DAC_
DAC_
DAC_
DAC_
DAC_
DAC_
2P5_AN 2P5_AN 2P5_AN 2P5_AN 2P5_AN 2P5_AN 2P5_AN
DAC_
VBG
NEG
DAC_
2P5_AN
GND
GND
GND
GND
GND
GND
GND
GND
GND
H
SYS
REF+
GND
GND
GND
GND
GND
DNC
GND
GND
GND
DAC_
2P5_AN
J
SYS
REF–
GND
GND
GND
GND
GND
GND
DNC
DAC_
2P5_AN
GND
GND
SDIO
SDO
SCLK
K
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DNC
GND
GND
GND
GND
GND
GND
DAC_
1P2_
SER
GND
GND
SERDIN
0+
GND
DAC_
1P2_
SER
GND
GND
SERDIN
0–
L
M
SERDIN
7+
SERDIN
7–
N
GND
P
SERDIN
6+
GND
GND
GND
GND
GND
GND
GND
GND
DAC_
IRQ
GND
GND
1P2_
SER
DAC_
TX_
1P2_
ENABLE RESET VDD_IO
SER
DAC_
1P2_
DIG
DAC_
1P2_
DIG
GND
DAC_
1P2_
SER
DAC_
1P2_
DIG
GND
GND
GND
GND
DAC_
1P2_
SER
DAC_
1P2_
SER
DAC_
1P2_
SER
GND
GND
DAC_
DAC_ DAC_
3P3_
1P2_
1P2_
SER SERDES SYNC
DAC_
1P2_
SER
DAC_
1P2_
SER
GND
GND
DNC
DAC_
1P2_
DIG
DAC_
1P2_
DIG
GND
DAC_
1P2_
SER
DAC_
1P2_
DIG
GND
GND
GND
VDD_IO CS_DAC
DAC_
1P2_
DIG
DAC_
1P2_
DIG
DAC_
1P2_
DIG
DAC_
1P2_
SER
GND
GND
GND
SYNC
OUT–
DAC_
1P2_
SER
DAC_
1P2_
SER
DAC_
3P3_
SYNC
GND
GND
SERDIN
1+
SYNC
OUT+
DAC_
1P2_
SER
DAC_
1P2_
SER
DAC_
1P2_
SER
GND
GND
SERDIN
1–
R
SERDIN
6–
GND
GND
GND
DAC_
1P2_
SER
T
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
U
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
V
GND
GND
GND
GND
GND
GND
GND
GND
SERDIN SERDIN
5+
5–
GND
SERDIN SERDIN
4+
4–
SERPLL_
LDO_
GND
BYPASS
SERDIN SERDIN
3–
3+
GND
SERDIN SERDIN
2–
2+
3.3V ANALOG SUPPLY, BUFFER OUTPUT
–5V ANALOG SUPPLY, BUFFER REFERENCE
5V ANALOG SUPPLY, BUFFER INPUT
1.2V SERDES SUPPLY
1.2V DIGITAL SUPPLY
I/O PINS SUPPLY (1.8V TO 3.3V)
2.5V ANALOG SUPPLY, DAC OUTPUT
3.3V SYNCOUT+/SYNCOUT– SUPPLY
–1.2V ANALOG SUPPLY, DAC OUTPUT
SERDES LANE x
1.2V ANALOG SUPPLY, DAC CLOCK
SYSTEM REFERENCE POSITIVE AND NEGATIVE
1.2V ANALOG SUPPLY, DAC MIXED-SIGNAL
RF SIGNALS
CMOS I/O
BYPASS NODE
GND REFERENCE
REFERENCE NODE
DNC
20810-003
DNC = DO NOT CONNECT. LEAVE THESE PINS FLOATING.
Figure 3. Pin Configuration
Table 13. Pin Function Descriptions
Pin No.
A1 to A8, A10 to A18, B1 to B12, B15 to B18, C1, C2, C8
to C10, C12, C15, C18, D1, D2, D9, D10, D18, E2, E18,
F2 to F4, F10, F11, F17, F18, G1 to G9, G17, G18, H2
to H6, H8 to H10, H14 to H18, J2 to J7, J10, J11, J15
to J18, K1 to K12, K14 to K18, L2, L3, L6 to L14, L16,
L17, M2, M3, M9, M14, M16, M17, N1 to N3, N5, N16
to N18, P2 to P4, P9, P11, P16, P17, R2 to R4, R8, R9,
R11, R16, R17, T1 to T18, U1 to U18, V1 to V3, V6, V9,
V10, V13, V16 to V18
A9
Mnemonic
GND
Description
Ground.
RFOUT
Device RF Output. Internally matched to a 50 Ω singleended load impedance.
Rev. 0 | Page 15 of 138
AD9166
Data Sheet
Pin No.
B13
Mnemonic
AMP_VBG
B14
CS_AMP
C3, C4, D3 to D5, D17, E3 to E5, E15 to E17
C5 to C7, C13, C14, D12, D13, D16, G10 to G16, H11,
H13, J9
C11, D11
DAC_N1P2_AN
DAC_2P5_AN
C16
ISET
C17
VREF
D6, E6
D7, D8, E9, E10, E11
D14, D15
E1, F1
AMP_3P3
AMP_N5
DAC_1P2_AN
CLK+, CLK−
E7, E8
AMP_3P3_OUT
E12, M7, M12
VDD_IO
E13, E14, F5, F6, F12 to F16
F7, F8, F9
DAC_1P2_CLK
AMP_5V_IN
H1, J1
SYSREF+, SYSREF−
H7, J8, K13, P8
DNC
H12
DAC_VBGNEG
J12
SDIO
J13
SDO
J14
SCLK
L1, M1
L4, L15, M4, M8, M10, M11, M15, N4, N15, P5, P6, P10,
P13, P14, R5 to R7, R13 to R15
L5
L18, M18
M5
SERDIN7+, SERDIN7−
DAC_1P2_SER
AMP_1P8_BYPASS
IRQ
SERDIN0+, SERDIN0−
TX_ENABLE
Rev. 0 | Page 16 of 138
Description
Amplifier Band Gap Voltage. Connect Pin B13 to a 0.1 μF
capacitor to ground, and a 1 kΩ resistor in series with a
1 μF capacitor to ground. For information about the
voltage measured at this pin, VBGA, see the Amplifier
Junction Temperature Sensor section.
Amplifier Serial Port Chip Select (Active Low) Input.
CMOS levels on Pin B14 are determined with respect to
VDD_IO.
−1.2 V Analog Supply Voltage.
2.5 V Analog Supply Voltage.
Bypass Node for Internal1.8 V Analog Supply. Short
Pin C11 and Pin D11 and connect a 1 μF capacitor to
ground.
DAC Reference Current. Connect Pin C16 with a 9.76 kΩ
resistor (RSET) to DAC_N1P2_AN.
DAC 1.2 V Reference Input/Output. Connect Pin C17 with
a 1 μF capacitor to ground.
3.3 V Analog Supply Voltage.
−5 V Analog Supply Voltage.
1.2 V Analog Supply Voltage.
Positive and Negative Device Clock Inputs. When FIR85 is
disabled, the input frequency to these pins (fCLK) is the
DAC clock frequency (fDAC). When FIR85 is enabled, fDAC =
2× fCLK.
3.3 V Analog Supply Voltage for the Output Stage of the
Amplifier.
Supply Voltage for CMOS Input/Output and SPI.
Operational for 1.8 V to 3.3 V plus tolerance (see Table 1
for details).
1.2 V Clock Supply Voltage.
5 V Analog Supply Voltage for the Input Stage of the
Amplifier. Pin F7 to Pin F9 internally supply the full-scale
current to the output stage of the DAC.
System Reference Positive and Negative Inputs. The H1
and J1 pins are self biased for ac coupling. They both can
be either ac-coupled or dc-coupled.
Do Not Connect. Do not connect these pins. Leave the
DNC pins floating.
DAC Band Gap Voltage. Connect Pin H12 with a 0.1 μF
capacitor to DAC_N1P2_AN.
Serial Port Data Input/Output. CMOS levels on Pin J12 are
determined with respect to VDD_IO. See the Serial Data
I/O (SDIO) section for details.
Serial Port Data Output. CMOS levels on Pin J13 are
determined with respect to VDD_IO.
Serial Port Data Clock. CMOS levels on Pin J14 are
determined with respect to VDD_IO. See the Serial Clock
(SCLK) section for details.
SERDES Lane 7 Negative and Positive Inputs.
1.2 V SERDES Digital Supply.
Interrupt Request Output (Active Low, Open Drain).
SERDES Lane 1 Positive and Negative Inputs.
Transmit Enable Input. Pin M5 can be used instead of the
DAC output bias power-down bits in Register 0x040,
Bits[1:0], to enable the DAC output. CMOS levels are
determined with respect to VDD_IO.
Data Sheet
AD9166
Pin No.
M6
Mnemonic
RESET
M13
CS_DAC
N6 to N14
DAC_1P2_DIG
P1, R1
P7, P15
P12, R12
P18, R18
R10
SERDIN6+, SERDIN6−
DAC_3P3_SYNC
SYNCOUT−,
SYNCOUT+
SERDIN1+, SERDIN1−
SERPLL_LDO_BYPASS
V15, V14
V12, V11
V7, V8
V4, V5
SERDIN2+, SERDIN2−
SERDIN3+, SERDIN3−
SERDIN4+, SERDIN4−
SERDIN5+, SERDIN5−
Rev. 0 | Page 17 of 138
Description
Reset (Active Low) Input. CMOS levels on Pin M6 are
determined with respect to VDD_IO.
DAC Serial Port Chip Select (Active Low) Input. CMOS
levels on Pin M13 are determined with respect to
VDD_IO.
1.2 V Digital Supply Voltage for the Digital Signal
Processing (DSP) Blocks of the DAC.
SERDES Lane 6 Negative and Positive Inputs.
3.3 V SERDES Sync Supply Voltage.
Negative and Positive LVDS Sync (Active Low) Output
Signals.
SERDES Lane 1 Positive and Negative Inputs.
SERDES PLL Supply Voltage Bypass. Connect this pin with
a 1 Ω resistor in series with a 1 μF capacitor to ground.
SERDES Lane 2 Positive and Negative Inputs.
SERDES Lane 3 Positive and Negative Inputs.
SERDES Lane 4 Negative and Positive Inputs.
SERDES Lane 5 Negative and Positive Inputs.
AD9166
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
AC PERFORMANCE (2× NRZ (FIR85) MODE)
IOUTFS = 20 mA, fCLK = 6.0 GHz, FIR85 enabled (fDAC = 2 × fCLK), interpolation = 4, nominal supplies, TA = 25°C, unless otherwise noted.
When data is transmitted across a JESD204B link: if fCLK ≤ 5.0 GHz, then interpolation = 2×; if fCLK > 5.0 GHz, then interpolation = 4×.
10
10
–10
–20
–20
–40
–40
POWER (dBm)
–10
–40
–50
–60
–40
–50
–60
–60
–60
–80
–80
–90
–90
–100
–100
0
0.9dBm
0
2000
4000
6000
8000
10000
12000
FREQUENCY (MHz)
20810-004
0
8000
10000
12000
10
0
–10
–20
–20
–40
–40
POWER (dBm)
–10
–40
–50
–60
–40
–50
–60
–60
–60
–80
–80
–90
–100
–100
2000
4000
6000
8000
10000
12000
FREQUENCY (MHz)
20810-005
–90
0
–4.2dBm
0
2000
4000
6000
8000
10000
12000
FREQUENCY (MHz)
Figure 5. Single-Tone Spectrum at fOUT = 1875 MHz
20810-008
3.6dBm
0
POWER (dBm)
6000
Figure 7. Single-Tone Spectrum at fOUT = 5032 MHz
10
Figure 8. Single-Tone Spectrum at fOUT = 7738 MHz
10
10
1.2dBm
0
0
–10
–20
–20
–40
–40
POWER (dBm)
–10
–40
–50
–60
–50
–60
–60
–80
–80
–90
–90
0
2000
4000
6000
8000
10000
FREQUENCY (MHz)
12000
Figure 6. Single-Tone Spectrum at fOUT = 3679 MHz
–10.2dBm
–40
–60
20810-006
POWER (dBm)
4000
FREQUENCY (MHz)
Figure 4. Single-Tone Spectrum at fOUT = 71 MHz
–100
2000
–100
0
2000
4000
6000
8000
10000
FREQUENCY (MHz)
Figure 9. Single-Tone Spectrum at fOUT = 9222 MHz
Rev. 0 | Page 18 of 138
12000
20810-009
POWER (dBm)
0
20810-007
4.5dBm
Data Sheet
AD9166
0
FOLDED SECOND HARMONIC
FOLDED THIRD HARMONIC
–20
–10
–40
SFDR (dBc)
0
–20
–100
0
2000
4000
6000
8000
10000
12000
fOUT (MHz)
–120
IOUTFS = 20mA, DIGITAL SCALE = 0dB
IOUTFS = 40mA, DIGITAL SCALE = 0dB
IOUTFS = 40mA, DIGITAL SCALE = –6dB
0
0
fCLK ± fOUT SPURIOUS OUTPUT POWER (dBc)
0.4
0.2
0
–0.2
–0.4
–0.6
–1.0
0
–10
–20
–30
–40
–50
–60
DIGITAL SCALE (dBFS)
–40
–60
–80
–100
IOUTFS = 20mA, DIGITAL SCALE = 0dB
IOUTFS = 40mA, DIGITAL SCALE = 0dB
IOUTFS = 40mA, DIGITAL SCALE = –6dB
0
2000
4000
6000
8000
10000
12000
fOUT (MHz)
Figure 14. fCLK ± fOUT Spurious Output Power vs. fOUT,
over Digital Scale and IOUTFS
0
0
WORST CASE IMD3, IMD5, IMD7 (dBc)
REAL SECOND HARMONIC
REAL THIRD HARMONIC
–20
–40
–60
–80
–100
IOUTFS = 20mA, DIGITAL SCALE = 0dB
IOUTFS = 40mA, DIGITAL SCALE = 0dB
IOUTFS = 40mA, DIGITAL SCALE = –6dB
0
2000
4000
6000
8000
10000
fOUT (MHz)
Figure 12. SFDR vs. fOUT over Digital Scale and IOUTFS,
Real Second and Third Harmonics
12000
IMD3
IMD5
IMD7
–20
–40
–60
–80
–100
–120
20810-011
SFDR (dBc)
12000
+fOUT
–fOUT
Figure 11. Output Power Error vs. Digital Scale, over IOUTFS, fOUT = 503 MHz
–120
10000
–20
–120
20810-031
–0.8
8000
IOUTFS = 20mA, DIGITAL SCALE = 0dB
IOUTFS = 40mA, DIGITAL SCALE = 0dB
IOUTFS = 40mA, DIGITAL SCALE = –6dB
0
2000
4000
6000
fOUT (MHz)
8000
10000
12000
20810-014
OUTPUT POWER ERROR (dB)
0.6
6000
Figure 13. SFDR vs. fOUT over Digital Scale and IOUTFS,
Folded Second and Third Harmonics
1.0
0.8
4000
fOUT (MHz)
Figure 10. Single-Tone Output Power vs. fOUT, over Digital Scale and IOUTFS
IOUTFS = 40mA
IOUTFS = 20mA
IOUTFS = 10mA
2000
20810-012
IOUTFS = 20mA, DIGITAL SCALE = 0dB
IOUTFS = 40mA, DIGITAL SCALE = 0dB
IOUTFS = 40mA, DIGITAL SCALE = –6dB
20810-013
–40
–50
–60
–80
–30
20810-010
SINGLE-TONE OUTPUT POWER (dBm)
10
Figure 15. Worst Case Third-Order, Fifth-Order, and Seventh-Order
Intermodulation (IMD3, IMD5, IMD7) vs. fOUT, over Digital Scale and IOUTFS
Rev. 0 | Page 19 of 138
AD9166
Data Sheet
0
0
FOLDED SECOND HARMONIC
FOLDED THIRD HARMONIC
–20
–20
–40
–40
SFDR (dBc)
–60
–80
–80
–100
IOUTFS = 20mA, DIGITAL SCALE = 0dB
IOUTFS = 40mA, DIGITAL SCALE = 0dB
IOUTFS = 40mA, DIGITAL SCALE = –6dB
2000
4000
6000
8000
10000
12000
fOUT (MHz)
–120
20810-015
0
Figure 16. Second-Order Intermodulation (IMD2) vs. fOUT, over Digital Scale
and IOUTFS
4000
6000
8000
10000
12000
Figure 19. SFDR vs. fOUT over fDAC, Folded Second and Third Harmonics
–20
–25
–30
fDAC = 6.0 GSPS
fDAC = 10.0 GSPS
fDAC = 12.0 GSPS
–35
0
2000
4000
6000
8000
10000
12000
IMD3
IMD5
IMD7
–20
–40
–60
–80
–100
–120
fDAC = 6.0 GSPS
fDAC = 10.0 GSPS
fDAC = 12.0 GSPS
0
2000
4000
6000
8000
10000
12000
fOUT (MHz)
Figure 17. Single-Tone Output Power vs. fOUT over fDAC
20810-019
WORST CASE IMD3, IMD5, IMD7 (dBc)
–15
20810-016
SINGLE-TONE OUTPUT POWER (dBm)
–10
fOUT (MHz)
Figure 20. Worst Case IMD3, IMD5, IMD7 vs. fOUT over fDAC
0
0
REAL SECOND HARMONIC
REAL THIRD HARMONIC
HIGH
LOW
–20
–40
–40
IMD2 (dBc)
–20
–60
–80
–60
–80
–100
fDAC = 6.0 GSPS
fDAC = 10.0 GSPS
fDAC = 12.0 GSPS
0
2000
4000
6000
8000
10000
12000
fOUT (MHz)
–100
20810-017
SFDR (dBc)
2000
0
–5
–120
0
fOUT (MHz)
0
–40
fDAC = 6.0 GSPS
fDAC = 10.0 GSPS
fDAC = 12.0 GSPS
20810-018
–100
–120
–60
Figure 18. SFDR vs. fOUT over fDAC, Real Second and Third Harmonics
–120
fDAC = 6.0 GSPS
fDAC = 10.0 GSPS
fDAC = 12.0 GSPS
0
2000
4000
6000
8000
fOUT (MHz)
Figure 21. IMD2 vs. fOUT over fDAC
Rev. 0 | Page 20 of 138
10000
12000
20810-020
IMD2 (dBc)
HIGH
LOW
Data Sheet
AD9166
0
–10
–15
–20
–25
–30
–35
–40
TJ = +105°C
TJ = +60°C
TJ = +5°C
–45
0
2000
4000
6000
8000
10000
12000
fOUT (MHz)
–20
–40
–60
–80
–100
–120
TJ = +105°C
TJ = +60°C
TJ = +5°C
0
10000
12000
HIGH
LOW
–20
–20
–40
–40
IMD2 (dBc)
–60
–80
–60
–80
–100
–100
TJ = +105°C
TJ = +60°C
TJ = +5°C
2000
4000
6000
8000
10000
–120
20810-022
0
12000
fOUT (MHz)
TJ = +105°C
TJ = +60°C
TJ = +5°C
0
–135
SINGLE-TONE NSD (dBc/Hz)
–20
–100
8000
10000
12000
6000
fDAC = 6.0 GSPS
fDAC = 10.0 GSPS
fDAC = 12.0 GSPS
FOLDED SECOND HARMONIC
FOLDED THIRD HARMONIC
–80
6000
Figure 26. IMD2 vs. fOUT over Temperature
0
–60
4000
fOUT (MHz)
Figure 23. SFDR vs. fOUT over Temperature, Real Second and Third Harmonics
–40
2000
20810-025
SFDR (dBc)
8000
0
REAL SECOND HARMONIC
REAL THIRD HARMONIC
–140
–145
–150
–155
TJ = +105°C
TJ = +60°C
TJ = +5°C
0
2000
4000
6000
8000
10000
–160
20810-023
SFDR (dBc)
6000
Figure 25. Worst Case IMD3, IMD5, IMD7 vs. fOUT over Temperature
0
–120
4000
fOUT (MHz)
Figure 22. Single-Tone Output Power vs. fOUT, over Temperature
–120
2000
20810-026
–50
IMD3
IMD5
IMD7
20810-024
WORST CASE IMD3, IMD5, IMD7 (dBc)
–5
20810-021
SINGLE-TONE OUTPUT POWER (dBm)
0
12000
fOUT (MHz)
Figure 24. SFDR vs. fOUT over Temperature, Folded Second and Third
Harmonics
0
1000
2000
3000
fOUT (MHz)
4000
5000
Figure 27. Single-Tone NSD vs. fOUT over fCLK, IOUTFS = 40 mA, NSD Measured at
10% Offset from fOUT
Rev. 0 | Page 21 of 138
AD9166
Data Sheet
–135
–60
–145
–150
–155
0
1000
2000
3000
4000
5000
6000
fOUT (MHz)
–120
–140
–160
–180
10
CLOCK SOURCE:
R&S SMA100B
ULTRALOW PHASE NOISE OPTION
100
1k
10k
100k
1M
10M
100M
1G
FREQUENCY OFFSET (Hz)
–60
–135
SINGLE SIDEBAND PHASE NOISE (dBc/Hz)
TJ = +105°C
TJ = +60°C
TJ = –5°C
–140
–145
–150
–155
0
1000
2000
3000
fOUT (MHz)
4000
5000
6000
Figure 29. Single-Tone NSD vs. fOUT over Temperature, IOUTFS = 40 mA,
NSD Measured at 10% Offset from fOUT
+10dBm
+6dBm
0dBm
–6dBm
–12dBm
–80
–100
–120
–140
–160
–180
10
20810-028
SINGLE-TONE NSD (dBc/Hz)
–100
Figure 30. Single Sideband Phase Noise vs. Frequency Offset over fOUT,
fDAC = 12,042.24 MSPS
Figure 28. Single-Tone NSD vs. fOUT over Digital Scale, IOUTFS = 40 mA,
NSD Measured at 10% Offset from fOUT
–160
–80
CLOCK SOURCE:
R&S SMA100B
ULTRALOW PHASE NOISE OPTION
100
1k
10k
100k
1M
FREQUENCY OFFSET (Hz)
10M
100M
1G
20810-030
–160
900MHz
1800MHz
3600MHz
4500MHz
7200MHz
CLOCK SOURCE
20810-029
SINGLE SIDEBAND PHASE NOISE (dBc/Hz)
–140
20810-027
SINGLE-TONE NSD (dBc/Hz)
DIGITAL SCALE = 0
DIGITAL SCALE = –6
Figure 31. Single Sideband Phase Noise vs. Frequency Offset over Clock
Power, fDAC = 12,042.24 MSPS, fOUT = 3.6 GHz
Rev. 0 | Page 22 of 138
Data Sheet
AD9166
LTE PERFORMANCE (2× NRZ (FIR85) MODE)
20810-037
20810-040
IOUTFS = 20 mA, fCLK = 6021.12 MHz, FIR85 enabled (fDAC = 2× fCLK), nominal supplies, TA = 25°C, unless otherwise noted. When data is
transmitted across a JESD204B link: if fCLK ≤ 5.0 GHz, then interpolation = 2×; if fCLK > 5.0 GHz, then interpolation = 4×.
Figure 35. 20 MHz LTE Carrier ACLR at 2685.0 MHz
20810-038
20810-041
Figure 32. 20 MHz LTE Carrier ACLR at 889.0 MHz
Figure 36. 20 MHz LTE Carrier ACLR at 3695.0 MHz
–64
FIRST ACLR
SECOND ACLR
THIRD ACLR
FOURTH ACLR
FIFTH ACLR
–66
–68
–70
–72
–74
–76
500
1000
1500
2000
2500
3000
3500
fOUT (MHz)
Figure 37. Worst Case 20 MHz LTE Carrier ACLR vs. fOUT
Figure 34. 20 MHz LTE Carrier ACLR at 2165.0 MHz
Rev. 0 | Page 23 of 138
4000
20810-042
WORST CASE 20MHz LTE CARRIER ACLR (dBc)
20810-039
Figure 33. 20 MHz LTE Carrier ACLR at 1875.0 MHz
AD9166
Data Sheet
802.11AC PERFORMANCE (2× NRZ (FIR85) MODE)
IOUTFS = 20 mA, fCLK = 6021.12 MHz, FIR85 enabled (fDAC = 2× fCLK), nominal supplies, TA = 25°C, unless otherwise noted. When data is
transmitted across a JESD204B link: if fCLK ≤ 5.0 GHz, then interpolation = 2×; if fCLK > 5.0 GHz, then interpolation = 4×.
FIRST ACLR
SECOND ACLR
THIRD ACLR
–50
–55
–60
–65
–70
5200
5300
5400
5500
5600
5700
5800
fOUT (MHz)
Figure 38. 20 MHz 802.11AC ACLR at 5825.0 MHz
Figure 41. Worst Case 80 MHz 802.11AC ACLR vs. fOUT
–45
–30
FIRST ACLR
SECOND ACLR
THIRD ACLR
BANDWIDTH = 80MHz, STANDARD: 802.11AC
–35
–55
–40
EVM (dB)
–50
–60
–45
–55
5200
5300
5400
5500
5600
5700
5800
fOUT (MHz)
5900
20810-033
–70
5100
0
1
2
3
4
5
FREQUENCY (Hz)
6
7
8
20810-036
–50
–65
Figure 42. EVM vs. Frequency, 80 MHz Channel, Swept Across First, Second,
and Third Nyquist, fDAC = 11796.48 MSPS
Figure 39. Worst Case 20 MHz 802.11AC ACLR vs. fOUT
20810-034
WORST CASE 20MHz 802.11AC ACLR (dBc)
20810-035
WORST CASE 80MHz 802.11AC ACLR (dBc)
20810-032
–45
Figure 40. 80 MHz 802.11AC ACLR at 5530.0 MHz
Rev. 0 | Page 24 of 138
Data Sheet
AD9166
TERMINOLOGY
Offset Error
Offset error is the deviation of the DAC output current from the
ideal of 0 mA.
Gain Error
Gain error is the difference between the actual and ideal output
span. The actual span is determined by the difference between
the output when the input is at its minimum code and the
output when the input is at its maximum code.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either TMIN or TMAX. For offset
and gain drift, the drift is reported in ppm of full-scale range
(FSR) per degree Celsius. For reference drift, the drift is reported
in ppm per degree Celsius.
Settling Time
Settling time is the time required for the output to reach and
remain within a specified error band around its final value,
measured from the start of the output transition.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels relative to carrier (dBc),
between the peak amplitude of the output signal and the peak
spurious signal within the dc to Nyquist frequency of the DAC.
Typically, energy in this band is rejected by the interpolation
filters. This specification, therefore, defines how well the
interpolation filters work and the effect of other parasitic
coupling paths on the DAC output.
x-Order Intermodulation Distortion (IMDx)
IMDx (where x is 2, 3, 5, or 7 for second-order, third-order,
fifth-order, or seventh-order intermodulation distortion) is the
difference, in decibels relative to carrier (dBc), between the peak
amplitude of the output signal and the peak intermodulation
product of a specific x-order within the dc to Nyquist frequency
of the DAC. The signal is composed of two continuous wave
tones. If multiple IMDx products are present, the IMDx that is
located nearest to the signal and containing the highest power is
chosen to calculate the difference. This specification defines the
linearity of the analog output stage.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in decibels.
Error Vector Magnitude (EVM)
EVM defines the average deviation of a modulation symbol
from its ideal location within a decision boundary. Typically,
EVM is quoted as the rms average of all error vector
magnitudes between the received symbols and their ideal
locations, for a given modulation order. For example, EVM for a
quadrature phase shift keying (QPSK) signal is the average of
the EVM across four decision boundaries. EVM is measured
using a baseband signal that is a pseudorandom binary
sequence (PRBS) of a statistically significant length.
Interpolation Filter
If the digital inputs to the DAC are sampled at a multiple rate of
the interpolation rate (fDATA), a digital filter can be constructed that
has a sharp transition band near fDATA/2. Images that typically
appear around the output data rate (fDAC) can be greatly suppressed.
Adjacent Channel Leakage Ratio (ACLR)
ACLR is the ratio in decibels relative to the carrier (dBc)
between the measured power within a channel relative to its
adjacent channel.
Adjusted DAC Update Rate
The adjusted DAC update rate is the DAC update rate divided
by the smallest interpolating factor. For clarity on DACs with
multiple interpolating factors, the adjusted DAC update rate for
each interpolating factor can be given.
Physical Lane
Physical Lane x refers to SERDINx±, where x represents 0 to 7.
Logical Lane
Logical Lane x (where x represents 0 to 7) refers to physical
lanes after optionally being remapped by the crossbar block
(Register 0x308 to Register 0x30B).
Link Lane
Link Lane x refers to logical lanes considered in the link, where
x represents 0 to 7.
Rev. 0 | Page 25 of 138
AD9166
Data Sheet
THEORY OF OPERATION
The AD9166 is a high performance, wideband, transmit
subsystem, composed of a high speed JESD204B SERDES
interface, a flexible 16-bit digital datapath, a I/Q DAC core,
along with an integrated differential to single-ended buffer
amplifier that is matched to a 50 Ω load at dc to 10 GHz.
digital datapath. The 100 MHz speed of the SPI write interface
enables rapid updating of the frequency tuning word (FTW) of
the NCO.
The AD9166 DAC core uses the patented quad-switch
architecture, which enable DAC decoder settings that can extend
the output frequency range into the second and third Nyquist
zones with mix mode , RZ mode, and 2× NRZ mode (with
FIR85 enabled). The output can cover a range from 0 Hz to
more than 9 GHz in 2× NRZ mode. Mix mode can be used to
access 1.5 GHz to around 9 GHz at a reduced device power
consumption when compared to 2× NRZ. The NCO can then
shift a signal of up to 1.8 GHz instantaneous bandwidth to the
desired fOUT.
Figure 1 shows a functional block diagram of the AD9166. Eight
high speed serial lanes carry data at a maximum speed of
12.5 Gbps, and either a 5 GSPS real input or a 2.5 GSPS complex
input data rate to the digital datapath. Compared to either LVDS
or CMOS interfaces, the SERDES interface simplifies pin count,
board layout, and input clock requirements to the device.
The clock for the input data is derived from the device clock
(required by the JESD204B specification). This device clock is
sourced with a high fidelity, direct, external device sampling
clock. The performance of the DAC core can be optimized by using
on-chip adjustments to the device clock input accessible through
the SPI port. The SERDES interface can be configured to operate in
one-lane, two-lane, three-lane, four-lane, six-lane, or eight-lane
mode, depending on the required input data rate.
The digital datapath of the AD9166 offers a bypass (1×) mode
and several interpolation modes (2×, 3×, 4×, 6×, 8×, 12×, 16×,
and 24×) through either an initial half-band (2×) or third-band
(3×) filter with programmable 80% or 90% bandwidth, and
three subsequent half-band filters (all 90%) with a maximum
DAC core sample rate of 6.0 GSPS. An inverse sinc filter is
provided to compensate for sinc related roll-off. An additional
half-band filter, FIR85, takes advantage of the quad-switch
architecture to interpolate on the falling edge of the clock, and
effectively double the DAC update rate in 2× NRZ mode. A 48-bit
programmable modulus numerically controlled oscillator (NCO) is
provided to enable digital frequency shifts of signals with near
infinite precision. The NCO can be operated alone in NCO only
mode or with digital data from the SERDES interface and
In addition to the main 48-bit NCO, the AD9166 also offers an
FFH NCO for selected DDS applications. The FFH NCO consists
of 32, 32-bit NCOs, each with its own phase accumulator, a
FTW select register to select one of the NCOs, and a phase
coherent hopping mode. Together, these elements enable phase
coherent FFH. With the FTW select register and the 100 MHz
SPI, dwell times as fast as 260 ns can be achieved.
The differential core output is buffered and converted to a
single-ended output. The buffer is designed using a proprietary
BiCMOS process, which greatly improves the spectral response
of the core at higher operating frequencies. The improved
spectral response is essential for applications where extra wide
signal bandwidth and spectral flatness and purity are required.
Its output has impedance match to 50 Ω, up to 10 GHz, which
eases impedance matching concerns in wideband applications.
The differential to single-ended buffer eliminates the need for
an expensive, wideband balun, and supports the full operating
range of the DAC core, from true dc to 9 GHz. DC coupling
also allows baseband waveform generation, eliminating the
need for external bias tees or similar circuitry.
The AD9166 is capable of multichip synchronization that can both
synchronize multiple subsystems and establish a constant and
deterministic latency (latency locking) path to the subsystem
output. The latency for each of the subsystems remains constant
to within several device clock cycles from link establishment to
link establishment. An external alignment (SYSREF+ or
SYSREF−) signal makes the AD9166 Subclass 1 compliant.
Several modes of SYSREF± signal handling are available for use
in the system.
An SPI configures the various functional blocks and monitors
their statuses. The various functional blocks and the data interface
must be set up in a specific sequence for proper operation (see the
Start-Up Sequence section). Simple SPI initialization routines set
up the JESD204B link and are included in the evaluation board
package. This data sheet describes the various blocks of the
AD9166 in greater detail. Descriptions of the JESD204B
interface, control parameters, and various registers to set up and
monitor the device are provided. The recommended start-up
routine reliably sets up the data link.
Rev. 0 | Page 26 of 138
Data Sheet
AD9166
SERIAL PORT OPERATION
The AD9166 includes two separate SPI controllers, one for the
DAC and one for the amplifier. Either the DAC or the amplifier
can be addressed using the same SDIO, SDO, and SCLK pins,
while asserting the corresponding chip select pin, CS_AMP or
CS_DAC. CS_AMP and CS_DAC cannot be asserted
simultaneously to address both the DAC and the amplifier
during the same communication cycle, as described in the Chip
Select (CS_AMP and CS_DAC) section.
The remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the device and the
system controller. Phase 2 of the communication cycle is a transfer
of one or more data bytes. Eight × N SCLK cycles are needed to
transfer N bytes during the transfer cycle. Registers change
immediately upon writing to the last bit of each transfer byte,
except for the FTW and NCO phase offsets, which change only
when the frequency tuning word bit, FTW_LOAD_REQ, is set.
The serial port is a flexible, synchronous serial communications
port that allows easy interfacing with many industry-standard
microcontrollers and microprocessors. The serial input/output
(I/O) is compatible with most synchronous transfer formats,
including both the Motorola SPI and Intel® SSR protocols. The
interface allows read/write access to all registers that configure
the AD9166. MSB first or LSB first transfer formats are supported.
The serial port interface can be configured as a 4-wire interface
or a 3-wire interface in which the input and output share a singlepin I/O (SDIO).
DATA FORMAT
SIO J12
SDO J13
CS_DAC M13
SPI
PORT
20810-078
SCLK J14
CS_AMP B14
Figure 43. Serial Port Interface Pins
There are two phases to a communication cycle with the AD9166.
Phase 1 is the instruction cycle (the writing of an instruction
byte into the device), coincident with the first 16 SCLK rising
edges. The instruction word provides the serial port controller
with information regarding the data transfer cycle, Phase 2 of
the communication cycle. The Phase 1 instruction word defines
whether the upcoming data transfer is a read or write, along with
the starting register address for the following data transfer.
A logic high on the pin followed by a logic low resets the serial
port timing to the initial state of the instruction cycle. From this
state, the next 16 rising SCLK edges represent the instruction
bits of the current I/O operation.
The remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the device and
the system controller. Phase 2 of the communication cycle is a
transfer of one or more data bytes. Eight × N SCLK cycles are
needed to transfer N bytes during the transfer cycle. Registers
change immediately upon writing to the last bit of each transfer
byte, except for the FTW and NCO phase offsets, which change
only when the frequency tuning word FTW_LOAD_REQ bit is set.
A logic high on CS_AMP or CS_DAC followed by a logic low
resets the serial port timing to the initial state of the instruction
cycle. From this state, the next 16 rising SCLK edges represent
the instruction bits of the current I/O operation.
The instruction byte contains the information listed in Table 14.
Table 14. Serial Port Instruction Word
I15 (MSB)
R/W
I[14:0]
A[14:0]
R/W, Bit I15 of the instruction word, determines whether a
read or a write data transfer occurs after the instruction word
write. Logic 1 indicates a read operation, and Logic 0 indicates a
write operation.
A14 to A0, Bit I14 to Bit I0 of the instruction word, determine
the register that is accessed during the data transfer portion of
the communication cycle. For multibyte transfers, A[14:0] is the
starting address. The remaining register addresses are generated
by the device based on the address increment bit. If the address
increment bits are set high (Register 0x000, Bit 5 and Bit 2), multibyte SPI writes start on A[14:0] and increment by 1 for every
eight bits sent or received. If the address increment bits are set
to 0, the address decrements by 1 every eight bits.
SERIAL PORT PIN DESCRIPTIONS
Serial Clock (SCLK)
The serial clock pin synchronizes data to and from the device
and runs the internal state machines. The maximum frequency
of SCLK is 100 MHz. All data input is registered on the rising
edge of SCLK. All data is driven out on the falling edge of SCLK.
Chip Select (CS_AMP and CS_DAC)
The AD9166 includes two chip select pins, one for the DAC
(CS_DAC) and one for the buffer amplifier (CS_AMP),
hereafter referred to as CS_x. The correct CS_x pin must be
asserted to address the particular silicon die. CS_AMP and
CS_DAC cannot be asserted simultaneously.
An active low input starts and gates a communication cycle.
CS_x allows more than one device to be used on the same serial
communications line. The SDIO pin goes to a high impedance
state when this input is high. During the communication cycle,
the chip select must stay low.
Serial Data I/O (SDIO)
The SDIO pin is a bidirectional data line. In 4-wire mode, the
SDIO pin acts as the data input and the SDO pin acts as the data
output.
Rev. 0 | Page 27 of 138
AD9166
Data Sheet
When ADDRINC or ADDRINC_M is 1, the multicycle
addresses are incremented. When ADDRINC or ADDRINC_M
is 0, the addresses are decremented. A new write cycle can
always be initiated by bringing CS_x high and then low again.
SERIAL PORT OPTIONS
The serial port can support both MSB first and LSB first data
formats. This functionality is controlled by the LSB first bit
(Register 0x000, Bit 6 and Bit 1). The default is MSB first (LSB
bit = 0).
To prevent confusion and to ensure consistency between
devices, the chip tests the first nibble following the address
phase, ignoring the second nibble. This test is completed
independently from the LSB first bits and ensures that there are
extra clock cycles following the soft reset bits (Register 0x000,
Bit 0 and Bit 7). This test of the first nibble only applies when
writing to Register 0x000.
When the LSB first bits = 0 (MSB first), the instruction and data
bits must be written from MSB to LSB. Read/write (R/W) is
followed by the instruction word, A[14:0], and D[7:0], the dataword. When the LSB first bits = 1 (LSB first), the opposite is
true. A[0:14] is followed by R/W, which is subsequently
followed by D[0:7].
INSTRUCTION CYCLE
The serial port supports a 3-wire or 4-wire interface. When the
SDO active bits = 1 (Register 0x000, Bit 4 and Bit 3), a 4-wire
interface with a separate input pin (SDIO) and output pin (SDO) is
used. When the SDO active bits = 0, the SDO pin is unused and
the SDIO pin is used for both the input and the output.
DATA TRANSFER CYCLE
CS_x
SDIO
Multibyte Data Transfers
R/W A14 A13
A3
A2 A1
A0 D7N D6N D5N
Figure 44. Serial Register Interface Timing, MSB First, Register 0x000, Bit 5
and Bit 2 = 0
Multibyte data transfers can be performed by holding CS_AMP
or CS_DAC low for multiple data transfer cycles (eight SCLK
cycles) after the first data transfer word following the instruction
cycle. The first eight SCLK cycles following the instruction cycle
read from or write to the register provided in the instruction
cycle. For each additional eight SCLK cycles, the address is
either incremented or decremented and the read/write occurs
on the new register. The direction of the address is set using
ADDRINC or ADDRINC_M (Register 0x000, Bit 5 and Bit 2).
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS_x
SDIO
A0
A1 A2
A12 A13 A14 R/W D00 D10 D20
Figure 45. Serial Register Interface Timing, LSB First, Register 0x000, Bit 5 and
Bit 2 = 1
SCLK
20810-081
tDV
DATA BIT n
DATA BIT n – 1
Figure 46. Timing Diagram for Serial Port Register Read
tS
tH
CS_x
tPWH
tPWL
SDIO
tDH
INSTRUCTION BIT 15
INSTRUCTION BIT 14
INSTRUCTION BIT 0
Figure 47. Timing Diagram for Serial Port Register Write
Rev. 0 | Page 28 of 138
20810-082
SCLK
tDS
D4N D5N D6N D7N
20810-080
SCLK
CS_x
SDIO
D30 D20 D10 D00
20810-079
SCLK
Data Sheet
AD9166
JESD204B SERIAL DATA INTERFACE
JESD204B OVERVIEW
The AD9166 has eight JESD204B data ports that receive data.
The eight JESD204B ports can be configured as part of a single
JESD204B link that uses a single system reference (SYSREF±) and
device clock (CLK±).
The JESD204B serial interface hardware consists of three layers:
the physical layer, the data link layer, and the transport layer.
These sections of the hardware are described in subsequent
sections, including information for configuring every aspect of
the interface. Figure 48 shows the communication layers
implemented in the AD9166 serial data interface to recover the
clock and deserialize, descramble, and deframe the data before it
is sent to the digital signal processing section of the device.
The physical layer establishes a reliable channel between the
transmitter and the receiver, the data link layer is responsible
for unpacking the data into octets and descrambling the data.
The transport layer receives the descrambled JESD204B frames
and converts them to DAC samples.
Various JESD204B parameters (L, F, K, M, N, NP, S, HD) define
how the data is packed and tell the device how to turn the serial
data into samples. These parameters are defined in the Transport
Layer section. The AD9166 also has a descrambling option (see
the Descrambler section for more information).
The various combinations of JESD204B parameters that are
supported depend solely on the number of lanes. Thus, a
unique set of parameters can be determined by selecting the
lane count to be used. In addition, the interpolation rate and
number of lanes can be used to define the rest of the configuration needed to set up the AD9166. The interpolation rate and
the number of lanes are selected in Register 0x110.
The AD9166 has a single DAC output. However, for the
purposes of the complex signal processing on chip, whenever
interpolation is used, the converter count is defined as M = 2.
For a particular application, the number of converters to use
(M) and the data rate variable (DataRate) are known. The lane
rate variable (LaneRate) and number of lanes (L) can be traded
off as follows:
DataRate = (DACRate)/(InterpolationFactor)
LaneRate = (20 × DataRate × M)/L
where LaneRate must be between 750 Mbps and 12.5 Gbps.
Achieving and recovering synchronization of the lanes is very
important. To simplify the interface to the transmitter, the
AD9166 designates a master synchronization signal for each
JESD204B link. The SYNCOUT− and SYNCOUT+ pins are used
as the master signal for all lanes. If any lane in a link loses
synchronization, a resynchronization request is sent to the
transmitter via the synchronization signal of the link. The
transmitter stops sending data and instead sends synchronization
characters to all lanes in that link until resynchronization is
achieved.
SYNCOUT+/SYNCOUT–
PHYSICAL
LAYER
SERDIN7±
TRANSPORT
LAYER
QBD/
DESCRAMBLER
FRAME TO
SAMPLES
I DATA[15:0]
DESERIALIZER
TO DAC
DSP BLOCK
Q DATA[15:0]
DESERIALIZER
20810-083
SERDIN0±
DATA LINK
LAYER
SYSREF±
Figure 48. Functional Block Diagram of Serial Link Receiver
Table 15. Single-Link JESD204B Operating Modes
Parameter
Lane Count
Converter Count
Octets per Frame per Lane
Samples per Converter per Frame
Parametric Symbol
L
M
F
S
Rev. 0 | Page 29 of 138
1
1
2
4
1
2
2
2
2
1
3
3
2
4
3
Number of Lanes (L)
4
6
8
4
6
8
2
2
1 (real), 2 (complex)
1
2
1
1
3
4 (real), 2 (complex)
AD9166
Data Sheet
Table 16. Data Structure per Lane for JESD204B Operating Modes1
JESD204B Operating Mode
L = 8, M = 1, F = 1, S = 4
L = 8, M = 2, F = 1, S = 2
L = 6, M = 2, F = 2, S = 3
L = 4, M = 2, F = 1, S = 1
L = 3, M = 2, F = 4, S = 3
L = 2, M = 2, F = 2, S = 1
L = 1, M = 2, F = 4, S = 1
1
Lane No.
Lane 0
Lane 1
Lane 2
Lane 3
Lane 4
Lane 5
Lane 6
Lane 7
Lane 0
Lane 1
Lane 2
Lane 3
Lane 4
Lane 5
Lane 6
Lane 7
Lane 0
Lane 1
Lane 2
Lane 3
Lane 4
Lane 5
Lane 0
Lane 1
Lane 2
Lane 3
Lane 0
Lane 1
Lane 2
Lane 0
Lane 1
Lane 0
Frame 0
M0S0[15:8]
M0S0[7:0]
M0S1[15:8]
M0S1[7:0]
M0S2[15:8]
M0S2[7:0]
M0S3[15:8]
M0S3[7:0]
M0S0[15:8]
M0S0[7:0]
M0S1[15:8]
M0S1[7:0]
M1S0[15:8]
M1S0[7:0]
M1S1[15:8]
M1S1[7:0]
M0S0[15:8]
M0S1[15:8]
M0S2[15:8]
M1S0[15:8]
M1S1[15:8]
M1S2[15:8]
M0S0[15:8]
M0S0[7:0]
M1S0[15:8]
M1S0[7:0]
M0S0[15:8]
M0S2[15:8]
M1S1[15:8]
M0S0[15:8]
M1S0[15:8]
M0S0[15:8]
Frame 1
Frame 2
Frame 3
M0S1[15:8]
M1S0[15:8]
M1S2[15:8]
M0S1[7:0]
M1S0[7:0]
M1S2[7:0]
M1S0[15:8]
M1S0[7:0]
M0S0[7:0]
M0S1[7:0]
M0S2[7:0]
M1S0[7:0]
M1S1[7:0]
M1S2[7:0]
M0S0[7:0]
M0S2[7:0]
M1S1[7:0]
M0S0[7:0]
M1S0[7:0]
M0S0[7:0]
Mx is the converter number and Sy is the sample number. For example, M0S0 means Converter 0, Sample 0. Blank cells are not applicable.
Rev. 0 | Page 30 of 138
Data Sheet
AD9166
PHYSICAL LAYER
The physical layer of the JESD204B interface, hereafter referred
to as the deserializer, has eight identical channels. Each channel
consists of the terminators, an equalizer, a clock and data recovery
(CDR) circuit, and the 1:40 demux function (see Figure 49).
use the TERM_BLKx_CTRLREG1 registers (Register 0x2A8 and
Register 0x2AF). Set the registers as follows:
DESERIALIZER
TERMINATION
EQUALIZER
CDR
1:40
20810-084
SPI
CONTROL
FROM SERDES PLL
Figure 49. Deserializer Block Diagram
JESD204B data is input to the AD9166 via the SERDINx± 1.2 V
differential input pins as per the JESD204B specification.
Interface Power-Up and Input Termination
Before using the JESD204B interface, it must be powered up by
setting Register 0x200, Bit 0 = 0. In addition, each physical lane
(PHY) that is not being used (SERDINx±) must be powered
down. To do so, set the corresponding Bit x for Physical Lane x in
Register 0x201 as follows:
Receiver Eye Mask
The AD9166 complies with the JESD204B specification regarding
the receiver eye mask and is capable of capturing data that
complies with this mask. Figure 50 shows the receiver eye mask
normalized to the data rate interval with a 600 mV VTT swing.
See the JESD204B specification for more information regarding
the eye mask and permitted receiver eye opening.
LV-OIF-11G-SR RECEIVER EYE MASK
525
Set the bit to 0 when the physical lane is used.
Set the bit to 1 when the physical lane is not used.
AMPLITUDE (mV)
Individual offsets from the autocalibration value for each lane
are programmed in Bits[3:0] of Register 0x2BB to Register 0x2C2.
The value is a signed magnitude, with Bit 3 as the sign bit. The
total range of the termination resistor value is about 94 Ω to 120 Ω,
with approximately 3.5% increments across the range (for example,
smaller steps at the bottom of the range than at the top).
The AD9166 autocalibrates the input termination to 50 Ω.
Before running the termination calibration, Register 0x2A7 and
Register 0x2AE must be written as described in Table 17 to
guarantee proper calibration. The termination calibration begins
when Register 0x2A7, Bit 0 and Register 0x2AE, Bit 0 transition
from low to high.
Register 0x2A7 controls autocalibration for PHY 0, PHY 1,
PHY 6, and PHY 7.
Register 0x2AE controls autocalibration for PHY 2, PHY 3,
PHY 4, and PHY 5.
The PHY x termination autocalibration routine is listed in Table 17.
55
0
–55
–525
0
0.35
0.5
0.65
1.00
TIME (UI)
Figure 50. Receiver Eye Mask for 600 mV VTT Swing
Clock Relationships
The following clock rates are used throughout the remainder of the
JESD204B Serial Data Interface section. The relationship between
any of the clocks can be derived from the following equations:
Table 17. PHYx Termination Autocalibration Routine
DataRate = (DACRate)/(InterpolationFactor)
Address
0x2A7
Value
0x01
LaneRate = (20 × DataRate × M)/L
0x2AE
0x01
Description
Autocalibrate PHY 0, PHY 1, PHY 6, and
PHY 7 terminations
Autocalibrate PHY 2, PHY 3, PHY 4, and
PHY 5 terminations
20810-085
SERDINx±
Default setting: set to 0xXXX0XXXX. The termination
block autocalibrates the termination values.
Overwrite setting: set to 0xXXX1XXXX to overwrite the
autocalibration with the termination values in Bits[3:1] of
Register 0x2A8 and Register 0x2AF.
ByteRate = LaneRate/10
The input termination voltage of the DAC is sourced externally
through the DAC_1P2_SER pins. It is recommended that the
JESD204B inputs be ac-coupled to the JESD204B transmit device
using 100 nF capacitors.
The calibration code of the termination can be read from
Bits[3:0] in Register 0x2AC (PHY 0, PHY 1, PHY 6, and PHY 7)
and Register 0x2B3 (PHY 2, PHY 3, PHY 4, and PHY 5). If
needed, the termination values can be adjusted or set using
several registers. To override the autocalibrated termination values,
where:
M is the JESD204B parameter for converters per link.
L is the JESD204B parameter for lanes per link.
This relationship comes from 8-bit/10-bit encoding, where each
byte is represented by 10 bits.
PCLK Rate = ByteRate/4
The processing clock is used for a quad-byte decoder.
FrameRate = ByteRate/F
where F is JESD204B parameter for octets per frame per lane.
PCLK Factor = FrameRate/PCLK Rate = 4/F
Rev. 0 | Page 31 of 138
AD9166
Data Sheet
SERDES PLL
Functional Overview of the SERDES PLL
To generate the lane rate clock inside the device, a CDR
sampling mode must be selected as follows:
The independent SERDES phase-locked loop (PLL) uses
Integer N techniques to achieve clock synthesis. The entire
SERDES PLL is integrated on chip, including the voltage
controlled oscillator (VCO) and the loop filter. The SERDES
PLL VCO operates over the range of 6 GHz to 12.5 GHz.
In the SERDES PLL, a VCO divider block divides the VCO
clock by 2 to generate a 3 GHz to 6.25 GHz quadrature clock for
the deserializer cores. This clock is the input to the CDR block
that is described in the Clock and Data Recovery section.
The reference clock to the SERDES PLL is always running at a
frequency, fREF, that is equal to 1/40 of the lane rate (PCLK rate).
The fREF frequency is divided by an integer factor, set by SERDES_
PLL_DIV_FACTOR, to deliver a clock to the phase frequency
detector (PFD) block, fPFD, that is between 35 MHz and 80 MHz.
Table 18 includes the respective SERDES_PLL_DIV_FACTOR
register settings for each of the desired PLL_REF_CLK_RATE
options available.
Table 18. SERDES PLL Divider Settings
Lane Rate
(Gbps)
0.750 to 1.5625
1.5 to 3.125
3 to 6.25
6 to 12.5
PLL_REF_CLK_RATE
(Register 0x084,
Bits[5:4])
0b01 = 2×
0b00 = 1×
0b00 = 1×
0b00 = 1×
SERDES_PLL_DIV_FACTOR
(Register 0x289, Bits[1:0])
0b10 = ÷1
0b10 = ÷1
0b01 = ÷2
0b00 = ÷4
SERDES PLL Enable and Recalibration
Register 0x280 controls the synthesizer enable and recalibration.
To enable the SERDES PLL, first set the PLL divider register
(see Table 18). Then enable the SERDES PLL by writing
Register 0x280, Bit 0 = 1. If a recalibration is needed, write
Register 0x280, Bit 2 = 0b1 and then reset the bit to 0b0. The
rising edge of the bit causes a recalibration to begin.
Confirm that the SERDES PLL is working by reading
Register 0x281. If Register 0x281, Bit 0 = 1, the SERDES PLL
has locked. If Register 0x281, Bit 3 = 1, the SERDES PLL
calibration has completed. If Register 0x281, Bit 4 or Bit 5 is
high, the PLL reaches the lower or upper end of its calibration
band and must be recalibrated by writing 0 and then 1 to
Register 0x280, Bit 2.
Clock and Data Recovery (CDR)
The deserializer is equipped with a CDR circuit. Instead of
recovering the clock directly from the JESD204B serial lanes, the
CDR circuit continuously aligns the phase of the sampling
clocks for each SERDES lane with the incoming bit stream from
the JESD204B transmitter. The sampling clocks are derived
from the SERDES PLL. The 3 GHz to 6.25 GHz sampling clocks
are derived from the SERDES PLL, as shown in Figure 54, at the
input to the CDR.
For a lane rate greater than 6.25 Gbps, use half rate CDR.
For a lane rate between 3 Gbps and 6.25 Gbps, disable half
rate operation.
For a lane rate less than 3 Gbps, disable full rate and enable
2× oversampling to recover the appropriate lane rate clock.
Table 19 lists the CDR sampling settings that must be set
depending on the lane rate value.
Table 19. CDR Operating Modes
Lane Rate
(Gbps)
0.750 to 1.5625
1.5 to 3.125
3 to 6.25
6 to 12.5
SPI_ENHALFRATE
(Register 0x230,
Bit 5)
0 (full rate)
0 (full rate)
0 (full rate)
1 (half rate)
SPI_DIVISION_RATE
(Register 0x230,
Bits[2:1])
0b10 (divide by 4)
0b01 (divide by 2)
0b00 (no divide)
0b00 (no divide)
The CDR circuit synchronizes the phase used to sample the data on
each serial lane independently. This independent phase adjustment
per serial interface ensures accurate data sampling and eases the
implementation of multiple serial interfaces on a PCB.
After configuring the CDR circuit, reset it and then release the
reset by writing 0 and then writing 1 to Register 0x206, Bit 0.
In some clocking configuration, it may be necessary to reset the
CDR after the JESD204B transmitter begins sending /K/
characters as part of the JESD204B serial link establishment, so
that the CDR restarts its search loop and aligns the clocks
correctly (see the JESD204B Serial Link Establishment section).
Power-Down Unused PHYs
Unused lanes that are left enabled consume extra power
unnecessarily. Each lane that is not in use (SERDINx±) must be
powered off by writing a 1 to the corresponding bit of PHY_PD
(Register 0x201).
Equalization
To compensate for signal integrity distortions for each PHY
channel due to PCB trace length and impedance, the AD9166
employs an easy to use, low power equalizer on each JESD204B
channel. The AD9166 equalizers can compensate for insertion
losses far greater than required by the JESD204B specification.
The equalizers have two modes of operation that are determined
by the EQ_POWER_MODE register setting in Register 0x268,
Bits[7:6]. In low power mode (Register 0x268, Bits[7:6] = 0b01)
and operating at the maximum lane rate of 12.5 Gbps, the
equalizer can compensate for up to 11.5 dB of insertion loss. In
normal mode (Register 0x268, Bits[7:6] = 0b00), the equalizer
can compensate for up to 17.2 dB of insertion loss. This performance is shown in Figure 51 as an overlay to the JESD204B
specification for insertion loss. Figure 51 shows the equalization
performance at 12.5 Gbps, near the maximum baud rate for the
AD9166.
Rev. 0 | Page 32 of 138
Data Sheet
AD9166
JESD204B SPEC ALLOWED
CHANNEL LOSS
2
AD9166 ALLOWED
CHANNEL LOSS
(NORMAL MODE)
22
6.250
9.375
4
5
6
7
8
9
–20
–25
STRIPLINE = 6"
STRIPLINE = 10"
STRIPLINE = 15"
STRIPLINE = 20"
STRIPLINE = 25"
STRIPLINE = 30"
FREQUENCY (GHz)
Figure 53. Insertion Loss of 50 Ω Microstrips on FR4
Figure 51. Insertion Loss Allowed
MODE
HALF RATE
FULL RATE, NO DIV
FULL RATE, DIV 2
FULL RATE, DIV 4
INTERPOLATION
JESD LANES
REG 0x110
DAC CLOCK
÷4
PCLK
GENERATOR
10
–15
–35
FREQUENCY (GHz)
3
0
–40
3.125
2
Figure 52. Insertion Loss of 50 Ω Striplines on FR4
–30
20
1
FREQUENCY (GHz)
EXAMPLE OF
AD9166
COMPATIBLE
CHANNEL
(NORMAL MODE)
18
24
0
CDR OVERSAMP
REG 0x289
PLL REF CLOCK
VALID RANGE
35MHz TO 80MHz
÷4, ÷2,
OR ÷1
DIVIDE (N)
20
40
80
160
ENABLE HALF RATE
DIVISION RATE
REG 0x230
SAMPLE CLOCK
I, Q TO CDR
VALID RANGE
3GHz TO 6.25GHz
CP
LF
PLL_REF_CLK_RATE
1×, 2×, 4×
REG 0x084
÷2
CDR
÷N
÷8
÷6 TO ÷127,
DEFAULT: 10
Figure 54. SERDES PLL Synthesizer Block Diagram Including VCO Divider Block
Rev. 0 | Page 33 of 138
JESD LANE CLOCK
(SAME RATE AS PCLK)
20810-086
16
–40
ATTENUATION (dB)
14
STRIPLINE = 6"
STRIPLINE = 10"
STRIPLINE = 15"
STRIPLINE = 20"
STRIPLINE = 25"
STRIPLINE = 30"
–35
20810-087
12
–25
–10
EXAMPLE OF
AD9166
COMPATIBLE
CHANNEL (LOW
POWER MODE)
AD9166 ALLOWED
CHANNEL LOSS
(LOW POWER MODE)
–20
–5
6
8
–15
–30
EXAMPLE OF
JESD204B
COMPLIANT
CHANNEL
4
10
–10
20810-089
0
–5
20810-088
Low power mode is recommended if the insertion loss of the
JESD204B PCB channels is less than that of the most lossy
supported channel for low power mode (shown in Figure 51). If
the insertion loss is greater than that, but still less than that of
the most lossy supported channel for normal mode (shown in
Figure 51), use normal mode. At 12.5 Gbps operation, the
equalizer in normal mode consumes about 4 mW more power
per lane than in low power equalizer mode. Note that either mode
can be used in conjunction with transmitter preemphasis to
ensure functionality and/or optimize for power.
0
ATTENUATION (dB)
Figure 52 and Figure 53 are provided as points of reference for
hardware designers and show the insertion loss for various
lengths of well laid out stripline and microstrip transmission
lines, respectively. See the Hardware Considerations section for
specific layout recommendations for the JESD204B channel.
AD9166
Data Sheet
between serial lanes. Each AD9166 serial interface link can issue
a synchronization request by setting its SYNCOUT± signal low.
The synchronization protocol follows Section 4.9 of the JESD204B
standard. When a stream of four consecutive /K/ symbols is
received, the AD9166 deactivates the synchronization request
by setting the SYNCOUT± signal high at the next internal local
multiframe clock (LMFC) rising edge. Then, AD9166 waits for
the transmitter to issue an initial lane alignment sequence
(ILAS). During the ILAS, all lanes are aligned using the /A/ to /R/
character transition as described in the JESD204B Serial Link
Establishment section. Elastic buffers hold early arriving lane
data until the alignment character of the latest lane arrives. At
this point, the buffers for all lanes are released and all lanes are
aligned (see Figure 56).
DATA LINK LAYER
The data link layer of the AD9166 JESD204B interface accepts
the deserialized data from the PHYs and deframes, and descrambles them so that data octets are presented to the transport layer to
be put into DAC samples. The architecture of the data link layer
is shown in Figure 55. The data link layer consists of a synchronization FIFO for each lane, a crossbar switch, a deframer, and a
descrambler.
The AD9166 can operate as a single-link high speed JESD204B
serial data interface. All eight lanes of the JESD204B interface
handle link layer communications such as code group synchronization (CGS), frame alignment, and frame synchronization.
The AD9166 decodes 8-bit/10-bit control characters, allowing
marking of the start and end of the frame and alignment
DATA LINK LAYER
SYNCOUT+/SYNCOUT–
LANE 7 DATA CLOCK
SYSREF±
CROSSBAR
SWITCH
SERDIN7±
FIFO
LANE 0 OCTETS
LANE 7 OCTETS
SYSTEM CLOCK
PHASE DETECT
20810-090
LANE 7 DESERIALIZED
AND DESCRAMBLED DATA
SERDIN0±
FIFO
DESCRAMBLE
LANE 0 DATA CLOCK
QUAD-BYTE
DEFRAMER
QBD
8-BIT/10-BIT DECODE
LANE 0 DESERIALIZED
AND DESCRAMBLED DATA
PCLK
SPI CONTROL
Figure 55. Data Link Layer Block Diagram
L RECEIVE LANES
(EARLIEST ARRIVAL) K K K R D D
D D A R Q C
L RECEIVE LANES K K K K K K K R D D
(LATEST ARRIVAL)
C
D D A R Q C
D D A R D D
C
D D A R D D
0 CHARACTER ELASTIC BUFFER DELAY OF LATEST ARRIVAL
4 CHARACTER ELASTIC BUFFER DELAY OF EARLIEST ARRIVAL
D D A R Q C
K = K28.5 CODE GROUP SYNCHRONIZATION COMMA CHARACTER
A = K28.3 LANE ALIGNMENT SYMBOL
F = K28.7 FRAME ALIGNMENT SYMBOL
R = K28.0 START OF MULTIFRAME
Q = K28.4 START OF LINK CONFIGURATION DATA
C = JESD204x LINK CONFIGURATION PARAMETERS
D = Dx.y DATA SYMBOL
Figure 56. Lane Alignment During ILAS
Rev. 0 | Page 34 of 138
C
D D A R D D
20810-091
L ALIGNED
RECEIVE LANES K K K K K K K R D D
Data Sheet
AD9166
JESD204B Serial Link Establishment
If any of these errors exist, they are reported back to the
transmitter in one of the following ways (see the JESD204B
Error Monitoring section for details):
A brief summary of the high speed serial link establishment
process for Subclass 1 is provided. See Section 5.3.3 of the
JESD204B specifications document for complete details.
Step 1: Code Group Synchronization
Each receiver must locate /K/ (K28.5) characters in its input bit
stream. After four consecutive /K/ characters are detected on all
link lanes, the receiver block deasserts the SYNCOUT± signal
to the transmitter block at the receiver LMFC edge.
The transmitter captures the change in the SYNCOUT± signal
and, at a future transmitter LMFC rising edge, starts the ILAS.
Step 2: Initial Lane Alignment Sequence
The main purposes of this phase are to align all the lanes of the
link and to verify the parameters of the link.
Before the link is established, write each of the link parameters
to the receiver device to designate how data is sent to the
receiver block.
The ILAS consists of four or more multiframes. The last character
of each multiframe is a multiframe alignment character, /A/.
The first, third, and fourth multiframes are populated with
predetermined data values. Note that Section 8.2 of the JESD204B
specifications document describes the data ramp that is expected
during ILAS. The AD9166 does not require this ramp. The
deframer uses the final /A/ of each lane to align the ends of the
multiframes within the receiver. The second multiframe contains
an /R/ (K.28.0), /Q/ (K.28.4), and then data corresponding to the
link parameters. Additional multiframes can be added to the
ILAS if needed by the receiver. By default, the AD9166 uses four
multiframes in the ILAS (this can be changed in Register 0x478). If
using Subclass 1, exactly four multiframes must be used.
After the last /A/ character of the last ILAS, multiframe data
begins streaming. The receiver adjusts the position of the /A/
character such that it aligns with the internal LMFC of the
receiver at this point.
Step 3: Data Streaming
In this phase, data is streamed from the transmitter block to the
receiver block. Optionally, data can be scrambled. Scrambling
does not start until the very first octet following the ILAS.
The receiver block processes and monitors the data it receives
for errors, including the following:
Bad running disparity (8-bit/10-bit error)
Not in table (8-bit/10-bit error)
Unexpected control character
Bad ILAS
Interlane skew error (through character replacement)
SYNCOUT± signal assertion: resynchronization
(SYNCOUT± signal pulled low) is requested at each error
for the last two errors. For the first three errors, an optional
resynchronization request can be asserted when the error
counter reaches a set error threshold.
For the first three errors, each multiframe with an error in
it causes a small pulse on SYNCOUT±.
Errors can optionally trigger an interrupt request (IRQ)
event, which can be sent to the transmitter.
For more information about the various test modes for
verifying the link integrity, see the JESD204B Test Modes
section.
Lane First In/First Out (FIFO)
The FIFOs in front of the crossbar switch and deframer synchronize the samples sent on the high speed serial data interface
with the deframer clock by adjusting the phase of the incoming
data. The FIFO absorbs timing variations between the data source
and the deframer to allow up to two PCLK cycles of drift from
the transmitter. The FIFO_STATUS_REG_0 register and FIFO_
STATUS_REG_1 register (Register 0x30C and Register 0x30D,
respectively) can be monitored to identify whether the FIFOs
are full or empty.
Lane FIFO Interrupt Request (IRQ)
An aggregate lane FIFO overflow/underflow error bit is also
available as an IRQ event. Use Register 0x020, Bit 2 to enable
the FIFO overflow/underflow error bit, and then use
Register 0x024, Bit 2 to read back its status and reset the IRQ
signal. See the Interrupt Request Operation section for more
information.
Crossbar Switch
Register 0x308 to Register 0x30B allow arbitrary mapping of
physical lanes (SERDINx±) to logical lanes used by the SERDES
deframers.
Table 20. Crossbar Registers
Address
0x308
0x308
0x309
0x309
0x30A
0x30A
0x30B
0x30B
Bits
[2:0]
[5:3]
[2:0]
[5:3]
[2:0]
[5:3]
[2:0]
[5:3]
Logical Lane
SRC_LANE0
SRC_LANE1
SRC_LANE2
SRC_LANE3
SRC_LANE4
SRC_LANE5
SRC_LANE6
SRC_LANE7
Write each SRC_LANEx with the number (x) of the desired
physical lane (SERDINx±) from which to obtain data. By
default, all logical lanes use the corresponding physical lane as
their data source. For example, by default, SRC_LANE0 = 0.
Rev. 0 | Page 35 of 138
AD9166
Data Sheet
Therefore, Logical Lane 0 obtains data from Physical Lane 0
(SERDIN0±). To use SERDIN4± as the source for Logical Lane 0
instead, the user must write SRC_LANE0 = 4 (decimal).
Lane Inversion
Register 0x334 allows inversion of desired logical lanes, which
can be used to ease routing of the SERDINx± signals. For each
Logical Lane x, set Bit x of Register 0x334 to 1 to invert it.
Deframer
The AD9166 consists of one quad-byte deframer (QBD). The
QBD accepts the 8-bit/10-bit encoded data from the deserializer
(via the crossbar switch), decodes it, and descrambles it into
JESD204B frames before passing it to the transport layer to be
converted to DAC samples. The deframer processes four symbols
(or octets) per processing clock (PCLK) cycle.
The deframer uses the JESD204B parameters that the user has
programmed into the register map to identify how the data is
packed, and unpacks it. The JESD204B parameters are
described in detail in the Transport Layer section. Many of the
parameters are also needed in the transport layer to convert
JESD204B frames into samples.
Descrambler
The AD9166 provides an optional descrambler block using a
self synchronous descrambler with the following polynomial:
1 + x14 + x15
Because SYSREF± is sampled with fCLK ÷ 4, there is a four-fCLK cycle
ambiguity between the SYSREF± edge and fCLK. The phase of the
fCLK ÷ 4 clock used to sample SYSREF± is stored in Register 0x037,
Bits[7:0] and Register 0x038, Bits[3:0] as a thermometer code. This
value determines which fCLK cycle the SYSREF± edge corresponds
to, which is used to compensate for the cycle ambiguity and
improve deterministic latency uncertainty. The compensation must
be performed outside the AD9166 by delaying or advancing the
data samples, fCLK, or the SYSREF± signal to be sampled. After
compensation, the deterministic latency uncertainty can be
improved to 0 fCLK cycles between device resets, as long as the
sample and hold times for SYSREF± are met across the device
operating conditions.
As an indication whether setup and hold times for SYSREF± were
met, monitor the values in SYNC_LMFC_STATx (Register 0x034
and Register 0x035) after a SYSREF± edge is sampled, resetting
the register before each reading by writing 0x0 to Register 0x34.
The SYNC_LMFC_STATx value must be constant across
multiple readings. Refer to the Sync Procedure section for more
details.
The AD9166 supports a periodic SYSREF± signal. The periodicity
can be continuous, strobed, or gapped periodic. The SYSREF±
signal can always be dc-coupled (with a common-mode voltage
of 0 V to 1.25 V). When dc-coupled, a small amount of commonmode current ( 4/SYSREF± frequency. In
addition, the edge rate must be sufficiently fast to meet the
SYSREF± vs. device clock (fCLK) keep out window requirements.
Synchronizing LMFC Signals
It is possible to use ac-coupled mode without meeting the
frequency to time constant constraints (τ = RC and τ > 4/SYSREF±
frequency) by using SYSREF± hysteresis (Register 0x088 and
Register 0x089). However, using hysteresis increases the fCLK
keep out window (the setup and hold specifications in Table 10
do not apply) by an amount depending on the SYSREF±
frequency, level of hysteresis, capacitor choice, and edge rate.
SYSREF± Signal
The SYSREF± signal is a differential source synchronous input
that synchronizes the LMFC signals in both the transmitter and
receiver in a JESD204B Subclass 1 system to achieve deterministic
latency.
The SYSREF± signal is sampled by a divide by 4 version of the
device clock (fCLK). For fixed phase alignment between signals,
generate the device clock and SYSREF± signals from the same
source, such as the HMC7044 clock generator. When designing
for optimum deterministic latency operation, consider the
timing distribution skew of the SYSREF± signal in a multipoint
link system (multichip).
Rev. 0 | Page 36 of 138
SYSREF+
50Ω
50Ω
SYSREF−
3kΩ
19kΩ
19kΩ
3kΩ
20810-147
The first step to ensuring synchronization across links and
devices begins with synchronizing the LMFC signals. In
Subclass 0, the LMFC signal is synchronized to an internal
processing clock. In Subclass 1, LMFC signals are synchronized
to an external SYSREF± signal.
Figure 57. SYSREF± Input Circuit
Data Sheet
AD9166
3.
Sync Processing Modes Overview
The AD9166 supports several LMFC sync processing modes.
These modes are one shot, continuous, and monitor modes. All
sync processing modes perform a phase check to confirm that the
LMFC is phase aligned to an alignment edge. In Subclass 1, the
SYSREF± signal acts as the alignment edge. In Subclass 0, an
internal processing clock (PCLK) acts as the alignment edge.
The sync modes are described in the following sections (One-Shot
Sync Mode (SYNC_MODE = Register 0x03A, Bits[1:0] = 0b10),
Continuous Sync Mode (SYNC_MODE = Register 0x03A,
Bits[1:0] = 0b01), Monitor Sync Mode (SYNC_MODE = Register
0x03A, Bits[1:0]) = 0b00), and Sync Procedure). See the Sync
Procedure section for details on the procedure for syncing the
LMFC signals.
One-Shot Sync Mode (SYNC_MODE = Register 0x03A,
Bits[1:0] = 0b10)
In one-shot sync mode, a phase check occurs on only the first
alignment edge that is received after the sync machine is armed.
After the phase is aligned on the first edge, the AD9166 transitions
to monitor mode. Though an LMFC synchronization occurs only
once, the SYSREF± signal can still be continuous. In this case,
the phase is monitored and reported, but no clock phase
adjustment occurs.
4.
5.
6.
Continuous Sync Mode (SYNC_MODE = Register 0x03A,
Bits[1:0] = 0b01)
Continuous sync mode must be used in Subclass 1 only with a
periodic SYSREF± signal. In continuous sync mode, a phase
check/alignment occurs on every alignment edge.
Continuous sync mode differs from one-shot sync mode in two
ways. First, no SPI cycle is required to arm the device. The
alignment edge seen after continuous sync mode is enabled
results in a phase check. Second, a phase check occurs on every
alignment edge in continuous sync mode.
Monitor Sync Mode (SYNC_MODE = Register 0x03A,
Bits[1:0]) = 0b00)
Monitor sync mode allows the user to monitor the phase error in
real time. Use this sync mode with a periodic SYSREF± signal. The
phase is monitored and reported, but no clock phase
adjustment occurs.
When an alignment request (SYSREF± edge) occurs, snapshots
of the last phase error are placed into readable registers for
reference (Register 0x037 and Register 0x038, Bits[3:0]), and, if
appropriate, the IRQ_SYSREF_JITTER interrupt is set.
Sync Procedure
The procedure for enabling the sync is as follows:
1.
2.
Set up the DAC; the SERDES PLL locks it and enables the
CDR (see the Start-Up Sequence section).
Set Register 0x039 (SYSREF± jitter window). A minimum
of four fCLK cycles is recommended. See Table 22 for
settings.
7.
8.
9.
Optionally, read back the SYSREF± count to check whether
the SYSREF± pulses are being received.
a. Set Register 0x036 = 0. Writing anything to
SYSREF_COUNT resets the count.
b. Set Register 0x034 = 0. Writing anything to
SYNC_LMFC_STAT0 saves the data for readback and
registers the count.
c. Read SYSREF_COUNT from the value from
Register 0x036.
Perform a one-shot sync.
a. Set Register 0x03A = 0x00. Clear one shot mode if
already enabled.
b. Set Register 0x03A = 0x02. Enable one-shot sync
mode. The state machine enters monitor mode after a
sync occurs.
Optionally, read back the SYNC_LMFC_STATx registers to
verify that the synchronization completed correctly.
a. Set Register 0x034 = 0. Register 0x034 must be written
to read the value.
b. Read Register 0x035 and Register 0x034 to find the
value of SYNC_LMFC_STATx. It is recommended to
set SYNC_LMFC_STATx to 0 but it can be set to 4, or
a LMFC period in fCLK − 4, due to jitter.
Optionally, read back the SYSREF_PHASEx registers to
identify which phase of the divide by 4 was used to sample
SYSREF±. Read Register 0x038 and Register 0x037 as
thermometer code. The MSBs of Register 0x037, Bits[7:4]
normally show the thermometer code value.
Turn the link on (Register 0x300, Bit 0 = 1).
Read back Register 0x302 (dynamic link latency).
Repeat reestablishment of the link several times (Step 1 to
Step 7) and note the dynamic link latency values. Based on the
noted values, program the LMFC delay (Register 0x304) and
the LMFC variable (Register 0x306), and then restart the link.
Table 21. Sync Processing Modes
Sync Processing Mode
No synchronization
One shot
Continuous
SYNC_MODE (Register 0x03A, Bits[1:0])
0b00
0b10
0b01
Table 22. SYSREF± Jitter Window Tolerance
SYSREF± Jitter Window
Tolerance (fCLK Cycles)
±½
±4
±8
±12
±16
±20
±24
±28
1
SYSREF_JITTER_WINDOW
(Register 0x039, Bits[5:0])1
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
The two least significant digits are ignored because the SYSREF± signal is
sampled with a divide by 4 version of fCLK. As a result, the jitter window is set
by the fCLK ÷ 4 clock rather than fCLK. It is recommended that at least a fourdevice clock SYSREF± jitter window be chosen.
Rev. 0 | Page 37 of 138
AD9166
Data Sheet
Deterministic Latency
Subclass 1
JESD204B systems contain various clock domains distributed
throughout its system. Data traversing from one clock domain
to a different clock domain can lead to ambiguous delays in the
JESD204B link. These ambiguities lead to nonrepeatable latencies
across the link from power cycle to power cycle with each new
link establishment. Section 6 of the JESD204B specification
addresses the issue of deterministic latency with mechanisms
defined as Subclass 1 and Subclass 2.
Subclass 1 mode gives deterministic latency and allows latency
to stay repeatable within a specified number of device clock
(fCLK) periods between synchronization events, as specified in
Table 4. This mode requires an external SYSREF± signal that is
accurately phase aligned to fCLK.
Deterministic Latency Requirements
Several key factors are required for achieving deterministic
latency in a JESD204B Subclass 1 system.
The AD9166 supports JESD204B Subclass 0 and Subclass 1
operation, but not Subclass 2. Write the subclass to Register 0x458,
Bits[7:5].
SYSREF± signal distribution skew within the system must
be less than the desired uncertainty.
SYSREF± setup and hold time requirements must be met
for each device in the system.
The total latency variation across all lanes, links, and
devices must be ≤10 PCLK periods, which includes both
variable delays and the variation in fixed delays from lane
to lane, link to link, and device to device in the system.
Subclass 0
The Subclass 0 mode gives deterministic latency to within
32 fCLK cycles. This mode does not require any signal on the
SYSREF± pins, which can be left disconnected.
Subclass 0 still requires that all lanes arrive within the same LMFC
cycle.
Link Delay
The link delay of a JESD204B system is the sum of the fixed and
variable delays from the transmitter, channel, and receiver as
shown in Figure 58.
LINK DELAY = FIXED DELAY + VARIABLE DELAY
LOGIC DEVICE
(JESD204B Tx)
CHANNEL
JESD204B Rx
DSP
DAC
POWER CYCLE
VARIANCE
LMFC
ALIGNED DATA
AT Rx OUTPUT
ILAS
DATA
ILAS
DATA
FIXED DELAY
VARIABLE
DELAY
Figure 58. JESD204B Link Delay = Fixed Delay + Variable Delay
Rev. 0 | Page 38 of 138
20810-095
DATA AT
Tx INPUT
Data Sheet
AD9166
For proper functioning, all lanes on a link must be read during
the same LMFC period. Section 6.1 of the JESD204B specification states that the LMFC period must be larger than the maximum
link delay. For the AD9166, this is not necessarily the case.
Instead, the AD9166 uses a local LMFC for each link (LMFCRx)
that can be delayed from the SYSREF± aligned LMFC.
Because the LMFC is periodic, this delay can account for any
amount of fixed delay. As a result, the LMFC period must only
be larger than the variation in the link delays, and the AD9166 can
achieve proper performance with a smaller total latency.
Figure 59 and Figure 60 show a case where the link delay is
greater than an LMFC period. Note that it can be accommodated
by delaying LMFCRx.
POWER CYCLE
VARIANCE
LMFC
ILAS
DATA
LATE ARRIVING
LMFC REFERENCE
Figure 59. Link Delay > LMFC Period Example
Setting LMFCDel appropriately ensures that all the corresponding
data samples arrive in the same LMFC period. Then, LMFCVar
is written into the receive buffer delay to absorb all link delay
variation. This write ensures that all data samples have arrived
before reading. By setting these to fixed values across runs and
devices, deterministic latency is achieved.
The receive buffer delay described in the JESD204B specification
takes values from one frame clock cycle to K frame clock cycles,
and the receive buffer delay of the AD9166 takes values from 0
PCLK cycles to 10 PCLK cycles. As a result, up to 10 PCLK
cycles of total delay variation can be absorbed. LMFCVar and
LMFCDel are both in PCLK cycles. The PCLK factor, or
number of frame clock cycles per PCLK cycle, is equal to 4/F.
For more information on this relationship, see the Clock
Relationships section.
Two examples follow that show how to determine LMFCVar
and LMFCDel. After they are calculated, write LMFCDel into
Register 0x304 for all devices in the system, and write LMFCVar
to Register 0x306 for all devices in the system.
POWER CYCLE
VARIANCE
LMFC
ALIGNED DATA
ILAS
DATA
LMFCRX
LMFC_DELAY_0
LMFC REFERENCE FOR ALL POWER CYCLES
FRAME CLOCK
Figure 60. LMFC_DELAY_0 to Compensate for Link Delay > LMFC Period
Rev. 0 | Page 39 of 138
20810-094
EARLY ARRIVING
LMFC REFERENCE
20810-093
ALIGNED DATA
The method to select the LMFCDel (Register 0x304), and
LMFCVar (Register 0x306) variables is described in the Link
Delay Setup Example, with Known Delays section.
AD9166
Data Sheet
Link Delay Setup Example, with Known Delays
4.
All the known system delays can be used to calculate LMFCVar
and LMFCDel. The example shown in Figure 61 is demonstrated
in the following steps.
Note that this example is in Subclass 1 to achieve deterministic
latency, which has a PCLK factor (4/F) of two frame clock
cycles per PCLK cycle, and uses K = 32 (frames/multiframe).
Because PCBFixed