Dual, 16-Bit, 6.2 GSPS
RF DAC with Single Channelizer
AD9171
Data Sheet
FEATURES
GENERAL DESCRIPTION
Supports single-band wireless applications
1 complex data input channel per RF DAC
516 MSPS maximum complex input data rate per input
channel
1 independent NCO per input channel
Proprietary, low spurious and distortion design
2-tone IMD = −83 dBc at 1.8 GHz, −7 dBFS/tone RF output
SFDR < −80 dBc at 1.8 GHz, −7 dBFS RF output
Flexible 8-lane, 15.4 Gbps JESD204B interface
Supports single-band use cases
Supports 12-bit high density mode for increased data
throughput
Multiple chip synchronization
Supports JESD204B Subclass 1
Selectable interpolation filter for a complete set of input
data rates
2×, 3×, 4×, and 6× configurable data channel interpolation
6× and 8× configurable final interpolation
Final 48-bit NCO that operates at the DAC rate to support
frequency synthesis up to 3.1 GHz
Transmit enable function allows extra power saving and
downstream circuitry protection
High performance, low noise PLL clock multiplier
Supports 6.2 GSPS DAC update rate
Observation ADC clock driver with selectable divide ratios
Low power
1.45 W at 6 GSPS, single-channel mode
10 mm × 10 mm, 144-ball BGA_ED with metal enhanced
thermal lid, 0.80 mm pitch
The AD9171 is a high performance, dual, 16-bit digital-to-analog
converter (DAC) that supports DAC sample rates to 6.2 GSPS.
The device features an 8-lane, 15.4 Gbps JESD204B data input port,
a high performance, on-chip DAC clock multiplier, and digital
signal processing capabilities targeted at single-band direct to
radio frequency (RF) wireless applications.
The AD9171 features one complex data input channels per RF
DAC. Each data input channel includes a configurable gain
stage, an interpolation filter, and a channel numerically
controlled oscillator (NCO) for flexible, frequency planning. The
device supports up to a 516 MSPS complex data rate per input
channel.
The AD9171 is available in a 144-ball BGA_ED package.
PRODUCT HIGHLIGHTS
1.
2.
Supports one complex data input channel per RF DAC at a
maximum complex input data rate of 513 MSPS with 12-bit
resolution and 516 MSPS with 16-bit resolution options.
There is one independent NCO per input channel.
Low power dual converter decreases the amount of power
consumption needed in high bandwidth and multichannel
applications.
APPLICATIONS
Wireless communications infrastructure
Single-band base station radios
Instrumentation, automatic test equipment (ATE)
Rev. B
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AD9171
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
JESD204B Serial Data Interface .................................................... 23
Applications ....................................................................................... 1
JESD204B Overview .................................................................. 23
General Description ......................................................................... 1
Physical Layer ............................................................................. 25
Product Highlights ........................................................................... 1
Data Link Layer .......................................................................... 27
Revision History ............................................................................... 2
Syncing LMFC Signals ............................................................... 30
Functional Block Diagram .............................................................. 3
Transport Layer .......................................................................... 35
Specifications..................................................................................... 4
JESD204B Test Modes ............................................................... 36
DC Specifications ......................................................................... 4
JESD204B Error Monitoring..................................................... 38
Digital Specifications ................................................................... 5
Digital Datapath ............................................................................. 41
Power Supply DC Specifications ................................................ 5
Total Datapath Interpolation .................................................... 41
Serial Port and CMOS Pin Specifications ................................. 6
Channel Digital Datapath ......................................................... 42
Digital Input Data Timing Specifications ................................. 7
Main Digital Datapath ............................................................... 45
JESD204B Interface Electrical and Speed Specifications ........ 8
Interrupt Request Operation ........................................................ 51
Input Data Rates and Signal Bandwidth Specifications .......... 8
Interrupt Service Routine .......................................................... 51
AC Specifications.......................................................................... 9
Applications Information .............................................................. 52
Absolute Maximum Ratings.......................................................... 11
Hardware Considerations ......................................................... 52
Reflow Profile .............................................................................. 11
Analog Interface Considerations .................................................. 55
Thermal Characteristics ............................................................ 11
DAC Input Clock Configurations ............................................ 55
ESD Caution ................................................................................ 11
Clock Output Driver .................................................................. 57
Pin Configuration and Function Descriptions ........................... 12
Analog Outputs .......................................................................... 57
Typical Performance Characteristics ........................................... 15
Start-Up Sequence .......................................................................... 58
Terminology .................................................................................... 19
Register Summary .......................................................................... 65
Theory of Operation ...................................................................... 20
Register Details ............................................................................... 73
Serial Port Operation ..................................................................... 21
Outline Dimensions ..................................................................... 134
Data Format ................................................................................ 21
Ordering Guide ........................................................................ 134
Serial Port Pin Descriptions ...................................................... 21
Serial Port Options ..................................................................... 21
REVISION HISTORY
8/2019—Rev. A to Rev. B
Changes to Figure 12 ...................................................................... 16
Added Figure 13; Renumbered Sequentially .............................. 16
Changes to Figure 48 and Table 32............................................... 43
Changes to Figure 49 ...................................................................... 44
Change to Table 38 ......................................................................... 47
Changes to Figure 54 ...................................................................... 48
Changes to Figure 65 ...................................................................... 55
Changes to Table 49 ........................................................................ 60
Changes to Table 50 ........................................................................ 61
Changes to Table 55 ........................................................................ 84
5/2019—Rev. 0 to Rev. A
Changes to Noise Spectral Density Parameters, Table 8 ............. 9
Changes to L12 Pin Description, Table 11 .................................. 14
Changes to SYSREF± Sampling Section ...................................... 29
Changes to Subclass 1 Section ...................................................... 30
Change to Figure 37 ....................................................................... 31
Changes to Table 32 ....................................................................... 42
Change to SPI_CHIPGRADE Register, Table 54 ....................... 64
Change to DATAPATH_NCO_SYNC_CFG Register,
Table 54 ............................................................................................ 97
Change to SPI_CHIPGRADE Register, Table 55 ....................... 72
Change to DATAPATH_NCO_SYNC_CFG Register,
Table 54 ............................................................................................ 92
Changes to Ordering Guide ........................................................ 132
1/2018—Revision 0: Initial Version
Rev. B | Page 2 of 134
Data Sheet
AD9171
FUNCTIONAL BLOCK DIAGRAM
NCO
N
SERDIN0±
SERDES
JESD204B
RAMP UP/
DOWN GAIN
AD9171
CHANNEL 0 GAIN
PA PROTECT
M
NCO
DAC 0
DAC0±
DAC 1
DAC1±
RAMP UP/
DOWN GAIN
CHANNEL 1 GAIN
SERDIN7±
NCO
N
PA PROTECT
M
NCO
SYNCOUT0±
SYNCOUT1±
Figure 1. Functional Block Diagram
Rev. B | Page 3 of 134
PLL
÷2, ÷3
16262-001
CLOCK
RECEIVER
CLKIN+
CLOCK
DRIVER
CLKOUT–
CLOCK
RECEIVER
CLKOUT+
CLOCK DIVIDER
÷1, ÷2, ÷3, ÷4
SYSREF–
CS
SCLK
SPI
SDIO
ISET
TXEN0
TXEN1
IRQ0
IRQ1
VREF
SDO
RESET
DAC ALIGN
DETECT
SYSREF+
CLOCK DISTRIBUTION
AND
CONTROL LOGIC
SYNCHRONIZATION
LOGIC
AD9171
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) =
20 mA, unless otherwise noted. For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which
corresponds to TJ = 51°C.
Table 1.
Parameter
RESOLUTION
ACCURACY
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
ANALOG OUTPUTS (DAC0+, DAC0−, DAC1+, DAC1−)
Gain Error (with Internal ISET Reference)
Full-Scale Output Current
Minimum
Maximum
Common-Mode Voltage
Differential Impedance
DAC DEVICE CLOCK INPUT (CLKIN+, CLKIN−)
Differential Input Power
Minimum
Maximum
Differential Input Impedance 1
Common-Mode Voltage
CLOCK OUTPUT DRIVER (CLKOUT+, CLKOUT−)
Differential Output Power
Minimum
Maximum
Differential Output Impedance
Common-Mode Voltage
Output Frequency
TEMPERATURE DRIFT
Gain
REFERENCE
Internal Reference Voltage
ANALOG SUPPLY VOLTAGES
AVDD1.0
AVDD1.8
DIGITAL SUPPLY VOLTAGES
DVDD1.0
DAVDD1.0
DVDD1.8
SERDES SUPPLY VOLTAGES
SVDD1.0
1
Test Conditions/Comments
RSET = 5 kΩ
RSET = 5 kΩ
Min
16
14.2
23.6
Typ
Max
Unit
Bit
±7
±7
LSB
LSB
±15
%
16
26
0
100
17.8
28.8
mA
mA
V
Ω
RLOAD = 100 Ω differential on-chip
AC-coupled
0
6
100
0.5
dBm
dBm
Ω
V
AC-coupled
−9
0
100
0.5
dBm
dBm
Ω
V
MHz
727.5
See the DAC Input Clock Configurations section for more details.
Rev. B | Page 4 of 134
3000
10
ppm/°C
0.495
V
0.95
1.71
1.0
1.8
1.05
1.89
V
V
0.95
0.95
1.71
1.0
1.0
1.8
1.05
1.05
1.89
V
V
V
0.95
1.0
1.05
V
Data Sheet
AD9171
DIGITAL SPECIFICATIONS
AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC IOUTFS = 20 mA, unless otherwise
noted. For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = +25°C, which corresponds to TJ = 51°C.
Table 2.
Parameter
DAC UPDATE RATE
Minimum
Maximum 1
Adjusted 2
DAC PHASE-LOCKED LOOP (PLL) VOLTAGE CONTROLLED OSCILLATOR
(VCO) FREQUENCY RANGES
VCO Output Divide by 2
VCO Output Divide by 3
PHASE FREQUENCY DETECT INPUT FREQUENCY RANGES
9.96 GHz ≤ VCO Frequency ≤ 10.87 GHz
VCO Frequency < 9.96 GHz or VCO Frequency > 10.87 GHz
DAC DEVICE CLOCK INPUT (CLKIN+, CLKIN−) FREQUENCY RANGES
PLL Off
PLL On
Test Conditions/Comments
Min
Typ
Max
Unit
2.91
GSPS
GSPS
MSPS
4.37
2.91
6.2
4.14
GSPS
GSPS
25
25
225
770
MHz
MHz
2.91
25
50
75
100
6.2
770
1540
2310
3080
GHz
MHz
MHz
MHz
MHz
6.2
516
M divider set to divide by 1
M divider set to divide by 2
M divider set to divide by 3
M divider set to divide by 4
The maximum DAC update rate varies depending on the selected JESD204B mode and the lane rate for the given configuration used. The maximum DAC rate
according to lane rate and voltage supply levels is listed in Table 3.
2
The adjusted DAC update rate is calculated as fDAC, divided by the minimum required interpolation factor for a given mode or the maximum channel data rate for a
given mode. Different modes have different maximum DAC update rates, minimum interpolation factors, and maximum channel data rates, as shown in Table 12.
1
POWER SUPPLY DC SPECIFICATIONS
AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC IOUTFS = 20 mA, unless otherwise
noted. For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which corresponds to TJ = 51°C.
Table 3.
Parameter
DUAL-LINK MODE, Mode 0 (L = 1,
M = 2, NP = 16, N = 16)
AVDD1.0
AVDD1.8
DVDD1.0
Test Conditions/Comments
5.89824 GSPS DAC rate, 184.32 MHz PLL reference clock, 16× total
interpolation (2×, 8×), 40 MHz tone at −3 dBFS, channel NCO
disabled, main NCO = 1.8425 GHz, SYNCOUTx± in LVDS mode
All supply levels set to nominal values
All supplies at 5% tolerance
Combined current consumption with the DAVDD1.0 supply
All supply levels set to nominal values
All supplies at 5% tolerance
DVDD1.8
SVDD1.0
Total Power Dissipation
Rev. B | Page 5 of 134
Min
Typ
Max
Unit
400
425
110
670
745
130
mA
mA
mA
625
670
35
175
1.45
960
1070
50
340
2.15
mA
mA
mA
mA
W
AD9171
Parameter
DUAL-LINK, MODE 3 (NCO ONLY,
SINGLE-CHANNEL MODE,
NO SERDES)
AVDD1.0
Data Sheet
Test Conditions/Comments
6 GSPS DAC rate, 300 MHz PLL reference clock, 8× total
interpolation (1×, 8×), no input tone (dc internal level =
0x50FF), channel NCO = 40 MHz, main NCO = 1.8425 GHz
Min
All supply levels set to nominal values
All supplies at 5% tolerance
AVDD1.8
DVDD1.0
DVDD1.8
SVDD1.0
Combined current consumption with the DAVDD1.0 supply
All supply levels set to nominal values
All supplies at 5% tolerance
All supply levels set to nominal values
All supplies at 5% tolerance
Total Power Dissipation
Typ
Max
Unit
410
435
110
660
750
130
mA
mA
mA
500
515
0.3
5
3
1.1
780
950
1
100
120
1.671
mA
mA
mA
mA
mA
W
SERIAL PORT AND CMOS PIN SPECIFICATIONS
AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC IOUTFS = 20 mA, unless otherwise
noted. For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which corresponds to TJ = 51°C.
Table 4.
Parameter
WRITE OPERATION
Maximum SCLK Clock Rate
SCLK Clock High
SCLK Clock Low
SDIO to SCLK Setup Time
SCLK to SDIO Hold Time
CS to SCLK Setup Time
SCLK to CS Hold Time
READ OPERATION
SCLK Clock Rate
SCLK Clock High
SCLK Clock Low
SDIO to SCLK Setup Time
SCLK to SDIO Hold Time
CS to SCLK Setup Time
SCLK to SDIO Data Valid Time
SCLK to SDO Data Valid Time
CS to SDIO Output Valid to High-Z
CS to SDO Output Valid to High-Z
INPUTS (SDIO, SCLK, CS, RESET, TXEN0, and TXEN1)
Voltage Input
High
Low
Current Input
High
Low
Symbol
fSCLK, 1/tSCLK
tPWH
tPWL
tDS
tDH
tS
tH
Test Comments/Conditions
See Figure 26
SCLK = 20 MHz
SCLK = 20 MHz
Min
Typ
Max
80
5.03
1.6
1.154
0.577
1.036
−5.3
Unit
MHz
ns
ns
ns
ns
ns
ps
See Figure 25
fSCLK, 1/tSCLK
tPWH
tPWL
tDS
tDH
tS
tDV
tDV
48.58
Not shown in Figure 25 or Figure 26
Not shown in Figure 25 or Figure 26
VIH
VIL
5.03
1.6
1.158
0.537
1.036
9.6
13.7
5.4
9.59
1.48
0.425
IIH
IIL
±100
±100
Rev. B | Page 6 of 134
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V
nA
nA
Data Sheet
Parameter
OUTPUTS (SDIO, SDO)
Voltage Output
High
0 mA load
4 mA load
Low
0 mA load
4 mA load
Current Output
High
Low
INTERRUPT OUTPUTS (IRQ0, IRQ1)
Voltage Output
High
Low
AD9171
Symbol
Test Comments/Conditions
Min
Typ
Max
Unit
VOH
1.69
1.52
V
V
VOL
0.045
0.175
IOH
IOL
4
4
VOH
VOL
V
V
mA
mA
1.71
0.075
V
V
DIGITAL INPUT DATA TIMING SPECIFICATIONS
AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC IOUTFS = 20 mA, unless otherwise
noted. For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which corresponds to TJ = 51°C.
Table 5.
Parameter
LATENCY 1
Channel Interpolation Factor, Main Datapath
Interpolation Factor
2×, 6×
2×, 8×
3×, 6×
3×, 8×
4×, 6×
4×, 8×
6×, 6×
6×, 8×
DETERMINISTIC LATENCY
Fixed
Variable
SYSREF± TO LOCAL MULTIFRAME CLOCK (LMFC)
DELAY
1
2
Test Conditions/Comments
LMFC_VAR_x = 12, LMFC_DELAY_x = 12,
unless otherwise noted
JESD204B Mode 3
JESD204B Mode 5
JESD204B Mode 0
JESD204B Mode 3
JESD204B Mode 3
JESD204B Mode 5
JESD204B Mode 3
JESD204B Mode 5
JESD204B Mode 0
JESD204B Mode 0
JESD204B Mode 0
JESD204B Mode 0
Min
Typ
Max
1970
1770
2020
2500
2880
2630
3310
2980
2410
3090
3190
4130
DAC clock cycle
DAC clock cycle
DAC clock cycle
DAC clock cycle
DAC clock cycle
DAC clock cycle
DAC clock cycle
DAC clock cycle
DAC clock cycle
DAC clock cycle
DAC clock cycle
DAC clock cycle
13
2
Indicates the relationship between the
SYSREF± signal and the LMFC Clock
Phase 0
0
Unit
PCLK 2
PCLK cycles
DAC clock cycles
Total latency (or pipeline delay) through the device is calculated as follows: total latency = interface latency + fixed latency + variable latency + pipeline delay.
PCLK is the internal processing clock for the AD9171 and equals the lane rate ÷ 40.
Rev. B | Page 7 of 134
AD9171
Data Sheet
JESD204B INTERFACE ELECTRICAL AND SPEED SPECIFICATIONS
AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC IOUTFS = 20 mA, unless otherwise
noted. For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which corresponds to TJ = 51°C.
Table 6.
Parameter
JESD204B SERIAL INTERFACE RATE (SERIAL LANE RATE)
JESD204B DATA INPUTS
Input Leakage Current
Logic High
Logic Low
Unit Interval
Common-Mode Voltage
Differential Voltage
Differential Impedance
SYSREF± INPUT
Differential Impedance
DIFFERENTIAL OUTPUTS (SYNCOUT0±, SYNCOUT1±) 1
Output Differential Voltage
Output Offset Voltage
SINGLE-ENDED OUTPUTS (SYNCOUT0±, SYNCOUT1±)
Output Voltage
High
Low
Current Output
High
Low
1
Symbol
Test Conditions/Comments
Min
3
TA = 25°C
Input level = 1.0 V ± 0.25 V
Input level = 0 V
UI
VRCM
R_VDIFF
ZRDIFF
AC-coupled
At dc
Typ
Max
15.4
Unit
Gbps
66.7
+1.1
1050
120
µA
µA
ps
V
mV
Ω
10
−4
333
−0.05
110
80
100
100
Ω
Driving 100 Ω differential load
VOD
VOS
320
1.08
390
1.12
460
1.15
mV
V
0.045
V
V
Driving 100 Ω differential load
VOH
VOL
1.69
IOH
IOL
0
0
mA
mA
IEEE Standard 1596.3 LVDS compatible.
INPUT DATA RATES AND SIGNAL BANDWIDTH SPECIFICATIONS
AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) =
20 mA, unless otherwise noted. For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which
corresponds to TJ = 51°C.
Table 7.
Parameter 1
INPUT DATA RATE PER INPUT
CHANNEL
COMPLEX SIGNAL BANDWIDTH PER
INPUT CHANNEL
MAXIMUM NCO CLOCK RATE
Channel NCO
Main NCO
MAXIMUM NCO SHIFT FREQUENCY
RANGE
Channel NCO
Main NCO
MAXIMUM FREQUENCY SPACING
ACROSS INPUT CHANNELS
1
Test Conditions/Comments
1 complex channel enabled
Min
Max
516
Unit
MSPS
413.34
MHz
−258
+258
6.2
MHz
GHz
−258.34
−3.1
+258.34
+3.1
412.8
MHz
GHz
MHz
1 complex channel enabled (0.8 × fDATA)
Maximum NCO output frequency × 0.8
Typ
Values listed for these parameters are the maximum possible when considering all JESD204B modes of operation. Some modes are more limiting, based on other
parameters.
Rev. B | Page 8 of 134
Data Sheet
AD9171
AC SPECIFICATIONS
AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC IOUTFS = 20 mA, unless otherwise
noted. For the minimum and maximum, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which corresponds to TJ = 51°C.
Table 8.
Parameter
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
Single Tone, fDAC = 6000 MSPS, Mode 0 (L = 1, M = 2)
fOUT = 100 MHz
fOUT = 500 MHz
fOUT = 950 MHz
fOUT = 1840 MHz
fOUT = 2650 MHz
Single-Band Application—Band 3 (1805 MHz to
1880 MHz)
SFDR Harmonics
In-Band
Digital Predistortion (DPD) Band
Second Harmonic
Third Harmonic
Fourth and Fifth Harmonic
SFDR Nonharmonics
In-Band
DPD Band
ADJACENT CHANNEL LEAKAGE RATIO
4C-WCDMA
fDAC = 6000 MSPS, Mode 0 (L = 1, M = 2)
THIRD-ORDER INTERMODULATION DISTORTION (IMD)
fDAC = 6000 MSPS, Mode 0 (L = 1, M = 2)
NOISE SPECTRAL DENSITY (NSD)
Single Tone, fDAC = 6000 MSPS
fOUT = 200 MHz
fOUT = 500 MHz
fOUT = 950 MHz
fOUT = 1850 MHz
fOUT = 2150 MHz
Single Tone, fDAC = 3000 MSPS
fOUT = 200 MHz
fOUT = 500 MHz
fOUT = 950 MHz
SINGLE-SIDEBAND PHASE NOISE OFFSET
Test Conditions/Comments
Min
Typ
Max
Unit
−7 dBFS, shuffle enabled
−85
−85
−78
−75
−69
dBc
dBc
dBc
dBc
dBc
−82
−80
−82
−80
−95
dBc
dBc
dBc
dBc
dBc
−74
−74
dBc
dBc
−71
−66
dBc
dBc
−74
−72
dBc
dBc
−164
−163
−161
−157
−155
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
-163
-159
-155
dBc/Hz
dBc/Hz
dBc/Hz
−97
−105
−114
−126
−133
−137
−148
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Mode 0, 2× to 8×, fDAC = 6000 MSPS,
368.64 MHz reference clock
−7 dBFS, shuffle enabled
DPD bandwidth = data rate × 0.8
−7 dBFS, shuffle enabled
−1 dBFS digital backoff
fOUT = 1840 MHz
fOUT = 2650 MHz
Two-tone test, −7 dBFS/tone, 1 MHz spacing
fOUT = 1840 MHz
fOUT = 2650 MHz
0 dBFS, NSD measurement taken at 10% away
from fOUT, shuffle on
Loop filter component values according to
Figure 66 are as follows: C1 = 22 nF, R1 = 232 Ω,
C2 = 2.4 nF, C3 = 33 nF; PFD frequency =
500 MHz, fOUT = 1.8 GHz, fDAC = 6 GHz
1 kHz
10 kHz
100 kHz
600 kHz
1.2 MHz
1.8 MHz
6 MHz
Rev. B | Page 9 of 134
AD9171
Parameter
DAC TO DAC OUTPUT ISOLATION
Data Sheet
Test Conditions/Comments
Taken using the AD9171-FMC-EBZ evaluation
board
Min
Typ
Max
Unit
Single-Band—fDAC = 6000 MSPS, Mode 0 (L = 1, M = 2)
fOUT = 1840 MHz
fOUT = 2100 MHz
fOUT = 2650 MHz
Rev. B | Page 10 of 134
−81
−78
−73
dBc
dBc
dBc
Data Sheet
AD9171
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Table 9.
Parameter
ISET, FILT_COARSE, FILT_BYP, FILT_VCM
SERDINx±
SYNCOUT0±, SYNCOUT1±, RESET,
TXEN0, TXEN1, IRQ0, IRQ1, CS, SCLK,
SDIO, SDO
DAC0±, DAC1±, CLKIN±, CLKOUT±,
FILT_FINE
SYSREF±
AVDD1.0, DVDD1.0, SVDD1.0 to GND
AVDD1.8, DVDD1.8 to GND
Maximum Junction Temperature (TJ)1
Storage Temperature Range
Reflow
1
Rating
−0.3 V to AVDD1.8 + 0.3 V
−0.2 V to SVDD1.0 + 0.2 V
−0.3 V to DVDD1.8 + 0.3 V
−0.2 V to AVDD1.0 + 0.2 V
−0.2 V to DVDD1.0 + 0.2 V
−0.2 V to +1.2 V
−0.3 V to 2.2 V
118°C
−65°C to +150°C
260°C
Some operating modes of the device may cause the device to approach or
exceed the maximum junction temperature during operation at supported
ambient temperatures. Removal of heat from the device may require
additional measures such as active airflow, heat sinks, or other measures.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
REFLOW PROFILE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJC is
the junction to case thermal resistance.
Thermal resistances and thermal characterization parameters are
specified vs. the number of PCB layers in different airflow velocities
(in m/sec). The use of appropriate thermal management techniques is recommended to ensure that the maximum junction
temperature does not exceed the limits shown in Table 9.
Use the values in Table 10 in compliance with JEDEC 51-12.
Table 10. Simulated Thermal Resistance vs. PCB Layers1
PCB Type
JEDEC 2s2p Board
12-Layer PCB2
N/A means not applicable.
Non JEDEC thermal resistance.
3
1SOP PCB with no vias in PCB.
4
1SOP PCB with 7 × 7 standard JEDEC vias.
1
2
The AD9171 reflow profile is in accordance with the JEDEC
JESD20 criteria for Pb-free devices. The maximum reflow
temperature is 260°C.
Airflow
Velocity
(m/sec)
0.0
1.0
2.5
0.0
1.0
2.5
ESD CAUTION
Rev. B | Page 11 of 134
θJA
25.3
22.6
21.0
15.4
13.1
11.6
θJC_TOP
2.43
N/A
N/A
2.4
N/A
N/A
θJC_BOT
3.04
N/A
N/A
2.6
N/A
N/A
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
AD9171
Data Sheet
1
2
3
4
5
6
7
8
9
10
11
12
A
GND
SERDIN7+
SERDIN6+
SERDIN5+
SERDIN4+
GND
GND
SERDIN3+
SERDIN2+
SERDIN1+
SERDIN0+
GND
B
GND
SERDIN7–
SERDIN6–
SERDIN5–
SERDIN4–
GND
GND
SERDIN3–
SERDIN2–
SERDIN1–
SERDIN0–
GND
C
SVDD1.0
SVDD1.0
GND
GND
SVDD1.0
DVDD1.8
SVDD1.0
SVDD1.0
GND
GND
SVDD1.0
SVDD1.0
D
SYNCOUT1+
SYNCOUT1–
DVDD1.8
TXEN1
GND
SVDD1.0
GND
TXEN0
IRQ0
DVDD1.8
SYNCOUT0–
SYNCOUT0+
E
DNC
DNC
DVDD1.8
SDO
SCLK
CS
SDIO
RESET
IRQ1
DVDD1.8
DNC
DNC
F
GND
GND
GND
DAVDD1.0
DVDD1.0
DVDD1.0
DVDD1.0
DVDD1.0
DAVDD1.0
GND
GND
GND
G
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
H
SYSREF+
SYSREF–
AVDD1.0
AVDD1.0
AVDD1.0
FILT_FINE
FILT_
COARSE
AVDD1.0
AVDD1.0
AVDD1.0
GND
CLKIN–
J
GND
DNC
GND
GND
GND
AVDD1.0
FILT_BYP
GND
GND
GND
GND
CLKIN+
K
CLKOUT+
GND
AVDD1.8
DNC
AVDD1.8
FILT_VCM
AVDD1.8
GND
GND
AVDD1.8
GND
GND
L
CLKOUT–
GND
AVDD1.8
GND
GND
AVDD1.8
AVDD1.8
GND
GND
AVDD1.8
GND
ISET
M
GND
AVDD1.0
GND
DAC1+
DAC1–
GND
GND
DAC0–
DAC0+
GND
AVDD1.0
GND
GROUND
SERDES INPUT
1.0V DIGITAL SUPPLY
DAC PLL LOOP FILTER PINS
CMOS I/O
1.0V ANALOG SUPPLY
SYSREF±/SYNCOUTx±
1.0V DIGITAL-TO-ANALOG SUPPLY
DAC RF OUTPUTS
REFERENCE
1.8V ANALOG SUPPLY
1.0V SERDES SUPPLY
1.8V DIGITAL SUPPLY
RF CLOCK PINS
DNC = DO NOT CONNECT
16262-002
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 11. Pin Function Descriptions
Pin No.
1.0 V Supply
H3 to H5, H8 to H10, J6, M2, M11
Mnemonic
Description
AVDD1.0
1.0 V Clock and Analog Supplies. These pins supply the clock receivers, clock
distribution, the on-chip DAC clock multiplier, and the DAC analog core. Clean
power supply rail sources are required on these pins.
1.0 V Digital Supplies. These pins supply power to the DAC digital circuitry.
Clean power supply rail sources are required on these pins.
1.0 V Digital to Analog Supplies. These pins can share a supply rail with the
DVDD1.0 supply (electrically connected) but must have separate supply plane
and decoupling capacitors for the PCB layout to improve isolation for these
two pins. Clean power supply rail sources are required on these pins.
1.0 V SERDES Supplies to the JESD204B Data Interface. Clean power supply rail
sources are required on these pins.
F5 to F8
DVDD1.0
F4, F9
DAVDD1.0
C1, C2, C5, C7, C8, C11, C12, D6
SVDD1.0
1.8 V Supply
K3, K5, K7, K10, L3, L6, L7, L10
C6, D3, D10, E3, E10
AVDD1.8
DVDD1.8
1.8 V Analog Supplies to the On-Chip DAC Clock Multiplier and the DAC
Analog Core. Clean power supply rail sources are required on these pins.
1.8 V Digital Supplies to the JESD204B Data Interface and the Other
Input/Output Circuitry, Such as the Serial Port Interface (SPI). Clean power supply
rail sources are required on these pins.
Rev. B | Page 12 of 134
Data Sheet
Pin No.
Ground
A1, A6, A7, A12, B1, B6, B7, B12, C3, C4,
C9, C10, D5, D7, F1 to F3, F10 to F12,
G1 to G12, H11, J1, J3 to J5, J8 to J11,
K2, K8, K9, K11, K12, L2, L4, L5, L8, L9,
L11, M1, M3, M6, M7, M10, M12
RF Clock
J12
H12
K1
L1
System Reference
H1
H2
On-Chip DAC PLL Loop Filter
H6
H7
J7
K6
SERDES Data Bits
A2
B2
A3
B3
A4
B4
A5
B5
A8
B8
A9
B9
A10
B10
A11
B11
Sync Output
D12
AD9171
Mnemonic
Description
GND
Device Common Ground.
CLKIN+
Positive Device Clock Input. This pin is the clock input for the on-chip DAC
clock multiplier, REFCLK, when the DAC PLL is on. This pin is also the clock
input for the DAC sample clock or device clock (DACCLK) when the DAC PLL is
off. AC couple this input. There is an internal 100 Ω resistor between this pin
and CLKIN−.
Negative Device Clock Input.
Positive Device Clock Output. This pin is the clock output of a divided down
DACCLK and is available with the DAC PLL on and off. The divide down ratios
are by 1, 2, or 4.
Negative Device Clock Output.
CLKIN−
CLKOUT+
CLKOUT−
SYSREF+
SYSREF−
Positive System Reference Input. It is recommended to ac couple this pin, but
dc coupling is also acceptable. See Table 6 for the dc common-mode voltage.
Negative System Reference Input. It is recommended to ac couple this pin, but
dc coupling is also acceptable. See Table 6 for the dc common-mode voltage.
FILT_FINE
FILT_COARSE
FILT_BYP
FILT_VCM
On-Chip DAC Clock Multiplier and PLL Fine Loop Filter Input.
On-Chip DAC Clock Multiplier and PLL Coarse Loop Filter Input.
On-Chip DAC Clock Multiplier and LDO Bypass.
On-Chip DAC Clock Multiplier and VCO Common-Mode Input.
SERDIN7+
SERDIN7−
SERDIN6+
SERDIN6−
SERDIN5+
SERDIN5−
SERDIN4+
SERDIN4−
SERDIN3+
SERDIN3−
SERDIN2+
SERDIN2−
SERDIN1+
SERDIN1−
SERDIN0+
SERDIN0−
SERDES Data Bit 7, Positive.
SERDES Data Bit 7, Negative.
SERDES Data Bit 6, Positive.
SERDES Data Bit 6, Negative.
SERDES Data Bit 5, Positive.
SERDES Data Bit 5, Negative.
SERDES Data Bit 4, Positive.
SERDES Data Bit 4, Negative.
SERDES Data Bit 3, Positive.
SERDES Data Bit 3, Negative.
SERDES Data Bit 2, Positive.
SERDES Data Bit 2, Negative.
SERDES Data Bit 1, Positive.
SERDES Data Bit 1, Negative.
SERDES Data Bit 0, Positive.
SERDES Data Bit 0, Negative.
SYNCOUT0+
Positive Sync (Active Low) Output Signal, Channel Link 0. This pin is LVDS or
CMOS selectable.
Negative Sync (Active Low) Output Signal, Channel Link 0. This pin is LVDS or
CMOS selectable.
Positive Sync (Active Low) Output Signal, Channel Link 1. This pin is LVDS or
CMOS selectable.
Negative Sync (Active Low) Output Signal, Channel Link 1. This pin is LVDS or
CMOS selectable.
D11
SYNCOUT0−
D1
SYNCOUT1+
D2
SYNCOUT1−
Rev. B | Page 13 of 134
AD9171
Pin No.
Serial Port Interface
E4
E7
E5
E6
E8
Interrupt Request
D9
E9
CMOS Input/Outputs
D8
D4
DAC Analog Outputs
M9
M8
M4
M5
Reference
L12
Do Not Connect
E1, E2, E11, E12, J2, K4
Data Sheet
Mnemonic
Description
SDO
SDIO
SCLK
CS
RESET
Serial Port Data Output (CMOS Levels with Respect to DVDD1.8).
Serial Port Data Input/Output (CMOS Levels with Respect to DVDD1.8).
Serial Port Clock Input (CMOS Levels with Respect to DVDD1.8).
Serial Port Chip Select, Active Low (CMOS Levels with Respect to DVDD1.8).
Reset, Active Low (CMOS Levels with Respect to DVDD1.8).
IRQ0
Interrupt Request 0. This pin is an open-drain, active low output (CMOS levels
with respect to DVDD1.8). Connect a pull-up resistor to DVDD1.8 to prevent this
pin from floating when inactive.
Interrupt Request 1. This pin is an open-drain, active low output (CMOS levels
with respect to DVDD1.8). Connect a pull-up resistor to DVDD1.8 to prevent this
pin from floating when inactive.
IRQ1
TXEN0
TXEN1
Transmit Enable for DAC0. The CMOS levels are determined with respect to
DVDD1.8.
Transmit Enable for DAC1. The CMOS levels are determined with respect to
DVDD1.8.
DAC0+
DAC0−
DAC1+
DAC1−
DAC0 Positive Current Output.
DAC0 Negative Current Output.
DAC1 Positive Current Output.
DAC1 Negative Current Output.
ISET
Device Bias Current Setting Pin. Connect a 5 kΩ resistor from this pin to GND,
preferably with 4/SYSREF± frequency. In addition, the
edge rate must be sufficiently fast to allow SYSREF± sampling
clocks to correctly sample the rising SYSREF± edge before the
next sample clock.
When ac coupling the SYSREF± inputs, ensure that the
SYSREF_INPUTMODE bit (Register 0x084, Bit 6) is set to 0,
ac-coupled, to enable the internal receiver biasing circuitry and
prevent overstress on the SYSREF± receiver pins. AC coupling
allows a differential voltage swing from 200 mV to 1 V on the
SYSREF± pins.
SYSREF± Sampling
The SYSREF± signal is sampled by a divide by 4 version of the
DAC clock. Thus, the minimum pulse width of the SYSREF±
signal must exceed 4 DAC clock periods to ensure accurate
sampling. The delay between the SYSREF± and DAC clock
input signal does not need to be timing constrained.
By default, the first SYSREF± rising edge at the SYSREF± inputs
that is detected after asserting the SYSREF_MODE_ONESHOT
bit (Register 0x03A, Bit 1) begins the synchronization and aligns
the internal LMFC signal with the sampled SYSREF± edge.
Register 0x036 (SYSREF_COUNT) indicates how many
captured SYSREF± edges are ignored after the SYSREF_MODE_
ONESHOT bit is asserted before the synchronization takes place.
For example, if SYSREF_COUNT is set to 3, the AD9171 does
not sync after the SYSREF_MODE_ONESHOT bit is asserted
until the arrival of the 4th SYSREF± edge.
In Subclass 1, after the one-shot synchronization occurs, the
SYSREF± signal is monitored to ensure that the subsequent
SYSREF± edges do not deviate from the internal LMFC clock
by more than a target amount.
240F
100Ω
SYSREF+
SYSREF± Jitter IRQ
DC SYSREF± MODE
SYSREF+
240F
104Ω
16262-036
The AD9171 requires a synchronization (sync) to align the
LMFC and other internal clocks before the SERDES links are
brought online. The synchronization is a one-shot sync, where
the synchronization process begins on the next edge of the
alignment signal following the assertion of the SYSREF_MODE_
ONESHOT control in Register 0x03A, Bit 1.
Register 0x039 (SYSREF_ERR_WINDOW) indicates the size of
the error window allowed, in DAC clock units. If a SYSREF±
edge varies from the internal LMFC clock by more than the
number of DAC clock units set in SYSREF_ERR_WINDOW,
the IRQ_SYSREF_JITTER is asserted.
Rev. B | Page 30 of 134
Data Sheet
AD9171
Table 20. SYSREF± Jitter Window Tolerance
SYSREF± Jitter Window
Tolerance (DAC Clock Cycles)
±½
±4
±8
±12
±16
±20
+24
±28
1
SYSREF_ERR_WINDOW
(Register 0x039, Bits[5:0])1
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
The two least significant digits are ignored because the SYSREF± signal is
sampled with a divide by 4 version of the DAC clock. As a result, the jitter
window is set by this divide by 4 clock rather than the DAC clock. It is
recommended that at least a four DAC clock SYSREF± jitter window be
chosen.
The IRQ_SYSREF_JITTER can be configured as described
in the Interrupt Request Operation section to indicate the
SYSREF± signal has varied, and to request the SPI sequence for
a sync be performed again.
Sync Procedure
The procedure for enabling the sync is as follows:
1.
2.
3.
4.
5.
6.
Set up the DAC and the SERDES PLL, and enable the CDR
(see the Start-Up Sequence section).
Set Register 0x03B to 0xF1 to enable the synchronization
circuitry. If using the soft on/off feature, set Register 0x03B
to Register 0xF3 to ramp the datapath data before and after
the synchronization.
If Subclass 1, configure the SYSREF± settings as follows:
a. Set Register 0x039 (SYSREF± jitter window).
See Table 20 for settings.
b. Set Register 0x036 = SYSREF_COUNT; leave as 0 to
bypass.
Perform a one-shot sync.
a. Set Register 0x03A = 0x00. Clear one-shot mode if
already enabled.
b. Set Register 0x03A = 0x02. Enable one-shot sync mode.
If Subclass 1, send a SYSREF± edge. If pulse counting,
multiple SYSREF± edges are required. Sending SYSREF±
edges triggers the synchronization.
Read back the SYNC_ROTATION_DONE bit
(Register 0x03A, Bit 4) to confirm the rotation occurred.
Step 6, described in the Sync Procedure section. When the
one-shot sync is triggered (writing Register 0x03A = 0x02), the
SYNCOUTx± signals deassert to drop the JESD204B links and
reassert the links after the rotation completes.
E
Deterministic Latency
JESD204B systems contain various clock domains distributed
throughout. Data traversing from one clock domain to a
different clock domain can lead to ambiguous delays in the
JESD204B link. These ambiguities lead to nonrepeatable
latencies across the link from power cycle to power cycle with
each new link establishment. Section 6 of the JESD204B
specification addresses the issue of deterministic latency with
mechanisms defined as Subclass 1 and Subclass 2.
The AD9171 supports JESD204B Subclass 0 and Subclass 1
operation, but not Subclass 2. Write the subclass to
Register 0x458, Bits[7:5].
Subclass 0
This mode gives deterministic latency to within several PCLK
cycles. It does not require any signal on the SYSREF± pins,
which can be left disconnected.
Subclass 0 requires that all lanes arrive within the same LMFC
cycle and the dual DACs must be synchronized to each other.
Subclass 1
This mode gives deterministic latency and allows the link to be
synchronized to within a few DAC clock cycles. Across the full
operating range, for both supply and temperature, it is within
±2.5 DAC clock periods for a 6 GHz DAC clock rate or ±4 DAC
clock periods for a 12.6 GHz DAC clock rate. If both supply and
temperature stability are maintained, the link can be
synchronized to within ±1.5 DAC clock periods for a 6 GHz
DAC clock rate or ±2.5 DAC clock periods for a 12.6 GHz DAC
clock rate. Achieving this latency requires an external, low jitter
SYSREF± signal that is accurately phase aligned to the DAC clock.
Deterministic Latency Requirements
Several key factors are required for achieving deterministic
latency in a JESD204B Subclass 1 system, as follows:
Resynchronizing LMFC Signals
If desired, the sync procedure can be repeated to realign the
LMFC clock to the reference signal by repeating Step 2 to
Rev. B | Page 31 of 134
The SYSREF± signal distribution skew within the system
must be less than the desired uncertainty.
The total latency variation across all lanes, links, and
devices must be ≤12 PCLK periods, which includes both
variable delays and the variation in fixed delays from lane
to lane, link to link, and device to device in the system.
AD9171
Data Sheet
LINK DELAY = DELAYFIXED + DELAYVARIABLE
LOGIC DEVICE
(JESD204B Tx)
JESD204B Rx
CHANNEL
DAC
DSP
POWER CYCLE
VARIANCE
LMFC
ILAS
DATA
ALIGNED DATA
AT Rx OUTPUT
ILAS
DATA
FIXED DELAY
VARIABLE
DELAY
16262-037
DATA AT
Tx INPUT
Figure 38. JESD204B Link Delay = Fixed Delay + Variable Delay
Link Delay
The method to select the LMFCDel (Register 0x304) and
LMFCVar (Register 0x306) variables is described in the Link
Delay Setup Example, with Known Delays section and the Link
Delay Setup Example, Without Known Delay section. Note that
the setting for LMFCDel must not equal or exceed the number
of PCLK cycles per LMFC period in the current mode.
The link delay of a JESD204B system is the sum of the fixed and
variable delays from the transmitter, channel, and receiver as
shown in Figure 38.
For proper functioning, all lanes on a link must be read during
the same LMFC period. Section 6.1 of the JESD204B specification states that the LMFC period must be larger than the maximum
link delay. For the AD9171, this is not necessarily the case; instead,
the AD9171 use a local LMFC for each link (LMFCRx) that can
be delayed from the SYSREF± aligned LMFC. Because the
LMFC is periodic, this delay can account for any amount of
fixed delay. As a result, the LMFC period must only be larger
than the variation in the link delays, and the AD9171 can achieve
proper performance with a smaller total latency. Figure 39 and
Figure 40 show a case where the link delay is greater than an
LMFC period. Note that it can be accommodated by delaying
LMFCRx.
Similarly, LMFCVar must not exceed the number of PCLK cycles
per LMFC period in the current mode or be set to LMFC Period Example
Two examples follow that show how to determine LMFCVar
and LMFCDel. After they are calculated, write LMFCDel into
Register 0x304 for all devices in the system, and write LMFCVar
to Register 0x306 for all devices in the system.
POWER CYCLE
VARIANCE
LMFC
ALIGNED DATA
ILAS
DATA
LMFC_DELAY
LMFC REFERENCE FOR ALL POWER CYCLES
FRAME CLOCK
16262-0309
LMFCRX
Figure 40. LMFC_DELAY_x to Compensate for Link Delay > LMFC
Rev. B | Page 32 of 134
Data Sheet
AD9171
LMFC
PCLK
FRAME CLOCK
DATA AT Tx FRAMER
ILAS
DATA
ALIGNED LANE DATA
AT Rx DEFRAMER OUTPUT
Tx VAR
DELAY
ILAS
Rx VAR
DELAY
DATA
PCB FIXED
DELAY
LMFCRX
TOTAL FIXED LATENCY = 30 PCLK CYCLES
TOTAL VARIABLE
LATENCY = 4
PCLK CYCLES
16262-040
LMFC DELAY = 26 FRAME CLOCK CYCLES
Figure 41. LMFC Delay Calculation Example
6.
Link Delay Setup Example, with Known Delays
All the known system delays can be used to calculate LMFCVar
and LMFCDel.
The example shown in Figure 41 is demonstrated in the following
steps. Note that this example is in Subclass 1 to achieve deterministic latency, and the example uses the case for F = 2; therefore, the
number of PCLK cycles per multiframe = 16. Because PCBFixed
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