Dual, 16-Bit, 12.6 GSPS
RF DAC and Direct Digital Synthesizer
AD9174
Data Sheet
FEATURES
Supports multiband wireless applications
3 bypassable, complex data input channels per RF DAC
3.08 GSPS maximum complex input data rate per input
channel
1 independent NCO per input channel
Proprietary, low spurious and distortion design
2-tone IMD3 = −83 dBc at 1.84 GHz, −7 dBFS/tone RF output
SFDR 11 Gbps
Lane rate ≤ 11 Gbps
Lane rate > 11 Gbps
Lane rate ≤ 11 Gbps1
11.67
12.37
11.79
12.6
If using the on-chip PLL, the maximum DAC speed is limited to the maximum PLL speed of 12.42 GSPS, as listed in Table 2.
Rev. B | Page 6 of 165
Typ
Max
Unit
GSPS
GSPS
GSPS
GSPS
Data Sheet
AD9174
POWER SUPPLY DC SPECIFICATIONS
AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) =
20 mA, unless otherwise noted. For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which
corresponds to TJ = 51°C.
Table 4.
Parameter
DUAL-LINK MODES
Mode 1 (L = 2, M = 4,
NP = 16, N = 16)
AVDD1.0
AVDD1.8
DVDD1.0
DVDD1.8
SVDD1.0
Total Power
Dissipation
Mode 4 (L = 4, M = 4,
NP = 16, N = 16)
AVDD1.0
AVDD1.8
DVDD1.0
DVDD1.8
SVDD1.0
Total Power
Dissipation
Mode 0 (L = 1, M = 2,
NP = 16, N = 16)
AVDD1.0
AVDD1.8
DVDD1.0
Test Conditions/Comments
Min
11.7965 GSPS DAC rate, 184.32 MHz PLL reference clock, 32× total
interpolation (4×, 8×), 40 MHz tone at −3 dBFS, channel gain = −6 dB, channel
NCOs = ±150 MHz, main NCO = 2 GHz, SYNCOUTx± in LVDS mode
All supply levels set to nominal values
All supply levels set to 5% tolerance
Combined current consumption with the DAVDD1.0 supply
All supply levels set to nominal values
All supplies at 5% tolerance
All supply levels set to nominal values
All supplies at 5% tolerance
Typ
Max
Unit
725
775
110
1020
1120
130
mA
mA
mA
1100
1170
35
290
305
2.37
1670
1850
50
510
560
3.38
mA
mA
mA
mA
mA
W
11.7965 GSPS DAC rate, 491.52 MHz PLL reference clock, 24× total
interpolation (3×, 8×), 40 MHz tone at −3 dBFS, channel gain = −6 dB, channel
NCOs = ±150 MHz, main NCO = 2 GHz, SYNCOUTx± in LVDS mode
Combined current consumption with the DAVDD1.0 supply
5.89824 GSPS DAC rate, 184.32 MHz PLL reference clock, 16× total
interpolation (2×, 8×), 40 MHz tone at −3 dBFS, channel NCO disabled,
main NCO = 1.8425 GHz, SYNCOUTx± in LVDS mode
All supply levels set to nominal values
All supplies at 5% tolerance
Combined current consumption with the DAVDD1.0 supply
All supply levels set to nominal values
All supplies at 5% tolerance
DVDD1.8
SVDD1.0
Total Power
Dissipation
Rev. B | Page 7 of 165
725
110
1150
35
425
2.56
mA
mA
mA
mA
mA
W
400
425
110
670
745
130
mA
mA
mA
570
610
35
175
1.40
960
1070
50
340
2.15
mA
mA
mA
mA
W
AD9174
Parameter
Mode 3 (L = 2, M = 2,
NP = 16, N = 16)
AVDD1.0
AVDD1.8
DVDD1.0
DVDD1.8
SVDD1.0
Total Power
Dissipation
Mode 9 (L = 4, M = 2,
NP = 16, N = 16)
AVDD1.0
AVDD1.8
DVDD1.0
DVDD1.8
SVDD1.0
Total Power
Dissipation
Mode 2 (L = 3, M = 6,
NP = 16, N = 16)
AVDD1.0
AVDD1.8
DVDD1.0
DVDD1.8
SVDD1.0
Total Power
Dissipation
SINGLE-LINK MODES
Mode 20 (L = 8, M = 1,
NP = 16, N = 16)
AVDD1.0
AVDD1.8
DVDD1.0
DVDD1.8
SVDD1.0
Data Sheet
Test Conditions/Comments
11.7965 GSPS DAC rate, 184.32 MHz PLL reference clock, 24× total
interpolation (3×, 8×), 40 MHz tone at −3 dBFS, channel NCO disabled,
main NCO = 2.655 GHz, SYNCOUTx± in LVDS mode
All supply levels set to nominal values
All supplies at 5% tolerance
Combined current consumption with the DAVDD1.0 supply
All supply levels set to nominal values
All supplies at 5% tolerance
All supply levels set to nominal values
All supplies at 5% tolerance
12 GSPS DAC rate, 187.5 MHz PLL reference clock, 8× total interpolation
(1×, 8×), 10 MHz tone at−3 dBFS, channel NCO disabled, main NCO =
3.072 GHz, SYNCOUTx± in LVDS mode
All supply levels set to nominal values
All supplies at 5% tolerance
Combined current consumption with the DAVDD1.0 supply
All supply levels set to nominal values
All supplies at 5% tolerance
All supply levels set to nominal values
All supplies at 5% tolerance
12 GSPS DAC rate, 375 MHz PLL reference clock, 48× total interpolation
(6×, 8×), 30 MHz tone at −3 dBFS, channel gain = −11 dB, channel NCOs =
20 MHz, main NCO = 2.1 GHz
All supply levels set to nominal values
All supplies at 5% tolerance
Combined current consumption with the DAVDD1.0 supply
All supply levels set to nominal values
All supplies at 5% tolerance
All supply levels set to nominal values
All supplies at 5% tolerance
6 GSPS DAC rate, 187.5 MHz PLL reference clock, 1× total interpolation
(1×, 1×), 1.8 GHz tone at −3 dBFS, channel and main NCOs disabled
All supply levels set to nominal values
All supplies at 5% tolerance
Combined current consumption with the DAVDD1.0 supply
All supply levels set to nominal values
All supplies at 5% tolerance
All supply levels set to nominal values
All supplies at 5% tolerance
Rev. B | Page 8 of 165
Min
Typ
Max
Unit
725
775
110
mA
mA
mA
1020
1070
35
245
250
2.25
mA
mA
mA
mA
mA
W
740
785
110
1030
1135
130
mA
mA
mA
1010
1070
35
530
550
2.54
1580
1740
50
840
910
3.63
mA
mA
mA
mA
mA
W
735
785
110
1030
1135
130
1370
1460
35
410
430
2.77
1800
1980
50
680
755
3.69
mA
mA
mA
mA
mA
mA
mA
mA
mA
W
400
430
75
670
745
100
mA
mA
mA
390
410
35
525
550
700
810
50
820
880
mA
mA
mA
mA
mA
Data Sheet
Parameter
Total Power
Dissipation
Mode 12 (L = 8, M = 2,
NP = 12, N = 12)
AVDD1.0
AVDD1.8
DVDD1.0
DVDD1.8
SVDD1.0
Total Power
Dissipation
DUAL-LINK, MODE 3 (NCO
ONLY, SINGLE-CHANNEL
MODE, NO SERDES)
Mode 3
AVDD1.0
AD9174
Test Conditions/Comments
Min
4 GSPS DAC rate, 187.5 MHz PLL reference clock, 1× total interpolation
(1×, 1×), 1 GHz tone at −3 dBFS, channel and main NCOs disabled
All supply levels set to nominal values
All supplies at 5% tolerance
Combined current consumption with the DAVDD1.0 supply
All supply levels set to nominal values
All supplies at 5% tolerance
All supply levels set to nominal values
All supplies at 5% tolerance
DVDD1.8
SVDD1.0
Total Power
Dissipation
DUAL-LINK, MODE 4 (NCO
ONLY, DUAL-CHANNEL
MODE, NO SERDES)
Mode 4
AVDD1.0
AVDD1.8
DVDD1.0
Max
2.34
Unit
W
300
315
75
550
620
100
mA
mA
mA
320
350
35
525
550
1.34
630
725
50
820
880
2.15
mA
mA
mA
mA
mA
W
410
435
110
660
750
130
mA
mA
mA
500
515
0.3
5
3
1.11
780
950
1
100
120
1.671
mA
mA
mA
mA
mA
W
750
790
110
1030
1130
130
mA
mA
mA
1200
1300
0.3
5
2.15
1590
1750
1
100
2.851
mA
mA
mA
mA
W
6 GSPS DAC rate, 300 MHz PLL reference clock, 8× total interpolation (1×, 8×),
no input tone (dc internal level = 0x50FF), channel NCO = 40 MHz, main
NCO = 1.8425 GHz
All supply levels set to nominal values
All supplies at 5% tolerance
AVDD1.8
DVDD1.0
Typ
1.51
Combined current consumption with the DAVDD1.0 supply
All supply levels set to nominal values
All supplies at 5% tolerance
All supply levels set to nominal values
All supplies at 5% tolerance
12 GSPS DAC rate, 500 MHz PLL reference clock, 32× total interpolation
(4×, 8×), no input tone (dc internal level = 0x2AFF), channel NCOs =
±150 MHz, main NCO = 2 GHz
All supply levels set to nominal values
All supplies at 5% tolerance
Combined current consumption with the DAVDD1.0 supply
All supply levels set to nominal values
All supplies at 5% tolerance
DVDD1.8
SVDD1.0
Total Power
Dissipation
Rev. B | Page 9 of 165
AD9174
Data Sheet
SERIAL PORT AND CMOS PIN SPECIFICATIONS
AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) =
20 mA, unless otherwise noted. For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which
corresponds to TJ = 51°C.
Table 5.
Parameter
WRITE OPERATION
Maximum SCLK Clock Rate
SCLK Clock High
SCLK Clock Low
SDIO to SCLK Setup Time
SCLK to SDIO Hold Time
CS to SCLK Setup Time
SCLK to CS Hold Time
READ OPERATION
SCLK Clock Rate
SCLK Clock High
SCLK Clock Low
SDIO to SCLK Setup Time
SCLK to SDIO Hold Time
CS to SCLK Setup Time
SCLK to SDIO Data Valid Time
SCLK to SDO Data Valid Time
CS to SDIO Output Valid to High-Z
Symbol
fSCLK, 1/tSCLK
tPWH
tPWL
tDS
tDH
tS
tH
SCLK = 20 MHz
SCLK = 20 MHz
Min
Typ
Max
80
5.03
1.6
1.154
0.577
1.036
−5.3
Unit
MHz
ns
ns
ns
ns
ns
ps
See Figure 50
fSCLK, 1/tSCLK
tPWH
tPWL
tDS
tDH
tS
tDV
tDV
48.58
Not shown in Figure 50 or
Figure 51
Not shown in Figure 50 or
Figure 51
CS to SDO Output Valid to High-Z
INPUTS (SDIO, SCLK, CS, RESET, TXEN0, and TXEN1)
Voltage Input
High
Low
Current Input
High
Low
OUTPUTS (SDIO, SDO)
Voltage Output
High
0 mA load
4 mA load
Low
0 mA load
4 mA load
Current Output
High
Low
INTERRUPT OUTPUTS (IRQ0, IRQ1)
Voltage Output
High
Low
Test Comments/Conditions
See Figure 51
VIH
VIL
IIH
IIL
5.03
1.6
1.158
0.537
1.036
9.6
13.7
5.4
MHz
ns
ns
ns
ns
ns
ns
ns
ns
9.59
ns
1.48
0.425
±100
V
V
±100
nA
nA
1.69
1.52
V
V
VOH
VOL
0.045
0.175
IOH
IOL
VOH
VOL
Rev. B | Page 10 of 165
4
4
V
V
mA
mA
1.71
0.075
V
V
Data Sheet
AD9174
DIGITAL INPUT DATA TIMING SPECIFICATIONS
AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) =
20 mA, unless otherwise noted. For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which
corresponds to TJ = 51°C.
Table 6.
Parameter
LATENCY1
Channel Interpolation Factor, Main Datapath
Interpolation Factor
1×, 1×2
1, 22
1, 42
1, 62
1, 82
1, 122
2, 62
2, 82
3, 62
3, 82
4, 62
4, 82
6, 62
6, 82
8, 62
8, 82
DETERMINISTIC LATENCY
Fixed
Variable
SYSREF± TO LMFC DELAY
Test Conditions/Comments
LMFC_VAR_x = 12, LMFC_DELAY_x = 12,
unless otherwise noted
JESD204B Mode 10,3 Mode 183
JESD204B Mode 11, Mode 19
JESD204B Mode 12, Mode 19
JESD204B Mode 203
JESD204B Mode 21
JESD204B Mode 83
JESD204B Mode 9
JESD204B Mode 83
JESD204B Mode 9
JESD204B Mode 83
JESD204B Mode 9
JESD204B Mode 3
JESD204B Mode 83
JESD204B Mode 9
JESD204B Mode 83
JESD204B Mode 9
JESD204B Mode 3, Mode 4
JESD204B Mode 5
JESD204B Mode 0
JESD204B Mode 3, Mode 4
JESD204B Mode 3, Mode 4
JESD204B Mode 5, Mode 6
JESD204B Mode 3, Mode 4
JESD204B Mode 5, Mode 6
JESD204B Mode 0, Mode 1, Mode 2
JESD204B Mode 0, Mode 1, Mode 2
JESD204B Mode 0, Mode 1, Mode 2
JESD204B Mode 0, Mode 1, Mode 2
JESD204B Mode 7
JESD204B Mode 7
Min
Typ
Max
420
440
590
700
750
670
700
1090
1140
1460
1530
1390
1820
1920
2700
2840
1970
1770
2020
2500
2880
2630
3310
2980
2410
3090
3190
4130
3300
4270
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
13
2
0
1
Unit
PCLK4
PCLK cycles
DAC clock cycles
Total latency (or pipeline delay) through the device is calculated as follows: total latency = interface latency + fixed latency + variable latency + pipeline delay.
The first value listed in this specification is the channel interpolation factor, and the second value is the main datapath interpolation factor.
LMFC_VAR_x = 7 and LMFC_DELAY_x = 4
4
PCLK is the internal processing clock for the AD9174 and equals the lane rate ÷ 40.
2
3
Rev. B | Page 11 of 165
AD9174
Data Sheet
JESD204B INTERFACE ELECTRICAL AND SPEED SPECIFICATIONS
AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) =
20 mA, unless otherwise noted. For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which
corresponds to TJ = 51°C.
Table 7.
Parameter
JESD204B SERIAL INTERFACE RATE (SERIAL LANE RATE)
JESD204B DATA INPUTS
Input Leakage Current
Logic High
Logic Low
Unit Interval
Common-Mode Voltage
Differential Voltage
Differential Impedance
SYSREF± INPUT
Differential Impedance
DIFFERENTIAL OUTPUTS (SYNCOUT0±, SYNCOUT1±)1
Output Differential Voltage
Output Offset Voltage
SINGLE-ENDED OUTPUTS (SYNCOUT0±, SYNCOUT1±)
Output Voltage
High
Low
Current Output
High
Low
1
Symbol
Test Conditions/Comments
Min
3
TA = 25°C
Input level = 1.0 V ± 0.25 V
Input level = 0 V
UI
VRCM
R_VDIFF
ZRDIFF
AC-coupled
At dc
Typ
Max
15.4
Unit
Gbps
66.7
+1.1
1050
120
μA
μA
ps
V
mV
Ω
10
−4
333
−0.05
110
80
100
100
Ω
Driving 100 Ω differential load
VOD
VOS
320
1.08
390
1.12
460
1.15
mV
V
0.045
V
V
Driving 100 Ω differential load
VOH
VOL
IOH
IOL
IEEE Standard 1596.3 LVDS compatible.
Rev. B | Page 12 of 165
1.69
0
0
mA
mA
Data Sheet
AD9174
INPUT DATA RATES AND SIGNAL BANDWIDTH SPECIFICATIONS
AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) =
20 mA, unless otherwise noted. For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which
corresponds to TJ = 51°C.
Table 8.
Parameter1
INPUT DATA RATE PER INPUT CHANNEL
Test Conditions/Comments
Min
Typ
Max
Unit
Channel datapaths bypassed (1× interpolation), single-DAC
mode, 16-bit resolution
Channel datapaths bypassed (1× interpolation), dual DAC
mode, 16-bit resolution
Channel datapaths bypassed (1× interpolation), dual DAC
mode, 12-bit resolution
1 complex channel enabled
2 complex channels enabled
3 complex channels enabled
6160
MSPS
3080
MSPS
4100
MSPS
3080
770
385
MSPS
MSPS
MSPS
1 complex channel enabled (0.8 × fDATA)
2 complex channels enabled (0.8 × fDATA)
3 complex channels enabled (0.8 × fDATA)
1232
616
308
MHz
MHz
MHz
1540
12.6
MHz
GHz
−770
+770
MHz
−6.3
+6.3
1232
GHz
MHz
COMPLEX SIGNAL BANDWIDTH PER INPUT
CHANNEL
MAXIMUM NCO CLOCK RATE
Channel NCO
Main NCO
MAXIMUM NCO SHIFT FREQUENCY RANGE
Channel NCO
Main NCO
MAXIMUM FREQUENCY SPACING
ACROSS INPUT CHANNELS
1
Channel summing node = 1.575 GHz, channel interpolation rate >
1×
fDAC = 12.6 GHz, main interpolation rate > 1×
Maximum NCO output frequency × 0.8
Values listed for these parameters are the maximum possible when considering all JESD204B modes of operation. Some modes are more limiting, based on other
parameters.
Rev. B | Page 13 of 165
AD9174
Data Sheet
AC SPECIFICATIONS
AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) =
20 mA, unless otherwise noted. For the minimum and maximum, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which
corresponds to TJ = 51°C.
Table 9.
Parameter
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
Single Tone, fDAC = 12000 MSPS, Mode 1 (L = 2, M = 4)
fOUT = 100 MHz
fOUT = 500 MHz
fOUT = 950 MHz
fOUT = 1840 MHz
fOUT = 2650 MHz
fOUT = 3700 MHz
Single Tone, fDAC = 6000 MSPS, Mode 0 (L = 1, M = 2)
fOUT = 100 MHz
fOUT = 500 MHz
fOUT = 950 MHz
fOUT = 1840 MHz
fOUT = 2650 MHz
Single Tone, fDAC = 3000 MSPS, Mode 10 (L = 8, M = 2)
fOUT = 100 MHz
fOUT = 500 MHz
fOUT = 950 MHz
Single-Band Application—Band 3 (1805 MHz to
1880 MHz)
SFDR Harmonics
In-Band
Digital Predistortion (DPD) Band
Second Harmonic
Third Harmonic
Fourth and Fifth Harmonic
SFDR Nonharmonics
In-Band
DPD Band
ADJACENT CHANNEL LEAKAGE RATIO
4-Channel WCDMA
fDAC = 1200 MSPS, Mode 1 (L = 2, M = 4)
fDAC = 6000 MSPS, Mode 0 (L = 1, M = 2)
THIRD-ORDER INTERMODULATION DISTORTION (IMD3)
fDAC = 12000 MSPS, Mode 1 (L = 2, M = 4)
fDAC = 6000 MSPS, Mode 0 (L = 1, M = 2)
Test Conditions/Comments
Min
Typ
Max
Unit
−7 dBFS, shuffle enabled
−81
−80
−75
−80
−75
−67
dBc
dBc
dBc
dBc
dBc
dBc
−85
−85
−78
−75
−69
dBc
dBc
dBc
dBc
dBc
−87
−84
−81
dBc
dBc
dBc
−82
−80
−82
−80
−95
dBc
dBc
dBc
dBc
dBc
−74
−74
dBc
dBc
−70
−68
−66
−71
−66
dBc
dBc
dBc
dBc
dBc
−83
−85
−77
−74
−72
dBc
dBc
dBc
dBc
dBc
−7 dBFS, shuffle enabled
−7 dBFS, shuffle enabled
Mode 0, 2× to 8×, fDAC = 6000 MSPS,
368.64 MHz reference clock
−7 dBFS, shuffle enabled
DPD bandwidth = data rate × 0.8
−7 dBFS, shuffle enabled
−1 dBFS digital backoff
fOUT = 1840 MHz
fOUT = 2650 MHz
fOUT = 3500 MHz
fOUT = 1840 MHz
fOUT = 2650 MHz
Two-tone test, −7 dBFS/tone, 1 MHz spacing
fOUT = 1840 MHz
fOUT = 2650 MHz
fOUT = 3700 MHz
fOUT = 1840 MHz
fOUT = 2650 MHz
Rev. B | Page 14 of 165
Data Sheet
Parameter
NOISE SPECTRAL DENSITY (NSD)
Single Tone, fDAC = 12000 MSPS
fOUT = 200 MHz
fOUT = 500 MHz
fOUT = 950 MHz
fOUT = 1850 MHz
fOUT = 2150 MHz
Single Tone, fDAC = 6000 MSPS
fOUT = 200 MHz
fOUT = 500 MHz
fOUT = 950 MHz
fOUT = 1850 MHz
fOUT = 2150 MHz
Single Tone, fDAC = 3000 MSPS
fOUT = 200 MHz
fOUT = 500 MHz
fOUT = 950 MHz
SINGLE-SIDEBAND PHASE NOISE OFFSET
1 kHz
10 kHz
100 kHz
600 kHz
1.2 MHz
1.8 MHz
6 MHz
DAC TO DAC OUTPUT ISOLATION
AD9174
Test Conditions/Comments
0 dBFS, NSD measurement taken at 10% away
from fOUT, shuffle on
Min
Typ
Max
Unit
−163
−163
−162
−160
−158
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−164
−163
−161
−157
−155
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−163
−159
−155
dBc/Hz
dBc/Hz
dBc/Hz
−97
−105
−114
−126
−133
−137
−148
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−77
−70
−68
dB
dB
dB
Loop filter component values according to
Figure 90 are as follows: C1 = 22 nF, R1 = 232 Ω,
C2 = 2.4 nF, C3 = 33 nF; PFD frequency =
500 MHz, fOUT = 1.8 GHz, fDAC = 12 GHz
Taken using the AD9174-FMC-EBZ evaluation
board
Dual Band—fDAC = 12000 MSPS, Mode 1 (L = 2, M = 4)
fOUT = 1840 MHz
fOUT = 2650 MHz
fOUT = 3700 MHz
Rev. B | Page 15 of 165
AD9174
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Table 10.
Parameter
ISET, FILT_COARSE, FILT_BYP, FILT_VCM
SERDINx±
SYNCOUT0±, SYNCOUT1±, RESET,
TXEN0, TXEN1, IRQ0, IRQ1, CS,
SCLK, SDIO, SDO
DAC0±, DAC1±, CLKIN±, CLKOUT±,
FILT_FINE
SYSREF±
AVDD1.0, DVDD1.0, SVDD1.0 to GND
AVDD1.8, DVDD1.8 to GND
Maximum Junction Temperature (TJ)1
Storage Temperature Range
Reflow
1
Rating
−0.3 V to AVDD1.8 + 0.3 V
−0.2 V to SVDD1.0 + 0.2 V
−0.3 V to DVDD1.8 + 0.3 V
−0.2 V to AVDD1.0 + 0.2 V
−0.2 V to DVDD1.0 + 0.2 V
−0.2 V to +1.2 V
−0.3 V to 2.2 V
118°C
−65°C to +150°C
260°C
Some operating modes of the device may cause the device to approach or
exceed the maximum junction temperature during operation at supported
ambient temperatures. Removal of heat from the device may require
additional measures such as active airflow, heat sinks, or other measures.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJC is
the junction to case thermal resistance.
Thermal resistances and thermal characterization parameters are
specified vs. the number of PCB layers in different airflow velocities
(in m/sec). The use of appropriate thermal management techniques is recommended to ensure that the maximum junction
temperature does not exceed the limits shown in Table 10.
Use the values in Table 11 in compliance with JEDEC 51-12.
Table 11. Simulated Thermal Resistance vs. PCB Layers1
PCB Type
JEDEC
2s2p
Board
12-Layer
PCB2
Airflow
Velocity
(m/sec)
0.0
1.0
2.5
0.0
1.0
2.5
1
REFLOW PROFILE
N/A means not applicable.
Non JEDEC thermal resistance.
3
1SOP PCB with no vias in PCB.
4
1SOP PCB with 7 × 7 standard JEDEC vias.
2
The AD9174 reflow profile is in accordance with the JEDEC
JESD20 criteria for Pb-free devices. The maximum reflow
temperature is 260°C.
θJA
25.3
22.6
21.0
15.4
13.1
11.6
ESD CAUTION
Rev. B | Page 16 of 165
θJC_TOP
2.43
N/A
N/A
2.4
N/A
N/A
θJC_BOT
3.04
N/A
N/A
2.6
N/A
N/A
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Data Sheet
AD9174
1
2
3
4
5
6
7
8
9
10
11
12
A
GND
SERDIN7+
SERDIN6+
SERDIN5+
SERDIN4+
GND
GND
SERDIN3+
SERDIN2+
SERDIN1+
SERDIN0+
GND
B
GND
SERDIN7–
SERDIN6–
SERDIN5–
SERDIN4–
GND
GND
SERDIN3–
SERDIN2–
SERDIN1–
SERDIN0–
GND
C
SVDD1.0
SVDD1.0
GND
GND
SVDD1.0
DVDD1.8
SVDD1.0
SVDD1.0
GND
GND
SVDD1.0
SVDD1.0
D
SYNCOUT1+
SYNCOUT1–
DVDD1.8
TXEN1
GND
SVDD1.0
GND
TXEN0
IRQ0
DVDD1.8
SYNCOUT0–
SYNCOUT0+
E
DNC
DNC
DVDD1.8
SDO
SCLK
CS
SDIO
RESET
IRQ1
DVDD1.8
DNC
DNC
F
GND
GND
GND
DAVDD1.0
DVDD1.0
DVDD1.0
DVDD1.0
DVDD1.0
DAVDD1.0
GND
GND
GND
G
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
H
SYSREF+
SYSREF–
AVDD1.0
AVDD1.0
AVDD1.0
FILT_FINE
FILT_
COARSE
AVDD1.0
AVDD1.0
AVDD1.0
GND
CLKIN–
J
GND
DNC
GND
GND
GND
AVDD1.0
FILT_BYP
GND
GND
GND
GND
CLKIN+
K
CLKOUT+
GND
AVDD1.8
DNC
AVDD1.8
FILT_VCM
AVDD1.8
GND
GND
AVDD1.8
GND
GND
L
CLKOUT–
GND
AVDD1.8
GND
GND
AVDD1.8
AVDD1.8
GND
GND
AVDD1.8
GND
ISET
M
GND
AVDD1.0
GND
DAC1+
DAC1–
GND
GND
DAC0–
DAC0+
GND
AVDD1.0
GND
GROUND
SERDES INPUT
1.0V DIGITAL SUPPLY
DAC PLL LOOP FILTER PINS
CMOS I/O
1.0V ANALOG SUPPLY
SYSREF±/SYNCOUTx±
1.0V DIGITAL/ANALOG SUPPLY
DAC RF OUTPUTS
REFERENCE
1.8V ANALOG SUPPLY
1.0V SERDES SUPPLY
1.8V DIGITAL SUPPLY
RF CLOCK PINS
DNC = DO NOT CONNECT
16794-002
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 12. Pin Function Descriptions
Pin No.
1.0 V Supply
H3, H4, H5, H8 to H10, J6, M2, M11
Mnemonic
Description
AVDD1.0
1.0 V Clock and Analog Supplies. These pins supply the clock receivers, clock
distribution, the on-chip DAC clock multiplier, and the DAC analog core. Clean
power supply rail sources are required on these pins.
1.0 V Digital Supplies. These pins supply power to the DAC digital circuitry.
Clean power supply rail sources are required on these pins.
1.0 V Digital to Analog Supplies. These pins can share a supply rail with the
DVDD1.0 supply (electrically connected) but must have separate supply plane
and decoupling capacitors for the PCB layout to improve isolation for these
two pins. Clean power supply rail sources are required on these pins.
1.0 V SERDES Supplies to the JESD204B Data Interface. Clean power supply rail
sources are required on these pins.
F5 to F8
DVDD1.0
F4, F9
DAVDD1.0
C1, C2, C5, C7, C8, C11, C12, D6
SVDD1.0
1.8 V Supply
K3, K5, K7, K10, L3, L6, L7, L10
C6, D3, D10, E3, E10
AVDD1.8
DVDD1.8
1.8 V Analog Supplies to the On-Chip DAC Clock Multiplier and the DAC
Analog Core. Clean power supply rail sources are required on these pins.
1.8 V Digital Supplies to the JESD204B Data Interface and the Other
Input/Output Circuitry, Such as the SPI. Clean power supply rail sources are
required on these pins.
Rev. B | Page 17 of 165
AD9174
Pin No.
Ground
A1, A6, A7, A12, B1, B6, B7, B12, C3, C4,
C9, C10, D5, D7, F1 to F3, F10 to F12,
G1 to G12, H11, J1, J3 to J5, J8 to J11,
K2, K8, K9, K11, K12, L2, L4, L5, L8, L9,
L11, M1, M3, M6, M7, M10, M12
RF Clock
J12
H12
K1
L1
System Reference
H1
H2
On-Chip DAC PLL Loop Filter
H6
Data Sheet
Mnemonic
Description
GND
Device Common Ground.
CLKIN+
Positive Device Clock Input. This pin is the clock input for the on-chip DAC
clock multiplier, REFCLK, when the DAC PLL is on. This pin is also the clock
input for the DAC sample clock or device clock (DACCLK) when the DAC PLL is
off. AC couple this input. There is an internal 100 Ω resistor between this pin
and CLKIN−.
Negative Device Clock Input.
Positive Device Clock Output. This pin is the clock output of a divided down
DACCLK and is available with the DAC PLL on and off. The divide down ratios
are by 1, 2, 3, or 4.
Negative Device Clock Output.
CLKIN−
CLKOUT+
CLKOUT−
SYSREF+
SYSREF−
FILT_FINE
H7
FILT_COARSE
J7
FILT_BYP
K6
FILT_VCM
SERDES Data Bits
A2
B2
A3
B3
A4
B4
A5
B5
A8
B8
A9
B9
A10
B10
A11
B11
SERDIN7+
SERDIN7−
SERDIN6+
SERDIN6−
SERDIN5+
SERDIN5−
SERDIN4+
SERDIN4−
SERDIN3+
SERDIN3−
SERDIN2+
SERDIN2−
SERDIN1+
SERDIN1−
SERDIN0+
SERDIN0−
Positive System Reference Input. It is recommended to ac couple this pin, but
dc coupling is also acceptable. See the SYSREF± specifications for the dc
common-mode voltage.
Negative System Reference Input. It is recommended to ac couple this pin, but
dc coupling is also acceptable. See the SYSREF± specifications for the dc
common-mode voltage.
On-Chip DAC Clock Multiplier and PLL Fine Loop Filter Input. If the PLL is not in
use, leave this pin floating and disable the PLL via the control registers.
On-Chip DAC Clock Multiplier and PLL Coarse Loop Filter Input. If the PLL is not
in use, leave this pin floating and disable the PLL via the control registers.
On-Chip DAC Clock Multiplier and LDO Bypass. Add a high quality ceramic
bypass capacitor between 2 μF and 10 μF at this node. Ideally this capacitor is
10 μF X7R or better. If the PLL is not in use, leave this pin floating and disable
the PLL via the control registers.
On-Chip DAC Clock Multiplier and VCO Common-Mode Input. If the PLL is not
in use, leave this pin floating and disable the PLL via the control registers.
SERDES Data Bit 7, Positive.
SERDES Data Bit 7, Negative.
SERDES Data Bit 6, Positive.
SERDES Data Bit 6, Negative.
SERDES Data Bit 5, Positive.
SERDES Data Bit 5, Negative.
SERDES Data Bit 4, Positive.
SERDES Data Bit 4, Negative.
SERDES Data Bit 3, Positive.
SERDES Data Bit 3, Negative.
SERDES Data Bit 2, Positive.
SERDES Data Bit 2, Negative.
SERDES Data Bit 1, Positive.
SERDES Data Bit 1, Negative.
SERDES Data Bit 0, Positive.
SERDES Data Bit 0, Negative.
Rev. B | Page 18 of 165
Data Sheet
Pin No.
Sync Output
D12
AD9174
Mnemonic
Description
SYNCOUT0+
Positive Sync (Active Low) Output Signal, Channel Link 0. This pin is LVDS or
CMOS selectable.
Negative Sync (Active Low) Output Signal, Channel Link 0. This pin is LVDS or
CMOS selectable.
Positive Sync (Active Low) Output Signal, Channel Link 1. This pin is LVDS or
CMOS selectable.
Negative Sync (Active Low) Output Signal, Channel Link 1. This pin is LVDS or
CMOS selectable.
D11
SYNCOUT0−
D1
SYNCOUT1+
D2
SYNCOUT1−
Serial Port Interface
E4
E7
E5
E6
E8
SDO
SDIO
SCLK
CS
RESET
Serial Port Data Output (CMOS Levels with Respect to DVDD1.8).
Serial Port Data Input/Output (CMOS Levels with Respect to DVDD1.8).
Serial Port Clock Input (CMOS Levels with Respect to DVDD1.8).
Serial Port Chip Select, Active Low (CMOS Levels with Respect to DVDD1.8).
Reset, Active Low (CMOS Levels with Respect to DVDD1.8).
Interrupt Request
D9
IRQ0
Interrupt Request 0. This pin is an open-drain, active low output (CMOS levels
with respect to DVDD1.8). Connect a pull-up resistor to DVDD1.8 to prevent this
pin from floating when inactive.
Interrupt Request 1. This pin is an open-drain, active low output (CMOS levels
with respect to DVDD1.8). Connect a pull-up resistor to DVDD1.8 to prevent this
pin from floating when inactive.
E9
CMOS Input/Outputs
D8
D4
DAC Analog Outputs
M9
M8
M4
M5
Reference
L12
Do Not Connect
E1, E2, E11, E12, J2, K4
IRQ1
TXEN0
TXEN1
Transmit Enable for DAC0. The CMOS levels are determined with respect to
DVDD1.8.
Transmit Enable for DAC1. The CMOS levels are determined with respect to
DVDD1.8.
DAC0+
DAC0−
DAC1+
DAC1−
DAC0 Positive Current Output.
DAC0 Negative Current Output.
DAC1 Positive Current Output.
DAC1 Negative Current Output.
ISET
Device Bias Current Setting Pin. Connect a 5 kΩ resistor from this pin to GND,
preferably with 4/SYSREF± frequency. In addition, the
edge rate must be sufficiently fast to allow SYSREF± sampling
clocks to correctly sample the rising SYSREF± edge before the
next sample clock.
When ac coupling the SYSREF± inputs, ensure that the
SYSREF_INPUTMODE bit (Register 0x084, Bit 6) is set to 0,
ac-coupled, to enable the internal receiver biasing circuitry and
prevent overstress on the SYSREF± receiver pins. AC coupling
allows a differential voltage swing from 200 mV to 1 V on the
SYSREF± pins.
SYSREF± Jitter Window
Tolerance (DAC Clock Cycles)
±½
±4
±8
±12
±16
±20
+24
±28
1
SYSREF_ERR_WINDOW
(Register 0x039, Bits[5:0])1
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
The two least significant digits are ignored because the SYSREF± signal is
sampled with a divide by 4 version of the DAC clock. As a result, the jitter
window is set by this divide by 4 clock rather than the DAC clock. It is
recommended that at least a four-DAC clock SYSREF± jitter window be
chosen.
The IRQ_SYSREF_JITTER can be configured as described
in the Interrupt Request Operation section to indicate the
SYSREF± signal has varied, and to request the SPI sequence for
a sync be performed again.
Sync Procedure
SYSREF± Sampling
The procedure for enabling the sync is as follows:
The SYSREF± signal is sampled by a divide by 4 version of the
DAC clock. Thus, the minimum pulse width of the SYSREF±
signal must exceed 4 DAC clock periods to ensure accurate
sampling. The delay between the SYSREF± and DAC clock
input signal does not need to be timing constrained.
1.
2.
Rev. B | Page 42 of 165
Set up the DAC and the SERDES PLL, and enable the CDR
(see the Start-Up Sequence section).
Set Register 0x03B to 0xF1 to enable the synchronization
circuitry. If using the soft on/off feature, set Register 0x03B
to 0xF3 to ramp the datapath data before and after the
synchronization.
Data Sheet
3.
4.
5.
6.
AD9174
If Subclass 1, configure the SYSREF± settings as follows:
a. Set Register 0x039 (SYSREF± jitter window). See Table 24
for settings.
b. Set Register 0x036 = SYSREF_COUNT. Leave the
setting as 0 to bypass.
Perform a one-shot sync.
a. Set Register 0x03A = 0x00. Clear one-shot mode if
already enabled.
b. Set Register 0x03A = 0x02. Enable one-shot sync
mode.
If Subclass 1, send a SYSREF± edge. If pulse counting,
multiple SYSREF± edges are required. Sending SYSREF±
edges triggers the synchronization.
Read back the SYNC_ROTATION_DONE bit
(Register 0x03A, Bit 4) to confirm the rotation occurred.
Subclass 0
Subclass 0 mode provides deterministic latency to within
several PCLK cycles. It does not require any signal on the
SYSREF± pins, which can be left disconnected.
Subclass 0 still requires that all lanes arrive within the same LMFC
cycle and the dual DACs must be synchronized to each other.
Subclass 1
This mode gives deterministic latency and allows the link to be
synchronized to within a few DAC clock cycles. Across the full
operating range, for both supply and temperature, it is within
±2.5 DAC clock periods for a 6 GHz DAC clock rate or ±4 DAC
clock periods for a 12.6 GHz DAC clock rate. If both supply and
temperature stability are maintained, the link can be
synchronized to within ±1.5 DAC clock periods for a 6 GHz
DAC clock rate or ±2.5 DAC clock periods for a 12.6 GHz DAC
clock rate. Achieving this latency requires an external, low jitter
SYSREF± signal that is accurately phase aligned to the DAC clock.
Resynchronizing LMFC Signals
If desired, the sync procedure can be repeated to realign the
LMFC clock to the reference signal by repeating Step 2 to
Step 6, described in the Sync Procedure section. When the
one-shot sync is armed (writing Register 0x03A = 0x02), the
SYNCOUTx± signals deassert to drop the JESD204B links and
reassert after the rotation completes.
Deterministic Latency Requirements
Several key factors are required for achieving deterministic
latency in a JESD204B Subclass 1 system, as follows:
Deterministic Latency
The SYSREF± signal distribution skew within the system
must be less than the desired uncertainty.
The total latency variation across all lanes, links, and
devices must be ≤12 PCLK periods, which includes both
variable delays and the variation in fixed delays from lane
to lane, link to link, and device to device in the system.
JESD204B systems contain various clock domains distributed
throughout. Data traversing from one clock domain to a
different clock domain can lead to ambiguous delays in the
JESD204B link. These ambiguities lead to nonrepeatable
latencies across the link from power cycle to power cycle with
each new link establishment. Section 6 of the JESD204B
specification addresses the issue of deterministic latency with
mechanisms defined as Subclass 1 and Subclass 2.
The AD9174 supports JESD204B Subclass 0 and Subclass 1
operation, but not Subclass 2. Write the subclass to
Register 0x458, Bits[7:5].
LINK DELAY = DELAYFIXED + DELAYVARIABLE
LOGIC DEVICE
(JESD204B Tx)
CHANNEL
JESD204B Rx
DSP
DAC
POWER CYCLE
VARIANCE
LMFC
ALIGNED DATA
AT Rx OUTPUT
ILAS
DATA
ILAS
DATA
FIXED DELAY
VARIABLE
DELAY
Figure 63. JESD204B Link Delay = Fixed Delay + Variable Delay
Rev. B | Page 43 of 165
16794-023
DATA AT
Tx INPUT
AD9174
Data Sheet
Link Delay
cycles. The PCLK factor, or number of frame clock cycles per
PCLK cycle, is equal to 4/f. For more information on this
relationship, see the Clock Relationships section.
The link delay of a JESD204B system is the sum of the fixed and
variable delays from the transmitter, channel, and receiver as
shown in Figure 63.
For proper functioning, all lanes on a link must be read during
the same LMFC period. Section 6.1 of the JESD204B specification states that the LMFC period must be larger than the maximum
link delay. For the AD9174, this is not necessarily the case. Instead,
the AD9174 use a local LMFC for each link (LMFCRx) that can
be delayed from the SYSREF± aligned LMFC. Because the
LMFC is periodic, this delay can account for any amount of
fixed delay. As a result, the LMFC period must only be larger
than the variation in the link delays, and the AD9174 can achieve
proper performance with a smaller total latency. Figure 64 and
Figure 65 show a case where the link delay is greater than an LMFC
period. The link delay can be accommodated by delaying LMFCRx.
POWER CYCLE
VARIANCE
DATA
LATE ARRIVING
LMFC REFERENCE
All the known system delays can be used to calculate LMFCVar
and LMFCDel.
The example shown in Figure 66 is demonstrated in the following
steps. This example is in Subclass 1 to achieve deterministic latency,
and the example uses the case for F = 2. Therefore, the number of
PCLK cycles per multiframe = 16. Because PCBFixed LMFC Period Example
POWER CYCLE
VARIANCE
3.
LMFC
ALIGNED DATA
ILAS
DATA
LMFC_DELAY
LMFC REFERENCE FOR ALL POWER CYCLES
FRAME CLOCK
16794-025
LMFCRX
4.
Figure 65. LMFC_DELAY_x to Compensate for Link Delay > LMFC
The method to select the LMFCDel (Register 0x304) and
LMFCVar (Register 0x306) variables is described in the Link
Delay Setup Example, with Known Delays section and the Link
Delay Setup Example, Without Known Delay section. The setting
for LMFCDel must not equal or exceed the number of PCLK
cycles per LMFC period in the current mode. Similarly, LMFCVar
must not exceed the number of PCLK cycles per LMFC period in
the current mode or be set to
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