AD9175BBPZRL

Dual, 11-Bit/16-Bit, 12.6 GSPS RF DAC with Wideband Channelizers AD9175 Data Sheet FEATURES Supports multiband wireless applications 3 bypassable, complex data input channels per RF DAC 3.08 GSPS maximum complex input data rate per input channel, 11-bit resolution 1 independent NCO per input channel Proprietary, low spurious and distortion design 2-tone IMD3 = −83 dBc at 1.84 GHz, −7 dBFS/tone RF output SFDR 11 Gbps Lane rate ≤ 11 Gbps Lane rate > 11 Gbps Lane rate ≤ 11 Gbps1 11.67 12.37 11.79 12.6 If using the on-chip PLL, the maximum DAC speed is limited to the maximum PLL speed of 12.42 GSPS, as listed in Table 2. Rev. B | Page 5 of 150 Typ Max Unit GSPS GSPS GSPS GSPS AD9175 Data Sheet POWER SUPPLY DC SPECIFICATIONS AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) = 20 mA, unless otherwise noted. For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which corresponds to TJ = 51°C. Table 4. Parameter DUAL-LINK MODES Mode 1 (L = 2, M = 4, NP = 16, N = 16) AVDD1.0 AVDD1.8 DVDD1.0 DVDD1.8 SVDD1.0 Total Power Dissipation Mode 4 (L = 4, M = 4, NP = 16, N = 16) AVDD1.0 AVDD1.8 DVDD1.0 DVDD1.8 SVDD1.0 Total Power Dissipation Mode 0 (L = 1, M = 2, NP = 16, N = 16) AVDD1.0 AVDD1.8 DVDD1.0 Test Conditions/Comments Min 11.7965 GSPS DAC rate, 184.32 MHz PLL reference clock, 32× total interpolation (4×, 8×), 40 MHz tone at −3 dBFS, channel gain = −6 dB, channel NCOs = ±150 MHz, main NCO = 2 GHz, SYNCOUTx± in LVDS mode All supply levels set to nominal values All supply levels set to 5% tolerance Combined current consumption with the DAVDD1.0 supply All supply levels set to nominal values All supplies at 5% tolerance All supply levels set to nominal values All supplies at 5% tolerance Typ Max Unit 725 775 110 1020 1120 130 mA mA mA 1100 1170 35 290 305 2.37 1670 1850 50 510 560 3.38 mA mA mA mA mA W 11.7965 GSPS DAC rate, 491.52 MHz PLL reference clock, 24× total interpolation (3×, 8×), 40 MHz tone at −3 dBFS, channel gain = −6 dB, channel NCOs = ±150 MHz, main NCO = 2 GHz, SYNCOUTx± in LVDS mode Combined current consumption with the DAVDD1.0 supply 5.89824 GSPS DAC rate, 184.32 MHz PLL reference clock, 16× total interpolation (2×, 8×), 40 MHz tone at −3 dBFS, channel NCO disabled, main NCO = 1.8425 GHz, SYNCOUTx± in LVDS mode All supply levels set to nominal values All supplies at 5% tolerance Combined current consumption with the DAVDD1.0 supply All supply levels set to nominal values All supplies at 5% tolerance DVDD1.8 SVDD1.0 Total Power Dissipation Rev. B | Page 6 of 150 725 110 1150 35 425 2.56 mA mA mA mA mA W 400 425 110 670 745 130 mA mA mA 570 610 35 175 1.40 960 1070 50 340 2.15 mA mA mA mA W Data Sheet Parameter Mode 3 (L = 2, M = 2, NP = 16, N = 16) AVDD1.0 AVDD1.8 DVDD1.0 DVDD1.8 SVDD1.0 Total Power Dissipation Mode 9 (L = 4, M = 2, NP = 16, N = 16) AVDD1.0 AVDD1.8 DVDD1.0 DVDD1.8 SVDD1.0 Total Power Dissipation Mode 2 (L = 3, M = 6, NP = 16, N = 16) AVDD1.0 AVDD1.8 DVDD1.0 DVDD1.8 SVDD1.0 Total Power Dissipation SINGLE-LINK MODES Mode 17 (L = 8, M = 2, NP = 12, N = 11) AVDD1.0 AVDD1.8 DVDD1.0 DVDD1.8 AVDD1.0 AD9175 Test Conditions/Comments 11.7965 GSPS DAC rate, 184.32 MHz PLL reference clock, 24× total interpolation (3×, 8×), 40 MHz tone at −3 dBFS, channel NCO disabled, main NCO = 2.655 GHz, SYNCOUTx± in LVDS mode All supply levels set to nominal values All supplies at 5% tolerance Combined current consumption with the DAVDD1.0 supply All supply levels set to nominal values All supplies at 5% tolerance All supply levels set to nominal values All supplies at 5% tolerance 12 GSPS DAC rate, 184.32 MHz PLL reference clock, 8× total interpolation (1×, 8×), 10 MHz tone at −3 dBFS, channel NCO disabled, main NCO = 3.072 GHz, SYNCOUTx± in LVDS mode All supply levels set to nominal values All supplies at 5% tolerance Combined current consumption with the DAVDD1.0 supply All supply levels set to nominal values All supplies at 5% tolerance All supply levels set to nominal values All supplies at 5% tolerance 12 GSPS DAC rate, 375 MHz PLL reference clock, 48× total interpolation (6×, 8×), 30 MHz tone at −3 dBFS, channel gain = −11 dB, channel NCOs = 20 MHz, main NCO = 2.1 GHz All supply levels set to nominal values All supplies at 5% tolerance Combined current consumption with the DAVDD1.0 supply All supply levels set to nominal values All supplies at 5% tolerance All supply levels set to nominal values All supplies at 5% tolerance 3.4 GSPS DAC rate, 187.5 MHz PLL reference clock, 1× total interpolation (1×, 1×), 1.2 GHz tone at −3 dBFS, channel and main NCOs disabled All supply levels set to nominal values All supplies at 5% tolerance Combined current consumption with the DVDD1.0 supply All supply levels set to nominal values All supplies at 5% tolerance All supply levels set to nominal values All supplies at 5% tolerance Rev. B | Page 7 of 150 Min Typ Max Unit 725 775 110 mA mA mA 1020 1070 35 245 250 2.25 mA mA mA mA mA W 740 785 110 1030 1135 130 mA mA mA 1010 1070 35 530 550 2.54 1580 1740 50 840 910 3.63 mA mA mA mA mA W 735 785 110 1030 1135 130 1370 1460 35 410 430 2.77 1800 1980 50 680 755 3.69 mA mA mA mA mA mA mA mA mA W 260 275 85 510 580 100 mA mA mA 500 515 0.3 5 3 780 950 1 100 120 mA mA mA mA mA AD9175 Parameter Total Power Dissipation DUAL-LINK, MODE 3 (NCO ONLY, SINGLE-CHANNEL MODE, NO SERDES) Mode 3 AVDD1.0 Data Sheet Test Conditions/Comments Min DVDD1.8 SVDD1.0 Total Power Dissipation DUAL-LINK, MODE 4 (NCO ONLY, DUAL-CHANNEL MODE, NO SERDES) Mode 4 AVDD1.0 AVDD1.8 DVDD1.0 Max 2.05 Unit W 410 435 110 660 750 130 mA mA mA 500 515 0.3 5 3 1.11 780 950 1 100 120 1.671 mA mA mA mA mA W 750 790 110 1030 1130 130 mA mA mA 1200 1300 0.3 5 2.15 1590 1750 1 100 2.851 mA mA mA mA W 6 GSPS DAC rate, 300 MHz PLL reference clock, 8× total interpolation (1×, 8×), no input tone (dc internal level = 0x50FF), channel NCO = 40 MHz, main NCO = 1.8425 GHz All supply levels set to nominal values All supplies at 5% tolerance AVDD1.8 DVDD1.0 Typ 1.2 Combined current consumption with the DAVDD1.0 supply All supply levels set to nominal values All supplies at 5% tolerance All supply levels set to nominal values All supplies at 5% tolerance 12 GSPS DAC rate, 500 MHz PLL reference clock, 32× total interpolation (4×, 8×), no input tone (dc internal level = 0x2AFF), channel NCOs = ±150 MHz, main NCO = 2 GHz All supply levels set to nominal values All supplies at 5% tolerance Combined current consumption with the DAVDD1.0 supply All supply levels set to nominal values All supplies at 5% tolerance DVDD1.8 SVDD1.0 Total Power Dissipation SERIAL PORT AND CMOS PIN SPECIFICATIONS AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) = 20 mA, unless otherwise noted. For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which corresponds to TJ = 51°C. Table 5. Parameter WRITE OPERATION Maximum SCLK Clock Rate SCLK Clock High SCLK Clock Low SDIO to SCLK Setup Time SCLK to SDIO Hold Time CS to SCLK Setup Time SCLK to CS Hold Time Symbol fSCLK, 1/tSCLK tPWH tPWL tDS tDH tS tH READ OPERATION SCLK Clock Rate SCLK Clock High SCLK Clock Low SDIO to SCLK Setup Time fSCLK, 1/tSCLK tPWH tPWL tDS Test Comments/Conditions See Figure 53 SCLK = 20 MHz SCLK = 20 MHz Min Typ Max 80 5.03 1.6 1.154 0.577 1.036 −5.3 Unit MHz ns ns ns ns ns ps See Figure 52 Rev. B | Page 8 of 150 48.58 5.03 1.6 1.158 MHz ns ns ns Data Sheet AD9175 Parameter SCLK to SDIO Hold Time CS to SCLK Setup Time SCLK to SDIO Data Valid Time SCLK to SDO Data Valid Time CS to SDIO Output Valid to High-Z Symbol tDH tS tDV tDV Test Comments/Conditions Not shown in Figure 52 or Figure 53 Not shown in Figure 52 or Figure 53 CS to SDO Output Valid to High-Z INPUTS (SDIO, SCLK, CS, RESET, TXEN0, and TXEN1) Voltage Input High Low Current Input High Low OUTPUTS (SDIO, SDO) Voltage Output High 0 mA load 4 mA load Low 0 mA load 4 mA load Current Output High Low INTERRUPT OUTPUTS (IRQ0, IRQ1) Voltage Output High Low VIH VIL Min 0.537 1.036 9.6 13.7 5.4 Typ Max 9.59 ns 1.48 0.425 IIH IIL Unit ns ns ns ns ns ±100 V V ±100 nA nA 1.69 1.52 V V VOH VOL 0.045 0.175 IOH IOL 4 4 VOH VOL V V mA mA 1.71 0.075 V V DIGITAL INPUT DATA TIMING SPECIFICATIONS AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) = 20 mA, unless otherwise noted. For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which corresponds to TJ = 51°C. Table 6. Parameter LATENCY1 Channel Interpolation Factor, Main Datapath Interpolation Factor 1, 12 1, 82 1, 122 2, 62 Test Conditions/Comments LMFC_VAR_x = 12, LMFC_DELAY_x = 12, unless otherwise noted JESD204B Mode 153 JESD204B Mode 16 JESD204B Mode 17 JESD204B Mode 3 JESD204B Mode 83 JESD204B Mode 9 JESD204B Mode 83 JESD204B Mode 9 JESD204B Mode 3, Mode 4 JESD204B Mode 5 Rev. B | Page 9 of 150 Min Typ 420 440 590 1390 1820 1920 2700 2840 1970 1770 Max Unit DAC clock cycles DAC clock cycles DAC clock cycles DAC clock cycles DAC clock cycles DAC clock cycles DAC clock cycles DAC clock cycles DAC clock cycles DAC clock cycles AD9175 Parameter 2, 82 3, 62 7 3, 82 4, 62 4, 82 6, 62 6, 82 8, 62 8, 82 DETERMINISTIC LATENCY Fixed Variable SYSREF± TO LMFC DELAY Data Sheet Test Conditions/Comments JESD204B Mode 0 JESD204B Mode 3, Mode 4 JESD204B Mode 3, Mode 4 JESD204B Mode 5, Mode 6 JESD204B Mode 3, Mode 4 JESD204B Mode 5, Mode 6 JESD204B Mode 0, Mode 1, Mode 2 JESD204B Mode 0, Mode 1, Mode 2 JESD204B Mode 0, Mode 1, Mode 2 JESD204B Mode 0, Mode 1, Mode 2 JESD204B Mode 7 JESD204B Mode 7 Min Typ 2020 2500 2880 2630 3310 2980 2410 3090 3190 4130 3300 4270 Max Unit DAC clock cycles DAC clock cycles DAC clock cycles DAC clock cycles DAC clock cycles DAC clock cycles DAC clock cycles DAC clock cycles DAC clock cycles DAC clock cycles DAC clock cycles DAC clock cycles 13 2 PCLK4 PCLK cycles DAC clock cycles 0 1 Total latency (or pipeline delay) through the device is calculated as follows: total latency = interface latency + fixed latency + variable latency + pipeline delay. The first value listed in this specification is the interpolation factor, and the second value is the main datapath interpolation factor. 3 LMFC_VAR_x = 7 and LMFC_DELAY_x = 4. 4 PCLK is the internal processing clock for the AD9175 and equals the lane rate ÷ 40. 2 JESD204B INTERFACE ELECTRICAL AND SPEED SPECIFICATIONS AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) = 20 mA, unless otherwise noted. For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which corresponds to TJ = 51°C. Table 7. Parameter JESD204B SERIAL INTERFACE RATE (SERIAL LANE RATE) JESD204B DATA INPUTS Input Leakage Current Logic High Logic Low Unit Interval Common-Mode Voltage Differential Voltage Differential Impedance SYSREF± INPUT Differential Impedance DIFFERENTIAL OUTPUTS (SYNCOUT0±, SYNCOUT1±)1 Output Differential Voltage Output Offset Voltage SINGLE-ENDED OUTPUTS (SYNCOUT0±, SYNCOUT1±) Output Voltage High Low Current Output High Low 1 Symbol Test Conditions/Comments Min 3 TA = 25°C Input level = 1.0 V ± 0.25 V Input level = 0 V UI VRCM R_VDIFF ZRDIFF AC-coupled At dc Typ Max 15.4 Unit Gbps 66.7 +1.1 1050 120 μA μA ps V mV Ω 10 −4 333 −0.05 110 80 100 100 Ω Driving 100 Ω differential load VOD VOS 320 1.08 390 1.12 460 1.15 mV V 0.045 V V Driving 100 Ω differential load VOH VOL IOH IOL IEEE Standard 1596.3 LVDS compatible. Rev. B | Page 10 of 150 1.69 0 0 mA mA Data Sheet AD9175 INPUT DATA RATES AND SIGNAL BANDWIDTH SPECIFICATIONS AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) = 20 mA, unless otherwise noted. For the minimum and maximum values, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which corresponds to TJ = 51°C. Table 8. Parameter1 INPUT DATA RATE PER INPUT CHANNEL Test Conditions/Comments Min Typ Max Unit Channel datapaths bypassed (1× interpolation), single DAC mode, 11-bit resolution 1 complex channel enabled, 16-bit resolution 1 complex channel enabled, 11-bit resolution 2 complex channels enabled 3 complex channels enabled 3400 MSPS 1230 3080 770 385 MSPS MSPS MSPS MSPS 1 complex channel enabled, 16-bit resolution (0.8 × fDATA) 1 complex channel enabled, 11-bit resolution (0.8 × fDATA) 2 complex channels enabled (0.8 × fDATA) 3 complex channels enabled (0.8 × fDATA) 1232 2464 616 308 MHz MHz MHz MHz 1540 12.6 MHz GHz −770 +770 MHz −6.3 +6.3 1232 GHz MHz COMPLEX SIGNAL BANDWIDTH PER INPUT CHANNEL MAXIMUM NCO CLOCK RATE Channel NCO Main NCO MAXIMUM NCO SHIFT FREQUENCY RANGE Channel NCO Main NCO MAXIMUM FREQUENCY SPACING ACROSS INPUT CHANNELS 1 Channel summing node = 1.575 GHz, channel interpolation rate > 1× fDAC = 12.6 GHz, main interpolation rate > 1× Maximum NCO output frequency × 0.8 Values listed for these parameters are the maximum possible when considering all JESD204B modes of operation. Some modes are more limiting, based on other parameters. Rev. B | Page 11 of 150 AD9175 Data Sheet AC SPECIFICATIONS AVDD1.0 = 1.0 V, AVDD1.8 = 1.8 V, DVDD1.0 = 1.0 V, DVDD1.8 = 1.8 V, SVDD1.0 = 1.0 V, and DAC output full-scale current (IOUTFS) = 20 mA, unless otherwise noted. For the minimum and maximum, TJ = −40°C to +118°C. For the typical values, TA = 25°C, which corresponds to TJ = 51°C. Table 9. Parameter SPURIOUS-FREE DYNAMIC RANGE (SFDR) Single Tone, fDAC = 12000 MSPS, Mode 1 (L = 2, M = 4) fOUT = 100 MHz fOUT = 500 MHz fOUT = 950 MHz fOUT = 1840 MHz fOUT = 2650 MHz fOUT = 3700 MHz Single Tone, fDAC = 6000 MSPS, Mode 0 (L = 1, M = 2) fOUT = 100 MHz fOUT = 500 MHz fOUT = 950 MHz fOUT = 1840 MHz fOUT = 2650 MHz Single Tone, fDAC = 3000 MSPS, Mode 10 (L = 8, M = 2) fOUT = 100 MHz fOUT = 500 MHz fOUT = 950 MHz Single-Band Application—Band 3 (1805 MHz to 1880 MHz) SFDR Harmonics In-Band Digital Predistortion (DPD) Band Second Harmonic Third Harmonic Fourth and Fifth Harmonic SFDR Nonharmonics In-Band DPD Band ADJACENT CHANNEL LEAKAGE RATIO 4-Channel WCDMA fDAC = 1200 MSPS, Mode 1 (L = 2, M = 4) fDAC = 6000 MSPS, Mode 0 (L = 1, M = 2) THIRD-ORDER INTERMODULATION DISTORTION (IMD3) fDAC = 12000 MSPS, Mode 1 (L = 2, M = 4) fDAC = 6000 MSPS, Mode 0 (L = 1, M = 2) Test Conditions/Comments Min Typ Max Unit −7 dBFS, shuffle enabled −81 −80 −75 −80 −75 −67 dBc dBc dBc dBc dBc dBc −85 −85 −78 −75 −69 dBc dBc dBc dBc dBc −87 −84 −81 dBc dBc dBc −82 −80 −82 −80 −95 dBc dBc dBc dBc dBc −74 −74 dBc dBc −70 −68 −66 −71 −66 dBc dBc dBc dBc dBc −83 −85 −77 −74 −72 dBc dBc dBc dBc dBc −7 dBFS, shuffle enabled −7 dBFS, shuffle enabled Mode 0, 2× to 8×, fDAC = 6000 MSPS, 368.64 MHz reference clock −7 dBFS, shuffle enabled DPD bandwidth = data rate × 0.8 −7 dBFS, shuffle enabled −1 dBFS digital backoff fOUT = 1840 MHz fOUT = 2650 MHz fOUT = 3500 MHz fOUT = 1840 MHz fOUT = 2650 MHz Two-tone test, −7 dBFS/tone, 1 MHz spacing fOUT = 1840 MHz fOUT = 2650 MHz fOUT = 3700 MHz fOUT = 1840 MHz fOUT = 2650 MHz Rev. B | Page 12 of 150 Data Sheet Parameter NOISE SPECTRAL DENSITY (NSD) Single Tone, fDAC = 12,000 MSPS fOUT = 200 MHz fOUT = 500 MHz fOUT = 950 MHz fOUT = 1850 MHz fOUT = 2150 MHz Single Tone, fDAC = 6000 MSPS fOUT = 200 MHz fOUT = 500 MHz fOUT = 950 MHz fOUT = 1850 MHz fOUT = 2150 MHz Single Tone, fDAC = 3000 MSPS fOUT = 100 MHz fOUT = 500 MHz fOUT = 950 MHz SINGLE-SIDEBAND PHASE NOISE OFFSET 1 kHz 10 kHz 100 kHz 600 kHz 1.2 MHz 1.8 MHz 6 MHz DAC TO DAC OUTPUT ISOLATION AD9175 Test Conditions/Comments 0 dBFS, NSD measurement taken at 10% away from fOUT, shuffle on Min Typ Max Unit −163 −163 −162 −160 −158 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −164 −163 −161 −157 −155 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −163 −159 −155 dBc/Hz dBc/Hz dBc/Hz −97 −105 −114 −126 −133 −137 −148 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −77 −70 −68 dB dB dB Loop filter component values according to Figure 92 are as follows: C1 = 22 nF, R1 = 232 Ω, C2 = 2.4 nF, C3 = 33 nF; PFD frequency = 500 MHz, fOUT = 1.8 GHz, fDAC = 12 GHz Taken using the AD9175-FMC-EBZ evaluation board Dual Band—fDAC = 12000 MSPS, Mode 1 (L = 2, M = 4) fOUT = 1840 MHz fOUT = 2650 MHz fOUT = 3700 MHz Rev. B | Page 13 of 150 AD9175 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 10. Parameter ISET, FILT_COARSE, FILT_BYP, FILT_VCM SERDINx± SYNCOUT0±, SYNCOUT1±, RESET, TXEN0, TXEN1, IRQ0, IRQ1, CS, SCLK, SDIO, SDO DAC0±, DAC1±, CLKIN±, CLKOUT±, FILT_FINE SYSREF± AVDD1.0, DVDD1.0, SVDD1.0 to GND AVDD1.8, DVDD1.8 to GND Maximum Junction Temperature (TJ)1 Storage Temperature Range Reflow 1 Rating −0.3 V to AVDD1.8 + 0.3 V −0.2 V to SVDD1.0 + 0.2 V −0.3 V to DVDD1.8 + 0.3 V −0.2 V to AVDD1.0 + 0.2 V −0.2 V to DVDD1.0 + 0.2 V −0.2 V to +1.2 V −0.3 V to 2.2 V 118°C −65°C to +150°C 260°C Some operating modes of the device may cause the device to approach or exceed the maximum junction temperature during operation at supported ambient temperatures. Removal of heat from the device may require additional measures such as active airflow, heat sinks, or other measures. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. θJA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. θJC is the junction to case thermal resistance. Thermal resistances and thermal characterization parameters are specified vs. the number of PCB layers in different airflow velocities (in m/sec). The use of appropriate thermal management techniques is recommended to ensure that the maximum junction temperature does not exceed the limits shown in Table 10. Use the values in Table 11 in compliance with JEDEC 51-12. Table 11. Simulated Thermal Resistance vs. PCB Layers1 PCB Type JEDEC 2s2p Board 12-Layer PCB2 Airflow Velocity (m/sec) 0.0 1.0 2.5 0.0 1.0 2.5 1 REFLOW PROFILE N/A means not applicable. Non JEDEC thermal resistance. 3 1SOP PCB with no vias in PCB. 4 1SOP PCB with 7 × 7 standard JEDEC vias. 2 The AD9175 reflow profile is in accordance with the JEDEC JESD20 criteria for Pb-free devices. The maximum reflow temperature is 260°C. θJA 25.3 22.6 21.0 15.4 13.1 11.6 ESD CAUTION Rev. B | Page 14 of 150 θJC_TOP 2.43 N/A N/A 2.4 N/A N/A θJC_BOT 3.04 N/A N/A 2.6 N/A N/A Unit °C/W °C/W °C/W °C/W °C/W °C/W Data Sheet AD9175 1 2 3 4 5 6 7 8 9 A GND SERDIN7+ SERDIN6+ SERDIN5+ SERDIN4+ GND GND SERDIN3+ SERDIN2+ B GND SERDIN7– SERDIN6– SERDIN5– SERDIN4– GND GND SERDIN3– C SVDD1.0 SVDD1.0 GND GND SVDD1.0 DVDD1.8 SVDD1.0 D SYNCOUT1+ SYNCOUT1– DVDD1.8 TXEN1 GND SVDD1.0 E DNC DNC DVDD1.8 SDO SCLK F GND GND GND DAVDD1.0 G GND GND GND H SYSREF+ SYSREF– J GND K 10 11 12 SERDIN1+ SERDIN0+ GND SERDIN2– SERDIN1– SERDIN0– GND SVDD1.0 GND GND SVDD1.0 SVDD1.0 GND TXEN0 IRQ0 DVDD1.8 SYNCOUT0– SYNCOUT0+ CS SDIO RESET IRQ1 DVDD1.8 DNC DNC DVDD1.0 DVDD1.0 DVDD1.0 DVDD1.0 DAVDD1.0 GND GND GND GND GND GND GND GND GND GND GND GND AVDD1.0 AVDD1.0 AVDD1.0 FILT_FINE FILT_ COARSE AVDD1.0 AVDD1.0 AVDD1.0 GND CLKIN– DNC GND GND GND AVDD1.0 FILT_BYP GND GND GND GND CLKIN+ CLKOUT+ GND AVDD1.8 DNC AVDD1.8 FILT_VCM AVDD1.8 GND GND AVDD1.8 GND GND L CLKOUT– GND AVDD1.8 GND GND AVDD1.8 AVDD1.8 GND GND AVDD1.8 GND ISET M GND AVDD1.0 GND DAC1+ DAC1– GND GND DAC0– DAC0+ GND AVDD1.0 GND GROUND SERDES INPUT 1.0V DIGITAL SUPPLY DAC PLL LOOP FILTER PINS CMOS I/O 1.0V ANALOG SUPPLY SYSREF±/SYNCOUTx± 1.0V DIGITAL/ANALOG SUPPLY DAC RF OUTPUTS REFERENCE 1.8V ANALOG SUPPLY 1.0V SERDES SUPPLY 1.8V DIGITAL SUPPLY RF CLOCK PINS DNC = DO NOT CONNECT 16795-002 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 12. Pin Function Descriptions Pin No. 1.0 V Supply H3, H4, H5, H8 to H10, J6, M2, M11 Mnemonic Description AVDD1.0 1.0 V Clock and Analog Supplies. These pins supply the clock receivers, clock distribution, the on-chip DAC clock multiplier, and the DAC analog core. Clean power supply rail sources are required on these pins. 1.0 V Digital Supplies. These pins supply power to the DAC digital circuitry. Clean power supply rail sources are required on these pins. 1.0 V Digital to Analog Supplies. These pins can share a supply rail with the DVDD1.0 supply (electrically connected) but must have separate supply plane and decoupling capacitors for the PCB layout to improve isolation for these two pins. Clean power supply rail sources are required on these pins. 1.0 V SERDES Supplies to the JESD204B Data Interface. Clean power supply rail sources are required on these pins. F5 to F8 DVDD1.0 F4, F9 DAVDD1.0 C1, C2, C5, C7, C8, C11, C12, D6 SVDD1.0 1.8 V Supply K3, K5, K7, K10, L3, L6, L7, L10 C6, D3, D10, E3, E10 AVDD1.8 DVDD1.8 1.8 V Analog Supplies to the On-Chip DAC Clock Multiplier and the DAC Analog Core. Clean power supply rail sources are required on these pins. 1.8 V Digital Supplies to the JESD204B Data Interface and the Other Input/Output Circuitry, Such as the SPI. Clean power supply rail sources are required on these pins. Rev. B | Page 15 of 150 AD9175 Pin No. Ground A1, A6, A7, A12, B1, B6, B7, B12, C3, C4, C9, C10, D5, D7, F1 to F3, F10 to F12, G1 to G12, H11, J1, J3 to J5, J8 to J11, K2, K8, K9, K11, K12, L2, L4, L5, L8, L9, L11, M1, M3, M6, M7, M10, M12 RF Clock J12 H12 K1 L1 System Reference H1 H2 On-Chip DAC PLL Loop Filter H6 Data Sheet Mnemonic Description GND Device Common Ground. CLKIN+ Positive Device Clock Input. This pin is the clock input for the on-chip DAC clock multiplier, REFCLK, when the DAC PLL is on. This pin is also the clock input for the DAC sample clock or device clock (DACCLK) when the DAC PLL is off. AC couple this input. There is an internal 100 Ω resistor between this pin and CLKIN−. Negative Device Clock Input. Positive Device Clock Output. This pin is the clock output of a divided down DACCLK and is available with the DAC PLL on and off. The divide down ratios are by 1, 2, 3, or 4. Negative Device Clock Output. CLKIN− CLKOUT+ CLKOUT− SYSREF+ SYSREF− FILT_FINE H7 FILT_COARSE J7 FILT_BYP K6 FILT_VCM SERDES Data Bits A2 B2 A3 B3 A4 B4 A5 B5 A8 B8 A9 B9 A10 B10 A11 B11 SERDIN7+ SERDIN7− SERDIN6+ SERDIN6− SERDIN5+ SERDIN5− SERDIN4+ SERDIN4− SERDIN3+ SERDIN3− SERDIN2+ SERDIN2− SERDIN1+ SERDIN1− SERDIN0+ SERDIN0− Positive System Reference Input. It is recommended to ac couple this pin, but dc coupling is also acceptable. See the SYSREF± specifications for the dc common-mode voltage. Negative System Reference Input. It is recommended to ac couple this pin, but dc coupling is also acceptable. See the SYSREF± specifications for the dc common-mode voltage. On-Chip DAC Clock Multiplier and PLL Fine Loop Filter Input. If the PLL is not in use, leave this pin floating and disable the PLL via the control registers. On-Chip DAC Clock Multiplier and PLL Coarse Loop Filter Input. If the PLL is not in use, leave this pin floating and disable the PLL via the control registers. On-Chip DAC Clock Multiplier and LDO Bypass. Add a high quality ceramic bypass capacitor between 2 μF and 10 μF at this node. Ideally this capacitor is 10 μF X7R or better. If the PLL is not in use, leave this pin floating and disable the PLL via the control registers. On-Chip DAC Clock Multiplier and VCO Common-Mode Input. If the PLL is not in use, leave this pin floating and disable the PLL via the control registers. SERDES Data Bit 7, Positive. SERDES Data Bit 7, Negative. SERDES Data Bit 6, Positive. SERDES Data Bit 6, Negative. SERDES Data Bit 5, Positive. SERDES Data Bit 5, Negative. SERDES Data Bit 4, Positive. SERDES Data Bit 4, Negative. SERDES Data Bit 3, Positive. SERDES Data Bit 3, Negative. SERDES Data Bit 2, Positive. SERDES Data Bit 2, Negative. SERDES Data Bit 1, Positive. SERDES Data Bit 1, Negative. SERDES Data Bit 0, Positive. SERDES Data Bit 0, Negative. Rev. B | Page 16 of 150 Data Sheet Pin No. Sync Output D12 AD9175 Mnemonic Description SYNCOUT0+ Positive Sync (Active Low) Output Signal, Channel Link 0. This pin is LVDS or CMOS selectable. Negative Sync (Active Low) Output Signal, Channel Link 0. This pin is LVDS or CMOS selectable. Positive Sync (Active Low) Output Signal, Channel Link 1. This pin is LVDS or CMOS selectable. Negative Sync (Active Low) Output Signal, Channel Link 1. This pin is LVDS or CMOS selectable. D11 SYNCOUT0− D1 SYNCOUT1+ D2 SYNCOUT1− Serial Port Interface E4 E7 E5 E6 E8 SDO SDIO SCLK CS RESET Serial Port Data Output (CMOS Levels with Respect to DVDD1.8). Serial Port Data Input/Output (CMOS Levels with Respect to DVDD1.8). Serial Port Clock Input (CMOS Levels with Respect to DVDD1.8). Serial Port Chip Select, Active Low (CMOS Levels with Respect to DVDD1.8). Reset, Active Low (CMOS Levels with Respect to DVDD1.8). Interrupt Request D9 IRQ0 Interrupt Request 0. This pin is an open-drain, active low output (CMOS levels with respect to DVDD1.8). Connect a pull-up resistor to DVDD1.8 to prevent this pin from floating when inactive. Interrupt Request 1. This pin is an open-drain, active low output (CMOS levels with respect to DVDD1.8). Connect a pull-up resistor to DVDD1.8 to prevent this pin from floating when inactive. E9 CMOS Input/Outputs D8 D4 DAC Analog Outputs M9 M8 M4 M5 Reference L12 Do Not Connect E1, E2, E11, E12, J2, K4 IRQ1 TXEN0 TXEN1 Transmit Enable for DAC0. The CMOS levels are determined with respect to DVDD1.8. Transmit Enable for DAC1. The CMOS levels are determined with respect to DVDD1.8. DAC0+ DAC0− DAC1+ DAC1− DAC0 Positive Current Output. DAC0 Negative Current Output. DAC1 Positive Current Output. DAC1 Negative Current Output. ISET Device Bias Current Setting Pin. Connect a 5 kΩ resistor from this pin to GND, preferably with 4/SYSREF± frequency. In addition, the edge rate must be sufficiently fast to allow SYSREF± sampling clocks to correctly sample the rising SYSREF± edge before the next sample clock. When ac coupling the SYSREF± inputs, ensure that the SYSREF_INPUTMODE bit (Register 0x084, Bit 6) is set to 0, ac-coupled, to enable the internal receiver biasing circuitry and prevent overstress on the SYSREF± receiver pins. AC coupling allows a differential voltage swing from 200 mV to 1 V on the SYSREF± pins. SYSREF± Jitter Window Tolerance (DAC Clock Cycles) ±½ ±4 ±8 ±12 ±16 ±20 +24 ±28 1 SYSREF_ERR_WINDOW (Register 0x039, Bits[5:0])1 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C The two least significant digits are ignored because the SYSREF± signal is sampled with a divide by 4 version of the DAC clock. As a result, the jitter window is set by this divide by 4 clock rather than the DAC clock. It is recommended that at least a four-DAC clock SYSREF± jitter window be chosen. The IRQ_SYSREF_JITTER can be configured as described in the Interrupt Request Operation section to indicate the SYSREF± signal has varied, and to request the SPI sequence for a sync be performed again. SYSREF± Sampling The SYSREF± signal is sampled by a divide by 4 version of the DAC clock. Thus, the minimum pulse width of the SYSREF± signal must exceed 4 DAC clock periods to ensure accurate sampling. The delay between the SYSREF± and DAC clock input signal does not need to be timing constrained. By default, the first SYSREF± rising edge at the SYSREF± inputs that is detected after asserting the SYSREF_MODE_ONESHOT bit (Register 0x03A, Bit 1) begins the synchronization and aligns the internal LMFC signal with the sampled SYSREF± edge. Rev. B | Page 40 of 150 Data Sheet AD9175 Sync Procedure each new link establishment. Section 6 of the JESD204B specification addresses the issue of deterministic latency with mechanisms defined as Subclass 1 and Subclass 2. The procedure for enabling the sync is as follows: 2. 3. 4. 5. 6. Set up the DAC and the SERDES PLL, and enable the CDR (see the Start-Up Sequence section). Set Register 0x03B to 0xF1 to enable the synchronization circuitry. If using the soft on/off feature, set Register 0x03B to 0xF3 to ramp the datapath data before and after the synchronization. If Subclass 1, configure the SYSREF± settings as follows: a. Set Register 0x039 (SYSREF± jitter window). See Table 24 for settings. b. Set Register 0x036 = SYSREF_COUNT. Leave the setting as 0 to bypass. Perform a one-shot sync. a. Set Register 0x03A = 0x00. Clear one-shot mode if already enabled. b. Set Register 0x03A = 0x02. Enable one-shot sync mode. If Subclass 1, send a SYSREF± edge. If pulse counting, multiple SYSREF± edges are required. Sending SYSREF± edges triggers the synchronization. Read back the SYNC_ROTATION_DONE bit (Register 0x03A, Bit 4) to confirm the rotation occurred. The AD9175 supports JESD204B Subclass 0 and Subclass 1 operation, but not Subclass 2. Write the subclass to Register 0x458, Bits[7:5]. Subclass 0 Subclass 0 mode provides deterministic latency to within several PCLK cycles. It does not require any signal on the SYSREF± pins, which can be left disconnected. Subclass 0 still requires that all lanes arrive within the same LMFC cycle and the dual DACs must be synchronized to each other. Subclass 1 Subclass 1 mode gives deterministic latency and allows the link to be synchronized to within a few DAC clock cycles. Across the full operating range, for both supply and temperature, it is within ±2.5 DAC clock periods for a 6 GHz DAC clock rate or ±4 DAC clock periods for a 12.6 GHz DAC clock rate. If both supply and temperature stability are maintained, the link can be synchronized to within ±1.5 DAC clock periods for a 6 GHz DAC clock rate or ±2.5 DAC clock periods for a 12.6 GHz DAC clock rate. Achieving this latency requires an external, low jitter SYSREF± signal that is accurately phase aligned to the DAC clock. Resynchronizing LMFC Signals If desired, the sync procedure can be repeated to realign the LMFC clock to the reference signal by repeating Step 2 to Step 6, described in the Sync Procedure section. When the one-shot sync is armed (writing Register 0x03A = 0x02), the SYNCOUTx± signals deassert to drop the JESD204B links and reassert after the rotation completes. Deterministic Latency Requirements Several key factors are required for achieving deterministic latency in a JESD204B Subclass 1 system, as follows:  The SYSREF± signal distribution skew within the system must be less than the desired uncertainty. The total latency variation across all lanes, links, and devices must be ≤12 PCLK periods, which includes both variable delays and the variation in fixed delays from lane to lane, link to link, and device to device in the system.  Deterministic Latency JESD204B systems contain various clock domains distributed throughout. Data traversing from one clock domain to a different clock domain can lead to ambiguous delays in the JESD204B link. These ambiguities lead to nonrepeatable latencies across the link from power cycle to power cycle with LINK DELAY = DELAYFIXED + DELAYVARIABLE LOGIC DEVICE (JESD204B Tx) CHANNEL JESD204B Rx POWER CYCLE VARIANCE LMFC DATA AT Tx INPUT ALIGNED DATA AT Rx OUTPUT ILAS DATA ILAS DATA FIXED DELAY VARIABLE DELAY Figure 65. JESD204B Link Delay = Fixed Delay + Variable Delay Rev. B | Page 41 of 150 16795-023 1. AD9175 Data Sheet Link Delay The link delay of a JESD204B system is the sum of the fixed and variable delays from the transmitter, channel, and receiver as shown in Figure 65. For proper functioning, all lanes on a link must be read during the same LMFC period. Section 6.1 of the JESD204B specification states that the LMFC period must be larger than the maximum link delay. For the AD9175, this is not necessarily the case. Instead, the AD9175 use a local LMFC for each link (LMFCRx) that can be delayed from the SYSREF± aligned LMFC. Because the LMFC is periodic, this delay can account for any amount of fixed delay. As a result, the LMFC period must only be larger than the variation in the link delays, and the AD9175 can achieve proper performance with a smaller total latency. Figure 66 and Figure 67 show a case where the link delay is greater than an LMFC period. The link delay can be accommodated by delaying LMFCRx. POWER CYCLE VARIANCE DATA 16795-024 ILAS EARLY ARRIVING LMFC REFERENCE Two examples follow that show how to determine LMFCVar and LMFCDel. After they are calculated, write LMFCDel into Register 0x304 for all devices in the system, and write LMFCVar to Register 0x306 for all devices in the system. Link Delay Setup Example, with Known Delays All the known system delays can be used to calculate LMFCVar and LMFCDel. The example shown in Figure 68 is demonstrated in the following steps. This example is in Subclass 1 to achieve deterministic latency, and the example uses the case for F = 2. Therefore, the number of PCLK cycles per multiframe = 16. Because PCBFixed LMFC Period Example POWER CYCLE VARIANCE 3. LMFC ALIGNED DATA ILAS DATA LMFC_DELAY LMFC REFERENCE FOR ALL POWER CYCLES FRAME CLOCK 16795-025 LMFCRX 4. Figure 67. LMFC_DELAY_x to Compensate for Link Delay > LMFC The method to select the LMFCDel (Register 0x304) and LMFCVar (Register 0x306) variables is described in the Link Delay Setup Example, with Known Delays section and the Link Delay Setup Example, Without Known Delay section. The setting for LMFCDel must not equal or exceed the number of PCLK cycles per LMFC period in the current mode. Similarly, LMFCVar must not exceed the number of PCLK cycles per LMFC period in the current mode or be set to 1), the available signal BW is 80% of the data rate. If the interpolation stages are bypassed (total interpolation = 1), the available signal BW is 50% of the data rate because complex data is not used. The signal bandwidth is calculated as follows: Available Signal Bandwidth 0.5 × fDATA 0.8 × fDATA (MAX DAC = (MAX DAC = (MAX DAC = (MAX DAC = (MAX DAC = 6GHz) 8GHz) 6GHz) 12GHz) 12GHz) –2000 –1000 0 1000 2000 3000 Figure 72. Band Responses of Total Interpolation Rates for 1×, 2×, 4×, and 6× at Each Respective Maximum Achievable DAC Rate Signal BW = 0.8 × fDATA, if total interpolation > 1 Signal BW = 0.5 × fDATA, if total interpolation = 1 Table 34. Interpolation Factor Register Settings Interpolation Factor 1× 2× 3× 4× 6× 8× 12× Main Datapath, Register 0x111, Bits[7:4] 0x1 0x2 Not applicable 0x4 0x6 0x8 0xC Channel Datapath, Register 0x111, Bits[3:0] 0x1 0x2 0x3 0x4 0x6 0x8 Not applicable 8× 12× 16× 18× 24× 32× 36× 48× 64× FILTER RESPONSE The interpolation values are programmed as shown in the Table 34. 4000 FREQUENCY (MHz) 16795-030 TOTAL DATAPATH INTERPOLATION Total Interpolation 1× (Bypass) 2×, 4×, 6×, 8×, 12×, 16×, 18×, 24×, 32×, 36×, 48×, 64× –1000 –750 –500 –250 0 250 FREQUENCY (MHz) 500 750 1000 16795-031 Each digital datapath consists of multiple channel datapaths (channelizers) that sum into a single datapath (main datapath), which in turn connects to its respective DAC core by default (see Figure 1). The channelizers and the main datapaths are fully bypassable, depending on the JESD204B mode selected by the user. There are a variety of digital processing blocks available within the channelizers and the main datapaths, including interpolation filters, bypassable NCOs that allow either digital I/Q modulation of samples or standalone (DDS) operation, PA protection blocks (power detection and protection (PDP) block), and digital gain blocks to ramp or set the sample gain. Table 35. Interpolation Modes and Useable Bandwidth FILTER RESPONSE The AD9175 has two independent digital datapaths, each typically supplying data samples to the respective DACx core. However, there are modulator switch configurations that allow additional ways to route the samples to either DAC0, DAC1, or both DACs. See the Modulator Switch section for more details. Figure 73. Band Responses of Total Interpolation Rates for 8×, 12×, 16×, 18×, 24×, 32×, 36×, 48×, and 64× at a 12 GHz DAC Rate Rev. B | Page 51 of 150 AD9175 Data Sheet CHANNEL DIGITAL DATAPATH 1× DIGITAL GAIN 2× 2× NCO 2× TO MAIN DATAPATH 3× JESD204B INTERFACE DIGITAL GAIN 2× 2× NCO 2× 3× DIGITAL GAIN 2× 2× NCO 2× 16795-033 3× Figure 74. Block Diagram of the Channel Digital Datapath per the Main DAC Output Whether one or all of the channelizers in each datapath are enabled is defined by the JESD204B mode selected by the user. Each channelizer consists of a digital gain stage, complex interpolation block, and a complex 48-bit modulus NCO. The channelizers and the summing node can be fully bypassed (1× interpolation selected). The interpolation rate selection is applied to all channelizers and cannot be independently controlled. However, the gain stage and complex NCO settings can all be controlled independently. The controls for these blocks are paged by the channel paging mask in the CHANNEL_PAGE bits (Register 0x008, Bits[5:0]), as described in Table 36. Each bit of the page mask corresponds to a channel datapath. The channelizers can be either paged individually to apply settings that are unique to a specific channel, or can be paged as a group to address multiple channelizers using a single set of SPI writes. Table 36. Channel Page Mask CHANNEL_PAGE (Register 0x008, Bits[5:0]) 0x01 (Bit 0) 0x02 (Bit 1) 0x04 (Bit 2) 0x08 (Bit 3) 0x10 (Bit 4) 0x20 (Bit 5) Channel Paged Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Digital Gain Each channelizer has an independent gain control that allows unique gain scaling for each complex data stream. The gain code for each channel is 12-bit resolution, located in Register 0x146 and Register 0x147, and can be calculated by the following formulas: 0 ≤ Gain ≤ (212 − 1)/211 −∞ dB < dB Gain ≤ +6.018 dB Gain = Gain Code  (1/2048) dB Gain = 20  log10 (Gain) Gain Code = 2048  Gain = 211 10(dB Gain/20) The gain code control (CHNL_GAIN) is paged with the channel page mask (CHANNEL_PAGE) in Register 0x008, Bits[5:0]. Because the output of all three channels is summed ahead of the main datapath, extra care must be used when setting the gain to avoid sample clipping if the combined amplitude exceeds full scale after being summed. For example, if all three channels are used and all three data streams contain samples that are >1/3 full scale, clipping may occur. In other words, at any specific point in time, the sum of the samples at the output of all enabled channels must be between −215 and +(215 − 1). Channel Datapath Updated Channel 0 of DAC0 Channel 1 of DAC0 Channel 2 of DAC0 Channel 0 of DAC1 Channel 1 of DAC1 Channel 2 of DAC1 Each of the digital blocks in the channels is described in more detail in the following sections. The digital gain feature is available in all JESD204B modes, except when 1× channel interpolation is used because the channel digital processing features are bypassed in that mode, as shown in Figure 75. Rev. B | Page 52 of 150 Data Sheet AD9175 Table 39. Channel NCO Phase Offset Registers The channel interpolation options available are bypass (1×), 2×, 3×, 4×, 6×, and 8×. Each of the half-band filters used for interpolation has up to 80% bandwidths with 85 dB of stop band rejection. The channel half-band cascaded configuration is shown in Figure 75, with each of the useable bandwidths of the channel interpolation filters listed in Table 37. Address 0x138 0x139 HB0 2× HB1 2× HB2 2× TB0 3× 16795-034 Channel Interpolation Figure 75. Channel Interpolation Half-Band Filter Block Diagram Table 37. Channel Interpolation Useable Bandwidths and Rejection Half-Band Filter HB0 TB0 HB1 HB2 1 Bandwidth (×fIN_FILTER)1 (%) 80 54 40 27 Stop Band Rejection (dB) 85 85 85 85 fIN_FILTER is the frequency at the input of the half-band filter. Channel Digital Modulation Each channelizer includes a 48-bit dual-modulus NCO to allow I/Q modulation of each channel data to an independent carrier frequency, each with its own phase offset control. The 48-bit NCO can be configured into either integer or modulus (DDS) mode. In modulus mode, the A/B ratio added to the integer FTW of the NCO allows the frequency to be synthesized with near infinite precision. See the 48-Bit Integer/Modulus NCO section for more details. NCO mode is selected as shown in Table 38. These controls are paged per the channel page masks in the CHANNEL_PAGE bits (Register 0x008, Bits[5:0]). Value DDSC_NCO_PHASE_OFFSET[7:0] DDSC_NCO_PHASE_OFFSET[15:8] Description 8 LSBs of phase offset 8 MSBs of phase offset 48-Bit Integer/Modulus NCO The 48-bit integer/modulus NCO combines an NCO block, a phase shifter, and a complex modulator to modulate the signal onto a user defined carrier frequency, as shown in Figure 76. This configuration allows output signals to be shifted anywhere across the output spectrum up to ±fNCO/2 with very fine frequency resolution. The NCO produces a quadrature carrier to translate the input signal to a new center frequency. A quadrature carrier is a pair of sinusoidal waveforms of the same frequency, offset 90° from each other. The frequency of the quadrature carrier is set using the FTW. The quadrature carrier is mixed with the I and Q data and then summed into the I and Q datapaths, as shown in Figure 76. Each of the channel 48-bit NCOs can be configured to run in integer mode (that is, when only the FTW value defines the NCO output frequency). The value of the FTW in part depends on the clock speed at which the NCO block is running (fNCO,CLK). For any channel NCO, the clock rate is equal to the rate of the summing node (maximum of 1.575 GSPS) and can be calculated by using the following formulas: fNCO,CLK = fDATA  Channel Interpolation or fNCO,CLK = fDAC/Main Interpolation = fSUMMING_NODE The FTWs for each individual NCO can be programmed separately and are calculated by using the following formulas: − fNCO,CLK/2 ≤ fCARRIER < + fNCO,CLK/2 DDSC_FTW = (fCARRIER/fNCO,CLK) × 248 Table 38. Channel Modulation Mode Selection Modulation Mode None 48-Bit Integer NCO 48-Bit Dual Modulus NCO Modulation Type Register 0x130, Register 0x130, Bit 6 Bit 2 0b0 0b0 0b1 0b0 0b1 0b1 The channel NCO blocks also contain sideband selection controls as well as options for how the FTW and phase offset controls are updated. The phase offset word control can be calculated as follows: −180° ≤ Degrees Offset ≤ +180° Degrees Offset = 180°  (DDSC_NCO_PHASE_OFFSET/215) where: DDSC_FTW is a 48-bit, twos complement number. fCARRIER is the output frequency of the NCO. fNCO,CLK is the sampling clock frequency of the NCO. The frequency tuning word is set as shown in Table 40. Table 40. Channel NCO FTW Registers Address 0x132 0x133 0x134 0x135 0x136 0x137 where DDSC_NCO_PHASE_OFFSET is a 16-bit twos complement value programmed in the registers listed in Table 39. Rev. B | Page 53 of 150 Value DDSC_FTW[7:0] DDSC_FTW[15:8] DDSC_FTW[23:16] DDSC_FTW[31:24] DDSC_FTW[39:32] DDSC_FTW[47:40] Description 8 LSBs of FTW Next eight bits of FTW Next eight bits of FTW Next eight bits of FTW Next eight bits of FTW 8 MSBs of FTW AD9175 Data Sheet Unlike other NCO control registers, the FTW registers are not applied to the NCO block immediately upon writing the control register. Instead, the FTW registers are applied on the rising edge of DDSC_FTW_LOAD_REQ (Register 0x131, Bit 0). After an update request, DDSC_FTW_LOAD_ACK (Register 0x131, Bit 1) must indicate a status high to acknowledge that the FTW has been updated. The DDSC_SEL_SIDEBAND bit (Register 0x130, Bit 1 = 0b1) is a convenience bit that controls whether the lower- or uppersideband of the modulated data is used, which is equivalent to flipping the sign of the FTW. I DATA Programmable Modulus Example Consider the case in which fNCO,CLK = 1500 MHz and the desired value of fCARRIER is 150 MHz. This scenario synthesizes an output frequency that is not a power of two submultiple of the sample rate, namely fCARRIER = (1/10) fNCO,CLK, which is not possible with a typical accumulator-based DDS. The frequency ratio, fCARRIER/ fNCO,CLK, leads directly to M and N, which are determined by reducing the fraction (150,000,000/1,500,000,000) to its lowest terms, that is, COS(ωn + θ) ω π θ NCO OUT_I SIN(ωn + θ) – where: X is the FTW, programmed in Register 0x132 to Register 0x137. A is programmed in Register 0x140 to Register 0x145. B is programmed in Register 0x13A to Register 0x13F. Because X, A, and B are 48-bit words, modulus mode allows the user to set the NCO output frequency (fCARRIER) with a precision of (fNCO,CLK)/2(2 × 48). INTERPOLATION DDSC_FTW[47:0] DDSC_NCO_PHASE_OFFSET [15:0] A X  f CARRIER M B   f NCO ,CLK N 2 48 OUT_Q + –1 DDSC_SEL_SIDEBAND 0 M/N = 150,000,000/1,500,000,000 = 1/10 1 Q DATA 16795-035 Therefore, M = 1 and N = 10. INTERPOLATION Figure 76. NCO Modulator Block Diagram Channel Modulus NCO Mode (Direct Digital Synthesis (DDS) Mode) Each 48-bit channel NCO can also be used in a dual modulus mode to create fractional frequencies beyond the 48-bit accuracy that integer mode provides, which may be of interest in applications where the NCO is running for prolonged periods of time without being reset, thus possibly resulting in a noticeable phase drift relative to other clocks in the system, even given the small initial frequency error of the 48-bit, integer NCO. The modulus mode is enabled by programming the DDSC_MODULUS_EN bit in the DDSC_DATAPATH_CFG register to 1 (Register 0x130, Bit 2 = 0b1). The frequency ratio for the programmable modulus DDS is very similar to that of the typical accumulator-based DDS. The only difference is that N is not required to be a power of two (as for integer NCOs) for the programmable modulus, but can be an arbitrary integer. In practice, hardware constraints place limits on the range of values for N. As a result, the modulus extends the use of the NCO to applications that require exact rational frequency synthesis. The underlying function of the programmable modulus technique is to alter the accumulator modulus. Implementation of the programmable modulus function within the AD9175 is such that the fraction, M/N, is expressible by the following equation. The form of the equation implies a compound frequency tuning word with X representing the integer part and A/B representing the fractional part. After calculation, X = 28,147,497,671,065, A = 3, and B = 5. Programming these values into the registers for X, A, and B (X is programmed in Register 0x132 to Register 0x137 for DDSC_FTWx, B is programmed in Register 0x13A to Register 0x13F for DDSC_ACC_MODULUSx, and A is programmed in Register 0x140 to Register 0x145 for DDSC_ ACC_DELTAx) causes the NCO to produce an output frequency of exactly 150 MHz given a 1500 MHz sampling clock. For more details, refer to the AN-953 Application Note. NCO Reset Resetting an NCO is useful when determining the start time and phase of a particular NCO. Each Channel NCO can be configured to reset in response to one of several events: a direct request via SPI (Register 0x131, Bit 0), a change to one of the FTW register values, or on the next SYSREF± rising edge. The reset method is controlled by Register 0x131. See the detailed description for Register 0x131 for more information. Channel Summing Node The outputs of the channelizers are combined at the summing node junction before being routed to the respective main datapath. The summation of any number of channels being used must not exceed a value range of ±215 to avoid clipping (binary overflow) of the 16-bit data samples that are summed into the main datapath. The maximum data rate for each channel when the channel interpolation is >1× is limited by the maximum speed of summing node junction, namely 1.575 GSPS. If the channel datapaths are bypassed (channel interpolation is 1×), the summing node block is also bypassed, as shown in Figure 74. Bypassing the channelizer(s) allows passing data to the main digital datapath at a higher data rate. See Table 13 for JESD204B modes and the corresponding maximum data rates. Rev. B | Page 54 of 150 Data Sheet AD9175 MAIN DIGITAL DATAPATH 1× RAMP UP/DOWN GAIN FROM CHANNELIZER OUTPUT MUX PA PROTECTION 2× 2× TO ANALOG DAC CORE NCO 16795-036 2× 3× Figure 77. Block Diagram of the Main Digital Datapath per Main DAC Output Each main digital datapath consists of a power amplifier (PA) protection block, a set of complex interpolation filters, a 48-bit complex main datapath NCO, and a ramp-up/ramp-down gain stage. The main datapaths are bypassable (1× interpolation selected), which bypasses all the digital processing blocks included in the main datapath. The interpolation selection is set to the same value for all main datapaths and cannot be independently controlled. However, the PA protection block, complex NCO settings, and gain ramp can all be configured independently. The controls for these blocks are paged by the main DAC datapath paging mask, MAINDAC_PAGE (Register 0x008, Bits[7:6]), as listed in Table 41. Each bit of the page mask corresponds to a main DAC datapath. The datapaths can be either paged individually to apply settings that are unique to a specific main datapath, or can be paged as a group to address both datapaths using a single set of SPI writes. Downstream Protection (PA Protection) The AD9175 has several circuits designed to quickly reduce (or squelch) the amplitude of the samples that are to arrive at either DAC core, and thus protect PAs or other external system components located downstream from the AD9175 outputs. The DACx outputs can be either gradually ramped up or ramped down, or turned on or off in response to the following trigger signals, as shown in Figure 78:     Table 41. Main DAC Datapath Page Mask MAINDAC_PAGE (Register 0x008, Bits[7:6]) 0x40 (Bit 6) 0x80 (Bit 7) DAC Paged DAC0 DAC1 DAC Datapath Updated DAC0 DAC1 PDP_PROTECT. This signal asserts when the calculated digital sample amplitude exceeds a programmable threshold. INTERFACE_PROTECT. This signal asserts when specific JESD204B errors occur. SPI_PROTECT. This signal asserts when the user writes the SPI control register directly. BSM_PROTECT. This signal triggers the blanking state machine (BSM) module, which flushes the datapath on the rising edge of the TXEN0 or TXEN1 signal, which may come from a SPI write or the external TXEN0 or TXEN1 pin. A number of flags are raised in response to the trigger events, that can also be routed to the IRQx I/O pins (IRQ0 and IRQ1), to possibly shut down other external downstream components or simply serve as indicators. Each digital block in the main datapath is described in more detail in the following sections. The DAC output on/off feature is similarly implemented through a feedforward trigger signal to the ramp-up/rampdown digital gain block at the end of the main datapath before the analog DAC core, which allows the DAC to be turned on or off gradually (or quickly). Rev. B | Page 55 of 150 AD9175 Data Sheet CHANNEL SUMMER RAMP UP/DOWN GAIN + (LONG/SHORT) PDP_PROTECT PDP ERROR TRIGGER SOURCE INTERFACE_PROTECT JESD204B ERRORS SPI_PROTECT SPI TXEN0/TXEN1 PIN SPI_TXEN TXEN DAC CORE NCO M BSM BSM_PROTECT FLUSH DATAPATH IRQ0/IRQ1 PIN ENA_SPI_TXEN 16795-037 CHANNEL DATAPATHS BYPASSED Figure 78. Block Diagram of Downstream Protection Triggers DATAPATH DATA SAMPLES SHORT_PA_THRESHOLD I2 + Q2 SHORT AVERAGE FILTER (2.6ns, 1.0µs) AT 12GHz LONG_PDP_PROTECT/ SHORT_PDP_PROTECT LONG AVERAGE FILTER 16795-038 (1.0µs, 1.0ms) AT 12GHz LONG_PA_THRESHOLD Figure 79. PDP Block Diagram Power Detection and Protection (PDP) Block The PDP block calculates the anticipated average power at the DACx core output and prevents overrange signals from being output from the AD9175, to avoid a potentially destructive breakdown of power sensitive devices, such as PAs. The protection block provides a signal, PDP_PROTECT, that can be used ramp down the DAC output and/or be routed to an I/O pin to flag external components to shut down. The PDP block uses a separate path with a shorter latency than the datapath to ensure that PDP_PROTECT is triggered before the overrange signal reaches the analog DAC cores (with the exception when the total interpolation is 1). The sum of I2 and Q2 are calculated as a representation of the input signal power (to improve response time, only the top six MSBs of data samples are used). The calculated sample power values are accumulated through a moving average filter with an output that is the average of the input signal power across a certain number of samples. There are two types of average filters with different lengths: a short filter that detects high power pulses that may result in voltage breakdown, and a long filter that detects sustained high power signals that may last longer than the thermal constant of the PA or another device. When the output of the averaging filter is larger than the threshold, the internal signal, PDP_PROTECT, goes high, which can optionally be configured to trigger an IRQ flag and turn off the DAC output through the ramp-up/ramp-down. The PDP block function is illustrated in Figure 79. The long and short averaging times are configured by the LONG_ PA_AVG_TIME (Register 0x585, Bits[3:0]) and the SHORT_ PA_AVG_TIME (Register 0x58A, Bits[1:0]) controls. Use the following calculations to determine the average window size times: Rev. B | Page 56 of 150 Length of Long Average Window = 2LONG_PP_AVG_TIME + 9 Data Sheet AD9175 Length of Short Average Window = 2SHORT_PA_AVG_TIME Table 44. Main Modulation Mode Selection When the calculated average power exceeds a specified threshold, a trigger signal is issued. The registers to program the thresholds for the long and short average filters, along with their respective detected power calculation readbacks, are listed in Table 42. Table 42. PDP Threshold and Power Calculation Controls Register 0x583 0x584 0x586 0x587 0x588 0x589 0x58B 0x58C Bits [7:0] [4:0] [7:0] [4:0] [7:0] [4:0] [7:0] [4:0] Control LONG_PA_THRESHOLD[7:0] LONG_PA_THRESHOLD[12:8] LONG_PA_POWER[7:0] LONG_PA_POWER[12:8] SHORT_PA_THRESHOLD[7:0] SHORT_PA_THRESHOLD[12:8] SHORT_PA_POWER[7:0] SHORT_PA_POWER[12:8] Modulation Mode None 48-Bit Integer NCO 48-Bit Dual Modulus NCO Modulation Type Register 0x112, Register 0x112, Bit 3 Bit 2 0b0 0b0 0b1 0b0 0b1 0b1 The main NCO blocks also contain sideband selection controls as well as options for how the FTW and phase offset controls are updated. The phase offset word control can be calculated as follows: −180° ≤ Degrees Offset ≤ +180° Degrees Offset = 180°  (DDSM_NCO_PHASE_OFFSET/215) where DDSM_NCO_PHASE_OFFSET is a 16-bit twos complement value programmed in the registers listed in Table 45. Table 45. Main Datapath NCO Phase Offset Registers The interpolation options available within the main datapath are bypass (1), 2, 4, 6, 8 and 12. Each of the half-band filters used for interpolation have up to 80% bandwidths with 85 dB of stop band rejection. The channel half-band cascaded configuration is shown in Figure 80, with each of the useable bandwidths of the interpolation filters listed in Table 43. Address 0x11C 0x11D HB3 2× HB4 2× TB1 3× HB5 2× 16795-039 Main Datapath Interpolation Figure 80. Main Datapath Interpolation Half-Band Filter Block Diagram Table 43. Main Datapath Interpolation Useable Bandwidths and Rejection Half-Band Filter HB3 HB4 TB1 HB5 Bandwidth (×fIN_FILTER) 80% 40% 27% 20% Stop Band Rejection (dB) 85 85 85 85 NCO mode is selected as shown in Table 44. These controls are paged per the main DAC page masks, MAINDAC_PAGE (Register 0x008, Bits[7:6]). Description 8 LSBs of phase offset 8 MSBs of phase offset 48-Bit Integer/Modulus NCO The main datapath NCOs use a similar architecture to the channelizer NCOs, as shown in Figure 76. Because the main datapath NCOs are clocked at the same rate as fDAC, this configuration allows output signals to be placed anywhere in the output spectrum up to ±fDAC/2 with very fine frequency resolution. The NCO produces a quadrature carrier to translate the input signal to a new carrier frequency, similar to the channelizer NCOs. Refer to the corresponding channelizer NCO section for more details. The FTW for the main datapath NCOs is calculated in the same manner as the FTW for the channelizer NCOs. An important distinction is that the clock rate of the main datapath NCOs (fNCO,CLK) is equal to the DAC sample rate (fDAC, 12.6 GSPS maximum). Calculate fNCO,CLK using the following formula: fNCO,CLK = fDAC = fDATA × Channel Interpolation  Main Interpolation Main Datapath Digital Modulation The main datapath 48-bit NCOs architecture is largely identical to the channelizer NCOs that were described in earlier sections. Their operation is similar as well. However, unlike the channelizer NCOs, the main datapath NCOs operate at a higher clock rate, the same rate as the analog DAC cores (fDAC), which allows the NCOs to generate frequencies across a wider range. See the 48-Bit Integer/Modulus NCO section for more details. Value DDSM_NCO_PHASE_OFFSET[7:0] DDSM_NCO_PHASE_OFFSET [15:8] The FTWs for each individual NCO can be programmed separately and are calculated using the following formulas: −fNCO,CLK /2 ≤ fCARRIER < + fNCO,CLK /2 DDSM_FTW = (fCARRIER /fNCO,CLK) × 248 where: fCARRIER is the output frequency of the NCO. fNCO,CLK is the sampling clock frequency of the NCO. DDSC_FTW is a 48-bit, twos complement number. The frequency tuning word is set as shown in Table 46. Rev. B | Page 57 of 150 AD9175 Data Sheet For more details and examples, see the Channel Modulus NCO Mode (Direct Digital Synthesis (DDS) Mode) section. The main datapath NCOs operate at a higher clock rate (fNCO, CLK) than the channel NCOs, and are addressed from a different set of SPI registers. Table 46. Main Datapath NCO FTW Registers Address 0x114 0x115 0x116 0x117 0x118 0x119 Value DDSM_FTW[7:0] DDSM_FTW[15:8] DDSM_FTW[23:16] DDSM_FTW[31:24] DDSM_FTW[39:32] DDSM_FTW[47:40] Description 8 LSBs of FTW Next 8 bits of FTW Next 8 bits of FTW Next 8 bits of FTW Next 8 bits of FTW 8 MSBs of FTW NCO Reset Resetting the main datapath NCOs can be useful when determining the start time and phase of an NCO. Each NCO can be configured to reset in response to one of several events: a direct request via SPI (Register 0x113, Bit 0), a change to one of the FTW register values, or on the next SYSREF± rising edge. The reset method is controlled by Register 0x113. See the detailed description of Register 0x113 in Table 61 for more information. Unlike other NCO control registers, the FTW registers are not applied to the NCO block immediately on writing the control register. Instead, the FTW registers are applied (reset) on the rising edge of DDSM_FTW_LOAD_REQ (Register 0x113, Bit 0). After an update request, DDSM_FTW_LOAD_ACK (Register 0x113, Bit 1) must indicate a high status to acknowledge that the FTW is updated. Calibration NCO The DDSC_SEL_SIDEBAND bit Register 0x112, Bit 1 = 0b1) is a convenience bit that controls whether the lower or upper sideband of the modulated data is used, which is equivalent to flipping the sign of the FTW. I DATA INTERPOLATION COS(ωn + θ) ω π DDSM_FTW[47:0] DDSM_NCO_PHASE_OFFSET [15:0] θ NCO OUT_I SIN(ωn + θ) – OUT_Q + –1 Q DATA 0 1 16795-040 DDSM_SEL_SIDEBAND INTERPOLATION Figure 81. NCO Modulator Block Diagram, Main Datapath Modulus NCO Mode (DDS) Each of the main datapath 48-bit NCOs can also be used in a dual modulus mode to create fractional frequencies beyond the 48-bit accuracy. The modulus mode is enabled by programming the DDSM_MODULUS_EN bit in the DDSM_DATAPATH_ CFG register to 1 (Register 0x112, Bit 2 = 0b1). In addition to the 48-bit NCO and the 31, 32-bit NCOs, there is a 32-bit calibration NCO, which is also part of the main datapath NCO block, shown in Figure 81. This NCO is separate from the 48-bit NCO, allowing a convenient method for generating a calibration tone without the need to modify the configuration of the main datapath. Similar to all other NCOs, this NCO can be used in NCO only mode, or used to translate incoming data to a new carrier frequency. Register 0x1E6, Bit 0 controls whether the 32-bit calibration NCO is connected to the main datapath, or whether the normal 48-bit main NCO is connected instead. To use the 32-bit calibration NCO, first enable the calibration NCO accumulator by setting Register 0x1E6, Bit 2 = 1. Then, program the calibration NCO FTW in Register 0x1E2 to Register 0x1E5 and update the FTW to take effect by toggling Register 0x113, Bit 0 from 0 to 1. Select the calibration NCO to be used instead of the main NCO by setting Register 0x1E6, Bit 0 = 1. Similar to other NCOs, the calibration NCO can be configured to operate in NCO only mode, which is enabled by setting Register 0x1E6, Bit 1 = 1. Set the amplitude of the tone can be set in Registers 0x148 and Register 0x149. Refer to the NCO Only Mode section for more details. The main datapath modulus NCOs are of a similar architecture to the channel modulus NCOs, and the X (FTW), A, and B values are calculated in a similar manner: A X  f CARRIER M B   f NCO ,CLK N 2 48 where: X is the FTW, programmed in Register 0x114 to Register 0x119. A is programmed in Register 0x12A to Register 0x12F. B is programmed in Register 0x124 to Register 0x129. Rev. B | Page 58 of 150 Data Sheet AD9175 To use any of the NCOs in NCO only mode, the user can elect to configure the AD9175 to operate in JESD204B Mode 0, Mode 1, or Mode 2, depending on the desired number of channel NCOs. Any other JESD204B mode can be selected instead, as long as the NCO is not bypassed (interpolation = 1). To enable the NCOs that connect to DAC1, a dual-link JESD204B mode can be configured. It is not necessary to establish the JESD204B link with an external source, such as an FPGA, and instead only a few SPI register writes are needed to enable the necessary JESD204B mode, to set up the clock domains corresponding to each NCO. NCO ONLY MODE The AD9175 NCOs can operate in standalone mode, where the JESD204B link is disconnected (or disabled) and one or more NCO tones are output from DAC0 and/or DAC1. The correct JESD204B mode must still be selected to configure the corresponding channelizer and/or main datapath clock domains. In NCO only mode, a single-tone sine wave is generated by each NCO by modulating the NCO output with dc samples that are generated internally. The amplitude of the dc samples directly corresponds to the amplitude of the NCO tone output by the DAC core. The amplitude of each channel NCO can be controlled independently by paging the correct channel registers (Register 0x148 and Register 0x149). Note however, that the main NCO amplitude is controlled by paging Channel 0 for NCO0 and Channel 1 for NCO1 (the dc word is shared between Channel NCOx and the main NCOx channel). In general, NCO only mode is a useful to bring up a transmitter radio signal chain without requiring a digital data source initially, or in applications where a sine wave output is all that is required (also known as DDS mode), such as in local oscillator (LO) generation or radar applications. There is an additional optional calibration NCO block that can be used as part of the initial system calibration without otherwise making changes to the configuration of the digital datapath. The data source of the digital datapaths in NCO only mode is the dc data word, meaning that whether the JESD204B link is initially brought up or not, the data from the link is not passed to the datapaths. However, the input to the datapaths is easily switched between the dc data input and SERDES block input, by either Register 0x130 or Register 0x1E6, depending on the datapath. The connection can be made on-the-fly, assuming that a JESD204B link is previously configured and proper data samples are supplied. During the transition, sensitive external components can be protected using the PA protection block as described previously. MODULATOR SWITCH For added flexibility, the final NCO block (NCO0 and NCO1, to correspond to the DAC core they feed by default, in Configuration 0) includes a modulator switch that allows the user to route the desired I and/or Q sample to one or all DAC cores. NCOx are located near the output of their respective main digital datapaths. The switch has four configurations, as shown in Figure 83 through Figure 86. DDSM_EN_CAL_ACC REG 0x1E6, BIT 2 CHANNEL GAIN N CHANNEL GAIN DDSM_EN_CAL_FREQ_TUNING REG 0x1E6, BIT 0 NCO DDSC_EN_DC_INPUT REG 0x130, BIT 0 N DC AMPLITUDE LEVEL (REG 0x148 TO REG 0x149) + PA PROTECT M DAC CORE NCO DDSM_EN_CAL_DC_INPUT REG 0x1E6, BIT 1 RAMP UP/DOWN GAIN NCO DDSC_EN_DC_INPUT REG 0x130, BIT 0 16795-148 N MAIN 48-BIT NCO REG 0x114 TO REG 0x119 NCO DDSC_EN_DC_INPUT REG 0x130, BIT 0 CHANNEL GAIN CALIBRATION 32-BIT NCO REG 0x1E2 TO REG 0x1E5 Figure 82. DC Amplitude Injection for NCO Only Mode Block Diagram DAC0 I DATA DAC0 Q DATA DAC0 NCO REAL DATA TO DAC0 CORE NCO DAC0 MOD SWITCH CONFIGURATION DAC1 I DATA DAC1 Q DATA DAC1 NCO REAL DATA TO DAC1 CORE NCO Figure 83. Configuration 0—DAC0 = I0, DAC1 = I1 Rev. B | Page 59 of 150 16795-041 DAC1 MOD SWITCH CONFIGURATION AD9175 Data Sheet DAC0 I DATA NCO DAC0 Q DATA SUM OF I NCO OUT DATA TO DAC0 CORE ÷2 DAC0 MOD SWITCH CONFIGURATION DAC1 MOD SWITCH CONFIGURATION ÷2 SUM OF Q NCO OUT DATA TO DAC1 CORE 16795-042 DAC1 I DATA NCO DAC1 Q DATA Figure 84. Configuration 1, CMPLX_MOD_DIV2_DISABLE = 0—DAC0 = I0 + I1, DAC1 = Q0 + Q1 DAC0 I DATA NCO DAC0 Q DATA DAC0 I DATA TO DAC0 CORE DAC0 MOD SWITCH CONFIGURATION DAC0 Q DATA TO DAC1 CORE DAC1 I DATA NCO DAC1 Q DATA 16795-043 DAC1 MOD SWITCH CONFIGURATION Figure 85. Configuration 2—DAC0 = I0, DAC1 = Q0 DAC0 I DATA DAC0 Q DATA ÷2 NCO SUM OF NCOs REAL DATA TO DAC0 CORE DAC0 MOD SWITCH CONFIGURATION DAC1 MOD SWITCH CONFIGURATION DAC1 I DATA NO DATA TO DAC1 CORE 16795-044 DAC1 Q DATA ZERO DATA NCO Figure 86. Configuration 3, CMPLX_MOD_DIV2_DISABLE = 0—DAC0 = I0 + I1, DAC1 = 0 Some configurations bypass the NCO altogether and route the complex I and Q samples from each datapath to the DAC core(s), whereas other modes route the output of the NCOs instead. Of particular interest may be Configuration 2, shown in Figure 85, where I samples are sent to DAC0 and Q samples are sent to DAC1, to operate the AD9175 as a traditional IF DAC. Configuration 3 routing also depends on whether NCO1 and/or DAC1 is enabled. The configurations are set via Register 0x112, Bits[5:4] and are paged by the MAINDAC_PAGE register control. Rev. B | Page 60 of 150 Data Sheet AD9175 Complex Modulator Switch Configurations The switch configurations described previously only support complex samples with the NCO bypassed. To support complex samples where the NCO is used, Configuration 3 can be additionally reconfigured to operate on complex samples at the output of the NCO(s), controlled by the EN_CMPLX_MOD bit (Register 0x112, Bit 6). The specific configuration also depends on whether NCO1 is enabled, as shown in Figure 87 and Figure 88. To set up Configuration 3A, set the EN_CMPLX_MOD bit to 1 and set the switch to Configuration 3, with both NCO0 and NCO1 enabled. The quadrature output of the NCO from each main datapath is also routed to DAC1 (no longer sends zero data out of DAC1 as in the default Configuration 3, shown in Figure 86). If NCO1 is disabled and EN_CMPLX_MOD = 1, the real output of NCO0 is sent to DAC0 and the quadrature output of the NCO0 is set to DAC 1. This setup is similar to Configuration 2, but with the samples picked up at the output of NCO0 (see Figure 87 and Figure 88). The divide by 2 block at the input of the mux switch can be disabled using the CMPLX_MOD_DIV2_DISABLE bit in Register 0x0FF. Otherwise, the output at DAC0 and DAC1 is 6 dB lower than anticipated because the divide by 2 block is enabled by default. The complete list of SPI writes required to enable each configuration is shown in Table 47. DAC0 I DATA NCO DAC0 Q DATA SUM OF I NCO OUT DATA TO DAC0 CORE ÷2 DAC0 MOD SWITCH MODE DAC1 MOD SWITCH MODE ÷2 SUM OF Q NCO OUT DATA TO DAC1 CORE 16795-442 DAC1 I DATA NCO DAC1 Q DATA Figure 87. Configuration 3A, EN_CMPLX_MOD = 1, CMPLX_MOD_DIV2_DISABLE = 0, both Main NCOs Enabled—DAC0 = I0_NCO + I1_NCO, DAC1 = Q0_NCO + Q1_NCO DAC0 I DATA DAC0 Q DATA NCO DAC0 I NCO OUT DATA TO DAC0 CORE DAC0 MOD SWITCH MODE DAC0 Q NCO OUT DATA TO DAC1 CORE DAC1 I DATA DAC1 Q DATA NCO 16795-443 DAC1 MOD SWITCH MODE Figure 88. Configuration 3B, EN_CMPLX_MOD = 1, CMPLX_MOD_DIV2_DISABLE = 1, DAC 1 Main NCO Disabled—DAC0 = I0_NCO, DAC1 = Q0_NCO Table 47. Required SPI Writes for Each Modulator Switch Configuration Configuration Configuration 0 Configuration 1 Configuration 2 Configuration 3 Complex Configuration 3A Complex Configuration 3B Register 0x112, Bit 6 (EN_COMPLEX_MOD) 0 0 0 0 1 1 Register 0x112, Bits[5:4] (DDSM_ MODE) 0 1 2 3 3 3 Rev. B | Page 61 of 150 Register 0x112, Bit 3 (Paged) NCO0 NCO1 Enable Enable 1 1 0 0 0 0 1 1 1 1 1 0 Register 0x0FF, Bit 1 (CMPLX_MOD_ DIV2_DISABLE) 0 0 0 0 0 1 AD9175 Data Sheet Ramp-Up/Ramp-Down Gain Block A ramp-up/ramp-down gain block is located at the output of each main datapath and before the samples are routed to the analog DAC core(s) for decoding. This block is an extension of the PDP block, and together these blocks protect downstream components from large signal peaks or sustained average power that exceeds a user defined threshold. Various trigger methods can be configured in the PA protection block to trigger a gain ramp-down to mute the data being transmitted out of the AD9175, as shown in Figure 78. The ramp-up and ramp-down steps can be configured via the SPI in Register 0x580, Bits[2:0]. The equation for the ramp-up and ramp-down occurs in 32 steps over 2(CODE + 8) DAC clock periods. This control can be configured individually for each of the DAC ramp blocks via the MAINDAC_PAGE control in Register 0x008. After the data is ramped down due to a trigger event, it can be ramped back up in two different ways, assuming the trigger event (error) was cleared. If the SPI protection control bit triggered the interrupt for a ramp-down, the data can be ramped-up by toggling Register 0x582, Bit 7 from 0 to 1, and then back to 0. Alternatively, an option exists to mute the digital data during a digital clock rotation if the ROTATE_SOFT_OFF_EN control in Register 0x581, Bit 2 is set to 1. When this bit is set, a synchronization logic rotation triggers the ramp-up/ramp-down block to ramp the output down, rotates the digital clocks, and then ramps the output back up. These actions occur only if Bit 1 of the ROTATION_MODE control in Register 0x03B is set to 1 to enable a datapath clock rotation when the synchronization logic rotates. Rev. B | Page 62 of 150 Data Sheet AD9175 INTERRUPT REQUEST OPERATION The AD9175 provides an interrupt request output signal (IRQ) on Pin D9 (IRQ0) and Pin E9 (IRQ1) that can be used to notify an external host processor of significant device events. The IRQ output can be switched between the IRQ0 pin or the IRQ1 pin by setting the corresponding bit for the IRQ signal in Register 0x028, Register 0x029, Register 0x02A, and Register 0x02B. Upon assertion of the interrupt, query the device to determine the precise event that occurred. The IRQx pins are open-drain, active low outputs. Pull the IRQx pins high, external to the device. These pins can be tied to the interrupt pins of other devices with open-drain outputs to wire. OR these pins together. Table 48. IRQ Register Block Details Register Block 0x020 to 0x27 Event Reported Per chip 0x4B8 to 0x4BB; 0x470 to 0x473 Per link and lane EVENT_STATUS INTERRUPT_SOURCE if IRQ is enabled; if not, it is an event INTERRUPT_SOURCE if IRQ is enabled; if not, 0 INTERRUPT SERVICE ROUTINE Interrupt request management starts by selecting the set of event flags that require host intervention or monitoring. Enable the events that require host action so that the host is notified when they occur. For events requiring host intervention upon IRQ activation, run the following routine to clear an interrupt request: Figure 89 shows a simplified block diagram of how the IRQx blocks works. If IRQ_EN is low, the INTERRUPT_SOURCE signal is set to 0. If IRQ_EN is high, any rising edge of EVENT causes the INTERRUPT_SOURCE signal to be set high. If any INTERRUPT_SOURCE signal is high, the IRQx pin is pulled low. INTERRUPT_SOURCE can be reset to 0 by either an IRQ_RESET signal or a DEVICE_RESET signal. 1. 2. 3. 4. Depending on the STATUS_MODE signal, EVENT_STATUS reads back an event signal or an INTERRUPT_SOURCE signal. The AD9175 has several IRQ register blocks that can monitor up to 86 events, depending on the device configuration. Certain details vary by IRQ register block, as described in Table 48. Table 49 shows the source registers of the IRQ_EN, IRQ_RESET, and STATUS_MODE signals in Figure 89, as well as the address where EVENT_STATUS is read back. Read the status of the event flag bits that are being monitored. Disable the interrupt by writing 0 to IRQ_EN. Read the event source. Perform any actions that may be required to clear the cause of the event. In many cases, no specific actions may be required. Verify that the event source is functioning as expected. Clear the interrupt by writing 1 to IRQ_RESET. Enable the interrupt by writing 1 to IRQ_EN. 5. 6. 7. 0 EVENT_STATUS 1 STATUS_MODE IRQ IRQ_EN EVENT 1 INTERRUPT_SOURCE 0 IRQ_EN OTHER INTERRUPT SOURCES IRQ_RESET 16795-045 DEVICE_RESET Figure 89. Simplified Schematic of IRQx Circuitry Table 49. IRQ Register Block Address of IRQ Signal Details Register Block 0x020 to 0x023 0x4B8 to 0x4BB 0x470 to 0x473 1 IRQ_EN 0x020 to 0x023; R/W per chip Address of IRQ Signals1 IRQ_RESET STATUS_MODE 0x024 to 0x027; per chip STATUS_MODE= IRQ_EN EVENT_STATUS 0x024 to 0x027; R per chip 0x4B8, 0x4B9; W per error type 0x4BA, 0x4BB; W per error type Not applicable, STATUS_MODE = 1 0x4BA, 0x4BB; W per chip 0x470 to 0x473; W per error type 0x470 to 0x473; W per link Not applicable, STATUS_MODE = 1 0x470 to 0x473; W per link R is read, W is write, and R/W is read/write. Rev. B | Page 63 of 150 AD9175 Data Sheet ANALOG INTERFACE The AD9175 uses a low jitter, differential clock receiver that is capable of interfacing directly to a differential or single-ended clock source. Because the input is self biased, with a nominal impedance of 100 Ω, it is recommended that the clock source be ac-coupled to the CLKIN± input pins. Phase noise performance can be improved with higher clock input levels (larger swing, resulting in higher effective slew rate), up to the recommended maximum limits. Because the DACCLK is the sampling clock for data within the analog cores (DACx), the quality of the clock signal at the AD9175 clock input pins is paramount and directly impacts the analog ac performance of the DAC. Select a clock source with phase noise and spur characteristics that meet the target application requirements. Generally, the use of a PLL/VCO or other clock multipliers, internal or external to the DAC, also multiplies the resulting phase noise (jitter). The best phase noise performance is typically achieved using an external clock running at the desired DAC clock rate, with the PLL/VCO bypassed. The typical phase noise performance when the AD9175 is directly clocked and the input clock duty cycle correction is on (enabled by default) is shown in Figure 90, compared with the phase noise due to the on-chip PLL/VCO. 0 PLL OFF (DIRECT CLOCK) PLL ON (PFD = 491.52MHz) –20 –40 –60 –80 –100 –120 –140 –160 –180 10 100 1k 10k 100k 1M FREQUENCY OFFSET (Hz) 10M 100M 16795-216 The AD9175 DAC sample clock or device clock (DACCLK) can be received directly through CLKIN± (Pin H12 and Pin J12) or generated using an integer PLL/VCO, integrated on-chip, with the reference clock provided through the same CLKIN± differential input pins. The DACCLK serves as a reference for all the clock domains within the AD9175. In cases where low phase noise is not a critical requirement, the PLL/VCO provides a convenient way to operate the AD9175 at DAC clock rates as high as 12.4 GHz without the need for complex, multigigahertz clocking solutions, The PLL reference frequency at CLKIN± can be typically orders of magnitude lower than the operating DACCLK rate. The PLL then generates a control voltage for a downstream VCO, which in effect multiplies the reference clock up to the desired DACCLK frequency. PHASE NOISE (dBc) DAC INPUT CLOCK CONFIGURATIONS Figure 90. Phase Noise vs. Frequency Offset; Direct Clock and PLL Phase Noise, 12 GHz DAC Sample Rate, 1.65 GHz Output Frequency CLK+ PLL/VCO + 50Ω 170kΩ 50Ω 170kΩ CLOCK/ PLL MUX TO DAC0 DCC1 TO DAC1 CLOCK/ PLL MUX – 16795-050 CLK– DCC0 OPTIMIZED INPUT BIAS Figure 91. Clock Receiver Input Simplified Equivalent Circuit Rev. B | Page 64 of 150 Data Sheet AD9175 DAC On-Chip PLL frequency, reference clock phase noise, and DAC output phase noise requirements. For example, to lower DACCLK jitter when using the PLL, a higher PFD frequency minimizes the contribution of in band noise from the PLL. Set the PLL filter bandwidth such that the in band noise of the PLL intersects with the openloop noise of the VCO to minimize the contributions of both blocks to the overall noise. The AD9175 includes an integer PLL/VCO block that allows generating a DAC clock (fDAC) from an external reference frequency (fREF) between 25 MHz and 3080 MHz, applied to the CLKIN± pins (see Figure 92). When using the on-chip PLL, select the predivider (M) via Register 0x793, Bits[1:0] to internally divide the reference frequency to be within the range of 25 MHz to 770 MHz of the phase frequency detector (PFD) circuitry block input. Enable the DAC PLL synthesizer by setting Register 0x095, Bit 0 to 0. The best jitter performance is typically achieved when using an external, high performance clock source. The DAC PLL uses an integer type synthesizer to generate the DACCLK for both DAC0 and DAC1, implying that the generated DACCLK must be an integer multiple of the input reference clock. The relationship between DAC clock and the reference clock is as follows: The internal VCO operates over a frequency range of 8.74 GHz to 12.4 GHz, with additional divider settings if a lower DACCLK is required by the application. The DAC clock rate is user configurable to be the VCO frequency (8.74 GHz to 12.4 GHz), the VCO frequency divided by 2 (4.37 GHz to 6.2 GHz), or the VCO frequency divided by 3 (2.92 GHz to 4.1 GHz) by setting Register 0x094, Bits[1:0]. See the Start-Up Sequence section for instructions on how to program the PLL. fDAC = (8 × N × fREF)/M/(Register 0x094, Bits[1:0] + 1) where: fDAC is the desired DAC clock rate. N is the VCO feedback divider ratio, ranging from 2 to 50. fREF is the reference clock. M is the reference clock divider ratio. The valid values for reference clock divider (predivider) are 1, 2, 3, or 4 by setting Register 0x793, Bits[1:0]. To generate the required VCO control voltage from the charge pump (CP) output, the AD9175 DAC PLL requires an external loop filter. The recommended filter is a passive low-pass filter of a topology similar to the one shown in Figure 92. Generally, the pass band width of the filter (bandwidth) trades off loop response time during a frequency change with loop stability after the initial frequency lock occurs. For proper filter layout and component selection, which results in optimal performance for most applications, refer to the documentation of the AD9175FMC-EBZ evaluation board. The user may however customize the filter to fit a specific application, according to the PFD The VCO automatic calibration is triggered by the falling edge of Register 0x792, Bit 1 transitioning from a logic high to logic low. A lock detector bit (Register 0x7B5, Bit 0) is provided to indicate that the DAC PLL achieved lock. If Register 0x7B5, Bit 0 = 1, the PLL has locked. OFF-CHIP FILTER FILT_VCM C1 R1 C3 PCB CHARGE PUMP PFD C2 FILT_COARSE FILT_FINE REG 0x799, BITS[5:0] N = 2 TO 50 REG 0x793, BITS[1:0] M = 1, 2, 3, 4 ÷M ÷N VCO ÷8 REG 0x094, BITS[1:0] REG 0x799, BITS[7:6] L = 1, 2, 3, 4 CLK RCVR ÷2 ÷L CLKIN– DAC REG 0x095, BIT 0 DACCLK CLK DRIVER CLKOUT+ CLKOUT+ Figure 92. DAC PLL and Clock Path Block Diagram Rev. B | Page 65 of 150 PCB 16795-051 CLKIN+ ÷3 AD9175 Data Sheet CLOCK OUTPUT DRIVER The AD9175 is capable of generating a high quality, divided down version of the DACCLK, which can be used to clock critical system components, such as a companion ADC. The integer clock divider supports divide ratios of 1, 2, 3, and 4 and can be programmed by Register 0x799, Bits[7:6] to set the desired output frequency. The 3 dB bandwidth of the clock driver is between 727.5 MHz and 3 GHz, although frequencies outside this range can be generated with some penalty to both power and spurious performance at the clock output. The clock driver does not have an impact on the performance of the DACx analog outputs. DAC output can be modeled as a pair of dc current sources that continuously provide dc, set to IOUTFS/2, summed with a parallel ac source set by the incoming data samples, namely DACCODE, that are sampled to the analog output at the rate of DACCLK. Together, the three current sources model the output switch network internal to each analog output, which define the instantaneous current out of the positive and negative branches of each differential output (IP and IN, respectively). Assuming that parasitic capacitances and inductances are negligible (which may not always be the case, especially at output frequencies above ~2 GHz), the output current presented to the load can be calculated as follows: IP = (DACCODE + 2N − 1) × ILSB ANALOG OUTPUTS The AD9175 provides two fully independent DAC cores, DAC0 and DAC1, each with a differential output. Figure 93 shows an equivalent output circuit for a single DAC core. Each output is internally terminated with a 100 Ω resistor (RINT) that eliminates the need to resistively terminate the DAC output externally on the PCB. To properly dc bias the output stage, two RF chokes, one for each output branch, are required to provide a dc current path for the standing current of each DACx output. The inductance value of the choke depends on the desired output frequency range. In general, a larger choke provides a lower cutoff output frequency. Due to parasitic capacitances and inductances at the output, a constant 100 Ω termination impedance cannot be easily maintained across the full operating frequency range of the AD9175, which can be anywhere between dc and >6 GHz, depending on the application. The output impedance of each DAC can be determined through measurement. Generally, when matching the DAC output to a typical single-ended 50 Ω load, a 2:1 balun is recommended when operating below ~2 GHz. A 1:1 balun is recommended when operating above ~2 GHz, which also extends the 3 dB roll-off of the output beyond 4 GHz with proper PCB layout techniques. DAC Full-Scale Power IOUTFS is the full-scale current output at the positive and negative branch of the DACx output, denoted as IP and IN in Figure 93 to Figure 95. The default full-scale current is set to 19.531 mA, although it can be adjusted from 15.625 mA to 25.977 mA by programming the appropriate value in Register 0x05A. IOUTFS = 15.625 mA + FSC_CTRL × (25/256) (mA) As shown in Figure 93 to Figure 95, the amount of power delivered to an external load depends on multiple factors, such as the IOUTFS setting, the internal impedance of the DAC, and the external loading and parasitic inductances and capacitances that the PCB and other components present at the output. The true power that can be delivered to a load is determined by measurements. Alternatively, the DAC output power can be estimated from the DAC equivalent model, by making certain assumptions about the parasitic loading presented by a particular PCB design. The IN = ((2N − 1 – 1) – DACCODE) × ILSB and, ILOAD = (IP – IN) × RINT/(RINT + RLOAD) where, ILSB = IOUTFS/2N DACCODE is a sample value between −2N − 1 and 2N – 1 − 1 (as a signed decimal representation of twos complement data). For a single-tone output (pure sinewave), the rms power delivered to the load can be calculated as follows: ILOAD(RMS) = ILOAD_MAX/√2 where ILOAD_MAX is the maximum load current delivered at the maximum DACCODE, as calculated previously, and, PLOAD (W) = (ILOAD(RMS))2 × RLOAD PLOAD (dBm) = 10 × log(PLOAD(W × 1000)) MSB Shuffle Depending on the analog signal level, some or all of the MSB current sources from the DAC may be static (unused). Particularly at lower signal levels, when most MSBs are static, any mismatch errors specific to the few MSBs that are dynamic may appear as a degradation to spurious performance at the analog outputs. On average, spurious performance is improved when the active MSBs are continuously remapped ( or shuffled) and randomly selected from the total number of available MSBs before sampling at the DACx analog outputs. MSB shuffle is a form of error averaging. Because the cumulative errors are pseudorandom, the improved SFDR comes at the expense of higher NSD. Shuffling is only feasible when there are spare MSBs available that are otherwise static, so that they can be randomly switched in. Therefore, the benefit from shuffling is diminished as the number of dynamic MSBs is increased, such as for signals that experience frequent peaks near the full-scale current of the DAC. With a sinusoidal output at full-scale, for example, the benefit from MSB shuffling is largely nonexistent when compared to performance with traditional (thermometer) encoding. Rev. B | Page 66 of 150 Data Sheet AD9175 Elevating the common-mode voltage to between 100 mV and 300 mV leads to performance degradation. Increasing the common-mode voltage beyond 300 mV may lead to longterm, irreversible damage of the analog outputs. As previously mentioned, MSB shuffling is a form of error averaging. A particular AD9175 device, with its own autocalibration factors and unique production process variations, may show improved spurious performance at some signal levels with MSB shuffle disabled. However, when a statically meaningful set of devices is considered, the overall spurious performance is shown to improve, on average. Ideally, the common-mode voltage at the analog outputs is kept near 0 V or GND, while the load impedance seen by the analog outputs is matched to their internal impedance. Replacing the RF chokes used in ac-coupled operation with 50 Ω resistors to GND is not recommended because this results in an excessive common-mode voltage, near 250 mV. Instead, tie the 50 Ω resistors to a −0.6 V reference supply, thus maintaining proper dc bias at the analog output devices internal to each DAC output. MSB shuffle can be enabled via the MSB_SHUFFLE_EN bit (Bit 4 of Register 0x151). DC-Coupled Operation In certain applications, it is desirable to dc couple the analog outputs to an external device, such as a modulator or a differential amplifier. The AD9175 analog outputs can be dc-coupled without performance degradation, as long as the common-mode voltage (the dc voltage common to both the positive and negative branches of a particular analog output) is kept below 100 mV. For ac-coupled operation, the outputs are typically dc shorted to GND or 0 V through RF chokes or particular balun configurations. It is possible to resistively match the 0 V common-mode output voltage of the AD9175 to a nonzero common-mode input voltage of a downstream device, such as the 0.5 V input common mode typical to some modulators. This matching inevitably leads to a loss in the maximum power that can be delivered to the downstream device, because some of the power is dissipated in the resistive matching network. DAC RF CHOKE IP DACx+ 50Ω IAC 50Ω AC IOUTFS/2 2:1 OR 1:1 DACx– IN DC IOUTFS/2 BALUN 50Ω LOAD RF CHOKE 16795-052 DC IOUTFS/2 IOUTFS = 15.625mA TO 25.977mA Figure 93. Equivalent DAC Output Circuit and Recommended DAC Output Network DAC RF CHOKE IP DC PATH DACx+ 50Ω IAC 50Ω AC IOUTFS/2 2:1 OR 1:1 DACx– DC PATH IN DC IOUTFS/2 BALUN 50Ω LOAD RF CHOKE 16795-053 DC IOUTFS/2 IOUTFS = 15.625mA TO 25.977mA Figure 94. DACx Output, DC Path (AC-Coupled Operation) DAC AC IOUTFS /2 IP 50Ω AC PATH 50Ω DC IOUTFS/2 RF CHOKE AC ILOAD DACx+ AC PATH DACx– AC ILOAD IN BALUN 2:1 OR 1:1 RF CHOKE IOUTFS = 15.625mA TO 25.977mA Figure 95. DACx Output, AC Path (AC-Coupled Operation) Rev. B | Page 67 of 150 50Ω LOAD 16795-054 DC IOUTFS/2 AD9175 Data Sheet APPLICATIONS INFORMATION HARDWARE CONSIDERATIONS Power Supply Recommendations All the AD9175 supply domains must remain as noise free as possible for the best operation. Power supply noise has a frequency component that affects performance, and is specified in V rms. An LC filter on the output of the power supply is recommended to attenuate the noise, and must be placed as close to the AD9175 as possible. The AVDD1.0 supply, which supplies the clock receiver and DAC analog core circuitry, and the AVDD1.8 supply, which powers the DAC output and DAC PLL blocks, are the most noise sensitive supplies on the device. It is highly recommended that AVDD1.0 and AVDD1.8 be supplied separately with ultralow noise regulators, such as the ADP1763 and ADM7154 or better to achieve the best phase noise performance possible. Noisier regulators impose phase noise onto the DAC output. The DVDD1.0 supply provides power to the digital datapath blocks and the SVDD1.0 supply powers the SERDES circuitry on the chip. The DVDD1.8 supply powers circuitry blocks related to the SPI, SYNCOUTx± transmitter, SYSREF receiver, IRQx, RESET, and TXENx circuitry. Take note of the maximum power consumption numbers shown in Table 4 to ensure the power supply design can tolerate temperature and IC process variation extremes. The amount of current drawn is dependent on the chosen use cases, and specifications are provided for several use cases to illustrate examples and contributions from individual blocks, and to assist in calculating the maximum required current per supply. Another consideration for the power supply design is peak current handling capability. The AD9175 draws more current in the main digital supply when synthesizing a signal with significant amplitude variations, such as a modulated signal, as compared to when in idle mode or synthesizing a dc signal. Therefore, the power supply must be able to supply current quickly to accommodate burst signals such as GSM, TDMA, or other signals that have an on or off time domain response. Because the amount of current variation depends on the signals used, it is best to perform lab testing first to establish ranges. A typical difference can be several hundred milliamperes. Power and Ground Planes Solid ground planes are recommended to avoid ground loops and to provide a solid, uninterrupted ground reference for the high speed transmission lines that require controlled impedances. It is recommended that power planes be stacked between ground layers for high frequency filtering. Doing so adds extra filtering and isolation between power supply domains in addition to the decoupling capacitors. Do not use segmented power planes as a reference for controlled impedances unless the entire length of the controlled impedance trace traverses across only a single segmented plane. These and additional guidelines for the topology of high speed transmission lines are described in the JESD204B Serial Interface Inputs (SERDIN0± to SERDIN7±) section. For some applications, where highest performance and higher output frequencies are required, the choice of PCB materials significantly impacts results. For example, materials such as polyimide or materials from the Rogers Corporation can be used, for example, to improve tolerance to high temperatures and improve performance. Rogers 4350 material is used for the top three layers in some of the evaluation board designs: between the top signal layer and the ground layer below it. JESD204B Serial Interface Inputs (SERDIN0± to SERDIN7±) When considering the layout of the JESD204B serial interface transmission lines, there are many factors to consider to maintain optimal link performance. Among these factors are insertion loss, return loss, signal skew, and the topology of the differential traces. Insertion Loss The JESD204B specification limits the amount of insertion loss allowed in the transmission channel (see Figure 58). The AD9175 equalization circuitry allows significantly more loss in the channel than is required by the JESD204B specification. It is still important that the designer of the PCB minimize the amount of insertion loss by adhering to the following guidelines:    Keep the differential traces short by placing the AD9175 as close to the transmitting logic device as possible and routing the trace as directly as possible between the devices. Route the differential pairs on a single plane using a solid ground plane as a reference. It is recommended to route the SERDES lanes on the same layer as the AD9175 to avoid vias being used in the SERDES lanes. Use a PCB material with a low dielectric constant (0. DDSM_ACC_DELTA must be >DDSM_ACC_MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Sets the main datapath NCO FTW. If DDSM_MODULUS_EN is low, the main datapath NCO frequency = fDAC × (DDSM_ FTW/248. If DDSM_MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ACC_DELTA/DDSM_ ACC_MODULUS)/ 248. DDSM_ACC_DELTA must be > 0. DDSM_ACC_DELTA must be > DDSM_ACC_MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Rev. B | Page 100 of 150 Reset Access 0x0 0x0 R R/W 0x0 R 0x0 R/W 0x0 R/W 0x0 R/W Data Sheet AD9175 Addr. 0x116 Name DDSM_FTW2 Bits [7:0] Bit Name DDSM_FTW[23:16] 0x117 DDSM_FTW3 [7:0] DDSM_FTW[31:24] 0x118 DDSM_FTW4 [7:0] DDSM_FTW[39:32] 0x119 DDSM_FTW5 [7:0] DDSM_FTW[47:40] 0x11C DDSM_PHASE_ OFFSET0 [7:0] DDSM_NCO_ PHASE_OFFSET[7:0] 0x11D DDSM_PHASE_ OFFSET1 [7:0] DDSM_NCO_ PHASE_ OFFSET[15:8] Settings Description Sets the main datapath NCO FTW. If DDSM_MODULUS_EN is low, the main datapath NCO frequency = fDAC × (DDSM_ FTW/248. If DDSM_MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ACC_DELTA/DDSM_ ACC_MODULUS)/248. DDSM_ACC_DELTA must be > 0. DDSM_ACC_DELTA must be > DDSM_ACC_MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Sets the main datapath NCO FTW. If DDSM_MODULUS_EN is low, the main datapath NCO frequency = fDAC × (DDSM_ FTW/248. If DDSM_MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ACC_DELTA/DDSM_ ACC_MODULUS)/248. DDSM_ACC_DELTA must be > 0. DDSM_ACC_DELTA must be > DDSM_ACC_MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Sets the main datapath NCO FTW. If DDSM_MODULUS_EN is low, the main datapath NCO frequency = fDAC × (DDSM_ FTW/248. If DDSM_MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ACC_DELTA/DDSM_ ACC_MODULUS)/248. DDSM_ACC_DELTA must be > 0. DDSM_ACC_DELTA must be > DDSM_ACC_MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Sets the main datapath NCO FTW. If DDSM_MODULUS_EN is low, the main datapath NCO frequency = fDAC × (DDSM_ FTW/248. If DDSM_MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ACC_DELTA/DDSM_ ACC_MODULUS)/248. DDSM_ACC_DELTA must be > 0. DDSM_ACC_DELTA must be > DDSM_ACC_MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Sets main datapath NCO phase offset. Code is in 16-bit, twos complement format. Degrees offset = 180 × (code/215). This control is paged by the MAINDAC_PAGE bits in Register 0x008. Sets main datapath NCO phase offset. Code is in 16-bit, twos complement format. Degrees offset = 180 × (code/215). This control is paged by the MAINDAC_PAGE bits in Register 0x008. Rev. B | Page 101 of 150 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W AD9175 Data Sheet Addr. 0x124 Name DDSM_ACC_ MODULUS0 Bits [7:0] Bit Name DDSM_ACC_ MODULUS[7:0] 0x125 DDSM_ACC_ MODULUS1 [7:0] DDSM_ACC_ MODULUS[15:8] 0x126 DDSM_ACC_ MODULUS2 [7:0] DDSM_ACC_ MODULUS[23:16] 0x127 DDSM_ACC_ MODULUS3 [7:0] DDSM_ACC_ MODULUS[31:24] 0x128 DDSM_ACC_ MODULUS4 [7:0] DDSM_ACC_ MODULUS[39:32] 0x129 DDSM_ACC_ MODULUS5 [7:0] DDSM_ACC_ MODULUS[47:40] 0x12A DDSM_ACC_DELTA0 [7:0] DDSM_ACC_ DELTA[7:0] Settings Description Sets DDSM_ACC_MODULUS. If DDSM_ MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ACC_DELTA/DDSM_ACC_ MODULUS)/248. DDSM_ACC_DELTA must be >0. DDSM_ACC_DELTA must be > DDSM_ACC_MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Sets DDSM_ACC_MODULUS. If DDSM_ MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ACC_DELTA/DDSM_ACC_ MODULUS)/248. DDSM_ACC_DELTA must be >0. DDSM_ACC_DELTA must be >DDSM_ACC_MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Sets DDSM_ACC_MODULUS. If DDSM_ MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ACC_DELTA/DDSM_ACC_ MODULUS)/248. DDSM_ACC_DELTA must be >0. DDSM_ACC_DELTA must be > DDSM_ACC_MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Sets DDSM_ACC_MODULUS. If DDSM_ MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ACC_DELTA/DDSM_ACC_ MODULUS)/248. DDSM_ACC_DELTA must be >0. DDSM_ACC_DELTA must be > DDSM_ACC_MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Sets DDSM_ACC_MODULUS. If DDSM_ MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ACC_DELTA/DDSM_ACC_ MODULUS)/248. DDSM_ACC_DELTA must be >0. DDSM_ACC_DELTA must be > DDSM_ACC_MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Sets DDSM_ACC_MODULUS. If DDSM_ MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ACC_DELTA/DDSM_ACC_ MODULUS)/248. DDSM_ACC_DELTA must be >0. DDSM_ACC_DELTA must be > DDSM_ACC_MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Sets DDSM_ACC_DELTA. If DDSM_ MODULUS_EN is high, main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ACC_DELTA/DDSM_ACC_MODULUS)/ 248. DDSM_ACC_DELTA must be > 0. DDSM_ACC_DELTA must be > DDSM_ACC_MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Rev. B | Page 102 of 150 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Data Sheet AD9175 Addr. 0x12B Name DDSM_ACC_DELTA1 Bits [7:0] Bit Name DDSM_ACC_ DELTA[15:8] 0x12C DDSM_ACC_DELTA2 [7:0] DDSM_ACC_ DELTA[23:16] 0x12D DDSM_ACC_DELTA3 [7:0] DDSM_ACC_ DELTA[31:24] 0x12E DDSM_ACC_DELTA4 [7:0] DDSM_ACC_ DELTA[39:32] 0x12F DDSM_ACC_DELTA5 [7:0] DDSM_ACC_ DELTA[47:40] 0x130 DDSC_DATAPATH_ CFG 7 6 RESERVED DDSC_NCO_EN Settings 0 1 [5:3] 2 RESERVED DDSC_MODULUS_ EN 0 1 1 DDSC_SEL_ SIDEBAND Description Sets DDSM_ACC_DELTA. If DDSM_ MODULUS_EN is high, main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ ACC_DELTA/DDSM_ACC_MODULUS)/248. DDSM_ACC_DELTA must be > 0. DDSM_ ACC_DELTA must be > DDSM_ACC_ MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Sets DDSM_ACC_DELTA. If DDSM_ MODULUS_EN is high, main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ ACC_DELTA/DDSM_ACC_MODULUS)/248. DDSM_ACC_DELTA must be > 0. DDSM_ ACC_DELTA must be > DDSM_ACC_ MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Sets DDSM_ACC_DELTA. If DDSM_ MODULUS_EN is high, main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ ACC_DELTA/DDSM_ACC_MODULUS)/248. DDSM_ACC_DELTA must be > 0. DDSM_ ACC_DELTA must be > DDSM_ACC_ MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Sets DDSM_ACC_DELTA. If DDSM_ MODULUS_EN is high, main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ ACC_DELTA/DDSM_ACC_MODULUS)/248. DDSM_ACC_DELTA must be > 0. DDSM_ ACC_DELTA must be > DDSM_ACC_ MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Sets DDSM_ACC_DELTA. If DDSM_ MODULUS_EN is high, main datapath NCO frequency = fDAC × (DDSM_FTW + DDSM_ ACC_DELTA/DDSM_ACC_MODULUS)/248. DDSM_ACC_DELTA must be > 0. DDSM_ ACC_DELTA must be > DDSM_ACC_ MODULUS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Reserved. Channel datapath modulation enable. If the JESD204B mode chosen is a complex mode (channel interpolation >1×), this bit must be set to 1 for each channel datapath being used. If no modulation is desired, set the FTW to 0. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Disable channel NCO. Enable channel NCO. Reserved. Enable channel modulus DDS. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Disable modulus DDS. Enable modulus DDS. Selects upper or lower sideband from modulation result. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Rev. B | Page 103 of 150 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 0x0 R/W R/W 0x0 R/W AD9175 Addr. Name Data Sheet Bits Bit Name 0 DDSC_EN_DC_ INPUT Settings 0 1 0 1 0x131 DDSC_FTW_UPDATE [7:3] 2 RESERVED DDSC_FTW_ LOAD_SYSREF 1 DDSC_FTW_ LOAD_ACK 0 1 0 DDSC_FTW_ LOAD_REQ 0 1 0x132 DDSC_FTW0 [7:0] DDSC_FTW[7:0] 0x133 DDSC_FTW1 [7:0] DDSC_FTW[15:8] 0x134 DDSC_FTW2 [7:0] DDSC_FTW[23:16] Description Use upper sideband. Use lower sideband = spectral flip. Enable test tone generation by sending dc to input level to channel DDS. Set the amplitude in the DC_TEST_INPUT_ AMPLITUDE control (Register 0x148 and Register 0x149). This control is paged by the CHANNEL_PAGE bits in Register 0x008. Disable test tone generation. Enable test tone generation. Reserved. Use next rising edge of SYSREF± to trigger FTW load and reset. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Frequency tuning word update acknowledge bit. This bit reads back 1 if the FTW and phase offset word is loaded properly. This control is paged by the CHANNEL_ PAGE bits in Register 0x008. FTW is not loaded. FTW is loaded. Frequency tuning word update request from the SPI. This control is paged by the CHANNEL_PAGE bits in Register 0x008. No FTW update. 0 to 1 transition loads the FTW. Sets the channel datapath NCO FTW. If DDSC_MODULUS_EN is low, the main datapath NCO frequency = fDAC × (DDSC_ FTW/248). If DDSC_MODULUS_EN is high, main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ACC_DELTA/DDSC_ ACC_MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ACC_DELTA must be > DDSC_ACC_MODULUS. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Sets the channel datapath NCO FTW. If DDSC_MODULUS_EN is low, the main datapath NCO frequency = fDAC × (DDSC_ FTW/248). If DDSC_MODULUS_EN is high, main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ACC_DELTA/DDSC_ ACC_MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ACC_DELTA must be > DDSC_ACC_MODULUS. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Sets the channel datapath NCO FTW. If DDSC_MODULUS_EN is low, the main datapath NCO frequency = fDAC × (DDSC_ FTW/248). If DDSC_MODULUS_EN is high, main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ACC_DELTA/DDSC_ ACC_MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ACC_DELTA must be > DDSC_ACC_MODULUS. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Rev. B | Page 104 of 150 Reset Access 0x0 R/W 0x0 0x0 R R/W 0x0 R 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Data Sheet AD9175 Addr. 0x135 Name DDSC_FTW3 Bits [7:0] Bit Name DDSC_FTW[31:24] 0x136 DDSC_FTW4 [7:0] DDSC_FTW[39:32] 0x137 DDSC_FTW5 [7:0] DDSC_FTW[47:40] 0x138 DDSC_PHASE_ OFFSET0 [7:0] DDSC_NCO_ PHASE_OFFSET[7:0] 0x139 DDSC_PHASE_ OFFSET1 [7:0] DDSC_NCO_ PHASE_ OFFSET[15:8] 0x13A DDSC_ACC_ MODULUS0 [7:0] DDSC_ACC_ MODULUS[7:0] 0x13B DDSC_ACC_ MODULUS1 [7:0] DDSC_ACC_ MODULUS[15:8] Settings Description Sets the channel datapath NCO FTW. If DDSC_MODULUS_EN is low, the main datapath NCO frequency = fDAC × (DDSC_ FTW/248). If DDSC_MODULUS_EN is high, main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ACC_DELTA/DDSC_ ACC_MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ACC_DELTA must be > DDSC_ACC_MODULUS. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Sets the channel datapath NCO FTW. If DDSC_MODULUS_EN is low, the main datapath NCO frequency = fDAC × (DDSC_ FTW/248). If DDSC_MODULUS_EN is high, main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ACC_DELTA/DDSC_ ACC_MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ACC_DELTA must be > DDSC_ACC_MODULUS. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Sets the channel datapath NCO FTW. If DDSC_MODULUS_EN is low, the main datapath NCO frequency = fDAC × (DDSC_ FTW/248). If DDSC_MODULUS_EN is high, main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ACC_DELTA/DDSC_ ACC_MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ACC_DELTA must be > DDSC_ACC_MODULUS. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Sets the channel NCO phase offset. Code is in 16-bit, twos complement format. Degrees offset = 180 × (code/215). This control is paged by the CHANNEL_PAGE bits in Register 0x008. Sets the channel NCO phase offset. Code is in 16-bit, twos complement format. Degrees offset = 180 × (code/215). This control is paged by the CHANNEL_PAGE bits in Register 0x008. Sets DDSC_ACC_MODULUS. If DDSC_ MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ACC_DELTA/DDSC_ACC_ MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ACC_DELTA must be > DDSC_ACC_MODULUS. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Sets DDSC_ACC_MODULUS. If DDSC_ MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ACC_DELTA/DDSC_ACC_ MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ACC_DELTA must be > DDSC_ACC_MODULUS. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Rev. B | Page 105 of 150 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W AD9175 Data Sheet Addr. 0x13C Name DDSC_ACC_ MODULUS2 Bits [7:0] Bit Name DDSC_ACC_ MODULUS[23:16] 0x13D DDSC_ACC_ MODULUS3 [7:0] DDSC_ACC_ MODULUS[31:24] 0x13E DDSC_ACC_ MODULUS4 [7:0] DDSC_ACC_ MODULUS[39:32] 0x13F DDSC_ACC_ MODULUS5 [7:0] DDSC_ACC_ MODULUS[47:40] 0x140 DDSC_ACC_DELTA0 [7:0] DDSC_ACC_ DELTA[7:0] 0x141 DDSC_ACC_ DELTA1 [7:0] DDSC_ACC_ DELTA[15:8] Settings Description Sets DDSC_ACC_MODULUS. If DDSC_ MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ACC_DELTA/DDSC_ACC_ MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ACC_DELTA must be > DDSC_ACC_MODULUS. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Sets DDSC_ACC_MODULUS. If DDSC_ MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ACC_DELTA/DDSC_ACC_ MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ACC_DELTA must be > DDSC_ACC_MODULUS. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Sets DDSC_ACC_MODULUS. If DDSC_ MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ACC_DELTA/DDSC_ACC_ MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ACC_DELTA must be > DDSC_ACC_MODULUS. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Sets DDSC_ACC_MODULUS. If DDSC_ MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ACC_DELTA/DDSC_ACC_ MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ACC_DELTA must be > DDSC_ACC_MODULUS. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Sets DDSC_ACC_DELTA. If DDSC_ MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ACC_DELTA/DDSC_ACC_ MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ACC_DELTA must be > DDSC_ACC_MODULUS. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Sets DDSC_ACC_DELTA. If DDSC_ MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ACC_DELTA/DDSC_ACC_ MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ACC_DELTA must be > DDSC_ACC_MODULUS. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Rev. B | Page 106 of 150 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Data Sheet AD9175 Addr. 0x142 Name DDSC_ACC_DELTA2 Bits [7:0] Bit Name DDSC_ACC_ DELTA[23:16] 0x143 DDSC_ACC_DELTA3 [7:0] DDSC_ACC_ DELTA[31:24] 0x144 DDSC_ACC_DELTA4 [7:0] DDSC_ACC_ DELTA[39:32] 0x145 DDSC_ACC_DELTA5 [7:0] DDSC_ACC_ DELTA[47:40] 0x146 CHNL_GAIN0 [7:0] CHNL_GAIN[7:0] 0x147 CHNL_GAIN1 [7:4] [3:0] RESERVED CHNL_GAIN[11:8] 0x148 DC_CAL_TONE0 [7:0] DC_TEST_INPUT_ AMPLITUDE[7:0] 0x149 DC_CAL_TONE1 [7:0] DC_TEST_INPUT_ AMPLITUDE[15:8] Settings Description Sets DDSC_ACC_DELTA. If DDSC_ MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ACC_DELTA/DDSC_ACC_ MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ACC_DELTA must be > DDSC_ACC_MODULUS. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Sets DDSC_ACC_DELTA. If DDSC_ MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ACC_DELTA/DDSC_ACC_ MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ACC_DELTA must be > DDSC_ACC_MODULUS. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Sets DDSC_ACC_DELTA. If DDSC_ MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ACC_DELTA/DDSC_ACC_ MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ACC_DELTA must be > DDSC_ACC_MODULUS. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Sets DDSC_ACC_DELTA. If DDSC_ MODULUS_EN is high, the main datapath NCO frequency = fDAC × (DDSC_FTW + DDSC_ACC_DELTA/DDSC_ACC_ MODULUS)/248. DDSC_ACC_DELTA must be > 0. DDSC_ACC_DELTA must be > DDSC_ACC_MODULUS. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Sets the scalar channel gain value. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Channel gain = CHNL_GAIN/211. Reserved. Sets the scalar channel gain value. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Channel gain = CHNL_GAIN/211. DC test tone amplitude. This value sets the I path and Q paths amplitudes independently. Set these bits to 0x50FF for a full-scale tone and ensure DDSC_EN_DC_INPUT in Register 0x130 Bit 0 is set to 1. This control is paged by the CHANNEL_PAGE control in Register 0x008. DC test tone amplitude. This value sets the I path and Q paths amplitudes independently. Set to 0x50FF for a full-scale tone and ensure that DDSC_EN_DC_INPUT (Register 0x130, Bit 0) is set to 1. This control is paged by the CHANNEL_PAGE bits in Register 0x008. Rev. B | Page 107 of 150 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x8 R R/W 0x0 R/W 0x0 R/W AD9175 Addr. 0x14B Name PRBS Data Sheet Bits 7 Bit Name PRBS_GOOD_Q Settings 1 0 6 PRBS_GOOD_I 0 1 5 4 RESERVED PRBS_INV_Q 0 1 3 PRBS_INV_I 0 1 2 PRBS_MODE 0 1 1 PRBS_RESET 0 1 0 PRBS_EN 0 1 0x14C 0x14D 0x14E PRBS_ERROR_I PRBS_ERROR_Q PRBS_CHANSEL [7:0] [7:0] [7:3] [2:0] PRBS_COUNT_I PRBS_COUNT_Q RESERVED PRBS_CHANSEL 0 1 2 3 4 5 6 0x151 DECODE_MODE 0x1DE SPI_ENABLE [7:5] 4 RESERVED MSB_SHUFFLE_EN [3:0] [7:2] 1 0 RESERVED RESERVED SPI_EN1 SPI_EN0 Description DAC1 good data indicator. Correct PRBS sequence detected. Incorrect sequence detected. Sticky; reset to 1 by PRBS_RESET. DAC0 good data indicator. Incorrect sequence detected. Sticky; reset to 1 by PRBS_RESET. Correct PRBS sequence detected. Reserved. DAC1 data inversion. Expect normal data. Expect inverted data. DAC0 data inversion. Expect normal data. Expect inverted data. Select which PRBS polynomial is used for the datapath PRBS test. 7-bit: x7 + x6 + 1. 15-bit: x15 + x14 + 1. Reset error counters. Normal operation. Reset counters. Enable PRBS checker. Disable. Enable. DAC0 PRBS error count. DAC1 PRBS error count. Reserved. Selects the channel to which the PRBS_ GOOD_x and PRBS_COUNT_x bit field readbacks correspond. Select Channel 0 for PRBS_COUNT_x and PRBS_GOOD_x (Channel 0, DAC0). Select Channel 1 for PRBS_COUNT_x and PRBS_GOOD_x (Channel 1, DAC0). Select Channel 2 for PRBS_COUNT_x and PRBS_GOOD_x (Channel 2, DAC0). Select Channel 3 for PRBS_COUNT_x and PRBS_GOOD_x (Channel 0, DAC1). Select Channel 4 for PRBS_COUNT_x and PRBS_GOOD_x (Channel 1, DAC1). Select Channel 5 for PRBS_COUNT_x and PRBS_GOOD_x (Channel 2, DAC1). OR all channels for PRBS_GOOD_x, sum all channels for PRBS_COUNT_x. Reserved. MSB shuffle control. Set =1 to enable shuffling the MSBs, or set = 0 to disable MSB shuffle and use the default (static) thermometer encoding instead. Reserved. Reserved. Enable SPI control. Enable SPI control. Rev. B | Page 108 of 150 Reset 0x0 Access R 0x0 R 0x0 0x1 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x0 0x0 0x7 R R R R/W 0x0 0x0 R R/W 0x0 0x0 0x1 0x1 R R R/W R/W Data Sheet AD9175 Addr. 0x1E2 Name DDSM_CAL_FTW0 Bits [7:0] Bit Name DDSM_CAL_ FTW[7:0] 0x1E3 DDSM_CAL_FTW1 [7:0] DDSM_CAL_ FTW[15:8] 0x1E4 DDSM_CAL_FTW2 [7:0] DDSM_CAL_ FTW[23:16] 0x1E5 DDSM_CAL_FTW3 [7:0] DDSM_CAL_ FTW[31:24] 0x1E6 DDSM_CAL_MODE_ DEF [7:3] 2 RESERVED DDSM_EN_CAL_ ACC Settings 0 1 1 DDSM_EN_CAL_ DC_INPUT 0 1 0 DDSM_EN_CAL_ FREQ_TUNE 0 1 0x1E7 0x200 DATAPATH_NCO_ SYNC_CFG MASTER_PD [7:2] RESERVED 1 ALL_NCO_SYNC_ ACK 0 START_NCO_SYNC [7:1] 0 RESERVED SERDES_MASTER_ PD Description FTW of the calibration accumulator. This control is paged by the MAINDAC_PAGE bits in Register 0x008. FTW of the calibration accumulator. This control is paged by the MAINDAC_PAGE bits in Register 0x008. FTW of the calibration accumulator. This control is paged by the MAINDAC_PAGE bits in Register 0x008. FTW of the calibration accumulator. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Reserved. Enable clock calibration accumulator. This bit must be first set high, and then must load the calibration FTW into Register 0x1E2 to Register 0x1E5 to take effect. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Disabled (does not clock the calibration frequency accumulator). Enables (turns on the clock to the calibration frequency accumulator). Enable dc input to calibration DDS. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Mux in datapath signal to the input of the final DDS. Mux in dc to the input of the final DDS. Enable tuning of the signal to calibration frequency for DAC0 only. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Disable calibration frequency tuning. Enable calibration frequency tuning. Reserved. Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R Acknowledge signal that all the active NCOs are loaded. This bit is the acknowledge indicator for both the START_NCO_SYNC bit (Bit 0 of this register) and the NCORST_ AFTER_ROT_EN bit (Register 0x03B, Bit 4) method of resetting the NCOs. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Used to start the sync of the NCOs on a rising edge of the SPI bit or SYSREF± signal, depending on which is chosen as the update trigger. Upon receiving a trigger, the FTWs are loaded first, and then a synchronization occurs. This control is paged by the MAINDAC_PAGE bits in Register 0x008. Reserved. Powers down the entire JESD204B receiver analog (all eight channels and bias). 0x0 R 0x0 R/W 0x0 0x1 R R/W Rev. B | Page 109 of 150 AD9175 Data Sheet Addr. 0x201 Name PHY_PD Bits [7:0] Bit Name PHY_PD 0x203 GENERIC_PD [7:2] 1 RESERVED PD_SYNCOUT0 0 Settings 0 1 Description SPI override to power down the individual PHYs. Bit 0 controls the SERDIN0± PHY. Bit 1 controls the SERDIN1± PHY. Bit 2 controls the SERDIN2± PHY. Bit 3 controls the SERDIN3± PHY. Bit 4 controls the SERDIN4± PHY. Bit 5 controls the SERDIN5± PHY. Bit 6 controls the SERDIN6± PHY. Bit 7 controls the SERDIN7± PHY. Reserved. Powers down the SYNCOUT0± driver. Enables the SYNCOUT0± output pins. Powers down the SYNCOUT0± output pins. Powers down the SYNCOUT1± driver. Enables the SYNCOUT1± output pins. Powers down the SYNCOUT1± output pins. 0x1 R/W 0 1 Reserved. PHY reset control bit. Set this bit to 1 to take the PHYs out of reset during device operation. SERDES configuration control register to set SERDES configuration address controls. SERDES configuration control register to commit the SERDES configuration controls written. Reserved. SERDES configuration control register to commit the SERDES configuration controls written. SERDES configuration control register to set the SERDES configuration control data. Equalizer setting for PHY 3 based on insertion loss of the system. Insertion loss ≤ 11 dB. Insertion loss > 11 dB. Equalizer setting for PHY 2 based on insertion loss of the system. Insertion loss ≤ 11 dB. Insertion loss > 11 dB. Equalizer setting for PHY 1 based on insertion loss of the system. Insertion loss ≤ 11 dB. Insertion loss > 11 dB. Equalizer setting for PHY 0 based on insertion loss of the system. Insertion loss ≤ 11 dB. Insertion loss > 11 dB. Output data inversion bit controls. Set Bit x corresponding to PHY x to invert the bit polarity. Not inverted. Inverted. Equalizer setting for PHY 7 based on insertion loss of the system. 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x3 R/W 0x3 R/W 0x3 R/W 0x3 R/W 0x66 R/W 0x3 R/W PD_SYNCOUT1 0x206 CDR_RESET [7:1] 0 RESERVED CDR_PHY_RESET 0x210 CBUS_ADDR [7:0] 0x212 CBUS_WRSTROBE_ PHY [7:0] SERDES_CBUS_ ADDR SERDES_CBUS_ WR0 0x213 CBUS_WRSTROBE_ OTHER [7:1] 0 RESERVED SERDES_CBUS_ WR1 0x216 CBUS_WDATA [7:0] 0x240 EQ_BOOST_PHY_ 3_0 [7:6] SERDES_CBUS_ DATA EQ_BOOST_PHY3 10 11 [5:4] EQ_BOOST_PHY2 10 11 [3:2] EQ_BOOST_PHY1 10 11 [1:0] EQ_BOOST_PHY0 10 11 0x234 CDR_BITINVERSE [7:0] SEL_IF_ PARDATAINV_DES_ RC_CH 0 1 0x241 EQ_BOOST_PHY_ 7_4 [7:6] EQ_BOOST_PHY7 Rev. B | Page 110 of 150 Reset 0xEE Access R/W 0x0 0x0 R R/W Data Sheet Addr. Name AD9175 Bits Bit Name [5:4] EQ_BOOST_PHY6 Settings 10 11 10 11 [3:2] EQ_BOOST_PHY5 10 11 [1:0] EQ_BOOST_PHY4 10 11 0x242 EQ_GAIN_PHY_3_0 [7:6] EQ_GAIN_PHY3 01 11 [5:4] EQ_GAIN_PHY2 01 11 [3:2] EQ_GAIN_PHY1 01 11 [1:0] EQ_GAIN_PHY0 01 11 0x243 EQ_GAIN_PHY_7_4 [7:6] EQ_GAIN_PHY7 01 11 [5:4] EQ_GAIN_PHY6 01 11 [3:2] EQ_GAIN_PHY5 01 11 [1:0] EQ_GAIN_PHY4 01 11 0x244 EQ_FB_PHY_0 [7:5] [4:0] RESERVED EQ_PHY_0 0x245 EQ_FB_PHY_1 [7:5] [4:0] RESERVED EQ_PHY1 0x246 EQ_FB_PHY_2 [7:5] [4:0] RESERVED EQ_PHY2 Description Insertion loss ≤ 11 dB. Insertion loss > 11 dB. Equalizer setting for PHY 6 based on insertion loss of the system. Insertion loss ≤ 11 dB. Insertion loss > 11 dB. Equalizer setting for PHY 5 based on insertion loss of the system. Insertion loss ≤ 11 dB. Insertion loss > 11 dB. Equalizer setting for PHY 4 based on insertion loss of the system. Insertion loss ≤ 11 dB. Insertion loss > 11 dB. Equalizer gain for PHY 3 based on insertion loss of the system. Insertion loss ≤ 11 dB. Insertion loss > 11 dB. Equalizer gain for PHY 2 based on insertion loss of the system. Insertion loss ≤ 11 dB. Insertion loss > 11 dB. Equalizer gain for PHY 1 based on insertion loss of the system. Insertion loss ≤ 11 dB. Insertion loss > 11 dB. Equalizer gain for PHY 0 based on insertion loss of the system. Insertion loss ≤ 11 dB. Insertion loss > 11 dB. Equalizer gain for PHY 7 based on insertion loss of the system. Insertion loss ≤ 11 dB. Insertion loss > 11 dB. Equalizer gain for PHY 6 based on insertion loss of the system. Insertion loss ≤ 11 dB. Insertion loss > 11 dB. Equalizer gain for PHY 5 based on insertion loss of the system. Insertion loss ≤ 11 dB. Insertion loss > 11 dB. Equalizer gain for PHY 4 based on insertion loss of the system. Insertion loss ≤ 11 dB. Insertion loss > 11 dB. Reserved. SERDES equalizer setting for PHY0. Set this control to 0x1F for optimal performance. Reserved. SERDES equalizer setting for PHY1. Set this control to 0x1F for optimal performance. Reserved. SERDES equalizer setting for PHY2. Set this control to 0x1F for optimal performance. Rev. B | Page 111 of 150 Reset Access 0x3 R/W 0x3 R/W 0x3 R/W 0x3 R/W 0x3 R/W 0x3 R/W 0x3 R/W 0x3 R/W 0x3 R/W 0x3 R/W 0x3 R/W 0x0 0x19 R R/W 0x0 0x19 R R/W 0x0 0x19 R R/W AD9175 Data Sheet Addr. 0x247 Name EQ_FB_PHY_3 Bits [7:5] [4:0] Bit Name RESERVED EQ_PHY3 0x248 EQ_FB_PHY_4 [7:5] [4:0] RESERVED EQ_PHY4 0x249 EQ_FB_PHY_5 [7:5] [4:0] RESERVED EQ_PHY5 0x24A EQ_FB_PHY_6 [7:5] [4:0] RESERVED EQ_PHY6 0x24B EQ_FB_PHY_7 [7:5] [4:0] RESERVED EQ_PHY7 0x250 LBT_REG_CNTRL_0 [7:0] EN_LBT_DES_ RC_CH 0x251 LBT_REG_CNTRL_1 [7:2] 1 RESERVED EN_LBT_ HALFRATE_DES_ RC 0 INIT_LBT_SYNC_ DES_RC RESERVED 0x253 SYNCOUT0_CTRL [7:1] 0 Settings SEL_SYNCOUT0_ MODE 0 1 0x254 SYNCOUT1_CTRL PLL_ENABLE_CTRL Reset 0x0 0x19 Access R R/W 0x0 0x19 R R/W 0x0 0x19 R R/W 0x0 0x19 R R/W 0x0 0x19 R R/W 0x0 R/W 0x0 0x1 R R/W 0x0 R/W 0x0 R/W This control determines the output driver mode for the SYNCOUT0± pin operation. Both SYNCOUT0± and SYNCOUT1± must be set to the same mode of operation. SYNCOUT0± is set to CMOS output. SYNCOUT0± is set to LVDS output. 0x0 R/W [7:1] RESERVED Reserved. 0x0 R/W 0 SEL_SYNCOUT1_ MODE This control determines the output driver mode for the SYNCOUT1± pin operation. Both SYNCOUT0± and SYNCOUT1± must be set to the same mode of operation. SYNCOUT1± is set to CMOS output. SYNCOUT1± is set to LVDS output. 0x0 R/W Reserved. Clears out loss of lock bit. 0x0 0x0 R R/W Pulse high to start VCO calibration (without restarting the regulator or remeasuring the temperature). SERDES circuitry blocks are powered off when this bit is set to 0. Set this bit to 1 at the end of the SERDES configuration writes. When this bit is set to 1, it powers up the SERDES PLL blocks and starts the LDO and calibration routine to lock the PLL automatically to the appropriate lane rate based on the JESD204B mode and interpolation options programmed in the device. The SERDES_PLL_LOCK bit (Register 0x281, Bit 0) reads 1 when the PLL achieves lock. 0x0 R/W 0x1 R/W 0 1 0x280 Description Reserved. SERDES equalizer setting for PHY3. Set this control to 0x1F for optimal performance. Reserved. SERDES equalizer setting for PHY4. Set this control to 0x1F for optimal performance. Reserved. SERDES equalizer setting for PHY5. Set this control to 0x1F for optimal performance. Reserved. SERDES equalizer setting for PHY6. Set this control to 0x1F for optimal performance. Reserved. SERDES equalizer setting for PHY7. Set this control to 0x1F for optimal performance. Enable loopback test for desired physical lanes per PHY, with Bit x corresponding to PHY x. Reserved. Enables half rate mode for the loopback test. If this bit is set to 1, the output data rate = 2× the input clock frequency. If this bit is set to 0, the output data rate = the input clock frequency. Initiate the loopback test by toggling this bit from 0 to 1, then back to 0. Reserved. [7:3] 2 1 0 RESERVED LOLSTICKYCLEAR_ LCPLL_RC LDSYNTH_LCPLL_ RC SERDES_PLL_ STARTUP Rev. B | Page 112 of 150 Data Sheet Addr. 0x281 Name PLL_STATUS 0x300 GENERAL_JRX_ CTRL_0 AD9175 Bits [7:1] 0 [7:4] 3 Bit Name RESERVED SERDES_PLL_LOCK RESERVED LINK_MODE 2 LINK_PAGE Settings 0 1 [1:0] LINK_EN 0x302 DYN_LINK_ LATENCY_0 [7:6] [5:0] RESERVED DYN_LINK_ LATENCY_0 0x303 DYN_LINK_ LATENCY_1 [7:6] [5:0] RESERVED DYN_LINK_ LATENCY_1 0x304 LMFC_DELAY_0 [7:6] [5:0] RESERVED LMFC_DELAY_0 0x305 LMFC_DELAY_1 [7:6] [5:0] RESERVED LMFC_DELAY_1 0x306 LMFC_VAR_0 [7:6] [5:0] RESERVED LMFC_VAR_0 0x307 LMFC_VAR_1 [7:6] [5:0] RESERVED LMFC_VAR_1 0x308 XBAR_LN_0_1 [7:6] [5:3] RESERVED LOGICAL_LANE1_ SRC 000 001 010 011 100 101 110 Description Reserved. PLL is locked when this bit is high. Reserved. Reads back 0 when in single-link mode and 1 when in dual-link mode. Link paging. This bit selects which link register map is used. This paging affects Register 0x400 to Register 0x4BB. Page QBD0 for Link 0. Page QBD1 for Link 1. These bits bring up the JESD204B digital receiver when all link parameters are programmed and all clocks are ready. Bit 0 applies to Link 0, whereas Bit 1 applies to Link 1. Link 1 is only available in dual-link mode. Reserved. Dynamic link latency, Link 0. Latency between the LMFC receiver for Link 0 and the last arriving LMFC boundary in units of PCLK cycles. Reserved. Dynamic link latency, Link 1. Latency between the LMFC receiver for Link 1 and the last arriving LMFC boundary in units of PCLK cycles. Reserved. LMFC delay, Link 0. Delay from the LMFC to the LMFC receiver for Link 0 in units of PCLK cycles. Reserved. LMFC delay, Link 1. Delay from the LMFC to the LMFC receiver for Link 1 in units of PCLK cycles. Reserved. Variable delay buffer, Link 0. These bits set when data is read from a buffer to be consistent across links and power cycles (in units of PCLK cycles). The maximum value is 0xC. Reserved. Variable delay buffer, Link 1. These bits set when data is read from a buffer to be consistent across links and power cycles (in units of PCLK cycles). The maximum value is 0xC. Reserved. Logical Lane 1 source. These bits select a physical lane to be mapped onto Logical Lane 1. Data is from SERDIN0±. Data is from SERDIN1±. Data is from SERDIN2±. Data is from SERDIN3±. Data is from SERDIN4±. Data is from SERDIN5±. Data is from SERDIN6±. Rev. B | Page 113 of 150 Reset 0x0 0x0 0x0 0x0 Access R R R R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R 0x0 0x0 R R 0x0 0x0 R R/W 0x0 0x0 R R/W 0x0 0x3F R R/W 0x0 0x3F R R/W 0x0 0x1 R R/W AD9175 Addr. Name Data Sheet Bits Bit Name [2:0] LOGICAL_LANE0_ SRC Settings 111 000 001 010 011 100 101 110 111 0x309 XBAR_LN_2_3 [7:6] [5:3] RESERVED LOGICAL_LANE3_ SRC 000 001 010 011 100 101 110 111 [2:0] LOGICAL_LANE2_ SRC 000 001 010 011 100 101 110 111 0x30A XBAR_LN_4_5 [7:6] [5:3] RESERVED LOGICAL_LANE5_ SRC 000 001 010 011 100 101 110 111 [2:0] LOGICAL_LANE4_ SRC 000 001 010 011 100 Description Data is from SERDIN7±. Logical Lane 0 source. These bits select a physical lane to be mapped onto Logical Lane 0. Data is from SERDIN0±. Data is from SERDIN1±. Data is from SERDIN2±. Data is from SERDIN3±. Data is from SERDIN4±. Data is from SERDIN5±. Data is from SERDIN6±. Data is from SERDIN7±. Reserved. Logical Lane 3 source. These bits select a physical lane to be mapped onto Logical Lane 3. Data is from SERDIN0±. Data is from SERDIN1±. Data is from SERDIN2±. Data is from SERDIN3±. Data is from SERDIN4±. Data is from SERDIN5±. Data is from SERDIN6±. Data is from SERDIN7±. Logical Lane 2 source. These bits select a physical lane to be mapped onto Logical Lane 2. Data is from SERDIN0±. Data is from SERDIN1±. Data is from SERDIN2±. Data is from SERDIN3±. Data is from SERDIN4±. Data is from SERDIN5±. Data is from SERDIN6±. Data is from SERDIN7±. Reserved. Logical Lane 5 source. These bits select a physical lane to be mapped onto Logical Lane 5. Data is from SERDIN0±. Data is from SERDIN1±. Data is from SERDIN2±. Data is from SERDIN3±. Data is from SERDIN4±. Data is from SERDIN5±. Data is from SERDIN6±. Data is from SERDIN7±. Logical Lane 4 source. These bits select a physical lane to be mapped onto Logical Lane 4. Data is from SERDIN0±. Data is from SERDIN1±. Data is from SERDIN2±. Data is from SERDIN3±. Data is from SERDIN4±. Rev. B | Page 114 of 150 Reset Access 0x0 R/W 0x0 0x3 R R/W 0x2 R/W 0x0 0x5 R R/W 0x4 R/W Data Sheet AD9175 Addr. Name Bits Bit Name 0x30B XBAR_LN_6_7 [7:6] [5:3] RESERVED LOGICAL_LANE7_ SRC Settings 101 110 111 000 001 010 011 100 101 110 111 [2:0] LOGICAL_LANE6_ SRC 000 001 010 011 100 101 110 111 0x30C FIFO_STATUS_REG_0 [7:0] LANE_FIFO_FULL 0x30D FIFO_STATUS_REG_1 [7:0] LANE_FIFO_EMPTY 0x311 SYNCOUT_GEN_0 [7:4] RESERVED 3 EOMF_MASK_1 0x0 0x7 R R/W 0x6 R/W 0x0 R 0x0 R R 0x0 R/W 0x0 R/W 1 Mask EOMF from QBD0. Assert SYNCOUT0± based on the loss of the multiframe synchronization. Do not assert SYNCOUT0± on loss of multiframe. Assert SYNCOUT0± on loss of multiframe. 0x0 R/W 0 1 Mask EOF from QBD1. Assert SYNCOUT1± based on loss of frame synchronization. Do not assert SYNCOUT1± on loss of frame. Assert SYNCOUT1± on loss of frame. 0x0 R/W 0 1 Mask EOF from QBD0. Assert SYNCOUT0± based on loss of frame synchronization. Do not assert SYNCOUT0± on loss of frame. Assert SYNCOUT0± on loss of frame. EOMF_MASK_0 0 0 Access 0x0 1 1 Reset Mask end of multiframe (EOMF) from QBD1. Assert SYNCOUT1± based on the loss of the multiframe synchronization. Do not assert SYNCOUT1± on loss of multiframe. Assert SYNCOUT1± on loss of multiframe. 0 2 Description Data is from SERDIN5±. Data is from SERDIN6±. Data is from SERDIN7±. Reserved. Logical Lane 7 source. These bits select a physical lane to be mapped onto Logical Lane 7. Data is from SERDIN0±. Data is from SERDIN1±. Data is from SERDIN2±. Data is from SERDIN3±. Data is from SERDIN4±. Data is from SERDIN5±. Data is from SERDIN6±. Data is from SERDIN7±. Logical Lane 6 source. These bits select a physical lane to be mapped onto Logical Lane 6. Data is from SERDIN0±. Data is from SERDIN1±. Data is from SERDIN2±. Data is from SERDIN3±. Data is from SERDIN4±. Data is from SERDIN5±. Data is from SERDIN6±. Data is from SERDIN7±. Bit x corresponds to FIFO full flag for data from SERDINx±. Bit x corresponds to FIFO empty flag for data from SERDINx±. Reserved. EOF_MASK_1 EOF_MASK_0 Rev. B | Page 115 of 150 AD9175 Data Sheet Addr. 0x312 Name SYNCOUT_GEN_1 Bits [7:4] Bit Name SYNC_ERR_DUR 0x315 PHY_PRBS_TEST_EN [3:0] [7:0] RESERVED PHY_TEST_EN Settings 0 1 0x316 PHY_PRBS_TEST_ CTRL 7 [6:4] RESERVED PHY_SRC_ERR_CNT 000 001 010 011 100 101 110 111 [3:2] PHY_PRBS_PAT_SE L 00 01 10 11 1 PHY_TEST_START 0 1 0 PHY_TEST_RESET 0 1 0x317 0x318 0x319 0x31A 0x31B 0x31C 0x31D 0x31E PHY_PRBS_TEST_ THRESHOLD_ LOBITS PHY_PRBS_TEST_ THRESHOLD_ MIDBITS PHY_PRBS_TEST_ THRESHOLD_HIBITS [7:0] PHY_PRBS_TEST_ ERRCNT_LOBITS PHY_PRBS_TEST_ ERRCNT_MIDBITS PHY_PRBS_TEST_ ERRCNT_HIBITS PHY_PRBS_TEST_ STATUS PHY_DATA_ SNAPSHOT_CTRL [7:0] [7:0] PHY_PRBS_ THRESHOLD_ LOBITS PHY_PRBS_ THRESHOLD_ MIDBITS PHY_PRBS_ THRESHOLD_ HIBITS PHY_PRBS_ERR_ CNT_LOBITS PHY_PRBS_ERR_ CNT_MIDBITS PHY_PRBS_ERR_ CNT_HIBITS PHY_PRBS_PASS [7:2] 1 RESERVED PHY_GRAB_MODE [7:0] [7:0] [7:0] [7:0] 0 1 Description Duration of SYNCOUTx± low for the purposes of the synchronization error report. Duration = (0.5 + code) PCLK cycles. To most closely match the specified value, set these bits as close as possible to f/2 PCLK cycles. These bits are shared between SYNCOUT0± and SYNCOUT1±. Reset 0x0 Access R/W Reserved. Enable PHY BER by ungating the clocks. PHY test disable. PHY test enable. Reserved. 0x0 0x0 R/W R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Bits[15:8] of the 24-bit threshold value to set the error flag for the PHY PRBS test. 0x0 R/W Bits[23:16] of the 24-bit threshold value to set the error flag for the PHY PRBS test. 0x0 R/W Bits[7:0] of the 24-bit reported PHY BER error count from the selected lane. Bits[15:8] of the 24-bit reported PHY BER error count from the selected lane. Bits[23:16] of the 24-bit reported PHY BER error count from the selected lane. Reports PHY BER pass/fail for each lane. Bit x is high when Lane x passes. Reserved. This bit determines whether to use the trigger to grab data. Grab data when PHY_GRAB_DATA is set. Grab data upon bit error. 0x0 R 0x0 R 0x0 R 0xFF R 0x0 0x0 R R/W Report Lane 0 error count. Report Lane 1 error count. Report Lane 2 error count. Report Lane 3 error count. Report Lane 4 error count. Report Lane 5 error count. Report Lane 6 error count. Report Lane 7 error count. Select PRBS pattern for PHY BER test. PRBS7. PRBS15. PRBS31. Not used. Starts and stops the PHY PRBS test. Test not started. Test started. Resets PHY PRBS test state machine and error counters. Not reset. Reset. Bits[7:0] of the 24-bit threshold value to set the error flag for the PHY PRBS test. Rev. B | Page 116 of 150 Data Sheet AD9175 Addr. Name Bits 0 Bit Name PHY_GRAB_DATA 0x31F PHY_SNAPSHOT_ DATA_BYTE0 PHY_SNAPSHOT_ DATA_BYTE1 PHY_SNAPSHOT_ DATA_BYTE2 PHY_SNAPSHOT_ DATA_BYTE3 PHY_SNAPSHOT_ DATA_BYTE4 SHORT_TPL_TEST_0 [7:0] PHY_SNAPSHOT_ DATA_BYTE0 PHY_SNAPSHOT_ DATA_BYTE1 PHY_SNAPSHOT_ DATA_BYTE2 PHY_SNAPSHOT_ DATA_BYTE3 PHY_SNAPSHOT_ DATA_BYTE4 SHORT_TPL_SP_ SEL 0x320 0x321 0x322 0x323 0x32C [7:0] [7:0] [7:0] [7:0] [7:4] Settings 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 [3:2] SHORT_TPL_CHAN _SEL 00 01 10 1 SHORT_TPL_TEST_ RESET 0 1 0 SHORT_TPL_TEST_ EN 0 1 0x32D SHORT_TPL_TEST_1 [7:0] SHORT_TPL_REF_ SP_LSB Description Transitioning this bit from 0 to 1 causes the logic to store current receive data from one lane. Current data received. Represents PHY_SNAPSHOT_DATA[7:0]. Current data received. Represents PHY_SNAPSHOT_DATA[15:8]. Current data received. Represents PHY_SNAPSHOT_DATA[23:16]. Current data received. Represents PHY_SNAPSHOT_DATA[31:24]. Current data received. Represents PHY_SNAPSHOT_DATA[39:32]. Short transport layer sample select. Selects which sample to check from a specific DAC. Sample 0. Sample 1. Sample 2. Sample 3. Sample 4. Sample 5. Sample 6. Sample 7. Sample 8. Sample 9. Sample 10. Sample 11. Sample 12. Sample 13. Sample 14. Sample 15. Short transport layer test channel select. Selects which subchannel of the DACx channelizer to test. Channel 0. Channel 1. Channel 2. Short transport layer test reset. Resets the result of short transport layer test. Not reset. Reset. Short transport layer test enable. Enable short transport layer test. Disable. Enable. Short transport layer reference sample, LSB. This bit field is the lower eight bits of the expected DAC sample during the short transport layer test and is used to compare with the received sample at the JESD204B receiver output. Rev. B | Page 117 of 150 Reset 0x0 Access R/W 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W AD9175 Data Sheet Addr. 0x32E Name SHORT_TPL_TEST_2 Bits [7:0] Bit Name SHORT_TPL_REF_ SP_MSB 0x32F SHORT_TPL_TEST_3 7 SHORT_TPL_LINK_ SEL Settings 0 1 6 SHORT_TPL_IQ_ SAMPLE_SEL 0 1 [5:1] 0 RESERVED SHORT_TPL_FAIL 0 1 0x334 JESD_BIT_INVERSE_ CTRL [7:0] JESD_BIT_INVERSE 0x400 DID_REG [7:0] DID_RD 0x401 BID_REG [7:0] BID_RD 0x402 LID0_REG 7 6 RESERVED ADJDIR_RD 5 PHADJ_RD [4:0] LL_LID0 7 SCR_RD 0x403 SCR_L_REG 0 1 [6:5] [4:0] RESERVED L_RD_1 Description Short transport layer test reference sample, MSB. This bit field is the upper eight bits of the expected DAC sample during the short transport layer test and is used to compare with the received sample at the JESD204B receiver output. For running STPL on dual-link JESD204B modes. Selects whether the STPL test is performed on samples that are addressed to the DAC0 channelizers/datapaths (Link 0), or the DAC1 channelizers/datapaths (Link 1). Link 0 samples are tested. Link 1 samples are tested. Selects which data stream (path) to test for a complex subchannel of the channelizer, I or Q. For nonIQ JESD204B modes, select the I path. Select to test the I data stream. Select to test the Q data stream. Reserved. Short transport layer test fail. This bit shows if the selected DAC sample matches the expected sample for the short transport layer test. If they match, the test passes. Otherwise, the test fails. Test pass. Test fail. Logical lane invert. Each bit of this control inverses the JESD204B deserialized data from one specific JESD204B receiver PHY. Set Bit x high to invert the JESD204B deserialized data on Logical Lane x. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Reserved. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Received ILAS LID configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Scrambling is disabled. Scrambling is enabled. Reserved. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Rev. B | Page 118 of 150 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 0x0 R/W R 0x0 R/W 0x0 R 0x0 R 0x0 0x0 R R 0x0 R 0x0 R 0x0 R 0x0 0x0 R R Data Sheet AD9175 Addr. Name Bits Bit Name 0x404 F_REG [7:0] F_RD_1 Settings 00000 00001 00010 00011 0 1 10 11 0x405 K_REG [7:5] [4:0] RESERVED K_RD_1 00000 11111 0x406 M_REG [7:0] M_RD_1 0x407 CS_N_REG [7:6] CS_RD 5 [4:0] RESERVED N_RD_1 [7:5] SUBCLASSV_RD [4:0] NP_RD_1 [7:5] JESDV_RD_1 0x408 0x409 NP_REG S_REG 000 001 0x40A HD_CF_REG [4:0] S_RD_1 7 HD_RD 0 1 [6:5] [4:0] RESERVED CF_RD 0x40B RES1_REG [7:0] RES1_RD 0x40C RES2_REG [7:0] RES2_RD Description 1 lane per converter device. 2 lanes per converter device. 3 lanes per converter device. 4 lanes per converter device. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. 1 octet per frame. 2 octets per frame. 3 octets per frame. 4 octets per frame. Reserved. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Default value. 32 frames per multiframe. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Reserved. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. JESD204A. JESD204B. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Low density mode. High density mode. Reserved. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Received ILAS configuration on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Rev. B | Page 119 of 150 Reset Access 0x0 R 0x0 0x0 R R 0x0 R 0x0 R 0x0 0x0 R R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 0x0 R R 0x0 R 0x0 R AD9175 Data Sheet Addr. 0x40D Name CHECKSUM0_REG Bits [7:0] Bit Name LL_FCHK0 0x40E COMPSUM0_REG [7:0] LL_FCMP0 0x412 LID1_REG [7:5] [4:0] RESERVED LL_LID1 0x415 CHECKSUM1_REG [7:0] LL_FCHK1 0x416 COMPSUM1_REG [7:0] LL_FCMP1 0x41A LID2_REG [7:5] [4:0] RESERVED LL_LID2 0x41D CHECKSUM2_REG [7:0] LL_FCHK2 0x41E COMPSUM2_REG [7:0] LL_FCMP2 0x422 LID3_REG [7:5] [4:0] RESERVED LL_LID3 0x425 CHECKSUM3_REG [7:0] LL_FCHK3 0x426 COMPSUM3_REG [7:0] LL_FCMP3 0x42A LID4_REG [7:5] [4:0] RESERVED LL_LID4 0x42D CHECKSUM4_REG [7:0] LL_FCHK4 0x42E COMPSUM4_REG [7:0] LL_FCMP4 0x432 LID5_REG [7:5] [4:0] RESERVED LL_LID5 0x435 CHECKSUM5_REG [7:0] LL_FCHK5 0x436 COMPSUM5_REG [7:0] LL_FCMP5 0x43A LID6_REG [7:5] RESERVED Settings Description Received checksum during ILAS on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Computed checksum on Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Reserved. Received ILAS LID configuration on Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Received checksum during ILAS on Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Computed checksum on Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Reserved. Received ILAS LID configuration on Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Received checksum during ILAS on Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Computed checksum on Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Reserved. Received ILAS LID configuration on Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Received checksum during ILAS on Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Computed checksum on Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Reserved. Received ILAS LID configuration on Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Received checksum during ILAS on Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Computed checksum on Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Reserved. Received ILAS LID configuration on Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Received checksum during ILAS on Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Computed checksum on Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Reserved. Rev. B | Page 120 of 150 Reset 0x0 Access R 0x0 R 0x0 0x0 R R 0x0 R 0x0 R 0x0 0x0 R R 0x0 R 0x0 R 0x0 0x0 R R 0x0 R 0x0 R 0x0 0x0 R R 0x0 R 0x0 R 0x0 0x0 R R 0x0 R 0x0 R 0x0 R Data Sheet AD9175 Addr. Name Bits [4:0] Bit Name LL_LID6 0x43D CHECKSUM6_REG [7:0] LL_FCHK6 0x43E COMPSUM6_REG [7:0] LL_FCMP6 0x442 LID7_REG [7:5] [4:0] RESERVED LL_LID7 0x445 CHECKSUM7_REG [7:0] LL_FCHK7 0x446 COMPSUM7_REG [7:0] LL_FCMP7 0x450 ILS_DID [7:0] DID 0x451 ILS_BID [7:0] BID 0x452 ILS_LID0 7 6 RESERVED ADJDIR 5 PHADJ [4:0] LID0 7 SCR 0x453 ILS_SCR_L Settings 0 1 [6:5] [4:0] RESERVED L_1 0x454 ILS_F [7:0] F_1 0x455 ILS_K [7:5] RESERVED Description Received ILAS LID configuration on Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Received checksum during ILAS on Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Computed checksum on Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Reserved. Received ILAS LID configuration on Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Received checksum during ILAS on Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Computed checksum on Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Device (link) identification number. This control is paged by the LINK_PAGE control in Register 0x300. Bank ID, extension to DID. This control is paged by the LINK_PAGE control in Register 0x300. This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Reserved. Direction to adjust the DAC LMFC. Link information is received on Link Lane 0 as specified in Section 8.3 of JESD204B. Only Link 0 is supported. This control is paged by the LINK_PAGE control in Register 0x300. Phase adjustment request to the DAC. Only Link 0 is supported. This control is paged by the LINK_PAGE control in Register 0x300. Lane identification number (within link). This control is paged by the LINK_PAGE control in Register 0x300. This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Scramble enabled for the link. This control is paged by the LINK_PAGE control in Register 0x300. Descrambling is disabled. Descrambling is enabled. Reserved. Number of lanes per converter (minus 1). This control is paged by the LINK_PAGE control in Register 0x300. Number of octets per frame per lane (minus 1). This control is paged by the LINK_PAGE control in Register 0x300. Reserved. Rev. B | Page 121 of 150 Reset 0x0 Access R 0x0 R 0x0 R 0x0 0x0 R R 0x0 R 0x0 R 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x1 R/W 0x0 0x7 R R/W 0x0 R/W 0x0 R AD9175 Data Sheet Addr. Name Bits [4:0] Bit Name K_1 0x456 ILS_M [7:0] M_1 0x457 ILS_CS_N [7:6] CS 5 [4:0] RESERVED N_1 [7:5] SUBCLASSV Settings 11111 0x458 ILS_NP 000 001 0x459 ILS_S [4:0] NP_1 [7:5] JESDV 000 001 0x45A ILS_HD_CF [4:0] S_1 7 HD 0 1 [6:5] [4:0] RESERVED CF 0x45B ILS_RES1 [7:0] RES1 0x45C ILS_RES2 [7:0] RES2 0x45D ILS_CHECKSUM [7:0] FCHK0 0x46C LANE_DESKEW 7 ILD7 0 1 Description Number of frames per multiframe (minus 1). This control is paged by the LINK_PAGE control in Register 0x300. 32 frames per multiframe. Number of subchannels per link (minus 1). This control is paged by the LINK_PAGE control in Register 0x300. Number of control bits per sample. Only Link 0 is supported. This control is paged by the LINK_PAGE control in Register 0x300. Reserved. Converter resolution (minus 1). This control is paged by the LINK_PAGE control in Register 0x300. Device subclass version. This control is paged by the LINK_PAGE control in Register 0x300. Subclass 0. Subclass 1. Total number of bits per sample (minus 1). This control is paged by the LINK_PAGE control in Register 0x300. JESD204 version. This control is paged by the LINK_PAGE control in Register 0x300. JESD204A. JESD204B. Number of samples per converter per frame cycle (minus 1). This control is paged by the LINK_PAGE control in Register 0x300. High density format, always set to 1. This control is paged by the LINK_PAGE control in Register 0x300. Low density mode. High density mode. Reserved. Number of control bits per sample. Only Link 0 is supported. This control is paged by the LINK_PAGE control in Register 0x300. Reserved field 1. This control is paged by the LINK_PAGE control in Register 0x300. Reserved field 2. This control is paged by the LINK_PAGE control in Register 0x300. Calculated link configuration checksum. This control is paged by the LINK_PAGE control in Register 0x300. This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Interlane deskew status for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Deskew failed. Deskew achieved. Rev. B | Page 122 of 150 Reset 0x1F Access R/W 0x1 R/W 0x0 R 0x0 0xF R R/W 0x0 R/W 0xF R/W 0x0 R/W 0x1 R/W 0x1 R 0x0 0x0 R R 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R Data Sheet Addr. Name AD9175 Bits 6 Bit Name ILD6 Settings 0 1 5 ILD5 0 1 4 ILD4 0 1 3 ILD3 0 1 2 ILD2 0 1 1 ILD1 0 1 0 ILD0 0 1 0x46D BAD_DISPARITY 7 BDE7 0 1 6 BDE6 0 1 5 BDE5 0 1 4 BDE4 0 1 Description Interlane deskew status for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Deskew failed. Deskew achieved. Interlane deskew status for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Deskew failed. Deskew achieved. Interlane deskew status for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Deskew failed. Deskew achieved. Interlane deskew status for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Deskew failed. Deskew achieved. Interlane deskew status for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Deskew failed. Deskew achieved. Interlane deskew status for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Deskew failed. Deskew achieved. Interlane deskew status for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Deskew failed. Deskew achieved. Bad disparity errors status for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Error count < error threshold (ETH)[7:0] value. Error count ≥ ETH[7:0] value. Bad disparity errors status for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Bad disparity errors status for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Bad disparity errors status for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Rev. B | Page 123 of 150 Reset 0x0 Access R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R AD9175 Addr. Name Data Sheet Bits 3 Bit Name BDE3 Settings 0 1 2 BDE2 0 1 1 BDE1 0 1 0 BDE0 0 1 0x46E NOT_IN_TABLE 7 NIT7 0 1 6 NIT6 0 1 5 NIT5 0 1 4 NIT4 0 1 3 NIT3 0 1 2 NIT2 0 1 1 NIT1 0 1 Description Bad disparity errors status for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Bad disparity errors status for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Bad disparity errors status for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Bad disparity errors status for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Not in table errors status for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Not in table errors status for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Not in table errors status for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Not in table errors status for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Not in table errors status for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Not in table errors status for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Not in table errors status for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Rev. B | Page 124 of 150 Reset 0x0 Access R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R Data Sheet Addr. Name AD9175 Bits 0 Bit Name NIT0 Settings 0 1 0x46F UNEXPECTED_ KCHAR 7 UEK7 0 1 6 UEK6 0 1 5 UEK5 0 1 4 UEK4 0 1 3 UEK3 0 1 2 UEK2 0 1 1 UEK1 0 1 0 UEK0 0 1 0x470 CODE_GRP_SYNC 7 CGS7 0 1 6 CGS6 0 1 Description Not in table errors status for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Unexpected K character errors status, Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Unexpected K character errors status, Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Unexpected K character errors status, Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Unexpected K character errors status, Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Unexpected K character errors status, Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Unexpected K character errors status, Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Unexpected K character errors status, Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Unexpected K character errors status, Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Code group synchronization status for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Code group synchronization status for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Rev. B | Page 125 of 150 Reset 0x0 Access R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R AD9175 Addr. Name Data Sheet Bits 5 Bit Name CGS5 Settings 0 1 4 CGS4 0 1 3 CGS3 0 1 2 CGS2 0 1 1 CGS1 0 1 0 CGS0 0 1 0x471 FRAME_SYNC 7 FS7 0 1 6 FS6 0 1 5 FS5 0 1 4 FS4 0 1 3 FS3 0 1 Description Code group synchronization status for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Code group synchronization status for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Code group synchronization status for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Code group synchronization status for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Code group synchronization status for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Code group synchronization status for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Frame synchronization status for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Frame synchronization status for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Frame synchronization status for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Frame synchronization status for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Frame synchronization status for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Rev. B | Page 126 of 150 Reset 0x0 Access R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R Data Sheet Addr. Name AD9175 Bits 2 Bit Name FS2 Settings 0 1 1 FS1 0 1 0 FS0 0 1 0x472 GOOD_CHECKSUM 7 CKS7 0 1 6 CKS6 0 1 5 CKS5 0 1 4 CKS4 0 1 3 CKS3 0 1 2 CKS2 0 1 1 CKS1 0 1 0 CKS0 0 1 Description Frame synchronization status for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Frame synchronization status for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Frame synchronization status for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Computed checksum status for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Checksum is incorrect. Checksum is correct. Computed checksum status for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Checksum is incorrect. Checksum is correct. Computed checksum status for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Checksum is incorrect. Checksum is correct. Computed checksum status for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Checksum is incorrect. Checksum is correct. Computed checksum status for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Checksum is incorrect. Checksum is correct. Computed checksum status for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Checksum is incorrect. Checksum is correct. Computed checksum status for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Checksum is incorrect. Checksum is correct. Computed checksum status for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Checksum is incorrect. Checksum is correct. Rev. B | Page 127 of 150 Reset 0x0 Access R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R AD9175 Addr. 0x473 Name INIT_LANE_SYNC Data Sheet Bits 7 Bit Name ILS7 Settings 0 1 6 ILS6 0 1 5 ILS5 0 1 4 ILS4 0 1 3 ILS3 0 1 2 ILS2 0 1 1 ILS1 0 1 0 ILS0 0 1 0x475 CTRLREG0 [7:4] 3 RESERVED SOFTRST 2 FORCESYNCREQ 1 0 RESERVED REPL_FRM_ENA Description Initial lane synchronization status for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Initial lane synchronization status for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Initial lane synchronization status for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Initial lane synchronization status for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Initial lane synchronization status for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Initial lane synchronization status for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Initial lane synchronization status for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Initial lane synchronization status for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Reserved. QBD soft reset. Active high synchronous reset. Resets all hardware to power-on state. This control is paged by the LINK_PAGE control in Register 0x300. Command from application to assert a synchronization request. Active high. This control is paged by the LINK_PAGE control in Register 0x300. Reserved. When this level input is set, it enables the replacement of frames received in error. This control is paged by the LINK_PAGE control in Register 0x300. This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Rev. B | Page 128 of 150 Reset 0x0 Access R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 0x0 R/W R/W 0x0 R/W 0x0 0x1 R R/W Data Sheet Addr. 0x476 Name CTRLREG1 AD9175 Bits [7:5] 4 Bit Name RESERVED QUAL_RDERR Settings 0 1 [3:1] 0 RESERVED FCHK_N 0 1 0x477 CTRLREG2 7 ILS_MODE 0 1 6 5 RESERVED REPDATATEST 4 QUETESTERR 0 1 Description Reserved. Error reporting behavior for concurrent not in table (NIT) and running disparity (RD) errors. This control is paged by the LINK_PAGE control in Register 0x300. Set this bit to 1. This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. NIT has no effect on RD error. NIT error masks concurrent with RD error. Reserved. Checksum calculation method. This control is paged by the LINK_PAGE control in Register 0x300. This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Checksum is calculated by summing the individual fields in the link configuration table as defined in Section 8.3, Table 20 of the JESD204B standard. Checksum is calculated by summing the registers containing the packed link configuration fields (sum of Register 0x450 to Register 0x45A, modulo 256). Data link layer test mode is enabled when this bit is set to 1. CGS pattern is followed by a perpetual ILAS sequence. This control is paged by the LINK_PAGE control in Register 0x300. This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Normal mode. CGS pattern is followed by a perpetual ILAS sequence. Reserved. Repetitive data test enable using the JTSPAT pattern. To enable the test, Bit 7 of this register must = 0. This control is paged by the LINK_PAGE control in Register 0x300. This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Queue test error mode. This control is paged by the LINK_PAGE control in Register 0x300. This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. When this bit = 0, simultaneous errors on multiple lanes are reported as one error. Selected when this bit = 1 and when REPDATATEST = 1. Detected errors from all lanes are trapped in a counter and sequentially signaled on SYNCOUTx±. Rev. B | Page 129 of 150 Reset 0x0 0x1 Access R R/W 0x0 0x0 R/W R/W 0x0 R/W 0x0 0x0 R/W R/W 0x0 R/W AD9175 Addr. Name 0x478 Data Sheet Bits 3 Bit Name AR_ECNTR KVAL [2:0] [7:0] RESERVED KSYNC 0x47C ERRORTHRES [7:0] ETH 0x47D SYNC_ASSERT_ MASK [7:3] [2:0] RESERVED SYNC_ASSERT_ MASK 0x480 ECNT_CTRL0 [7:6] [5:3] RESERVED ECNT_ENA0 [2:0] ECNT_RST0 Settings Description Automatic reset of error counter. The error counter that causes assertion of SYNCOUTx± is automatically reset to 0 when AR_ECNTR = 1. All other counters are unaffected. This control is paged by the LINK_PAGE control in Register 0x300. This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Reserved. Number of 4 × K multiframes during ILAS. This control is paged by the LINK_PAGE control in Register 0x300. This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Error counter threshold value. These bits set when a SYNCOUTx± error or IRQx interrupt is sent due to BD, NIT, or UEK errors. This control is paged by the LINK_PAGE control in Register 0x300. This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Reserved. SYNCOUTx± assertion enable mask for BD, NIT, and UEK error conditions. This control is paged by the LINK_PAGE control in Register 0x300. Active high, SYNCOUTx±assertion enable mask for BD, NIT, and UEK error conditions, respectively. When an error counter, in any lane, has reached the error threshold count, ETH[7:0], and the corresponding SYNC_ASSERT_MASK bit is set, SYNCOUTx± is asserted. The mask bits are as follows (the bit sequence is reversed with respect to the other error count controls and the error counters): Bit 2 = bad disparity error (BDE). Bit 1 = not in table error (NIT). Bit 0 = unexpected K character error (UEK). Reserved. Error counter enables for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Counters of each lane are addressed as follows: Bit 5 = unexpected K character error (UEK). Bit 4 = not in table error (NIT). Bit 3 = bad disparity error (BDE). Reset error counters for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Counters of each lane are addressed as follows: Bit 2 = bad disparity error (BDE). Bit 1 = not in table error (NIT). Bit 0 = unexpected K character error (UEK). Rev. B | Page 130 of 150 Reset 0x0 Access R/W 0x0 0x1 R R/W 0xFF R/W 0x0 0x7 R R/W 0x0 0x7 R R/W 0x7 R/W Data Sheet Addr. 0x481 0x482 0x483 0x484 Name ECNT_CTRL1 ECNT_CTRL2 ECNT_CTRL3 ECNT_CTRL4 AD9175 Bits [7:6] [5:3] Bit Name RESERVED ECNT_ENA1 [2:0] ECNT_RST1 [7:6] [5:3] RESERVED ECNT_ENA2 [2:0] ECNT_RST2 [7:6] [5:3] RESERVED ECNT_ENA3 [2:0] ECNT_RST3 [7:6] [5:3] RESERVED ECNT_ENA4 [2:0] ECNT_RST4 Settings Description Reserved. Error counter enables for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Counters of each lane are addressed as follows: Bit 5 = unexpected K character error (UEK). Bit 4 = not in table error (NIT). Bit 3 = bad disparity error (BDE). Reset error counters for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). Reserved. Error counter enables for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Counters of each lane are addressed as follows: Bit 5 = unexpected K character error (UEK). Bit 4 = not in table error (NIT). Bit 3 = bad disparity error (BDE). Reset error counters for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). Reserved. Error counter enables for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Counters of each lane are addressed as follows: Bit 5 = unexpected K character error (UEK). Bit 4 = not in table error (NIT). Bit 3 = bad disparity error (BDE). Reset error counters for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). Reserved. Error counter enables for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Counters of each lane are addressed as follows: Bit 5 = unexpected K character error (UEK). Bit 4 = not in table error (NIT). Bit 3 = bad disparity error (BDE). Reset error counters for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Counters of each lane are addressed as follows: Rev. B | Page 131 of 150 Reset 0x0 0x7 Access R R/W 0x7 R/W 0x0 0x7 R R/W 0x7 R/W 0x0 0x7 R R/W 0x7 R/W 0x0 0x7 R R/W 0x7 R/W AD9175 Data Sheet Addr. Name Bits Bit Name 0x485 ECNT_CTRL5 [7:6] [5:3] RESERVED ECNT_ENA5 [2:0] ECNT_RST5 [7:6] [5:3] RESERVED ECNT_ENA6 [2:0] ECNT_RST6 [7:6] [5:3] RESERVED ECNT_ENA7 [2:0] ECNT_RST7 [7:3] RESERVED 0x486 0x487 0x488 ECNT_CTRL6 ECNT_CTRL7 ECNT_TCH0 Settings Description Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). Reserved. Error counter enables for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Counters of each lane are addressed as follows: Bit 5 = unexpected K character error (UEK). Bit 4 = not in table error (NIT). Bit 3 = bad disparity error (BDE). Reset error counters for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). Reserved. Error counter enables for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Counters of each lane are addressed as follows: Bit 5 = unexpected K character error (UEK). Bit 4 = not in table error (NIT). Bit 3 = bad disparity error (BDE). Reset error counters for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). Reserved. Error counter enables for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Counters of each lane are addressed as follows: Bit 5 = unexpected K character error (UEK). Bit 4 = not in table error (NIT). Bit 3 = bad disparity error (BDE). Reset error counters for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). Reserved. Rev. B | Page 132 of 150 Reset Access 0x0 0x7 R R/W 0x7 R/W 0x0 0x7 R R/W 0x7 R/W 0x0 0x7 R R/W 0x7 R/W 0x0 R Data Sheet AD9175 Addr. Name Bits [2:0] Bit Name ECNT_TCH0 0x489 ECNT_TCH1 [7:3] [2:0] RESERVED ECNT_TCH1 0x48A ECNT_TCH2 [7:3] [2:0] RESERVED ECNT_TCH2 0x48B ECNT_TCH3 [7:3] [2:0] RESERVED ECNT_TCH3 Settings Description Terminal count hold enable of error counters for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. When set, the designated counter is to hold the terminal count value of 0xFF when it is reached until the counter is reset by the user. Otherwise, the designated counter rolls over. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Reserved. Terminal count hold enable of error counters for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. When set, the designated counter is to hold the terminal count value of 0xFF when it is reached until the counter is reset by the user. Otherwise, the designated counter rolls over. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Reserved. Terminal count hold enable of error counters for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. When set, the designated counter is to hold the terminal count value of 0xFF when it is reached until the counter is reset by the user. Otherwise, the designated counter rolls over. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Reserved. Terminal count hold enable of error counters for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. When set, the designated counter is to hold the terminal count value of 0xFF when it is reached until the counter is reset by the user. Otherwise, the designated counter rolls over. Counters of each lane are addressed as follows: Rev. B | Page 133 of 150 Reset 0x7 Access R/W 0x0 0x7 R R/W 0x0 0x7 R R/W 0x0 0x7 R R/W AD9175 Data Sheet Addr. Name Bits Bit Name 0x48C ECNT_TCH4 [7:3] [2:0] RESERVED ECNT_TCH4 0x48D ECNT_TCH5 [7:3] [2:0] RESERVED ECNT_TCH5 0x48E ECNT_TCH6 [7:3] [2:0] RESERVED ECNT_TCH6 0x48F ECNT_TCH7 [7:3] RESERVED Settings Description Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Reserved. Terminal count hold enable of error counters for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. When set, the designated counter is to hold the terminal count value of 0xFF when it is reached until the counter is reset by the user. Otherwise, the designated counter rolls over. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Reserved. Terminal count hold enable of error counters for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. When set, the designated counter is to hold the terminal count value of 0xFF when it is reached until the counter is reset by the user. Otherwise, the designated counter rolls over. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Reserved. Terminal count hold enable of error counters for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. When set, the designated counter is to hold the terminal count value of 0xFF when it is reached until the counter is reset by the user. Otherwise, the designated counter rolls over. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Reserved. Rev. B | Page 134 of 150 Reset Access 0x0 0x7 R R/W 0x0 0x7 R R/W 0x0 0x7 R R/W 0x0 R Data Sheet AD9175 Addr. Name Bits [2:0] Bit Name ECNT_TCH7 0x490 ECNT_STAT0 [7:4] 3 RESERVED LANE_ENA0 [2:0] ECNT_TCR0 [7:4] 3 RESERVED LANE_ENA1 [2:0] ECNT_TCR1 [7:4] 3 RESERVED LANE_ENA2 0x491 0x492 ECNT_STAT1 ECNT_STAT2 Settings Description Terminal count hold enable of error counters for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. When set, the designated counter is to hold the terminal count value of 0xFF when it is reached until the counter is reset by the user. Otherwise, the designated counter rolls over. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). This signal must only be programmed while the QBD is held in soft reset (Register 0x475, Bit 3), and must not be changed during normal operation. Reserved. This output indicates if Lane 0 is enabled. This control is paged by the LINK_PAGE control in Register 0x300. Terminal count reached indicator of error counters for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Set these bits to 1 when the corresponding counter terminal count value of 0xFF is reached. If ECNT_TCHx is set, the terminal count value for the corresponding counter is held until the counter is reset by the user; otherwise, the counter rolls over and continues counting. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). Reserved. This output indicates if Lane 1 is enabled. This control is paged by the LINK_PAGE control in Register 0x300. Terminal count reached indicator of error counters for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Set these bits to 1 when the corresponding counter terminal count value of 0xFF is reached. If ECNT_TCHx is set, the terminal count value for the corresponding counter is held until the counter is reset by the user; otherwise, the counter rolls over and continues counting. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). Reserved. This output indicates if Lane 2 is enabled. This control is paged by the LINK_PAGE control in Register 0x300. Rev. B | Page 135 of 150 Reset 0x7 Access R/W 0x0 0x0 R R 0x0 R 0x0 0x0 R R 0x0 R 0x0 0x0 R R AD9175 Data Sheet Addr. Name Bits [2:0] Bit Name ECNT_TCR2 0x493 ECNT_STAT3 [7:4] 3 RESERVED LANE_ENA3 [2:0] ECNT_TCR3 [7:4] 3 RESERVED LANE_ENA4 [2:0] ECNT_TCR4 [7:4] 3 RESERVED LANE_ENA5 0x494 0x495 ECNT_STAT4 ECNT_STAT5 Settings Description Terminal count reached indicator of error counters for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Set these bits to 1 when the corresponding counter terminal count value of 0xFF is reached. If ECNT_TCHx is set, the terminal count value for the corresponding counter is held until the counter is reset by the user; otherwise, the counter rolls over and continues counting. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). Reserved. This output indicates if Lane 3 is enabled. This control is paged by the LINK_PAGE control in Register 0x300. Terminal count reached indicator of error counters for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Set these bits to 1 when the corresponding counter terminal count value of 0xFF is reached. If ECNT_TCHx is set, the terminal count value for the corresponding counter is held until the counter is reset by the user; otherwise, the counter rolls over and continues counting. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). Reserved. This output indicates if Lane 4 is enabled. This control is paged by the LINK_PAGE control in Register 0x300. Terminal count reached indicator of error counters for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Set these bits to 1 when the corresponding counter terminal count value of 0xFF is reached. If ECNT_TCHx is set, the terminal count value for the corresponding counter is held until the counter is reset by the user; otherwise, the counter rolls over and continues counting. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). Reserved. This output indicates if Lane 5 is enabled. This control is paged by the LINK_PAGE control in Register 0x300. Rev. B | Page 136 of 150 Reset 0x0 Access R 0x0 0x0 R R 0x0 R 0x0 0x0 R R 0x0 R 0x0 0x0 R R Data Sheet AD9175 Addr. Name Bits [2:0] Bit Name ECNT_TCR5 0x496 ECNT_STAT6 [7:4] 3 RESERVED LANE_ENA6 [2:0] ECNT_TCR6 [7:4] 3 RESERVED LANE_ENA7 [2:0] ECNT_TCR7 7 BDE0 0x497 0x4B0 ECNT_STAT7 LINK_STATUS0 Settings 0 1 6 NIT0 0 Description Terminal count reached indicator of error counters for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Set these bits to 1 when the corresponding counter terminal count value of 0xFF is reached. If ECNT_TCHx is set, the terminal count value for the corresponding counter is held until the counter is reset by the user; otherwise, the counter rolls over and continues counting. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). Reserved. This output indicates if Lane 6 is enabled. This control is paged by the LINK_PAGE control in Register 0x300. Terminal count reached indicator of error counters for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Set these bits to 1 when the corresponding counter terminal count value of 0xFF is reached. If ECNT_TCHx is set, the terminal count value for the corresponding counter is held until the counter is reset by the user; otherwise, the counter rolls over and continues counting. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). Reserved. This output indicates if Lane 7 is enabled. This control is paged by the LINK_PAGE control in Register 0x300. Terminal count reached indicator of error counters for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Set these bits to 1 when the corresponding counter terminal count value of 0xFF is reached. If ECNT_TCHx is set, the terminal count value for the corresponding counter is held until the counter is reset by the user; otherwise, the counter rolls over and continues counting. Counters of each lane are addressed as follows: Bit 2 = unexpected K character error (UEK). Bit 1 = not in table error (NIT). Bit 0 = bad disparity error (BDE). Bad disparity errors status for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Not in table errors status for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Rev. B | Page 137 of 150 Reset 0x0 Access R 0x0 0x0 R R 0x0 R 0x0 0x0 R R 0x0 R 0x0 R 0x0 R AD9175 Addr. Name Data Sheet Bits Bit Name 5 UEK0 Settings 1 0 1 4 ILD0 0 1 3 ILS0 0 1 2 CKS0 0 1 1 FS0 0 1 0 CGS0 0 1 0x4B1 LINK_STATUS1 7 BDE1 0 1 6 NIT1 0 1 5 UEK1 0 1 4 ILD1 0 1 3 ILS1 0 1 Description Error count ≥ ETH[7:0] value. Unexpected K character errors status for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Interlane deskew status for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Deskew failed. Deskew achieved. Initial lane synchronization status for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Computed checksum status for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Checksum is incorrect. Checksum is correct. Frame synchronization status for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Code group synchronization status for Lane 0. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Bad disparity errors status for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Not in table errors status for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Unexpected K character errors status for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Interlane deskew status for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Deskew failed. Deskew achieved. Initial lane synchronization status for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Rev. B | Page 138 of 150 Reset Access 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R Data Sheet Addr. Name AD9175 Bits 2 Bit Name CKS1 Settings 0 1 1 FS1 0 1 0 CGS1 0 1 0x4B2 LINK_STATUS2 7 BDE2 0 1 6 NIT2 0 1 5 UEK2 0 1 4 ILD2 0 1 3 ILS2 0 1 2 CKS2 0 1 1 FS2 0 1 0 CGS2 0 1 Description Computed checksum status for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Checksum is incorrect. Checksum is correct. Frame synchronization status for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Code group synchronization status for Lane 1. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Bad disparity errors status for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Not in table errors status for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Unexpected K character errors status for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Interlane deskew status for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Deskew failed. Deskew achieved. Initial lane synchronization status for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Computed checksum status for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Checksum is incorrect. Checksum is correct. Frame synchronization status for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Code group synchronization status for Lane 2. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Rev. B | Page 139 of 150 Reset 0x0 Access R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R AD9175 Addr. 0x4B3 Name LINK_STATUS3 Data Sheet Bits 7 Bit Name BDE3 Settings 0 1 6 NIT3 0 1 5 UEK3 0 1 4 ILD3 0 1 3 ILS3 0 1 2 CKS3 0 1 1 FS3 0 1 0 CGS3 0 1 0x4B4 LINK_STATUS4 7 BDE4 0 1 6 NIT4 0 1 5 UEK4 0 1 Description Bad disparity errors status for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Not in table errors status for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Unexpected K character errors status for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Interlane deskew status for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Deskew failed. Deskew achieved. Initial lane synchronization status for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Computed checksum status for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Checksum is incorrect. Checksum is correct. Frame synchronization status for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Code group synchronization status for Lane 3. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Bad disparity errors status for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Not in table errors status for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Unexpected K character errors status for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Rev. B | Page 140 of 150 Reset 0x0 Access R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R Data Sheet Addr. Name AD9175 Bits 4 Bit Name ILD4 Settings 0 1 3 ILS4 0 1 2 CKS4 0 1 1 FS4 0 1 0 CGS4 0 1 0x4B5 LINK_STATUS5 7 BDE5 0 1 6 NIT5 0 1 5 UEK5 0 1 4 ILD5 0 1 3 ILS5 0 1 2 CKS5 0 1 Description Interlane deskew status for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Deskew failed. Deskew achieved. Initial lane synchronization status for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Computed checksum status for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Checksum is incorrect. Checksum is correct. Frame synchronization status for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Code group synchronization status for Lane 4. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Bad disparity errors status for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Not in table errors status for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Unexpected K character errors status for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Interlane deskew status for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Deskew failed. Deskew achieved. Initial lane synchronization status for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Computed checksum status for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Checksum is incorrect. Checksum is correct. Rev. B | Page 141 of 150 Reset 0x0 Access R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R AD9175 Addr. Name Data Sheet Bits 1 Bit Name FS5 Settings 0 1 0 CGS5 0 1 0x4B6 LINK_STATUS6 7 BDE6 0 1 6 NIT6 0 1 5 UEK6 0 1 4 ILD6 0 1 3 ILS6 0 1 2 CKS6 0 1 1 FS6 0 1 0 CGS6 0 1 0x4B7 LINK_STATUS7 7 BDE7 0 1 Description Frame synchronization status for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Code group synchronization status for Lane 5. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Bad disparity errors status for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Not in table errors status for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Unexpected K character errors status for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Interlane deskew status for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Deskew failed. Deskew achieved. Initial lane synchronization status for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Computed checksum status for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Checksum is incorrect. Checksum is correct. Frame synchronization status for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Code group synchronization status for Lane 6. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Bad disparity errors status for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Rev. B | Page 142 of 150 Reset 0x0 Access R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R Data Sheet Addr. Name AD9175 Bits 6 Bit Name NIT7 Settings 0 1 5 UEK7 0 1 4 ILD7 0 1 3 ILS7 0 1 2 CKS7 0 1 1 FS7 0 1 0 CGS7 0 1 0x4B8 JESD_IRQ_ENABLEA 7 EN_BDE 6 EN_NIT 5 EN_UEK 4 EN_ILD 3 EN_ILS Description Not in table errors status for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Unexpected K character errors status Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Error count < ETH[7:0] value. Error count ≥ ETH[7:0] value. Interlane deskew status for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Deskew failed. Deskew achieved. Initial lane synchronization status for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Computed checksum status for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Checksum is incorrect. Checksum is correct. Frame synchronization status for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Code group synchronization status for Lane 7. This control is paged by the LINK_PAGE control in Register 0x300. Synchronization lost. Synchronization achieved. Bad disparity error counter. This control is paged by the LINK_PAGE control in Register 0x300. Not in table error counter. This control is paged by the LINK_PAGE control in Register 0x300. Unexpected K error counter. This control is paged by the LINK_PAGE control in Register 0x300. Interlane deskew. This control is paged by the LINK_PAGE control in Register 0x300. Initial lane synchronization. This control is paged by the LINK_PAGE control in Register 0x300. Rev. B | Page 143 of 150 Reset 0x0 Access R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W AD9175 Addr. Name Data Sheet Bits 2 Bit Name EN_CKS 1 EN_FS 0 EN_CGS 0x4B9 JESD_IRQ_ENABLEB [7:1] 0 RESERVED EN_ILAS 0x4BA JESD_IRQ_STATUSA 7 IRQ_BDE 6 IRQ_NIT 5 IRQ_UEK 4 IRQ_ILD 3 IRQ_ILS 2 IRQ_CKS 1 IRQ_FS 0 IRQ_CGS 0x4BB JESD_IRQ_STATUSB [7:1] 0 RESERVED IRQ_ILAS 0x4BC IRQ_OUTPUT_MUX_ JESD [7:1] 0 RESERVED MUX_JESD_IRQ Settings Description Good checksum. This bit compares two checksums: the checksum that the transmitter sent over the link during the ILAS and the checksum that the receiver calculated from the ILAS data that the transmitter sent over the link. The checksum IRQ only looks at data sent by the transmitter and not the checksum programmed into Register 0x45D. This control is paged by the LINK_PAGE control in Register 0x300. Frame synchronization. This control is paged by the LINK_PAGE control in Register 0x300. Code group synchronization. This control is paged by the LINK_PAGE control in Register 0x300. Reserved. Configuration mismatch (checked for Lane 0 only). The ILAS IRQ compares the two sets of ILAS data obtained by the receiver. The first set of data is the ILAS data sent over the JESD204B link by the transmitter. The second set of data is the ILAS data programmed into the receiver via the SPI (Register 0x450 to Register 0x45D). If any of the data differs, the IRQ is triggered. All of the ILAS data, including the checksum, is compared. This control is paged by the LINK_PAGE control in Register 0x300. Bad disparity error counter. This control is paged by the LINK_PAGE control in Register 0x300. Not in table error counter. This control is paged by the LINK_PAGE control in Register 0x300. Unexpected K error counter. This control is paged by the LINK_PAGE control in Register 0x300. Interlane deskew. This control is paged by the LINK_PAGE control in Register 0x300. Initial lane synchronization. This control is paged by the LINK_PAGE control in Register 0x300. Good checksum. This control is paged by the LINK_PAGE control in Register 0x300. Frame synchronization. This control is paged by the LINK_PAGE control in Register 0x300. Code group synchronization. This control is paged by the LINK_PAGE control in Register 0x300. Reserved. Configuration mismatch (checked for Lane 0 only). This control is paged by the LINK_PAGE control in Register 0x300. Reserved. Selects which IRQ pin is connected to the JESD204B IRQx sources. Rev. B | Page 144 of 150 Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 0x0 R R/W Data Sheet AD9175 Addr. Name Bits Bit Name 0x580 BE_SOFT_OFF_ GAIN_CTRL 7 BE_SOFT_OFF_ GAIN_EN [6:3] [2:0] RESERVED BE_GAIN_RAMP_ RATE 7 ENA_SHORT_ PAERR_SOFTOFF 6 ENA_LONG_ PAERR_SOFTOFF [5:4] 3 RESERVED ENA_JESD_ERR_ SOFTOFF 2 ROTATE_SOFT_ OFF_EN 1 TXEN_SOFT_OFF_ EN 0 SPI_SOFT_OFF_EN 7 SPI_SOFT_ON_EN 6 LONG_LEVEL_ SOFTON_EN [5:0] [7:0] RESERVED LONG_PA_ THRESHOLD[7:0] 0x581 0x582 BE_SOFT_OFF_ ENABLE BE_SOFT_ON_ ENABLE 0x583 LONG_PA_THRES_ LSB 0x584 LONG_PA_THRES_ MSB [7:5] [4:0] RESERVED LONG_PA_ THRESHOLD[12:8] 0x585 LONG_PA_ CONTROL 7 LONG_PA_ENABLE [6:4] RESERVED Settings 0 1 Description Route the IRQ trigger signal to the IRQ0 pin. Route the IRQ trigger signal to the IRQ1 pin. Reset Access Must be 1 to use soft off/on. This control is paged by the MAINDAC_PAGE control in Register 0x008. Reserved. Sets ramp rate. The gain ramps from 0 to 1 (or 1 to 0) in 32 steps over 2(CODE + 8) DAC clock periods. This control is paged by the MAINDAC_PAGE control in Register 0x008. Enable short PA error soft off. This control is paged by the MAINDAC_PAGE control in Register 0x008. Enable long PA error soft off. This control is paged by the MAINDAC_PAGE control in Register 0x008. Reserved. Enable JESD204B side error soft off. This control is paged by the MAINDAC_PAGE control in Register 0x008. When set to 1, the synchronization logic rotation triggers the DAC output soft off. Register 0x03B, Bit 0 must also be high. This control is paged by the MAINDAC_PAGE control in Register 0x008. When set to 1, a TXENx falling edge triggers the DAC output soft off. This control is paged by the MAINDAC_PAGE control in Register 0x008. Force a soft off when gain is 1. This control is paged by the MAINDAC_PAGE control in Register 0x008. Force a soft on when gain is 0. This control is paged by the MAINDAC_PAGE control in Register 0x008. When set to 1, this bit enables the long level soft on. This control is paged by the MAINDAC_PAGE control in Register 0x008. Reserved. Long average power threshold for comparison. This control is paged by the MAINDAC_PAGE control in Register 0x008. Reserved. Long average power threshold for comparison. This control is paged by the MAINDAC_PAGE control in Register 0x008. Enable long average power calculation and error detection. This control is paged by the MAINDAC_PAGE control in Register 0x008. Reserved. 0x0 R/W 0x0 0x0 R R/W 0x1 R/W 0x1 R/W 0x0 0x0 R R/W 0x1 R/W 0x1 R/W 0x0 R/W 0x0 R/W 0x1 R/W 0x0 0x0 R/W R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R Rev. B | Page 145 of 150 AD9175 Data Sheet Addr. Name Bits [3:0] Bit Name LONG_PA_AVG_ TIME 0x586 LONG_PA_POWER_ LSB [7:0] LONG_PA_ POWER[7:0] 0x587 LONG_PA_POWER_ MSB [7:5] [4:0] RESERVED LONG_PA_ POWER[12:8] 0x588 SHORT_PA_THRES_ LSB [7:0] SHORT_PA_ THRESHOLD[7:0] 0x589 SHORT_PA_THRES_ MSB [7:5] [4:0] RESERVED SHORT_PA_ THRESHOLD[12:8] 0x58A SHORT_PA_ CONTROL 7 SHORT_PA_ENABLE [6:2] [1:0] RESERVED SHORT_PA_AVG_ TIME 0x58B SHORT_PA_POWER_ LSB [7:0] SHORT_PA_ POWER[7:0] 0x58C SHORT_PA_POWER_ [7:5] RESERVED Settings Description Sets length of long PA averaging time. This control is paged by the MAINDAC_PAGE control in Register 0x008. Averaging time = 29 + LONG_PA_AVG_TIME (PA clock periods). A PA clock period is calculated by the following: If the main interpolation is >1×, PA clock period = 4 × main interpolation × DAC clock period. If channel interpolation is >1×, PA clock period = 8 × main interpolation × DAC clock period. Otherwise, PA clock period = 32 × DAC clock period. Long average power readback. Power detected at data bus = I2 + Q2. The data bus calculation only uses the 6 MSBs of the I and Q data bus samples. This control is paged by the MAINDAC_PAGE control in Register 0x008. Reserved. Long average power readback. Power detected at data bus = I2 + Q2. The data bus calculation only uses the 6 MSBs of the I and Q data bus samples. This control is paged by the MAINDAC_PAGE control in Register 0x008. Short average power threshold for comparison. This control is paged by the MAINDAC_PAGE control in Register 0x008. Reserved. Short average power threshold for comparison. This control is paged by the MAINDAC_PAGE control in Register 0x008. Enable short average power calculation and error detection. This control is paged by the MAINDAC_PAGE control in Register 0x008. Reserved. Sets length of short PA averaging. This control is paged by the MAINDAC_PAGE control in Register 0x008. Averaging time = 2SHORT_PA_AVG_TIME (PA clock periods). A PA clock period is calculated by the following: If the main interpolation is >1×, PA clock period = 4 × main interpolation × DAC clock period. If channel interpolation is >1×, PA clock period = 8 × main interpolation × DAC clock period. Otherwise, PA clock period = 32 × DAC clock period. Short average power readback. Power detected at data bus = I2 + Q2. The data bus calculation only uses the 6 MSBs of the I and Q data bus samples. This control is paged by the MAINDAC_PAGE control in Register 0x008. Reserved. Rev. B | Page 146 of 150 Reset 0x0 Access R/W 0x0 R 0x0 0x0 R R 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R 0x0 R Data Sheet AD9175 Addr. Name Bits [4:0] Bit Name SHORT_PA_ POWER[12:8] 0x58D TXEN_SM_0 [7:1] 0 RESERVED ENA_TXENSM 0x596 BLANKING_CTRL [7:4] 3 RESERVED SPI_TXEN 2 ENA_SPI_TXEN [1:0] [7:0] RESERVED JESD_PA_INT_ CNTRL[7:0] 0x597 JESD_PA_INT0 0x598 JESD_PA_INT1 [7:1] 0 RESERVED JESD_PA_INT_ CNTRL[8] 0x599 TXEN_FLUSH_CTRL0 [7:1] 0 RESERVED SPI_FLUSH_EN 0x705 NVM_LOADER_EN [7:1] 0 RESERVED NVM_BLR_EN 0x790 DACPLL_PDCTRL0 7 PLL_PD5 [6:4] PLL_PD4 3 PLL_PD3 Settings Description Short average power readback. Power detected at data bus = I2 + Q2. The data bus calculation only uses the 6 MSBs of the I and Q data bus samples. This control is paged by the MAINDAC_PAGE control in Register 0x008. Reserved. Enable TXEN state machine. This control is paged by the MAINDAC_PAGE control in Register 0x008. Reserved. If ENA_SPI_TXEN (Bit 2 of this register) = 1, the value of this register is the value of the TXENx status. This control is paged by the MAINDAC_PAGE control in Register 0x008. Enable TXENx control via the SPI by setting this bit to 1. This control is paged by the MAINDAC_PAGE control in Register 0x008. Reserved. Each bit enables a JESD204B PA interrupt. Bit 8 = CGS. Bit 7 = frame sync. Bit 6 = good check sum. Bit 5 = initial lane sync. Bit 4 = interlane deskew. Bit 3 = bad disparity error counter. Bit 2 = NIT error counter. Bit 1= UEK error counter. Bit 0 = lane FIFO overflow or underflow. Reserved. Each bit enables a JESD204B PA interrupt. Bit 8 = CGS. Bit 7 = frame sync. Bit 6 = good check sum. Bit 5 = initial lane sync. Bit 4 = interlane deskew. Bit 3 = bad disparity error counter. Bit 2 = NIT error counter. Bit 1= UEK error counter. Bit 0 = lane FIFO overflow or underflow. Reserved. Enable datapath flush. This control is paged by the MAINDAC_PAGE control in Register 0x008. Reserved. Enable bootloader. This bit self clears when the boot loader completes or fails. PLL power-down control. Write this bit to 1 if bypassing the PLL. If using the PLL, keep this value at default (0). PLL power-down control. Write this bit to 1 if bypassing the PLL. If using the PLL, keep this value at default (0). PLL power-down control. Write this bit to 1 if bypassing the PLL. If using the PLL, keep this value default (0). Rev. B | Page 147 of 150 Reset 0x0 Access R 0x1 0x0 R/W R/W 0x0 0x0 R R/W 0x0 R/W 0x0 0x0 R R/W 0x0 0x0 R R/W 0x0 0x1 R R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W AD9175 Addr. 0x791 Name DACPLL_PDCTRL1 Data Sheet Bits 2 Bit Name PLL_PD2 1 PLL_PD1 0 PLL_PD0 [7:5] 4 RESERVED PLL_PD10 3 PLL_PD9 2 PLL_PD8 1 PLL_PD7 0 PLL_PD6 0x792 DACPLL_CTRL0 [7:2] 1 0 RESERVED D_CAL_RESET D_RESET_VCO_DIV 0x793 DACPLL_CTRL1 [7:2] [1:0] RESERVED M_DIVIDER−1 Settings 0 1 10 11 0x794 DACPLL_CTRL2 [7:6] [5:0] RESERVED DACPLL_CP 0x795 DACPLL_CTRL3 0x796 DACPLL_CTRL4 0x797 DACPLL_CTRL5 0x798 DACPLL_CTRL6 [7:4] [3:0] [7:4] [3:0] [7:6] [5:0] 7 6 RESERVED D_CP_CALBITS PLL_CTRL0 RESERVED RESERVED PLL_CTRL1 RESERVED PLL_CTRL3 Description PLL power-down control. Write this bit to 1 if bypassing the PLL. If using the PLL, keep this value at default (0). PLL power-down control. Write this bit to 1 if bypassing the PLL. If using the PLL, write this bit to 0. PLL power-down control. Write this bit to 1 if bypassing the PLL. If using the PLL, keep this value at default (0). Reserved. PLL power-down control. Write this bit to 1 if bypassing the PLL. If using the PLL, keep this value at default (0). PLL power-down control. Write this bit to 1 if bypassing the PLL. If using the PLL, keep this value at default (0). PLL power-down control. Write this bit to 1 if bypassing the PLL. If using the PLL, keep this value at default (0). PLL power-down control. Write this bit to 1 if bypassing the PLL. If using the PLL, keep this value at default (0). PLL power-down control. Write this bit to 1 if bypassing the PLL. If using the PLL, keep this value at default (0). Reserved. Resets VCO calibration. Setting this high holds the VCO output divider in reset. This has the effect of turning off the input (and output) of the ADC clock driver. Reserved. Programmable predivider value for PFD (in n − 1 notation). M_DIVIDER = PLL reference clock/PFD frequency. For optimal spectral performance, choose an M divider setting that selects a high PFD frequency within the allowable PFD range. Divide by 1. Divide by 2. Divide by 3. Divide by 4. Reserved. Charge pump current control. Charge pump current = 100 μA + code × 100 μA. Reserved. DAC PLL optimization control. DAC PLL optimization control. Reserved. Reserved. DAC PLL optimization control. Reserved. DAC PLL optimization control. Rev. B | Page 148 of 150 Reset 0x0 Access R/W 0x1 R/W 0x0 R/W 0x0 0x0 R/W R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x1 0x0 R R/W R/W 0x0 0x0 R R/W 0x0 0x4 R/W R/W 0x0 0x8 0xD 0x2 0x0 0x20 0x0 0x0 R/W R/W R/W R/W R/W R/W R R/W Data Sheet Addr. Name 0x799 DACPLL_CTRL7 AD9175 Bits [5:0] [7:6] Bit Name PLL_CTRL2 ADC_CLK_DIVIDER Settings 0 1 10 11 0x7A0 DACPLL_CTRL9 [5:0] N_DIVIDER [7:6] 5 RESERVED D_EN_VAR_FINE_ PRE RESERVED D_EN_VAR_ COARSE_PRE RESERVED RESERVED D_REGULATOR_ CAL_WAIT D_VCO_CAL_WAIT D_VCO_CAL_ CYCLES RESERVED RESERVED PLL_LOCK [4:3] 2 0x7A2 DACPLL_CTRL10 [1:0] 7 [6:5] [4:3] [2:1] 0x7B5 PLL_STATUS 0 [7:1] 0 Description DAC PLL optimization control. ADC clock output divider. Divide by 1. Divide by 2. Divide by 3. Divide by 4. Programmable divide by N value from 2 to 50. N_DIVIDER = (DAC frequency × M_DIVIDER)/(8 × reference clock frequency). Reserved. DAC PLL control. Reset 0x1C 0x0 Access R/W R/W 0x8 R/W 0x2 0x0 R/W R/W Reserved. DAC PLL control. 0x2 0x0 R/W R/W Reserved. Reserved. DAC PLL optimization control. 0x0 0x0 0x1 R/W R R/W DAC PLL optimization control. DAC PLL optimization control. 0x2 0x2 R/W R/W Reserved. Reserved. DAC PLL lock status. 0x1 0x0 0x0 R/W R R Rev. B | Page 149 of 150 AD9175 Data Sheet OUTLINE DIMENSIONS 10.10 10.00 SQ 9.90 A1 BALL CORNER INDICATOR A1 BALL CORNER R 1.0 12 11 10 9 8 7 6 5 4 3 2 1 A B C 9.80 9.70 SQ 9.60 D 8.80 SQ REF E F G 6.60 REF SQ H J 0.80 BSC K L M 1.71 1.56 1.41 TOP VIEW 0.60 REF 0.15 REF DETAIL A DETAIL A BOTTOM VIEW 0.87 REF SIDE VIEW 0.38 0.34 0.30 0.40 0.35 0.30 PKG-005195 SEATING PLANE 0.50 0.45 0.40 BALL DIAMETER COPLANARITY 0.12 COMPLIANT TO JEDEC STANDARDS MO-275-EEAB-1. 05-10-2016-A R 0.5~1.5 Figure 100. 144-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] (BP-144-1) Dimensions shown in millimeters ORDERING GUIDE Model1 AD9175BBPZ AD9175BBPZRL AD9175-FMC-EBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 144-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] 144-Ball Ball Grid Array, Thermally Enhanced [BGA_ED] Evaluation Board Z = RoHS Compliant Part. ©2018–2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16795-0-8/19(B) Rev. B | Page 150 of 150 Package Option BP-144-1 BP-144-1