AD9203ARURL7

10-Bit, 40 MSPS, 3 V, 74 mW A/D Converter AD9203 FEATURES FUNCTIONAL BLOCK DIAGRAM CLK AVDD DRVDD CLAMP AD9203 CLAMPIN AINP STBY A/D AINN SHA A/D GAIN SHA D/A A/D GAIN 3-STATE D/A REFTF CORRECTION LOGIC REFBF BANDGAP REFERENCE VREF OUTPUT BUFFERS OTR 10 + – REFSENSE D0 (LSB) 0.5V AVSS D9 (MSB) PWRCON DFS DRVSS 00573-001 CMOS 10-Bit, 40 MSPS sampling A/D converter Power dissipation: 74 mW (3 V supply, 40 MSPS) 17 mW (3 V supply, 5 MSPS) Operation between 2.7 V and 3.6 V supply Differential nonlinearity: −0.25 LSB Power-down (standby) mode, 0.65 mW ENOB: 9.55 @ fIN = 20 MHz Out-of-range indicator Adjustable on-chip voltage reference IF undersampling up to fIN = 130 MHz Input range: 1 V to 2 V p-p differential or single-ended Adjustable power consumption Internal clamp circuit Figure 1. APPLICATIONS CCD imaging Video Portable instrumentation IF and baseband communications Cable modems Medical ultrasound GENERAL DESCRIPTION The AD9203 is a monolithic low power, single supply, 10-bit, 40 MSPS analog-to-digital converter, with an on-chip voltage reference. The AD9203 uses a multistage differential pipeline architecture and guarantees no missing codes over the full operating temperature range. Its input range may be adjusted between 1 V and 2 V p-p. The AD9203 has an onboard programmable reference. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of an application. An external resistor can be used to reduce power consumption when operating at lower sampling rates. This yields power savings for users who do not require the maximum sample rate. This feature is especially useful at sample rates far below 40 MSPS. Excellent performance is still achieved at reduced power. For example, 9.7 ENOB performance may be realized with only 17 mW of power, using a 5 MHz clock. A single clock input is used to control all internal conversion cycles. The digital output data is presented in straight binary or twos complementary output format by using the DFS pin. An out-of-range signal (OTR) indicates an overflow condition that can be used with the most significant bit to determine over- or underrange. The AD9203 can operate with a supply range from 2.7 V to 3.6 V, an attractive option for low power operation in high-speed portable applications. The AD9203 is specified over industrial (−40°C to +85°C) temperature ranges and is available in a 28-lead TSSOP package. PRODUCT HIGHLIGHTS Low Power—The AD9203 consumes 74 mW on a 3 V supply operating at 40 MSPS. In standby mode, power is reduced to 0.65 mW. High Performance—Maintains better than 9.55 ENOB at 40 MSPS input signal from dc to Nyquist. Very Small Package—The AD9203 is available in a 28-lead TSSOP. Programmable Power—The AD9203 power can be further reduced by using an external resistor at lower sample rates. Built-In Clamp Function—Allows dc restoration of video signals. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. AD9203 TABLE OF CONTENTS Specifications..................................................................................... 3 Driving the Analog Input.......................................................... 13 Absolute Maximum Ratings............................................................ 5 Op Amp Selection Guide .......................................................... 14 Thermal Characteristics .............................................................. 5 Differential Mode of Operation ............................................... 15 ESD Caution.................................................................................. 5 Power Control............................................................................. 16 Pin Configuration and Function Descriptions............................. 6 Interfacing to 5 V Systems ........................................................ 16 Terminology ...................................................................................... 7 Clock Input and Considerations .............................................. 16 Typical Performance Characteristics ............................................. 8 Digital Inputs and Outputs ....................................................... 16 Operations ....................................................................................... 11 Applications..................................................................................... 18 Theory of Operation .................................................................. 11 Direct IF Down Conversion ..................................................... 18 Operational Modes..................................................................... 11 Ultrasound Applications ........................................................... 19 Input and Reference Overview ................................................. 12 Evaluation Board ............................................................................ 20 Internal Reference Connection ................................................ 12 Outline Dimensions ....................................................................... 25 External Reference Operation .................................................. 13 Ordering Guide .......................................................................... 25 Clamp Operation........................................................................ 13 REVISION HISTORY 8/04—Data sheet changed from Rev. A to Rev. B Changes to Table 5.......................................................................... 16 4/01—Data sheet changed from Rev. 0 to Rev. A Updated Format..................................................................Universal Changes to TPC 2 ............................................................................. 8 Added Figures 41 to 46 .................................................................. 23 7/99—Revision 0: Initial Version Rev. B | Page 2 of 28 AD9203 SPECIFICATIONS AVDD = 3 V, DRVDD = 3 V, FS = 40 MSPS, input span from 0.5 V to 2.5 V, internal 1 V reference, PWRCON = AVDD, 50% clock duty cycle, TMIN to TMAX unless otherwise noted. Table 1. Parameter RESOLUTION MAX CONVERSION RATE PIPELINE DELAY DC ACCURACY Differential Nonlinearity Integral Nonlinearity Offset Error Gain Error ANALOG INPUT Input Voltage Range Input Capacitance Aperture Delay Aperture Uncertainty (Jitter) Input Bandwidth (–3 dB) Input Referred Noise INTERNAL REFERENCE Output Voltage (0.5 V Mode) Output Voltage (1 V Mode) Output Voltage Tolerance (1 V Mode) Load Regulation POWER SUPPLY Operating Voltage Analog Supply Current Digital Supply Current Symbol Min FS 40 1 Max 5.5 DNL INL EZS EFS AIN CIN TAP TAJ BW ± 0.25 ± 0.7 ± 0.65 ± 1.4 ± 0.6 ± 2.8 ± 0.7 ± 4.0 1 VREF VREF AVDD DRVDD IAVDD IDRVDD 2.7 2.7 PD PSRR Unit Bits MSPS Clock Cycles 1.4 2.0 1.2 390 0.3 V p-p pF ns ps rms MHz mV 0.5 1 ±5 0.65 ± 30 1.2 V V mV mV 3.0 3.0 20.1 4.4 9.5 74 88.8 0.65 0.04 3.6 3.6 22.0 6.0 14.0 84.0 108.0 1.2 ± 0.25 V V mA mA mA mW mW mW % FS SINAD 57.2 59.7 59.3 dB dB 9.2 9.6 9.55 Bits Bits 57.5 60.0 59.5 dB dB ENOB 1 SNR 1 THD −76.0 −74.0 −65.0 dB dB SFDR 67.8 80 78 Rev. B | Page 3 of 28 Conditions LSB LSB % FSR % FSR 2 Power Consumption Power-Down Power Supply Rejection Ratio DYNAMIC PERFORMANCE (AIN = 0.5 dBFS) Signal-to-Noise and Distortion f = 4.8 MHz f = 20 MHz Effective Bits f = 4.8 MHz f = 20 MHz Signal-to-Noise Ratio f = 4.8 MHz f = 20 MHz Total Harmonic Distortion f = 4.8MHz f = 20 MHz Spurious-Free Dynamic Range f = 4.8 MHz1 f = 20 MHz Typ 10 dB dB Switched, Single-Ended REFSENSE = VREF REFSENSE = GND 1.0 mA Load fIN= 4.8 MHz, Output Bus Load = 10pF fIN= 20 MHz, Output Bus Load = 20 pF fIN= 4.8 MHz, Output Bus Load = 10pF fIN= 20 MHz, Output Bus Load = 20 pF AD9203 Parameter Two-Tone Intermodulation Distortion Differential Phase Differential Gain DIGITAL INPUTS High Input Voltage Low Input Voltage Clock Pulse Width High Clock Pulse Width Low Clock Period2 DIGITAL OUTPUTS High-Z Leakage Data Valid Delay Data Enable Delay Data High-Z Delay LOGIC OUTPUT (with DRVDD = 3 V) High Level Output Voltage (IOH = 50 µA) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOL= 1.6 mA) Low Level Output Voltage (IOL= 50 µA) 2 Min VIH VIL 2.0 Typ 68 0.2 0.3 Max Unit dB Degree % V V ns ns ns 0.4 11.25 11.25 25 IOZ tOD tDEN tDHZ ± 5.0 µA ns ns ns 5 6 6 VOH VOH VOL VOL Conditions f = 44.49 MHz and 45.52 MHz NTSC 40 IRE Ramp 2.95 2.80 Output = 0 to DRVDD CL= 20 pF CL= 20 pF CL= 20 pF V V V V 0.3 0.05 Differential Input (2 V p-p). The AD9203 will convert at clock rates as low as 20 kHz. N N+1 N+2 N–1 N+3 ANALOG INPUT N+4 N+6 N+5 CLOCK DATA OUT N–7 N–6 N–5 N–4 N–3 N–2 TOD = 3ns MIN 7ns MAX (CLOAD = 20pF) Figure 2. Timing Diagram Rev. B | Page 4 of 28 N–1 N N+1 00573-002 1 Symbol IMD DP DG AD9203 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter AVDD DRVDD AVSS AVDD REFCOM CLK Digital Outputs AINP VREF REFSENSE REFTF, REFBF STBY CLAMP CLAMPIN PWRCON DFS 3-STATE Junction Temperature Storage Temperature Lead Temperature (10 s) With Respect to AVSS DRVSS DRVSS DRVDD AVSS AVSS DRVSS AINN AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS Min –0.3 –0.3 –0.3 –3.9 –0.3 –0.3 –0.3 AVSS –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 Max +3.9 +3.9 +0.3 +3.9 +0.3 AVDD + 0.3 DRVDD + 0.3 AVDD + 0.3 Unit V V V V V V V V AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 150 V V V V V V V V V °C –65 +150 °C 300 °C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. THERMAL CHARACTERISTICS 28-Lead TSSOP JA = 97.9°C/W JC = 14.0°C/W ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 5 of 28 AD9203 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DRVSS 1 28 AVDD DRVDD 2 27 AVSS (LSB) D0 3 26 AINN D1 4 25 AINP D2 5 D3 6 D4 7 D5 8 24 REFBF AD9203 23 VREF TOP VIEW 22 REFTF (Not to Scale) 21 PWRCON D6 9 20 CLAMPIN D7 10 19 CLAMP D8 11 18 REFSENSE 17 STBY OTR 13 16 3-STATE DFS 14 15 CLK 00573-003 (MSB) D9 12 Figure 3. Pin Configuration Table 3. Pin Function Descriptions Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Name DRVSS DRVDD D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 OTR DFS CLK 3-STATE STBY REFSENSE CLAMP CLAMPIN PWRCON REFTF VREF REFBF AINP AINN AVSS AVDD Description Digital Ground. Digital Supply. Bit 0, Least Significant Bit. Bit 1. Bit 2. Bit 3. Bit 4. Bit 5. Bit 6. Bit 7. Bit 8. Bit 9, Most Significant Bit. Out-of-Range Indicator. Data Format Select HI: Twos Complement; LO: Straight Binary. Clock Input. HI: High Impedance State Output; LO: Active Digital Output Drives. HI: Power-Down Mode; LO: Normal Operation. Reference Select. HI: Enable Clamp; LO: Open Clamp. Clamp Signal Input. Power Control Input. Top Reference Decoupling. Reference In/Out. Bottom Reference Decoupling. Noninverting Analog Input. Inverting Analog Input. Analog Ground. Analog Supply. Rev. B | Page 6 of 28 AD9203 TERMINOLOGY Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Differential Nonlinearity Error (DNL, No Missing Codes) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 10-bit resolution indicates that all 1024 codes respectively, must be present over all operating ranges. Signal-To-Noise and Distortion (S/N+D, SINAD) Ratio S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. Effective Number of Bits (ENOB) For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula, N = (SINAD – 1.76)/6.02 it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels. Signal-To-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Spurious-Free Dynamic Range (SFDR) The difference in dB between the rms amplitude of the input signal and the peak spurious signal. Offset Error First transition should occur for an analog value 1/2 LSB above negative full scale. Offset error is defined as the deviation of the actual transition from that point. Gain Error The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur for an analog value 1 1/2 LSB below the positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. Power Supply Rejection The specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. Aperture Jitter Aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the A/D. Aperture Delay Aperture delay is a measure of the sample-and-hold amplifier (SHA) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion. Pipeline Delay (Latency) The number of clock cycles between conversion initiation and the associated output data being made available. New output data is provided on every rising edge. Rev. B | Page 7 of 28 AD9203 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 3 V, DRVDD = 3 V, FS = 40 MSPS, 1 V Internal Reference, PWRCON = AVDD, 50% Duty Cycle, unless otherwise noted. 61 85 2V SINGLE-ENDED INPUT 80 59 75 2V DIFFERENTIAL INPUT 70 SFDR (dB) 55 53 1V DIFFERENTIAL INPUT 1V DIFFERENTIAL INPUT 65 1V SINGLEENDED INPUT 60 55 2V DIFFERENTIAL INPUT 50 51 2V SINGLEENDED INPUT 00573-004 1V SINGLE-ENDED INPUT 47 0 20 40 60 80 INPUT FREQUENCY (MHz) 100 00573-007 45 49 40 35 120 Figure 4. SNR vs. Input Frequency and Configuration 0 20 40 60 80 INPUT FREQUENCY (MHz) –80 9.6 2V DIFFERENTIAL INPUT –75 55 –70 8.8 1V DIFFERENTIAL INPUT 8.0 1V DIFFERENTIAL INPUT 45 7.1 THD (dB) 50 ENOB SINAD (dB) –65 1V SINGLEENDED INPUT 6.3 40 60 80 INPUT FREQUENCY (MHz) –55 1V SINGLEENDED INPUT –50 00573-005 –40 2V SINGLEENDED INPUT 20 2V DIFFERENTIAL INPUT –60 –45 40 0 120 Figure 7. SFDR vs. Input Frequency and Configuration 60 35 100 100 5.5 120 2V SINGLEENDED INPUT –35 –30 Figure 5. SINAD vs. Input Frequency and Configuration 0 20 40 60 80 INPUT FREQUENCY (MHz) 00573-008 SNR (dB) 57 100 120 Figure 8. THD vs. Input Frequency and Configuration –75 –75 –70 –0.5dB –0.5dB –65 –65 THD (dB) –6.0dB –55 –55 –20dB –50 –20dB –45 –45 0 20 40 60 80 INPUT FREQUENCY (MHz) 100 –35 120 Figure 6. THD vs. Input Frequency and Amplitude (Differential Input VREF = 0.5 V) 00573-009 –40 00573-006 THD (dB) –6.0dB –60 0 20 40 60 80 INPUT FREQUENCY (MHz) 100 Figure 9. THD vs. Input Frequency and Amplitude (Differential Input VREF = 1 V) Rev. B | Page 8 of 28 120 AD9203 1.2E+07 1.0 0.8 10000000 1.0E+07 0.6 0.4 8.0E+06 LSB 0 –0.2 4.0E+06 –0.4 00573-010 4560 0.0E+00 10310 N–1 N CODE 00573-013 –0.6 2.0E+06 –0.8 –1.0 N+1 0 80 200 300 400 500 600 700 800 900 1024 10 SNR = 59.9dB THD = –75dB SFDR = 82dB 0 85 –10 –THD –20 70 –30 65 –40 60 dB +SNR/–THD (dB) 100 Figure 13. Typical DNL Performance Figure 10. Grounded Input Histogram SNR 55 –50 –60 –70 –80 50 –90 0 10 20 30 40 SAMPLE RATE (MSPS) 50 00573-014 40 –100 00573-011 45 –110 –120 60 0E+0 2.5E+6 5.0E+6 7.5E+6 10.0E+6 12.5E+6 15.0E+6 17.5E+6 20.0E+6 Figure 14. Single Tone Frequency Domain Performance (Input Frequency = 10 MHz, Sample Rate = 40 MSPS 2 V Differential Input, 8192 Point FFT) Figure 11. SNR and THD vs. Sample Rate (fIN = 20 MHz) 80 1.0 0.8 75 0.6 –THD +SNR/–THD (dB) 0.4 0.2 0 –0.2 70 65 60 –0.4 SNR –0.6 –0.8 –1.0 0 100 200 300 400 500 600 700 800 900 50 2.5 1024 Figure 12. Typical INL Performance 00573-015 55 00573-012 LSB HITS 0.2 6.0E+06 3.0 3.5 SUPPLY VOLTAGE (V) Figure 15. SNR and THD vs. Power Supply (fIN = 20 MHz, Sample Rate = 40 MSPS) Rev. B | Page 9 of 28 4.0 AD9203 0 0.2 –1 0.1 –3 VREF ERROR (%) AMPLITUDE (dB) –2 –4 –5 –6 0 0.5V –0.1 1V –0.2 –7 –9 10 100 INPUT FREQUENCY (MHz) –0.4 –40 1000 Figure 16. Full Power Bandwidth 3000 1V REFERENCE WAKE-UP TIME (µs) 2000 0.5V REFERENCE 1500 1000 00573-017 500 0 0 200 400 600 OFF-TIME (ms) –20 0 20 40 TEMPERATURE (°C) 60 80 Figure 18. Reference Voltage vs. Temperature 3500 2500 00573-018 00573-016 –0.3 –8 800 1000 Figure 17. Wake-Up Time vs. Off Time (VREF Decoupling = 10 µF) Rev. B | Page 10 of 28 100 AD9203 OPERATIONS THEORY OF OPERATION OPERATIONAL MODES The AD9203 implements a pipelined multistage architecture to achieve high sample rates while consuming low power. It distributes the conversion over several smaller A/D subblocks, refining the conversion with progressively higher accuracy as it passes the results from stage to stage. As a consequence of the distributed conversion, the AD9203 requires a small fraction of the 1023 comparators used in a traditional 10-bit flash-type A/D. A sample-and-hold function within each of the stages permits the first stage to operate on a new input sample while the remaining stages operate on preceding samples. The AD9203 may be connected in several input configurations, as shown in Table 4. Each stage of the pipeline, excluding the last, consists of a low resolution flash A/D connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each one of the stages to facilitate digital correction of flash errors. The last stage simply consists of a flash A/D. The input of the AD9203 incorporates a novel structure that merges the input sample-and-hold amplifier (SHA) and the first pipeline residue amplifier into a single, compact switched capacitor circuit. This structure achieves considerable noise and power savings over a conventional implementation that uses separate amplifiers by eliminating one amplifier in the pipeline. By matching the sampling network of the input SHA with the first stage flash A/D, the AD9203 can sample inputs well beyond the Nyquist frequency with no degradation in performance. Sampling occurs on the falling edge of the clock. The AD9203 may be driven differentially from a source that keeps the signal peaks within the power supply rails. Alternatively, the input may be driven into AINP or AINN from a single-ended source. The input span will be 2 the programmed reference voltage. One input will accept the signal, while the opposite input will be set to midscale by connecting it to the internal or an external reference. For example, a 2 V p-p signal may be applied to AINP while a 1 V reference is applied to AINN. The AD9203 will then accept a signal varying between 2 V and 0 V. See Figure 19, Figure 20, and Figure 21 for more details. The single-ended (ac-coupled) input of the AD9203 may also be clamped to ground by the internal clamp switch. This is accomplished by connecting the CLAMP pin to AINN or AINP. Digital output formats may be configured in binary and twos complement. This is determined by the potential on the DFS pin. If the pin is set to Logic 0, the data will be in straight binary format. If the pin is asserted to Logic 1, the data will be in twos complement format. Power consumption may be reduced by placing a resistor between PWRCON and AVSS. This may be done to conserve power when not encoding high-speed analog input frequencies or sampling at the maximum conversion rate. See the Power Control section for more information. Table 4. Modes Name 1 V Differential 2 V Differential 1 V Single-Ended 2 V Single-Ended Figure Number Figure 28 with VREF Connected to REFSENSE Figure 28 with REFSENSE Connected to AGND Figure 20 Figure 19 Advantages Differential Modes Yield the Best Dynamic Performance Differential Modes Yield the Best Dynamic Performance Video and Applications Requiring Clamping Require Single-Ended Inputs Video and Applications Requiring Clamping Require Single-Ended Inputs Rev. B | Page 11 of 28 AD9203 Figure 19 illustrates the input configured with a 1 V reference. This will set the single-ended input of the AD9203 in the 2 V span (2 × VREF). This example shows the AINN input is tied to the 1 V VREF. This will configure the AD9203 to accept a 2 V input centered around 1 V. Like the voltage applied to the top of the resistor ladder in a flash A/D converter, the value VREF defines the maximum input voltage to the A/D core. The minimum input voltage to the A/D core is automatically defined to be −VREF. 2V 0V The addition of a differential input structure gives the user an additional level of flexibility that is not possible with traditional flash converters. The input stage allows the user to easily configure the inputs for either single-ended operation or differential operation. The A/D’s input structure allows the dc offset of the input signal to be varied independently of the input span of the converter. Specifically, the input to the A/D core is the difference of the voltages applied at the AINP and AINN input pins. Therefore, the equation, AINN REFTF 2V 0.1µF ADC CORE 10µF 0.1µF REFBF 1V 0.1µF VREF 10µF VCORE = AINP − AINN AINP + 0.5V 0.1µF – (1) defines the output of the differential input stage and provides the input to the A/D core. LOGIC REFSENSE 00573-019 INPUT AND REFERENCE OVERVIEW AD9203 Figure 19. Internal Reference Set for a 2 V Span The voltage, VCORE, must satisfy the condition, −VREF ≤ VCORE ≤ VREF (2) where VREF is the voltage at the VREF pin. The actual span (AINP − AINN) of the ADC is ±VREF. Figure 20 illustrates the input configured with a 0.5 V reference. This will set the single-ended input of the ADC in a 1 V span (2 × VREF). The AINN input is tied to the 0.5 VREF. This will configure the AD9203 to accept a 1 V input centered around 0.5 V. While an infinite combination of AINP and AINN inputs exist that satisfy Equation 2, an additional limitation is placed on the inputs by the power supply voltages of the AD9203. The power supplies bound the valid operating range for AINP and AINN. The condition, AVSS − 0.3 V < AINP < AVDD + 0.3 V AVSS − 0.3 V < AINN < AVDD + 0.3 V 1V 0V AINP AINN REFTF 1.75V 0.1µF ADC CORE 10µF 0.1µF REFBF (3) 1.25V 0.1µF VREF 10µF + 0.5V 0.1µF – LOGIC REFSENSE AD9203 INTERNAL REFERENCE CONNECTION A comparator within the AD9203 will detect the potential of the VREF pin. If REFSENSE is grounded, the reference amplifier switch will connect to the resistor divider (see Figure 19). That will make VREF equal to 1 V. If resistors are placed between VREF, REFSENSE and ground, the switch will be connected to the REFSENSE position and the reference amplitude will depend on the external programming resistors (Figure 21). If REFSENSE is tied to VREF, the switch will also connect to REFSENSE and the reference voltage will be 0.5 V (Figure 20). REFTF and REFBF will drive the ADC conversion core and establish its maximum and minimum span. The range of the ADC will equal twice the voltage at the reference pin for either an internal or external reference. 00573-020 where AVSS is nominally 0 V and AVDD is nominally 3 V, defines this requirement. The range of valid inputs for AINP and AINN is any combination that satisfies both Equations 2 and 3. Figure 20. Internal Reference Set for a 1 V Span Figure 21 shows the reference programmed by external resistors for 0.75 V. This will set the ADC to receive a 1.5 V span centered about 0.75 V. The reference is programmed according to the algorithm: Rev. B | Page 12 of 28 VREF = 0.5 V × [1 + (RA/RB)] AD9203 1.5V 0V CLAMP OPERATION AINP REFTF 1.875V AINN 0.1µF ADC CORE 10µF 0.1µF The AD9203 contains an internal clamp. It may be used when operating the input in a single-ended mode. This clamp is very useful for clamping NTSC and PAL video signals to ground. The clamp cannot be used in the differential input mode. REFBF 1.125V REFSENSE AD9203 0.1µF 10µF VREF + VREF 0.5V 0.1µF AINN – CIN RA 1V p-p AD9203 00573-021 LOGIC REFSENSE ADC CORE AINP RB 0V DC 50Ω TYP CLAMPIN CLAMP Figure 21. Programmable Reference Configuration 00573-023 SW1 EXTERNAL REFERENCE OPERATION Figure 22 illustrates the use of an external reference. An external reference may be necessary for several reasons. Tighter reference tolerance will enhance the accuracy of the ADC and will allow lower temperature drift performance. When several ADCs track one another, a single reference (internal or external) will be necessary. The AD9203 will draw less power when an external reference is used. When the REFSENSE pin is tied to AVDD, the internal reference will be disabled, allowing the use of an external reference. INPUT BIAS (µA) 200 150 100 50 0 –50 3.0V 2.0V 1.0V AINP AD9203 EXTERNAL REF (2V) 00573-024 In Figure 22, an external reference is used to set the midscale set point for single-ended use. At the same time, it sets the input voltage span through a resistor divider. If the ADC is being driven differentially through a transformer, the external reference can set the center tap (common-mode voltage). 0 0.5 1.0 1.5 2.0 INPUT VOLTAGE (V) 2.5 3.0 Figure 24. Input Bias Current vs. Input Voltage (FS = 40 MSPS) AINN 10µF DRIVING THE ANALOG INPUT 0.1µF 1.5kΩ VREF A3 1V 0.1µF 1.5kΩ AVDD REFSENSE Figure 22. External Reference Configuration 00573-022 0.1µF Figure 23 shows the internal clamp circuitry and the external control signals needed for clamp operation. To enable the clamp, apply a logic high 1 to the CLAMP pin. This will close SW1, the internal switch. SW1 is opened by asserting the CLAMP pin low 0. The capacitor holds the voltage across CIN constant until the next interval. The charge on the capacitor will leak off as a function of input bias current (see Figure 24). 250 The AD9203 contains an internal reference buffer. It will load the external reference with an equivalent 10 kΩ load. The internal buffer will generate positive and negative full-scale references for the ADC core. 5V Figure 23. Clamp Configuration (VREF = 0.5 V) Figure 25 illustrates the equivalent analog input of the AD9203, (a switched capacitor input). Bringing CLK to a logic high, opens S3 and closes S1 and S2. The input source connected to AIN and must charge Capacitor CH during this time. Bringing CLK to a logic low opens S2, and then S1 opens followed by closing S3. This puts the input in the hold mode. Rev. B | Page 13 of 28 AD9203 C1 VIN S1 CH CP AVDD/2 00573-025 CP CH AD9203 The f–3 dB point can be approximated by the equation: The structure of the input SHA places certain requirements on the input drive source. The combination of the pin capacitance, CP, and the hold capacitance, CH, is typically less than 5 pF. The input source must be able to charge or discharge this capacitance to 10-bit accuracy in one half of a clock cycle. When the SHA goes into track mode, the input source must charge or discharge capacitor CH from the voltage already stored on CH to the new voltage. In the worst case, a full-scale voltage step on the input source must provide the charging current through the RON (100 Ω) of Switch 1 and quickly (within 1/2 CLK period) settle. This situation corresponds to driving a low input impedance. Adding series resistance between the output of the signal source and the AIN pin reduces the drive requirements placed on the signal source. Figure 26 shows this configuration. The bandwidth of the particular application limits the size of this resistor. To maintain the performance outlined in the data sheet specifications, the resistor should be limited to 50 Ω or less. The series input resistor can be used to isolate the driver from the AD9203’s switched capacitor input. The external capacitor may be selected to limit the bandwidth into the AD9203. Two input RC networks should be used to balance differential input drive schemes (Figure 26). The input span of the AD9203 is a function of the reference voltage. For more information regarding the input range, see the Internal Reference Connection and External Reference Operation sections of the data sheet. FS/2). The AD8138 provides a convenient method of converting a single-ended signal to a differential signal. This is an ideal method for generating a direct coupled signal to the AD9203. The AD8138 will accept a signal and shift it to an externally provided common-mode level. The AD8138 configuration is shown in Figure 28. 10µF 10µF 0.1µF 0.1µF 28 1.0V REF 5 20pF 4 1 0.1µF 3 49.9Ω 20pF –50 2 25 AVDD AINP DRVDD AD9203 AINN 26 –60 DIGITAL OUTPUTS –40 00573-030 49.9Ω AD8138 523Ω 0.5V REF –70 AVSS DRVSS 27 1 00573-028 6 2 The AD9203 can be easily configured for either a 1 V p-p or 2 V p-p input span by setting the internal reference. Other input spans can be realized with two external gain setting resistors as shown in Figure 21 of this data sheet. Figure 34 and Figure 35 demonstrate the SNR and SFDR performance over a wide range of amplitudes required by most communication applications. THD (dB) 499Ω 8 49.9Ω Transformers with other turns ratios may also be selected to optimize the performance of a given application. For example, selecting a transformer with a higher impedance ratio, such as minicircuits T16–6T with an impedance ratio of 16, effectively steps up the signal amplitude, thus further reducing the driving requirements of the signal source. –80 10kΩ 499Ω The center tap of the transformer provides a convenient means of level-shifting the input signal to a desired common-mode voltage. Figure 30 illustrates the performance of the AD9203 over a wide range of common-mode levels. 3V 3V 0.1µF 0.1µF 00573-029 VREF 10kΩ 499Ω Figure 28. AD8138 Driving an AD9203, a 10-Bit, 40 MSPS A/D Converter Figure 29 shows the schematic of a suggested transformer circuit. The circuit uses a Minicircuits RF transformer, model number T4–1T, which has an impedance ratio of four (turns ratio of 2). Rev. B | Page 15 of 28 –30 0 0.5 1.0 1.5 2.0 2.5 COMMON-MODE VOLTAGE (V) 3.0 Figure 30. THD vs. Common-Mode Voltage vs. THD (AIN = 2 V Differential) (fIN = 5 MHz, fS = 40 MSPS) 3.5 AD9203 –90 CLOCK INPUT AND CONSIDERATIONS The AD9203 internal timing uses the two edges of the clock input to generate a variety of internal timing signals. Sampling occurs on the falling edge. The clock input to the AD9203 operating at 40 MSPS may have a duty cycle between 45% to 55% to meet this timing requirement since the minimum specified tCH and tCL is 11.25 ns. For clock rates below 40 MSPS, the duty cycle may deviate from this range to the extent that both tCH and tCL are satisfied. See Figure 31 for dynamics vs. duty cycle. –80 THD (dB) THD –70 SNR –60 –40 40.0 00573-031 –50 42.5 45.0 47.5 50.0 52.5 DUTY CYCLE (%) 55.0 57.5 High-speed, high-resolution A/Ds are sensitive to the quality of the clock input. The degradation in SNR at a given full-scale input frequency (fIN) due only to aperture jitter (tA) can be calculated with the following equation: 60.0 Figure 31. THD and SNR vs. Clock Duty Cycle (fIN = 5 MHz Differential, Clock = 40 MSPS) SNR degradation = 20 log10 [1/2π fIN tA] In the equation, the rms aperture jitter, tA, represents the rootsum square of all the jitter sources, which include the clock input, analog input signal, and A/D aperture jitter specification. Undersampling applications are particularly sensitive to jitter. Table 5. Power Programming Resistance Clock MSPS Resistor Value (k) 1 50 5 to 10 100 15 to 20 200 >20 500 Clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9203. Power supplies for clock drivers should be separated from the A/D output driver supplies to avoid modulating the clock signal with digital noise. Low jitter crystal controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing or another method), it should be retimed by the original clock at the last step. POWER CONTROL Power consumed by the AD9203 may be reduced by placing a resistor between the PWRCON pin and ground. This function will be valuable to users who do not need the AD9203’s high conversion rate, but do need even lower power consumption. The external resistor sets the programming of the analog current mirrors. Table 5 illustrates the relationship between programmed power and performance. At lower clock rates, less power is required within the analog sections of the AD9203. Placing an external resistor on the PWRCON pin will shunt control current away from some of the current mirrors. This enables the ADC to convert low data rates with extremely low power consumption. INTERFACING TO 5 V SYSTEMS The AD9203 can be integrated into 5 V systems. This is accomplished by deriving a 3 V power supply from the existing 5 V analog power line through an AD3307-3 linear regulator. The clock input is referred to the analog supply. Its logic threshold is AVDD/2. DIGITAL INPUTS AND OUTPUTS Each of the AD9203 digital control inputs, 3-STATE, DFS, and STBY are referenced to analog ground. CLK is also referenced to analog ground. A low power mode feature is provided such that for STBY = HIGH and the static power of the AD9203 drops to 0.65 mW. Asserting the DFS pin high will invert the MSB pin, changing the data to a twos complement format. The AD9203 has an OTR (out of range) function. If the input voltage is above or below full scale by 1 LSB, the OTR flag will go high. See Figure 32. Care must be maintained so that logic inputs do not exceed the maximum rated values listed on the Specifications page. Rev. B | Page 16 of 28 AD9203 OTR DATA OUTPUTS 1 0 0 11111 11111 11111 11111 11111 11110 0 0 1 00000 00000 00000 00001 00000 00000 –FS 00573-032 OTR +FS –FS + 1 LSB +FS – 1 LSB Figure 32. Output Data Format G1 = 20dB 50Ω 50Ω G2 = 20dB AD9203 BANDPASS MINI CIRCUITS FILTER T4-6T 50Ω 1:4 200Ω AINP 200Ω AINN 22.1Ω 93.1Ω AVDD/2 Figure 33. Simplified IF Sampling Circuit Rev. B | Page 17 of 28 00573-033 SAW FILTER OUTPUT AD9203 APPLICATIONS In direct IF down conversion applications, one exploits the inherent sampling process of an ADC in which an IF signal lying outside the baseband region can be aliased back into the baseband region in a manner similar to a mixer downconverting an IF signal. Similar to the mixer topology, an image rejection filter is required to limit other potential interfering signals from also aliasing back into the ADC’s baseband region. A trade-off exists between the complexity of this image rejection filter and the ADC’s sample rate and dynamic range. The AD9203 is well suited for various IF sampling applications. Its low distortion input SHA has a full-power bandwidth extending to 130 MHz, thus encompassing many popular IF frequencies. Only the 2 V span should be used for undersampling beyond 20 MHz. A DNL of ±0.25 LSB combined with low thermal input referred noise allows the AD9203 in the 2 V span to provide >59 dB of SNR for a baseband input sine wave. Also, its low aperture jitter of 1.2 ps rms ensures minimum SNR degradation at higher IF frequencies. In fact, the AD9203 is capable of still maintaining 58 dB of SNR at an IF of 70 MHz with a 2 V input span. The distortion and noise performance of an ADC at the given IF frequency is of particular concern when evaluating an ADC for a narrowband IF sampling application. Both single tone and dual tone SFDR vs. amplitude are very useful in assessing an ADC’s dynamic and static nonlinearities. SNR vs. amplitude performance at the given IF is useful in assessing the ADC’s noise performance and noise contribution due to aperture jitter. In any application, one is advised to test several units of the same device under the same conditions to evaluate the given applications sensitivity to that particular device. Figure 34 and Figure 35 combine the dual tone SFDR as well as single tone SFDR and SNR performances at IF frequencies of 70 MHz, and 130 MHz. Note, the SFDR vs. amplitude data is referenced to dBFS while the single tone SNR data is referenced to dBc. The performance characteristics in these figures are representative of the AD9203 without any preceding gain stage. The AD9203 was operated in the differential mode (via transformer) with a 2 V span and a sample rate of 40 MSPS. The analog supply (AVDD) and the digital supply (DRVDD) were set to 3.0 V. 90 SFDR 2 TONE 80 70 SFDR 1 TONE 60 50 SNR 40 30 20 00573-034 Sampling IF signals above an ADC’s baseband region (i.e., dc to FS/2) is becoming increasingly popular in communication applications. This process is often referred to as direct IF down conversion or undersampling. There are several potential benefits in using the ADC to alias (or mix) down a narrow band or wide band IF signal. First and foremost is the elimination of a complete mixer stage with its associated amplifiers and filters, reducing cost and power dissipation. Second is the ability to apply various DSP techniques to perform such functions as filtering, channel selection, quadrature demodulation, data reduction, detection, etc. A detailed discussion on using this technique in digital receivers can be found in Analog Devices Application Notes AN-301 and AN-302. SNR/SFDR (dB) DIRECT IF DOWN CONVERSION 10 0 0 5 10 15 20 25 INPUT POWER LEVEL (dB FULL SCALE) 30 Figure 34. SNR/SFDR for IF @ 70 MHz (Clock = 40 MSPS) 80 SFDR 2 TONE 70 60 SFDR 1 TONE Rev. B | Page 18 of 28 50 40 SNR 30 20 10 0 00573-035 SNR/SFDR (dB) To maximize its distortion performance, the AD9203 should be configured in the differential mode with a 2 V span using a transformer. The center-tap of the transformer is biased to the reference output of the AD9203. Preceding the AD9203 and transformer is an optional bandpass filter as well as a gain stage. A low Q passive bandpass filter can be inserted to reduce out of band distortion and noise that lies within the AD9203’s 390 MHz bandwidth. A large gain stage(s) is often required to compensate for the high insertion losses of a SAW filter used for channel selection and image rejection. The gain stage will also provide adequate isolation for the SAW filter from the charge kick back currents associated with the AD9203’s switched capacitor input stage. 0 5 10 15 20 25 30 INPUT POWER LEVEL (dB FULL SCALE) Figure 35. SNR/SFDR for IF @ 130 MHz (Clock = 40 MSPS) 35 AD9203 ULTRASOUND APPLICATIONS The AD9203 provides excellent performance in 10-bit ultrasound applications. This is demonstrated by its high SNR with analog input frequencies up to and including Nyquist. The presence of spurs near the base of a fundamental frequency bin is demonstrated by Figure 37. Note that the spurs near the noise floor are more than 80 dB below fIN. This is especially valuable in Doppler ultrasound applications where low frequency shifts from the fundamental are important. AD9203 is powered from a 3 V supply rail while the high performance AD604 is powered from 5 V supply rails. An AD8138 is used to drive the AD9203. This is implemented due to the ability of differential drive techniques to cancel commonmode noise and input anomalies. The 74 mW power consumption gives the 40 MSPS AD9203 an order of magnitude improvement over older generation components. 10 CONDITIONED TRANSDUCER SIGNAL FUND 0 SINGLEENDED ANALOG AD604 TGC AMPLIFIER –10 3V AD9203 –20 AINP –30 AD8138 –40 AINN dB ANALOG INPUT SNR = 59.9dB THD = –75dB SFDR = 82dB GAIN CONTROL –50 –60 –70 1.5V –80 00573-036 –90 –100 Figure 36. Ultrasound Connection for the AD9203 –110 4.5E+6 Figure 36 illustrates the AD604 variable gain amplifier configured for time gain compensation (TGC). The low power 00573-037 3V 4.7E+6 4.9E+6 5.1E+6 5.3E+6 5.5E+6 fIN Figure 37. SFDR Performance Near the Fundamental Signal (8192 Point FFT, fIN = 5 MHz, FS = 40 MSPS) Rev. B | Page 19 of 28 AD9203 EVALUATION BOARD for single-ended and differential operation as well as 1 V and 2 V spans. Refer to Figure 39. The AD9203 evaluation board is shipped wired for 2 V differential operation. The board should be connected to power and test equipment as shown in Figure 38. It is easily configured 3V + DRVDD SYNTHESIZER 1MHz 1.9V p-p HP8644 ANTIALIASING FILTER 3V – – GND 3V + + +3-5D AVDD 3V – + GND AVEE J1 ANALOG INPUT AD9203 EVALUATION BOARD J5 EXTERNAL CLOCK OUTPUT WORD DSP EQUIPMENT 00573-038 SYNTHESIZER 40MHz 1V p-p HP8644 – Figure 38. Evaluation Board Connection Rev. B | Page 20 of 28 Figure 39. Evaluation Board (Rev. C) Rev. B | Page 21 of 28 1 2 00573-039 J1 R36 4.99kΩ C30 0.1µF R34 2kΩ R1 49.9Ω 2 3 A 1 B R4 49.9Ω SW8 R35 4.99Ω J4 2 1 J5 1 JP8 2 2 1 B C2 4.7µF 10V C1 0.1µF TP2 3 1 A SW7 2 AVDD 1 4 2 JP52 2 JP26 6 4 P 74LVX14 U6 TPB 1 2 74LVX14 U6 R53 49.9Ω 3 1 T1 6 1 2 3 1 1 JP65 2 2 C4 0.1µF R51 49.9Ω R54 200kΩ C6 0.1µF 1 JP3 2 C12 0.1µF C11 0.1µF 10V C9 1µF 2 1+ AVDD C5 10µF 10V C3 0.1µF TP1 1 A SW6 2 3 B C10 0.1µF JP64 R52 49.9Ω 74LVX14 U6 R2 100Ω S 5 TP12 CLK U6 8 1 1 JP54 JP53 2 2 B A R101 TBD BY USER R102 TBD BY USER R103 10Ω R104 10Ω C34 0.1µF 74LVX14 74LVX14 U6 13 12 74LVX14 U6 11 10 9 TP3 1 JP1 2 1 JP2 2 AVDD 1 JP58 2 2 C100 20pF AVDD JP63 C33 10µF 10V 1 U6 BYPASS C102 0.1µF AVDD C17 10µF 10V 20 26 25 24 23 22 21 17 19 16 15 1 U1 AVSS DFS 1 DRVSS 18 14 3 13 C18 10µF 10V D0 4 D1 5 D2 6 D3 7 D4 8 D5 9 D6 10 D7 11 D8 12 D9 OTR R55 TBD BY USER 27 C19 0.1µF JP51 REFSENSE AD9203 CLAMP IN AINN AINP REFBF REFTF VREF PWRCON CLAMP STBY 3-STATE 1 1 + 28 2 AVDD DRVDD CLK JP59 2 2 + 1 C16 0.1µF JP50 C101 20pF 2 1 2 2 D9 D8 D7 D5 D6 D4 D3 D2 D0 D1 R56 JP60 JP61 2 2 TBD BY USER 1 1 OTR DRVDD AVDD AD9203 Rev. B | Page 22 of 28 1 Figure 40. Evaluation Board (Rev. C) 00573-040 2 L1 1 R113 50Ω C7 33µF 16V L4 1 + C23 10µF 10V TP4 AGND3,4,5 1 J12 B4 1 TP20 R112 25Ω R111 1Ω DRVDD C14 0.1µF AVSS B 1 3 L2 1 B C45 0.1µF A 5 6 V– C26 10µF 10V A C13 0.1µF C24 0.1µF + C15 10µF 10V B1 1 DRVDD R108 1kΩ DRVDD AVDD + C44 10µF 10V FBEAD 2 R107 1kΩ + C25 33µF 16V TP21 U3 V+ 2 AD8131 OUT R105 TBD 1 8 R106 TBD 4 B3 AVDD C8 0.1µF AVEE C22 0.1µF FBEAD 2 FBEAD 2 + + B2 L3 1 C41 0.1µF D2 D1 D0 LSB11 LSB12 OTR CLK C40 0.1µF D9 D8 D7 D6 D5 D4 D3 + C31 10µF 10V TP29 13 22 23 24 21 14 15 16 17 18 19 20 13 23 22 24 21 14 15 16 17 18 19 20 C32 0.1µF +3-5D 74LVXC4245WM A1 B1 A2 B2 A3 B3 U5 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 VCCB VCCA T/R NC1 GD2 OE GD3 GD1 74LVXC4245WM A1 B1 A2 B2 A3 B3 U4 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 VCCB VCCA T/R NC1 GD2 OE GD3 GD1 FBEAD 2 12 11 2 1 3 10 9 8 7 6 5 4 12 11 2 1 3 10 9 8 7 6 5 4 B5 B6 1 1 RN2 7 22Ω 8 RN2 6 22Ω 9 RN2 5 22Ω 10 RN2 3 22Ω 12 RN2 4 22Ω 11 TP23 TP24 TP25 TP26 TP27 TP28 +3-5D C21 0.1µF +3-5D C20 0.1µF RN1 7 22Ω 8 RN2 1 22Ω 14 RN2 2 22Ω 13 RN1 6 22Ω 9 RN1 5 22Ω 10 RN1 4 22Ω 11 RN1 3 22Ω 12 RN1 2 22Ω 13 RN1 1 22Ω 14 P1 P1 39 P1 P1 37 35 33 P1 P1 29 31 P1 P1 25 27 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 23 21 19 17 15 13 11 9 7 5 3 1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 AD9203 00573-041 AD9203 00573-042 Figure 41. Evaluation Board Component Side Assembly (Not to Scale) 00573-043 Figure 42. Evaluation Board Component Side (Not to Scale) Figure 43. Evaluation Board Solder Side Assembly (Not to Scale) Rev. B | Page 23 of 28 00573-044 AD9203 00573-045 Figure 44. Evaluation Board Solder Side (Not to Scale) 00573-046 Figure 45. Evaluation Board Ground Plane (Not to Scale) Figure 46. Evaluation Board Power Plane (Not to Scale) Rev. B | Page 24 of 28 AD9203 OUTLINE DIMENSIONS 9.80 9.70 9.60 28 15 4.50 4.40 4.30 6.40 BSC 1 14 PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 1.20 MAX SEATING PLANE 0.20 0.09 8° 0° 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153AE Figure 47. 28-Lead Thin Shrink Small Outline Package (RU-28) Dimensions shown in inches and (millimeters) ORDERING GUIDE Model AD9203ARU AD9203ARURL7 AD9203ARUZ1 AD9203ARUZRL71 AD9203-EB 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 28-Lead Thin Shrink Small Outline 28-Lead Thin Shrink Small Outline 28-Lead Thin Shrink Small Outline 28-Lead Thin Shrink Small Outline Evaluation Board Z = Pb-free part. Rev. B | Page 25 of 28 Package Option RU-28 RU-28 RU-28 RU-28 AD9203 NOTES Rev. B | Page 26 of 28 AD9203 NOTES Rev. B | Page 27 of 28 AD9203 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C00573–0–8/04(B) Rev. B | Page 28 of 28