Octal, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter AD9212
FEATURES
Eight ADCs integrated into 1 package 100 mW ADC power per channel at 65 MSPS SNR = 60.8 dB (to Nyquist) Excellent linearity DNL = ±0.3 LSB (typical) INL = ±0.4 LSB (typical) Serial LVDS (ANSI-644, default) Low power reduced signal option, IEEE 1596.3 similar Data and frame clock outputs 325 MHz, full power analog bandwidth 2 V p-p input voltage range 1.8 V supply operation Serial port control Full-chip and individual-channel power-down modes Flexible bit orientation Built-in and custom digital test pattern generation Programmable clock and data alignment Programmable output resolution Standby mode
FUNCTIONAL BLOCK DIAGRAM
AVDD PDWN DRVDD DRGND
AD9212
VIN+A VIN–A VIN+B VIN–B VIN+C VIN–C VIN+D VIN–D VIN+E VIN–E VIN+F VIN–F VIN+G VIN–G VIN+H VIN–H VREF SENSE 0.5V REFT REFB REF SELECT SERIAL PORT INTERFACE ADC
12 SERIAL LVDS 12 ADC 12 ADC 12 ADC 12 ADC 12 ADC 12 ADC 12 ADC SERIAL LVDS SERIAL LVDS SERIAL LVDS SERIAL LVDS SERIAL LVDS SERIAL LVDS SERIAL LVDS
D+A D–A D+B D–B D+C D–C D+D D–D D+E D–E D+F D–F D+G D–G D+H D–H
APPLICATIONS
Medical imaging and nondestructive ultrasound Portable ultrasound and digital beam forming systems Quadrature radio receivers Diversity radio receivers Tape drives Optical networking Test equipment
FCO+ DATA RATE MULTIPLIER FCO– DCO+ DCO–
05968-001
RBIAS
AGND CSB
SDIO/ ODM
SCLK/ DTP
CLK+
CLK–
Figure 1.
GENERAL DESCRIPTION
The AD9212 is an octal, 10-bit, 40/65 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit that is designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 65 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO) for capturing data on the output and a frame clock (FCO) for signaling a new output byte are provided. Individual channel power-down is supported and typically consumes less than 2 mW when all channels are disabled.
Rev. 0
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The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom userdefined test patterns entered via the serial port interface (SPI®). The AD9212 is available in a Pb-free, 64-lead LFCSP package. It is specified over the industrial temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1. 2. 3. 4. Small Footprint. Eight ADCs are contained in a small, spacesaving package; low power of 100 mW/channel at 65 MSPS. Ease of Use. A data clock output (DCO) operates up to 300 MHz and supports double data rate operation (DDR). User Flexibility. Serial port interface (SPI) control offers a wide range of flexible features to meet specific system requirements. Pin-Compatible Family. This includes the AD9222 (12-bit), and AD9252 (14-bit).
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
AD9212 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 AC Specifications.......................................................................... 4 Digital Specifications ................................................................... 5 Switching Specifications .............................................................. 6 Timing Diagrams .............................................................................. 7 Absolute Maximum Ratings............................................................ 9 Thermal Impedance ..................................................................... 9 ESD Caution .................................................................................. 9 Pin Configuration and Function Descriptions ........................... 10 Equivalent Circuits ......................................................................... 12 Typical Performance Characteristics ........................................... 14 Theory of Operation ...................................................................... 19 Analog Input Considerations ................................................... 19 Clock Input Considerations ...................................................... 22 Serial Port Interface (SPI) .............................................................. 30 Hardware Interface..................................................................... 30 Memory Map .................................................................................. 32 Reading the Memory Map Table .............................................. 32 Reserved Locations .................................................................... 32 Default Values ............................................................................. 32 Logic Levels ................................................................................. 32 Evaluation Board ............................................................................ 36 Power Supplies ............................................................................ 36 Input Signals................................................................................ 36 Output Signals ............................................................................ 36 Default Operation and Jumper Selection Settings ................. 37 Alternative Analog Input Drive Configuration...................... 38 Outline Dimensions ....................................................................... 55 Ordering Guide .......................................................................... 55
REVISION HISTORY
10/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 56
AD9212 SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 1.
Parameter 1 RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error Reference Voltage (1 V Mode) REFERENCE Output Voltage Error (VREF = 1 V) Load Regulation @ 1.0 mA (VREF = 1 V) Input Resistance ANALOG INPUTS Differential Input Voltage Range (VREF = 1 V) Common-Mode Voltage Differential Input Capacitance Analog Bandwidth, Full Power POWER SUPPLY AVDD DRVDD IAVDD IDRVDD Total Power Dissipation (Including Output Drivers) Power-Down Dissipation Standby Dissipation 2 CROSSTALK CROSSTALK (Overrange Condition) 3
1 2
Temperature
Min 10
AD9212-40 Typ Max
Min 10
AD9212-65 Typ Max
Unit Bits
Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 1.7 1.7
Guaranteed ±1.5 ±3 ±0.4 ±0.3 ±0.1 ±0.15 ±2 ±17 ±21 ±2 3 6 2 AVDD/2 7 325 1.8 1.8 252 49.5 542 3 83 −90 −90
±8 ±8 ±1.2 ±0.7 ±0.4 ±0.5
Guaranteed ±1.5 ±3 ±3.2 ±0.4 ±0.3 ±0.4 ±2 ±17 ±21
±8 ±8 ±4.3 ±0.9 ±0.65 ±1
mV mV % FS % FS LSB LSB ppm/°C ppm/°C ppm/°C
±30
±2 3 6 2 AVDD/2 7 325
±30
mV mV kΩ V p-p V pF MHz
1.9 1.9 260 53 560 11
1.7 1.7
1.8 1.8 390 54 800 3 95 −90 −90
1.9 1.9 405 58 833 11
V V mA mA mW mW mW dB dB
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. Can be controlled via SPI. 3 Overrange condition is specific with 6 dB of the full-scale input range.
Rev. 0 | Page 3 of 56
AD9212
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 2.
Parameter 1 SIGNAL-TO-NOISE RATIO (SNR) Temperature Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 25°C Full Full Full Full 25°C Full Full Full Full Full 25°C 25°C AD9212-40 Min Typ Max 61.2 60.2 61.2 61.2 61.0 61.2 60.0 61.0 61.0 60.8 9.87 9.71 9.87 9.87 9.84 87 72 85 79 74 −87 −85 −79 −74 −90 −85 −85 −85 80.0 77.0 AD9212-65 Min Typ Max 60.8 60.8 58.5 60.8 60.7 60.7 60.6 57.0 60.5 60.4 9.81 9.81 9.43 9.81 9.79 81 79 62 77 69 77 72 −81 −79 −77 −62 −77 −69 −72 −86 −86 −85 −70 −85 77.0 77.0 Unit dB dB dB dB dB dB dB dB Bits Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)
EFFECTIVE NUMBER OF BITS (ENOB)
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
WORST HARMONIC (Second or Third)
WORST OTHER (Excluding Second or Third)
TWO-TONE INTERMODULATION DISTORTION (IMD)— AIN1 AND AIN2 = −7.0 dBFS
fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 35 MHz fIN = 70 MHz fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 35 MHz fIN = 70 MHz fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz fIN1 = 15 MHz, fIN2 = 16 MHz fIN1 = 70 MHz, fIN2 = 71 MHz
−72
−72
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
Rev. 0 | Page 4 of 56
AD9212
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 3.
Parameter 1 CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage 2 Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC INPUTS (PDWN, SCLK/DTP) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (CSB) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (SDIO/ODM) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC OUTPUT (SDIO/ODM) Logic 1 Voltage (IOH = 50 μA) Logic 0 Voltage (IOL = 50 μA) DIGITAL OUTPUTS (D+, D−), (ANSI-644) Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) DIGITAL OUTPUTS (D+, D−), (Low Power, Reduced Signal Option) Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default)
1 2
Temperature
Min
AD9212-40 Typ Max CMOS/LVDS/LVPECL
Min
AD9212-65 Typ Max CMOS/LVDS/LVPECL
Unit
Full Full 25°C 25°C Full Full 25°C 25°C Full Full 25°C 25°C Full Full 25°C 25°C Full Full
250 1.2 20 1.5 1.2 0 30 0.5 1.2 0 70 0.5 1.2 0 30 2 1.79 0.05 LVDS DRVDD + 0.3 0.3 3.6 0.3 3.6 0.3
250 1.2 20 1.5 1.2 30 0.5 1.2 70 0.5 1.2 0 30 2 1.79 0.05 LVDS 247 1.125 454 1.375 Offset binary DRVDD + 0.3 0.3 3.6 0.3 3.6 0.3
mV p-p V kΩ pF V V kΩ pF V V kΩ pF V V kΩ pF V V
Full Full
247 1.125
454 1.375 Offset binary
mV V
LVDS Full Full 150 1.10 250 1.30 Offset binary 150 1.10
LVDS 250 1.30 Offset binary mV V
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. This is specified for LVDS and LVPECL only.
Rev. 0 | Page 5 of 56
AD9212
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 4.
AD9212-40 Parameter 1 CLOCK 2 Maximum Clock Rate Minimum Clock Rate Clock Pulse Width High (tEH) Clock Pulse Width Low (tEL) OUTPUT PARAMETERS2, 3 Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) FCO Propagation Delay (tFCO) DCO Propagation Delay (tCPD) 4 DCO to Data Delay (tDATA)4 DCO to FCO Delay (tFRAME)4 Data to Data Skew (tDATA-MAX − tDATA-MIN) Wake-Up Time (Standby) Wake-Up Time (Power-Down) Pipeline Latency APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter) Out-of-Range Recovery Time Temp Full Full Full Full Full Full Full Full Full Full Full Full 25°C 25°C Full Min 40 10 12.5 12.5 1.5 2.3 300 300 2.3 tFCO + (tSAMPLE/20) (tSAMPLE/20) (tSAMPLE/20) ±50 600 375 8 3.1 1.5 7.7 7.7 2.3 300 300 2.3 tFCO + (tSAMPLE/20) (tSAMPLE/20) (tSAMPLE/20) ±50 600 375 8 3.1 Typ Max Min 65 10 AD9212-65 Typ Max Unit MSPS MSPS ns ns ns ps ps ns ns ps ps ps ns μs CLK cycles ps ps rms CLK cycles
1.5
3.1
1.5
3.1
(tSAMPLE/20) − 300 (tSAMPLE/20) − 300
(tSAMPLE/20) + 300 (tSAMPLE/20) + 300 ±200
(tSAMPLE/20) − 300 (tSAMPLE/20) − 300
(tSAMPLE/20) + 300 (tSAMPLE/20) + 300 ±200
25°C 25°C 25°C
750
