Data Sheet
AD9214
10-Bit, 65 MSPS/80 MSPS/105 MSPS 3 V Analog-to-Digital Converter
FEATURES
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FUNCTIONAL BLOCK DIAGRAM
SNR = 57 dB at 39 MHz Analog input (–0.5 dBFS)
Low power
► 190 mW at 65 MSPS
► 285 mW at 105 MSPS
30 mW power-down mode
300 MHz analog bandwidth
On-chip reference and track/hold
1 V p-p or 2 V p-p Analog input range option
Single 3.3 V supply operation (2.7 V to 3.6 V)
Twos complement or offset binary data format option
Figure 1.
APPLICATIONS
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Battery-powered instruments
Hand-held scopemeters
Low-cost digital oscilloscopes
Ultrasound equipment
Cable reverse path
Broadband wireless
Residential power line networks
GENERAL DESCRIPTION
The AD9214 is a 10-bit monolithic sampling analog-to-digital converter (ADC) with an on-chip track-and-hold circuit, and is optimized
for low cost, low power, small size, and ease of use. The product
operates up to 105 MSPS conversion rate with outstanding dynamic performance over its full operating range.
The ADC requires only a single 3.3 V (2.7 V to 3.6 V) power supply
and an encode clock for full performance operation. No external
reference or driver components are required for many applications.
The digital outputs are TTL/CMOS compatible and a separate
output power supply pin supports interfacing with 3.3 V or 2.5 V
logic.
The clock input is TTL/CMOS compatible. In the power-down state,
the power is reduced to 30 mW. A gain option allows support for
either 1 V p-p or 2 V p-p analog signal input swing.
Fabricated on an advanced CMOS process, the AD9214 is available in a 28-lead surface-mount plastic package (28-SSOP) specified over the industrial temperature range −40°C to +85°C).
PRODUCT HIGHLIGHTS
1. High Performance.
Outstanding ac performance from 65 MSPS to 105 MSPS. SNR
greater than 55 dB typical and as high as 58 dB.
2. Low Power.
The AD9214 at 285 mW consumes a fraction of the power
available in existing high-speed monolithic solutions. In sleep
mode, power is reduced to 30 mW.
3. Single Supply.
The AD9214 uses a single 3 V supply, simplifying system power
supply design. It also features a separate digital output driver
supply line to accommodate 2.5 V logic families.
4. Small Package.
The AD9214 is packaged in a small 28-lead surface-mount
plastic package (28-SSOP).
Rev. E
DOCUMENT FEEDBACK
TECHNICAL SUPPORT
Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to
change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Data Sheet
AD9214
TABLE OF CONTENTS
Features................................................................ 1
Applications........................................................... 1
Functional Block Diagram......................................1
General Description...............................................1
Product Highlights................................................. 1
Specifications........................................................ 3
DC Specifications............................................... 3
Digital Specifications.......................................... 4
AC Specifications............................................... 4
Switching Specifications.....................................5
Absolute Maximum Ratings...................................7
Explanation of Test Levels..................................7
ESD Caution.......................................................7
Pin Configuration and Function Descriptions........ 8
Typical Performance Characteristics..................... 9
Equivalent Circuits...............................................12
Terminology......................................................... 13
Theory of Operation.............................................15
Applying the AD9214........................................15
Power Supplies................................................ 16
Layout Information............................................16
Evaluation Board.............................................. 16
Schematic............................................................18
Outline Dimensions............................................. 21
Ordering Guide.................................................21
REVISION HISTORY
4/2022—Rev. D to Rev. E
Updated Format (Universal).............................................................................................................................1
Changes to Figure 29.................................................................................................................................... 15
Changes to Ordering Guide........................................................................................................................... 21
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Rev. E | 2 of 21
Data Sheet
AD9214
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 3 V, DrVDD = 3 V; TMIN = –40°C, TMAX = +85°C; external 1.25 V voltage reference and rated encode frequency used, unless otherwise
noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error1
Differential Nonlinearity2
(DNL)
Integral Nonlinearity2
(INL)
TEMPERATURE DRIFT
Offset Error
Gain Error1
Reference Voltage
REFERENCE (REF)
Internal Reference Voltage
Output Current3
Input Current4
Input Resistance
ANALOG INPUTS (AIN, AIN)
Differential Input Range
Common-Mode Voltage
Differential Input Resistance5
Differential Input Capacitance
POWER SUPPLY
Supply Voltages
AVDD
DrVDD
Supply Current
IAVDD (AVDD = 3.0 V)6
Power-Down Current7
IAVDD (AVDD = 3.0 V)
Power Consumption8
PSRR
Temp
Test
Level
AD9214-65
Min
Typ
AD9214-80
Max
Min
10
Guaranteed
Full
Full
Full
V
V
V
25°C
Full
Full
Full
VI
V
V
V
Full
Full
Full
Full
V
V
V
V
Full
Full
IV
IV
Full
VI
64
75
90
105
Full
Full
25°C
Full
VI
VI
I
V
10
190
±0.5
±2
15
220
10
250
±1
±2
15
300
±0.5
±0.75
−18
−2
−1.0
−1.0
−1.5
−1.8
16
150
80
1.18
1.23
200
123
10
1.18
1 or 2
AVDD/3
20
5
2.7
2.7
±0.5
±0.75
+18
+8
+1.2
+1.4
+1.5
+1.8
−18
−2
−1.0
−2.2
−2.5
16
150
80
1.28
1.23
200
123
10
2.7
2.7
1.28
Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.25 V external reference).
Measured with 1 V AIN range for AD9214-80 and AD9214-105. Measured with 2 V AIN range for AD9214-65.
3
REFSENSE externally connected to AGND, REF is configured as an output for the internal reference voltage.
4
REFSENSE externally connected to AVDD, REF is configured as an input for the external reference voltage.
5
I0 kΩ to AVDD/3 on each input.
±0.08
±1.5
1.18
1.23
200
123
10
2.7
2.7
Unit
Bits
+18
+8
+1.5
+1.7
+2.2
+2.5
LSB
%FS
LSB
LSB
LSB
LSB
ppm/°C
ppm/°C
ppm/°C
1.28
V
µA
µA
kΩ
V p-p
V
kΩ
pF
AVDD/3
20
5
3.6
3.6
2
0
Max
16
150
80
AVDD/3
20
5
3.6
3.6
Typ
Guaranteed
Guaranteed
VI
VI
VI
I
I
V
I
V
+18
+8
+1.0
+1.2
+1.35
+1.9
Min
10
1
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Max
10
25°C
Full
Full
25°C
25°C
Full
25°C
Full
−18
−2
−1.0
−1.0
−1.35
−1.9
Guaranteed
Guaranteed
0
Typ
AD9214-105
3.6
3.6
V
V
95
110
mA
10
285
±1
±2
15
325
mA
mW
LSB/V
mV/V
Rev. E | 3 of 21
Data Sheet
AD9214
SPECIFICATIONS
Table 1.
Parameter
6
Temp
AD9214-65
Test
Level
Min
Typ
AD9214-80
Max
Min
Typ
AD9214-105
Max
Min
Typ
Max
Unit
IAVDD is measured with an analog input of 10.3 MHz, 0.5 dBFS, sine wave, rated encode rate, and PWRDN = 0. See the Typical Performance Characteristics section and
Applying the AD9214 section for IDrVDD.
7
Power-down supply currents measured with PWRDN = 1; rated encode rate, AIN = full-scale dc input.
8
Power consumption measured with AIN = full-scale dc input.
DIGITAL SPECIFICATIONS
AVDD = 3 V, DrVDD = 3 V; TMIN = –40°C, TMAX = +85°C.
Table 2.
AD9214-65
Parameter
Temp
Test Level
Min
Logic “1” Voltage
Logic “0” Voltage
Input Capacitance
DIGITAL OUTPUTS2
Logic Compatibility
Full
Full
Full
IV
IV
V
2.0
Logic “1” Voltage
Full
VI
Logic “0” Voltage
Full
VI
Typ
AD9214-80
Max
Min
Typ
AD9214-105
Max
Min
Typ
Max
Unit
0.8
V
V
pF
DIGITAL INPUTS1
1
Digital Inputs include ENCODE and PWRDN.
2
Digital Outputs include D0–D9 and OR.
2.0
2.0
0.8
0.8
2.0
2.0
2.0
CMOS/T
TL
CMOS/T
TL
CMOS/T
TL
DrVDD –
50 mV
DrVDD –
50 mV
V
DrVDD –
50 mV
50
V
50
50
mV
AC SPECIFICATIONS
AC specifications based on a 1.0 V p-p full-scale input range for the AD9214-80 and AD9214-105, and a 2.0 V p-p full-scale input range for
the AD9214-65. An external reference is used. AVDD = 3 V, DrVDD = 3 V; ENCODE = maximum conversion rate; TMIN = –40°C, TMAX = +85°C;
external 1.25 V voltage reference used, unless otherwise noted.
Table 3.
Parameter
SNR
Analog Input @ –0.5 dBFS
10 MHz
39 MHz
51 MHz
70 MHz
SINAD
Analog Input @ –0.5 dBFS
10 MHz
39 MHz
51 MHz
70 MHz
EFFECTIVE NUMBER OF BITS
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Temp
Test
Level
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
AD9214-65
Min
Typ
I
I
V
V
55.5
I
I
V
V
55.0
AD9214-80
Max
Min
Typ
58.3
57.1
56.0
55.0
57.8
56.7
55.5
54.5
AD9214-105
Max
Min
Typ
Max
Unit
58.1
57.1
55.0
54.0
51.0
50.5
53.0
53.0
53.0
52.6
dB
dB
dB
dB
57.6
56.7
54.5
50.0
50.0
52.0
52.0
52.0
52.0
dB
dB
dB
dB
Rev. E | 4 of 21
Data Sheet
AD9214
SPECIFICATIONS
Table 3.
Parameter
Analog Input @ –0.5 dBFS
10 MHz
39 MHz
51 MHz
70 MHz
SECOND HARMONIC DISTORTION
Analog Input @ –0.5 dBFS
10 MHz
39 MHz
51 MHz
70 MHz
THIRD HARMONIC DISTORTION
Analog Input @ –0.5 dBFS
10 MHz
39 MHz
51 MHz
70 MHz
SFDR
Analog Input @ –0.5 dBFS
10 MHz
39 MHz
51 MHz
70 MHz
TWO-TONE INTERMOD DISTORTION1
Analog Input @ –0.5 dBFS
ANALOG INPUT BANDWIDTH
1
Temp
Test
Level
25°C
25°C
25°C
25°C
AD9214-65
Min
Typ
I
I
V
V
8.9
25°C
25°C
25°C
25°C
I
I
V
V
25°C
25°C
25°C
25°C
AD9214-80
Max
Min
Typ
9.3
9.2
9.0
8.8
9.3
9.2
8.8
8.5
–66
–79
–75
–64
–63
–74
–76
–72
–65
I
I
V
V
–63.5
–71
–70
–63
–63
25°C
25°C
25°C
25°C
I
I
V
V
63.5
71
70
63
63
25°C
V
76
25°C
V
300
AD9214-105
Max
Min
Typ
Max
Unit
8.4
8.4
8.4
8.4
Bit
Bit
Bit
Bit
–62
–62
–68
–71
–64
–62
dBc
dBc
dBc
dBc
–72
–74
–78
–59
–59
–64
–67
–71
–65
dBc
dBc
dBc
dBc
71
71
67
64
57
57
62
62
62
62
dBc
dBc
dBc
dBc
74
72
dBFS
300
300
MHz
F1 = 29.3 MHz, F2 = 30.3 MHz.
SWITCHING SPECIFICATIONS
AVDD = 3 V, DrVDD = 3 V; ENCODE = maximum conversion rate; TMIN = –40°C, TMAX = +85°C; external 1.25 V voltage reference used, unless
otherwise noted.
Table 4.
Parameter
Temp
Test
Level
ENCODE INPUT PARAMETERS1
Maximum Conversion Rate
Minimum Conversion Rate
Encode Pulse Width High (tEH)
Encode Pulse Width Low (tEL)
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
Full
Full
Full
Full
25°C
25°C
VI
IV
IV
IV
V
V
DATA OUTPUT PARAMETERS
Pipeline Delays
Full
IV
Full
V
Output Valid Time (tV)1
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AD9214-65
Min
Typ
Max
65
AD9214-80
Min
Typ
80
Min
Typ
20
5.0
5.0
20
3.8
3.8
2.0
3
2.0
3
2.0
3
5
5
5
4.5
3.0
Max
105
20
6.0
6.0
3.0
Max
AD9214-105
4.5
3.0
4.5
Unit
MSPS
MSPS
ns
ns
ns
ps rms
Clock
Cycle
ns
Rev. E | 5 of 21
Data Sheet
AD9214
SPECIFICATIONS
Table 4.
Parameter
Output Propagation Delay1 (tPD)
TRANSIENT RESPONSE TIME
OUT-OF-RANGE RECOVERY TIME
1
Temp
Test
Level
Full
25°C
25°C
V
V
V
AD9214-65
Min
Typ
Max
4.5
5
5
6.0
AD9214-80
Min
Typ
Max
4.5
5
5
6.0
AD9214-105
Min
Typ
Max
Unit
4.5
5
5
6.0
ns
ns
ns
tV and tPD are measured from the 1.5 V level of the ENCODE input to the 50% levels of the digital output swing. The digital output load during test is not to exceed an ac
load of 5 pF or a dc current of ±40 µA.
Figure 2. Timing Diagram
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Rev. E | 6 of 21
Data Sheet
AD9214
ABSOLUTE MAXIMUM RATINGS
EXPLANATION OF TEST LEVELS
Table 5.
Parameter
Electrical
AVDD Voltage
DrVDD Voltage
Analog Input Voltage
Analog Input Current
Digital Input Voltage
Digital Output Current
REF Input Voltage
Environmental1
Operating Temperature Range (Ambient)
Maximum Junction Temperature
Lead Temperature (Soldering, 10 sec)
Storage Temperature Range (Ambient)
1
Rating
4 V max
4 V max
−0.5 V to AVDD + 0.5 V
0.4 mA
−0.5 V to AVDD + 0.5 V
20 mA max
−0.5 V to AVDD + 0.5 V
−40°C to +125°C
150°C
150°C
−65°C to +150°C
Typical thermal impedances (package = 28 SSOP); θJA = 49°C/W. These
measurements were taken on a six-layer board in still air with a solid ground
plane.
Table 6.
Level
Description
I
II
100% production tested.
100% production tested at 25°C and guaranteed by design and
characterization at specified temperatures.
Sample tested only.
Parameter is guaranteed by design and characterization testing.
Parameter is a typical value only.
100% production tested at 25°C and guaranteed by design and
characterization for industrial temperature range.
III
IV
V
VI
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although
this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.
Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
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Rev. E | 7 of 21
Data Sheet
AD9214
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
OR
2
DFS/GAIN
3
REFSENSE
4
REF
5, 8, 11
6, 7, 12
9
10
AGND
AVDD
AIN
AIN
13
14
ENCODE
PWRDN
15, 23
16, 24
17 to 22, 25
to 28
DGND
DrVDD
D0 (LSB) to D5,
D6 to D9 (MSB)
CMOS Output; Out-of-Range Indicator. Logic HIGH indicates the analog input voltage was outside the converter’s range for the current
output data.
Data Format Select and Gain Mode Select. Connect externally to AVDD for twos complement data format and 1 V p-p analog input range.
Connect externally to AGND for Offset Binary data format and 1 V p-p analog input range. Connect externally to REF (Pin 4) for twos
complement data format and 2 V p-p analog input range. Floating this pin will configure the device for Offset Binary data format and a 2 V
p-p analog input range.
Reference Mode Select Pin for the ADC. This pin is normally connected externally to AGND, which enables the internal 1.25 V reference,
and configures REF (Pin 4) as an analog reference output pin. Connecting REFSENSE externally to AVDD disables the internal reference,
and configures REF (Pin 4) as an external reference input. In this case, the user must drive REF with a clean and accurate 1.25 V (± 5%)
reference input.
Reference input or output as configured by REFSENSE (Pin 3). When configured as an output (REFSENSE = AGND), the internal
reference (nominally 1.25 V) is enabled and is available to the user on this pin. When configured as an input (REFSENSE = AVDD), the
user must drive REF with a clean and accurate 1.25 V (± 5%) reference. This pin should be bypassed to AGND with an external 0.1 µF
capacitor, whether it is configured as an input or output.
Analog Ground.
Analog Power Supply, Nominally 3 V.
Positive terminal of the differential analog input for the ADC.
Negative terminal of the differential analog input for the ADC. This pin can be left open if operating in single-ended mode, but it is preferable
to match the impedance seen at the positive terminal (see Driving the Analog Inputs).
Encode Clock for the ADC. The AD9214 samples the analog signal on the rising edge of ENCODE.
CMOS-compatible power-down mode select, Logic LOW for normal operation; Logic HIGH for power-down mode (digital outputs in high
impedance state). PWRDN has an internal 10 kΩ pull-down resistor to ground.
Digital Output Ground.
Digital Output Driver Power Supply. Nominally 2.5 V to 3.6 V.
CMOS Digital Outputs of ADC.
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Rev. E | 8 of 21
Data Sheet
AD9214
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4. FFT: fS = 105 MSPS, fIN = ~50.3 MHz; AIN = –0.5 dBFS Differential, 1
V p-p Analog Input Range
Figure 5. FFT: fS = 80 MSPS, fIN = 70 MHz; AIN = –0.5 dBFS, 1 V p-p Analog
Input Range
Figure 6. FFT: fS = 105 MSPS; fIN = 70 MHz (1 V p-p)
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Figure 7. FFT: fS = 65 MSPS, fIN = 15.3 MHz (2 V p-p) with AD8138 Driving AIN
Figure 8. Harmonic Distortion (Second and Third) and SFDR vs. AIN
Frequency (1 V p-p, fS = 105 MSPS)
Figure 9. Harmonic Distortion (Second and Third) and SFDR vs. AIN
Frequency (1 V p-p, fS = 80 MSPS)
Rev. E | 9 of 21
Data Sheet
AD9214
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 10. Harmonic Distortion (Second and Third) and SFDR vs. AIN
Frequency (1 V p-p and 2 V p-p, fS = 65 MSPS)
Figure 13. SINAD and SFDR vs. Encode Rate (fIN = 10.3 MHz; 1 V p-p and 2 V
p-p)
Figure 11. Two-Tone Intermodulation Distortion (29.3 MHz, 30.3 MHz; 1 V p-p,
fS = 80 MSPS)
Figure 14. SINAD and SFDR vs. Encode Pulse Width High (1 V p-p)
Figure 12. Two-Tone Intermodulation Distortion (30 MHz and 31 MHz; 1 V p-p,
fS = 105 MSPS)
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Figure 15. IAVDD and IDrVDD vs. Encode Rate (fAIN = 10.3 MHz, –0.5 dBFS, and
–3 dBFS) CLOAD on Digital Outputs ~7 pF
Rev. E | 10 of 21
Data Sheet
AD9214
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 16. SINAD/SNR vs. Temperature (fAIN = 10.3 MHz, fENCODE = 105 MSPS,
1 V p-p)
Figure 19. ADC Reference vs. Current Load
Figure 20. INL @ 80 MSPS
Figure 17. ADC Gain vs. Temperature (with External 1.25 V Reference)
Figure 21. DNL @ 80 MSPS
Figure 18. ADC Reference vs. Temperature (with 200 µA Load)
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Rev. E | 11 of 21
Data Sheet
AD9214
EQUIVALENT CIRCUITS
Figure 22. Analog Input Stage
Figure 26. REF Configured as an Input
Figure 23. Encode Inputs
Figure 24. Digital Output Stage
Figure 25. REF Configured as an Output
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Rev. E | 12 of 21
Data Sheet
AD9214
TERMINOLOGY
Analog Bandwidth
Gain Error
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Gain error is the difference between the measured and ideal full
scale input voltage range of the ADC.
Aperture Delay
The delay between the 50% point of the rising edge of the ENCODE command and the instant at which the analog input is
sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Analog Input Resistance,
Differential Analog Input Capacitance, and
Differential Analog Input Impedance
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the second
harmonic component, reported in dBc.
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the third
harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a “best straight line” determined by
a least square curve fit.
The real and complex impedances measured at each analog input
port. The resistance is measured statically and the capacitance
and differential input impedances are measured with a network
analyzer.
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Differential Analog Input Voltage Range
Maximum Conversion Rate
The peak-to-peak differential voltage that must be applied to the
converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 degrees out of
phase. Peak-to-peak differential is computed by rotating the inputs
phase 180 degrees and taking the peak measurement again. Then
the difference is computed between both peak measurements.
The encode rate at which parametric testing is performed.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Effective Number of Bits
The effective number of bits (ENOB) is calculated
from the measured SNR based on the equation:
ENOB =
SINADMEASURED − 1.76 dB + 20 log Full Scale
Actual
6 . 02
Minimum Conversion Rate
Output Propagation Delay
The delay between a differential crossing of ENCODE and ENCODE and the time when all output data bits are within valid logic
levels.
Noise (for any range within the ADC):
VNOISE = Z × 0 . 001 × 10
FSdBm − SNRdBc − SignaldBFS
10
where:
Z is the input impedance.
FS is the full-scale of the device for the frequency in question.
SNR is the value for the particular input level.
Signal is the signal level within the ADC reported in dB below
full-scale. This value includes both thermal and quantization noise.
Encode Pulse Width/Duty Cycle
Power Supply Rejection Ratio (PSRR)
Pulse width high is the minimum amount of time that the ENCODE
pulse should be left in Logic "1" state to achieve rated performance;
pulse width low is the minimum time ENCODE pulse should be left
in low state. See timing implications of changing tENCH in text. At
a given clock rate, these specs define an acceptable Encode duty
cycle.
The ratio of a change in input offset voltage to a change in power
supply voltage.
Full-Scale Input Power
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set 0.5 dB below full scale) to
the rms value of the sum of all other spectral components, including
harmonics but excluding dc.
Expressed in dBm. Computed using the following equation:
PowerFULLSCALE = 10 log
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V2FULLSCALE rms
ZINPUT
0 . 001
Rev. E | 13 of 21
Data Sheet
AD9214
TERMINOLOGY
Signal-to-Noise Ratio (without Harmonics)
The ratio of the rms signal amplitude (set at 0.5 dB below full
scale) to the rms value of the sum of all other spectral components,
excluding the first five harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious component
may or may not be a harmonic. May be reported in dBc (that is,
degrades as signal level is lowered), or dBFS (always related back
to converter full scale).
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value of
the worst third order intermodulation product; reported in dBc.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an intermodulation distortion product. May be
reported in dBc (that is, degrades as signal level is lowered), or in
dBFS (always related back to converter full scale).
Worst Other Spur
The ratio of the rms signal amplitude to the rms value of the worst
spurious component (excluding the second and third harmonic)
reported in dBc.
Transient Response Time
Transient response is defined as the time it takes for the ADC
to reacquire the analog input after a transient from 10% above
negative full scale to 10% below positive full scale.
Out-of-Range Recovery Time
Out-of-range recovery time is the time it takes for the ADC to
reacquire the analog input after a transient from 10% above positive
full scale to 10% above negative full scale, or from 10% below
negative full scale to 10% below positive full scale.
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Rev. E | 14 of 21
Data Sheet
AD9214
THEORY OF OPERATION
The AD9214 architecture is a bit-per-stage pipeline converter utilizing switch capacitor techniques. These stages determine the 7
MSBs and drive a 3-bit flash. Each stage provides sufficient overlap
and error correction allowing optimization of comparator accuracy.
The input buffer is differential and both inputs are internally biased.
This allows the most flexible use of ac or dc and differential or
single-ended input modes. The output staging block aligns the data,
carries out the error correction and feeds the data to output buffers.
The output buffers are powered from a separate supply, allowing
support of different logic families. During power-down, the outputs
go to a high impedance state.
DFS/GAIN
The DFS/GAIN (Data Format Select/Gain) input (Pin 2) controls
both the output data format and gain (analog input voltage range) of
the ADC. The table below describes its operation.
Table 8. Data Format and Gain Configuration
External DFS/GAIN
Connection
Differential Analog Input
Voltage Range
Output Data Format
APPLYING THE AD9214
AGND
AVDD
REF
Floating
1 V p-p
1 V p-p
2 V p-p
2 V p-p
Offset Binary
Twos Complement
Twos Complement
Offset Binary
Encoding the AD9214
Driving the Analog Inputs
Any high-speed A/D converter is extremely sensitive to the quality
of the sampling clock provided by the user. A Track/ Hold circuit
is essentially a mixer. Any noise, distortion, or timing jitter on the
clock will be combined with the desired signal at the A/D output.
For that reason, considerable care has been taken in the design of
the ENCODE input of the AD9214, and the user is advised to give
commensurate thought to the clock source. The ENCODE input is
fully TTL/CMOS compatible, and should normally be driven directly
from a low jitter, crystal-controlled TTL/CMOS oscillator.
The analog input to the AD9214 is a differential buffer. As shown in
the equivalent circuits, each of the differential inputs is internally dc
biased at ~AVDD/3 to allow ac-coupling of the analog input signal.
The analog signal may be dc-coupled as well. In this case, the
dc load will be equivalent to ~10 kΩ to AVDD/3, and the dc commonmode level of the analog signals should be within the range of
AVDD/3 ±200 mV. For best dynamic performance, impedances at
AIN and AIN should match.
The ENCODE input is internally biased, allowing the user to ac-couple in the clock signal. The cleanest clock source is often a crystal
oscillator producing a pure sine wave. Figure 27 illustrates ac
coupling such a source to the ENCODE input.
Driving the analog input differentially optimizes ac performance,
minimizing even order harmonics and taking advantage of common-mode rejection of noise. A differential signal may be transformer-coupled, as illustrated in Figure 28, or driven from a high-performance differential amplifier such as the AD8138 illustrated in
Figure 29.
Figure 27. AC-Coupled Encode Circuit
Reference Circuit
The reference circuit of the AD9214 is configured by REFSENSE
(Pin 3). By externally connecting REFSENSE to AGND, the ADC
is configured to use the internal reference (~1.25 V), and the REF
pin connection (Pin 4) is configured as an output for the internal
reference voltage.
Figure 28. Single-Ended-to-Differential Conversion Using a Transformer
Special care was taken in the design of the analog input section
of the AD9214 to prevent damage and corruption of data when the
input is overdriven. The optimal input range is 1.0 V p-p, but the
AD9214 can support a 2.0 V p-p input range with some degradation
in performance (see Table 8).
If REFSENSE is externally connected to AVDD, the ADC is configured to use an external reference. In this mode, the REF pin is
configured as a reference input, and must be driven by an external
1.25 V reference.
In either configuration, the analog input voltage range (either 1
V p-p or 2 V p-p as determined by DFS/Gain) will track the
reference voltage linearly, and an external bypass capacitor should
be connected between REF and AGND to reduce noise on the
reference. In practice, no appreciable degradation in performance
occurs when an external reference is adjusted ±5%.
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Figure 29. DC-Coupled Analog Input Circuit
Rev. E | 15 of 21
Data Sheet
AD9214
THEORY OF OPERATION
POWER SUPPLIES
LAYOUT INFORMATION
The AD9214 has two power supplies, AVDD and DrVDD. AVDD and
AGND supply power to all the analog circuitry, the inputs and the
internal timing and digital error correction circuits. AVDD supply
current will vary slightly with encode rate, as noted in the Typical
Performance Characteristics section.
The schematic of the evaluation board (Figure 30) represents a
typical implementation of the AD9214. A multilayer board is recommended to achieve best results. It is highly recommended that high
quality, ceramic chip capacitors be used to decouple each supply
pin to ground directly at the device. The pinout of the AD9214
facilitates ease of use in the implementation of high frequency,
high resolution design practices. All of the digital outputs and their
supply and ground pin connections are segregated to one side
of the package, with the inputs on the opposite side for isolation
purposes.
DrVDD and DGND supply only the CMOS digital outputs, allowing
the user to adjust the voltage level to match downstream logic.
DrVDD current will vary depending on the voltage level, external
loading capacitance, and the encode frequency. Designs that minimize external load capacitance will reduce power consumption
and reduce supply noise that may affect ADC performance. The
maximum DrVDD current can be calculated as
IDrVDD = VDrVDD × CLOAD × fencode × N
where N is the number of output bits, 10 in the case of the AD9214.
This maximum current is for the condition of every output bit
switching on every clock cycle, which can only occur for a full-scale
square wave at the Nyquist frequency, fENCODE /2. In practice,
IDrVDD will be the average number of output bits switching, which
will be determined by the encode rate and the characteristics of
the analog input signal. The performance curves section provides
a reference of IDrVDD versus encode rate for a 10.3 MHz sine wave
driving the analog input.
Both power supply connections should be decoupled to ground at
or near the package connections, using high quality, ceramic chip
capacitors. A single ground plane is recommended for all ground
(AGND and DGND) connections.
The PWRDN control pin configures the AD9214 for a sleep mode
when it is logic HIGH. PWRDN floats logic LOW for normal operation. In sleep mode, the ADC is not active, and will consume less
power. When switching from sleep mode to normal operation, the
ADC will need ~15 clock cycles to recover to valid output data.
Digital Outputs
Care must be taken when designing the data receivers for the
AD9214. It is recommended that the digital outputs drive a series
resistor (for example, 100 Ω) followed by a gate like the 74LCX821.
To minimize capacitive loading, there should be only one gate on
each output pin. An example of this is shown in the evaluation
board schematic in Figure 30. The series resistors should be placed
as close to the AD9214 as possible to limit the amount of current
that can flow into the output stage. These switching currents are
confined between ground (DGND) and the DrVDD pins. Standard
TTL gates should be avoided since they can appreciably add to
the dynamic switching currents of the AD9214. It should also be
noted that extra capacitive loading will increase output timing and
invalidate timing specifications. Digital output timing is guaranteed
with 10 pF loads.
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Care should be taken when routing the digital output traces. To
prevent coupling through the digital outputs into the analog portion
of the AD9214, minimal capacitive loading should be placed on
these outputs. It is recommended that a fan-out of only one gate
should be used for all AD9214 digital outputs.
The layout of the encode circuit is equally critical. Any noise
received on this circuitry will result in corruption in the digitization
process and lower overall performance. The Encode clock must be
isolated from the digital outputs and the analog inputs.
EVALUATION BOARD
The AD9214 evaluation board offers designers an easy way to evaluate device performance. The user must supply an analog input
signal, encode clock reference, and power supplies. The digital
outputs of the AD9214 are latched on the evaluation board, and are
available with a data ready signal at a 40-pin edge connector. Refer
to the evaluation board and Schematic sections, and Table 11.
Power Connections
Power to the board is supplied via three detachable, 4-pin power
strips (U4, U9, and U10). These 12 pins should be driven as
outlined in the Table 9.
Table 9. Power Supply Connections for AD9214
Pin
Designator
External Supply Required
1
3
LVC
5V
3V
5 V (optional Z1 supply)
5
–5 V
–5 V (optional Z1 supply)
7
9
11
2, 4, 6, 8, 10, 12
VCC
VDD
DAC
GND
3V
3V
5V
Ground
Note that the +5 V and –5 V supplies are optional, and only
required if the user adds differential op amp Z1 to the board.
Reference Circuit
The evaluation board is configured at assembly to use the
AD9214's on-board reference. To supply an external reference,
the user must connect the REFSENSE pin to VCC by removing the
Rev. E | 16 of 21
Data Sheet
AD9214
THEORY OF OPERATION
jumper block connecting E25 to E26, and placing it between E19
and E24. In this configuration, an external 1.25 V reference must be
connected to jumper connection E23. Jumper connections E19 to
E21, E24, and resistors R13 to R14 are omitted at assembly, and
not used in the evaluation of the AD9214.
Gain/Data Format
The evaluation board is assembled with the DFS/GAIN pin connected to ground; this configures the AD9214 for a 1 V p-p analog input
range, and offset binary data format. The user may remove this
jumper and replace it to make one of the connections described
in the table below to configure the AD9214 for different gain and
output data format options.
Table 10. Data Format and Gain Configuration for Evaluation Board
DFS/GAIN Jumper DFS/GAIN
Placement
Connection
Differential
AINRange
Output Data
Format
E18 to E12
E16 to E11
E15 to E14
E17 to E13
1 V p-p
1 V p-p
2 V p-p
2 V p-p
Offset Binary
Twos Complement
Twos Complement
Offset Binary
AGND
AVDD
REF
Floating
replacing it between E3 and E2. In this configuration, capacitor C2
stabilizes the self-bias of AIN, and resistor R2 provides a matched
impedance for a 50 Ω source at J1.
Transformer T1 can be bypassed by moving the jumper normally
between E40 and E38 to connect E40 to E37, and moving the
jumper normally between E39 and E10 to connect E7 to E10.
In this configuration, the analog input of the AD9214 is driven
single ended, directly from J1; and R3 (normally omitted) should be
installed to terminate any cable connected to J1.
Using the AD8138
An optional driver circuit for the analog input, based on the AD8138
differential amplifier, is included in the layout of the AD9214 evaluation board. This portion of the evaluation circuit is not populated
when the board is manufactured, but can be easily be added by the
user. Resistors R5, R16, R18, and R25 are the feedback network
that sets the gain of the AD8138. Resistors R23 and R24 set the
common-mode voltage at the output of the op amp. Resistors R27
and R28, and capacitor C15, form a low-pass filter at the output of
the AD8138, limiting its noise contribution into the AD9214.
The evaluation board is configured at assembly so that the PWRDN
input floats low for normal operating condition. The user may add
a jumper between option holes E5 and E6 to connect PWRDN to
AVCC, configuring the AD9214 for power-down mode.
Once the drive circuit is populated, the user should remove the
jumper block normally between E40 and E38, and place it between
E40 and E41. This will ac-couple the analog input signal from SMB
connector J1 to the AD8138 drive circuit. The user will also need to
remove the jumper blocks that normally connect E39 to E10 and E1
to E3 to remove transformer T1 from the circuit.
Encode Signal and Distribution
DAC Reconstruction Circuit
The encode input signal should drive SMB connector J5, which
has an on-board 50 Ω termination. A standard CMOS compatible
pulse source is recommended. Alternatively, the user can adjust
the dc level of an ac-coupled clock source by adding resistor R11,
normally omitted. J5 drives the AD9214 ENCODE input and one
gate of U12, which buffers and distributes the clock signal to the
on-board latch (U3), the reconstruction DAC (U11), and the output
data connector (U2). The board comes assembled with timing
options optimized for the DAC and latch; the user may invert the
DR signal at Pin 37 of edge connector U2 by removing the jumper
block between E34 and E35, and reinstalling it between E35 and
E36.
The data available at output connector U2 is also reconstructed
by DAC U11, the AD9752. This 12-bit, high-speed digital-to-analog
converter is included as a tool in setting up and debugging the evaluation board. It should not be used to measure the performance
of the AD9214, as its performance will not accurately reflect the
performance of the ADC. The DAC’s output, available at J2, will
drive 50 Ω. The user can add a jumper block between E8 and E9 to
activate the SLEEP function of the DAC.
Power-Down
Analog Input
The analog input signal is connected to the evaluation board by
SMB connector J1. As configured at assembly, the signal is ac
coupled by capacitor C10 to transformer T1. This 1:1 transformer
provides a 50 Ω termination for connector J1 via 25 Ω resistors R1
and R4. T1 also converts the signal at J1 into a differential signal
for the analog inputs of the AD9214. Resistor R3, normally omitted,
can be used to terminate J1 if the transformer is removed.
The user can reconfigure the board to drive the AD9214 singleendedly by removing the jumper block between E1 and E3, and
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Rev. E | 17 of 21
Data Sheet
AD9214
SCHEMATIC
Figure 30. PCB Schematic
Figure 31. PCB Top Side Silkscreen
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Figure 32. PCB Top Side Copper
Rev. E | 18 of 21
Data Sheet
AD9214
SCHEMATIC
Figure 33. PCB Bottom Side Silkscreen
Figure 36. PCB Power Layers—Layers 3 and 4
Figure 34. PCB Bottom Side Copper
Figure 35. PCB Ground Layer—Layer TBD
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Rev. E | 19 of 21
Data Sheet
AD9214
SCHEMATIC
Table 11. AD9214/PCB Bill of Material
Number
Quantity
Reference Designator
Device
1
2
3
4
5
6
7
8
9
10
1
19
4
11
4
4
4
1
2
37
N/A
C1 to C3, C5 to C14, C16 to C20, C25 to C28
C21 to C24
C4
R1, R2, R4, R8
R7, R10, R12, R17
U5 to U8
R21
R6, R9
E1 to E6, E8 to E9, E11 to E27, E29, E31 to E41
11
12
13
14
15
16
17
18
3
1
1
1
1
1
1
3
J1, J2, J5
U12
U11
U3
U1
U2
T1
U4, U9, U10
191
201
211
221
231
241
251
261
271
281
291
3
2
1
4
1
1
3
2
3
1
1
C1, C20, C28
C30, C29
C15
R5, R18, R25, R26
R23
R24
R11, R15, R16
R13, R14
R27, R28, R3
R19
Z1
PCB
Capacitor
Capacitor
Capacitor
Resistor
Resistor
Resistor
Resistor
Resistor
Test Points
Jumper Connections
Connector
Clock Chip
DAC
Latch
ADC/DUT
40-Pin Header
Transformer
Power Strip
Power Connector
Capacitor
Capacitor
Capacitor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Op Amp
1
Package
Value
603
CAPTAJD
603
1206
1206
RPAK_742
1206
1206
0.1 µF
10 µF
0.01 µF
25 Ω
50 Ω
100 Ω
0Ω
2000 Ω
TSW-120-07-G-S
SMT-100-BK-G
51-52-220
SN74LVC86
AD9752
74LCX821
AD9214
Samtec TSW-120-07-G-D
Mini Circuits ADT1-1WT
Newark 95F5966
25.602.5453.0
0.1 µF
10 µF
15 pF
500 Ω
1 kΩ
4 kΩ
User Select
N/A
50 Ω
0Ω
AD8138
SMB
SOIC
SOIC
SOIC
SOIC
603
CAPTAJD
603
1206
1206
1206
1206
1206
1206
1206
SOIC
This item is included in the PCB design, but is omitted at assembly.
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Rev. E | 20 of 21
Data Sheet
AD9214
OUTLINE DIMENSIONS
Figure 37. 28-Lead Shrink Small Outline Package
(RS-28)
Dimensions shown in inches and millimeters
Updated: April 05, 2022
ORDERING GUIDE
Model1
Temperature Range
Package Description
Packing Quantity
Package
Option
AD9214BRSZ-105
AD9214BRSZ-65
AD9214BRSZ-80
AD9214BRSZ-RL105
AD9214BRSZ-RL65
AD9214BRSZ-RL80
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
28-Lead SSOP
28-Lead SSOP
28-Lead SSOP
28-Lead SSOP
28-Lead SSOP
28-Lead SSOP
Tube
Tube
Tube
Reel, 1500
Reel, 1500
Reel, 1500
RS-28
RS-28
RS-28
RS-28
RS-28
RS-28
1
Z = RoHS Compliant Part.
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registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887-2356, U.S.A.
Rev. E | 21 of 21
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