10-Bit, 65/80/105 MSPS,
3 V A/D Converter
AD9215
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS
AVDD
DRVDD
VIN+
PIPELINE
ADC CORE
SHA
VIN–
REFT
AD9215
REFB
CORRECTION LOGIC
10
OR
OUTPUT BUFFERS
D9 (MSB)
D0
VREF
CLOCK
DUTY CYCLE
STABLIZER
SENSE
Ultrasound equipment
IF sampling in communications receivers
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
REF
SELECT
MODE
SELECT
0.5V
AGND
CLK
PDWN
MODE DGND
02874-A-001
Single 3 V supply operation (2.7 V to 3.3 V)
SNR = 58 dBc (to Nyquist)
SFDR = 77 dBc (to Nyquist)
Low power ADC core: 96 mW at 65 MSPS, 104 mW
@ 80 MSPS, 120 mW at 105 MSPS
Differential input with 300 MHz bandwidth
On-chip reference and sample-and-hold amplifier
DNL = ±0.25 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty cycle stabilizer
Figure 1.
PRODUCT DESCRIPTION
The AD9215 is a family of monolithic, single 3 V supply, 10-bit,
65/80/105 MSPS analog-to-digital converters (ADC). This family
features a high performance sample-and-hold amplifier (SHA)
and voltage reference. The AD9215 uses a multistage differential
pipelined architecture with output error correction logic to provide 10-bit accuracy at 105 MSPS data rates and to guarantee no
missing codes over the full operating temperature range.
The wide bandwidth, truly differential sample-and-hold amplifier (SHA) allows for a variety of user-selectable input ranges
and offsets including single-ended applications. It is suitable for
multiplexed systems that switch full-scale voltage levels in
successive channels and for sampling single-channel inputs at
frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available ADCs, the AD9215
is suitable for applications in communications, imaging, and
medical ultrasound.
A single-ended clock input is used to control all internal conversion
cycles. A duty cycle stabilizer compensates for wide variations in the
clock duty cycle while maintaining excellent performance. The digital
output data is presented in straight binary or twos complement formats. An out-of-range signal indicates an overflow condition, which
can be used with the MSB to determine low or high overflow.
Rev. B
Fabricated on an advanced CMOS process, the AD9215 is available in both a 28-lead surface-mount plastic package and a
32-lead chip scale package and is specified over the industrial
temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
The AD9215 operates from a single 3 V power supply and
features a separate digital output driver supply to accommodate 2.5 V and 3.3 V logic families.
Operating at 105 MSPS, the AD9215 core ADC consumes
a low 120 mW; at 80 MSPS, the power dissipation is 104
mW; and at 65 MSPS, the power dissipation is 96 mW.
The patented SHA input maintains excellent performance
for input frequencies up to 200 MHz and can be configured for single-ended or differential operation.
The AD9215 is part of several pin compatible 10-, 12-, and
14-bit low power ADCs. This allows a simplified upgrade
from 10 bits to 12 bits for systems up to 80 MSPS.
The clock duty cycle stabilizer maintains converter performance over a wide range of clock pulse widths.
The out of range (OR) output bit indicates when the signal
is beyond the selected input range.
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 ©2003–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD9215
Data Sheet
TABLE OF CONTENTS
Specifications..................................................................................... 3
REVISION HISTORY
Absolute Maximum Ratings1 .......................................................... 6
2/13—Data Sheet Changed from a REV. A to a REV. B
Explanation of Test Levels ........................................................... 6
ESD Caution .................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Equivalent Circuits ....................................................................... 8
Definitions of Specifications ....................................................... 8
Typical Performance Characteristics ........................................... 10
Applying the AD9215 Theory of Operation ............................... 14
Clock Input and Considerations .............................................. 15
Evaluation Board ........................................................................ 18
Outline Dimensions ....................................................................... 33
Ordering Guide........................................................................... 34
Changes to Figure 4 and Added EPAD Note to Pin Configurations and Function Descriptions Section ..................................... 7
Changes to Voltage Reference Section........................................ 17
Changes to Evaluation Board Section......................................... 18
Updated Outline Dimensions ...................................................... 33
Changes to Ordering Guide ......................................................... 34
2/04—Data Sheet Changed from a REV. 0 to a REV. A
Renumbered Figures and Tables ..............................UNIVERSAL
Changes to Product Title ................................................................ 1
Changes to Features ........................................................................ 1
Changes to Product Description ................................................... 1
Changes to Product Highlights ..................................................... 1
Changes to Specifications ............................................................... 2
Changes to Figure 2 ......................................................................... 4
Changes to Figures 9 to 11 ........................................................... 10
Added Figure 14 ............................................................................ 10
Added Figures 16 and 18 .............................................................. 11
Changes to Figures 21 to 24 and 25 to 26................................... 12
Deleted Figure 25........................................................................... 12
Changes to Figures 28 and 29 ...................................................... 13
Changes to Figure 31..................................................................... 14
Changes t0 Figure 35 ..................................................................... 16
Changes to Figures 50 through 58............................................... 26
Added Table 11 .............................................................................. 31
Updated Outline Dimensions ...................................................... 32
Changes to Ordering Guide ......................................................... 33
5/03—Revision 0: Initial Version
Rev. B | Page 2 of 36
Data Sheet
AD9215
SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, specified maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference, unless otherwise
noted.
Table 1. DC Specifications
AD9215BRU-65/
AD9215BCP-65
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error 1
Gain Error1
Differential Nonlinearity (DNL) 2
Integral Nonlinearity (INL)2
TEMPERATURE DRIFT
Offset Error1
Gain Error1
Reference Voltage (1 V Mode)
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
Output Voltage Error (0.5 V Mode)
Load Regulation @ 0.5 mA
INPUT REFERRED NOISE
VREF = 0.5 V
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 0.5 V
Input Span, VREF = 1.0 V
Input Capacitance 3
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD2
IDRVDD2
PSRR
POWER CONSUMPTION
Sine Wave Input2
IAVDD2
IDRVDD2
Standby Power 4
AD9215BRU-80/
AD9215BCP-80
AD9215BRU-105/
AD9215BCP-105
Temp
Full
Test
Level
VI
Min
10
Full
Full
Full
Full
Full
VI
VI
VI
VI
VI
Guaranteed
±0.3
±2.0
0
+1.5
+4.0
−1.0 ±0.5
+1.0
±0.5
±1.2
Guaranteed
±0.3
±2.0
+1.5
+4.0
−1.0 ±0.5
+1.0
±0.5
±1.2
Guaranteed
±0.3
±2.0
+1.5
+4.0
−1.0 ±0.6
+1.2
±0.65 ±1.2
Full
Full
Full
V
V
V
+15
+30
±230
+15
+30
±230
+15
+30
±230
Full
Full
Full
Full
VI
V
V
V
±2
0.2
±1
0.2
25°C
25°C
V
V
0.8
0.4
0.8
0.4
0.8
0.4
LSB rms
LSB rms
Full
Full
Full
Full
IV
IV
V
V
1
2
2
7
1
2
2
7
1
2
2
7
V p-p
V p-p
pF
kΩ
Full
Full
IV
IV
Full
25°C
Full
Full
25°C
25°C
2.7
2.25
Typ
Max
Min
10
±35
3.0
2.5
3.3
3.6
VI
V
V
32
7.0
± 0.1
35
VI
V
V
96
18
1.0
Typ
±2
0.2
±1
0.2
2.7
2.25
Max
±35
3.0
2.5
3.3
3.6
34.5
8.6
± 0.1
39
104
20
1.0
Min
10
Typ
±2
0.2
±1
0.2
2.7
2.25
Max
Unit
Bits
% FSR
% FSR
LSB
LSB
ppm/°C
ppm/°C
ppm/°C
±35
mV
mV
mV
mV
3.0
2.5
3.3
3.6
V
V
40
11.3
± 0.1
44
mA
mA
% FSR
120
25
1.0
mW
mW
mW
With a 1.0 V internal reference.
Measured at fIN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 5 for the equivalent analog input structure.
4
Standby power is measured with a dc input, the CLK pin inactive (i.e., set to AVDD or AGND).
1
2
Rev. B | Page 3 of 36
AD9215
Data Sheet
AVDD = 3 V, DRVDD = 2.5 V, specified maximum conversion rate, 2 V p-p differential input, 1.0 V internal reference,
AIN = −0.5 dBFS, MODE = AVDD/3 (duty cycle stabilizer [DCS] enabled), unless otherwise noted.
Table 2. AC Specifications
Parameter
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.4 MHz
fIN = Nyquist1
fIN = 70 MHz
fIN = 100 MHz
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 2.4 MHz
fIN = Nyquist1
fIN = 70 MHz
fIN = 100 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.4 MHz
fIN = Nyquist1
fIN = 70 MHz
fIN = 100 MHz
WORST HARMONIC (Second or Third)
fIN = 2.4 MHz
fIN = Nyquist1
fIN = 70 MHz
fIN = 100 MHz
WORST OTHER (Excluding Second or Third)
fIN = 2.4 MHz
fIN = Nyquist1
fIN = 70 MHz
fIN = 100 MHz
TWO-TONE SFDR (AIN = –7 dBFS)
fIN1 = 70.3 MHz, fIN2 = 71.3 MHz
fIN1 = 100.3 MHz, fIN2 = 101.3 MHz
ANALOG BANDWIDTH
1
AD9215BRU-65/
AD9215BCP-65
AD9215BRU-80/
AD9215BCP-80
AD9215BRU-105/
AD9215BCP-105
Min
Typ
Min
Typ
Min
Temp
Test
Level
Full
25°C
Full
25°C
25°C
25°C
VI
I
VI
I
V
V
56.0
57.0
56.0
56.5
58.5
59.0
58.0
58.5
56.0
57.0
56.0
56.5
58.5
59.0
58.0
58.5
58.0
57.5
Full
25°C
Full
25°C
25°C
25°C
VI
I
VI
I
V
V
55.8
56.5
55.8
56.3
58.5
59.0
58.0
58.5
55.7
56.8
55.5
56.3
58.5
58.5
58.0
58.5
56.0
55.5
Full
25°C
Full
25°C
25°C
25°C
VI
I
VI
I
V
V
9.1
9.2
9.1
9.1
9.5
9.6
9.4
9.5
9.0
9.3
9.0
9.0
9.5
9.5
9.4
9.5
9.1
9.0
Full
25°C
Full
25°C
25°C
25°C
VI
I
VI
I
V
V
−78
−80
−77
−78
−64
−65
−64
−65
−78
−80
−76
−78
−70
−70
−64
−65
−63
−65
−78
−84
−74
−75
−75
−74
Full
25°C
Full
25°C
25°C
25°C
VI
I
VI
I
V
V
−77
−78
−77
−78
−67
−68
−67
−68
−77
−77
−77
−77
−80
−80
−66
−68
−66
−68
−73
−75
−71
−75
-75
−75
25°C
25°C
25°C
V
V
V
300
Tested at fIN = 35 MHz for AD9215-65; fIN = 39 MHz for AD9215-80; and fIN = 50 MHz for AD9215-105.
Rev. B | Page 4 of 36
Max
75
74
300
Max
56.6
56.4
56.5
56.1
9.2
9.1
Typ
Max
Unit
57.5
58.5
57.5
58.0
57.8
57.7
dB
dB
dB
dB
dB
dB
57.6
58.2
57.3
57.8
57.7
57.4
dB
dB
dB
dB
dB
dB
9.3
9.5
9.4
9.4
9.4
9.3
Bits
Bits
Bits
Bits
Bits
Bits
75
74
300
−70
−61
−66
−63
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
MHz
Data Sheet
AD9215
Table 3. Digital Specifications
AD9215BRU-65/
AD9215BCP-65
Parameter
LOGIC INPUTS (CLK, PDWN)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
LOGIC OUTPUTS 1
DRVDD = 2.5 V
High Level Output Voltage
Low Level Output Voltage
1
Temp
Test
Level
Full
Full
Full
Full
Full
IV
IV
IV
IV
V
2.0
Full
Full
IV
IV
2.45
Min
Typ
AD9215BRU-80/
AD9215BCP-80
Max
Min
Typ
AD9215BRU-105/
AD9215BCP-105
Max
Min
2.0
0.8
+10
+10
−650
−70
Typ
Max
Unit
0.8
+10
+10
V
V
µA
µA
pF
2.0
0.8
+10
+10
−650
−70
2
−650
−70
2
2
2.45
2.45
0.05
0.05
V
V
0.05
Output voltage levels measured with a 5 pF load on each output.
Table 4. Switching Specifications
AD9215BRU-65/
AD9215BCP-65
Parameter
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Minimum Conversion Rate
CLOCK Period
DATA OUTPUT PARAMETERS
Output Delay 1 (tOD)
Pipeline Delay (Latency)
Aperture Delay
Aperture Uncertainty (Jitter)
Wake-Up Time 2
OUT-OF-RANGE RECOVERY TIME
Temp
Test
Level
Full
Full
Full
VI
V
V
65
Full
Full
25°C
25°C
25°C
25°C
VI
V
V
V
V
V
2.5
Min
Typ
Min
Typ
AD9215BRU-105/
AD9215BCP-105
Max
Min
80
5
15.4
6.5
2.5
9.5
4.8
5
2.4
0.5
7
1
6.5
2.5
4.8
5
2.4
0.5
7
1
N+1
N+2
N–1
N+8
N+3
tA
N+7
N+4
N+5
N+6
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
N+1
tPD
N+2
02874-A-002
CLK
DATA
OUT
Figure 2. Timing Diagram
1
2
Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output.
Wake-up time is dependent on the value of decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.
Rev. B | Page 5 of 36
Max
5
12.5
4.8
5
2.4
0.5
7
1
Typ
105
5
N
ANALOG
INPUT
Max
AD9215BRU-80/
AD9215BCP-80
6.5
Unit
MSPS
MSPS
ns
ns
Cycles
ns
ps rms
ms
Cycles
AD9215
Data Sheet
ABSOLUTE MAXIMUM RATINGS1
Table 5.
With
Respect to
Mnemonic
ELECTRICAL
AVDD
AGND
DRVDD
DRGND
AGND
DRGND
AVDD
DRVDD
Digital Outputs
DRGND
CLK, MODE
AGND
VIN+, VIN−
AGND
VREF
AGND
SENSE
AGND
REFB, REFT
AGND
PDWN
AGND
ENVIRONMENTAL2
Operating Temperature
Junction Temperature
Lead Temperature (10 sec)
Storage Temperature
EXPLANATION OF TEST LEVELS
Min
Max
Unit
−0.3
−0.3
−0.3
−3.9
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
−0.3
+3.9
+3.9
+0.3
+3.9
DRVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
V
V
V
V
V
V
V
V
V
V
V
−40
+85
150
300
+150
°C
°C
°C
°C
−65
Test Level
I
100% production tested.
II
100% production tested at 25°C and sample tested at specified temperatures.
III
Sample tested only.
IV
Parameter is guaranteed by design and characterization
testing.
V
Parameter is a typical value only.
VI
100% production tested at 25°C; guaranteed by design and
characterization testing for industrial temperature range;
100% production tested at temperature extremes for military devices.
NOTES
1
Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2
Typical thermal impedances 28-lead TSSOP: θJA = 67.7°C/W, 32-lead LFCSP:
θJA = 32.7°C/W; heat sink soldered down to ground plane.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 6 of 36
Data Sheet
AD9215
28 D9 (MSB)
MODE 2
27 D8
SENSE 3
26 D7
VREF 4
25 D6
REFB 5
24 DRVDD
REFT 6
AD9215
DNC
CLK
DNC
PDWN
DNC
DNC
DNC
DNC
23 DRGND
TOP VIEW 22 D5
(Not to Scale)
AGND 8
21 D4
20 D3
VIN– 10
19 D2
AGND 11
18 D1
AVDD 12
17 D0 (LSB)
16 DNC
15 DNC
DNC = DO NOT CONNECT
NOTES
1. DNC = DO NOT CONNECT.
2. IT IS RECOMMENDED THAT THE EXPOSED PAD BE SOLDERED
TO THE GROUND PLANE FOR THE LFCSP PACKAGE. THERE IS
AN INCREASED RELIABILITY OF THE SOLDER JOINTS, AND
THE MAXIMUM THERMAL CAPABILITY OF THE PACKAGE IS
ACHIEVED WITH THE EXPOSED PAD SOLDERED TO THE
CUSTOMER BOARD.
02874-A-003
CLK 13
TOP VIEW
(Not to Scale)
VREF
SENSE
MODE
OR
D9 (MSB)
D8
D7
D6
(LSB) D0
D1
D2
D3
D4
D5
DRGND
DRVDD
VIN+ 9
PDWN 14
AD9215
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
AVDD 7
1
2
3
4
5
6
7
8
02874-A-004
OR 1
32
31
30
29
28
27
26
25
AVDD
AGND
VIN–
VIN+
AGND
AVDD
REFT
REFB
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 4. LFCSP (CP-32-7)
Figure 3. TSSOP (RU-28)
Table 6. Pin Function Descriptions
TSSOP Pin No.
1
2
3
4
5
6
7, 12
8, 11
9
10
13
14
15 to 16
17 to 22,
25 to 28
23
24
LFCSP Pin No.
21
22
23
24
25
26
27, 32
28, 31
29
30
2
4
1, 3, 5 to 8
9 to 14,
17 to 20
15
16
Mnemonic
OR
MODE
SENSE
VREF
REFB
REFT
AVDD
AGND
VIN+
VIN−
CLK
PDWN
DNC
D0 (LSB) to
D9 (MSB)
DRGND
DRVDD
N/A
33
EP
Description
Out-of-Range Indicator.
Data Format and Clock Duty Cycle Stabilizer (DCS) Mode Selection.
Reference Mode Selection.
Voltage Reference Input/Output.
Differential Reference (Negative).
Differential Reference (Positive).
Analog Power Supply.
Analog Ground.
Analog Input Pin (+).
Analog Input Pin (−).
Clock Input Pin.
Power-Down Function Selection (Active High).
Do not connect, recommend floating this pin.
Data Output Bits.
Digital Output Ground.
Digital Output Driver Supply. Must be decoupled to DRGND with a
minimum 0.1 μF capacitor. Recommended decoupling is 0.1 μF in parallel with 10 μF.
Exposed Pad. It is recommended that the exposed pad be soldered to the ground plane
for the LFCSP package. There is an increased reliability of the solder joints, and the
maximum thermal capability of the package is achieved with the exposed pad soldered
to the customer board.
Rev. B | Page 7 of 36
AD9215
Data Sheet
EQUIVALENT CIRCUITS
no missing codes to 10-bit resolution indicate that all 1024
codes, respectively, must be present over all operating ranges.
AVDD
Effective Number of Bits (ENOB)
MODE
02874-A-005
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula, it is possible to obtain a
measure of performance expressed as N, the effective number of
bits
Figure 5. Equivalent Analog Input Circuit
N = (SINAD – 1.76)/6.02
AVDD
Thus, the effective number of bits for a device for sine wave
inputs at a given input frequency can be calculated directly
from its measured SINAD.
20kΩ
02874-A-006
MODE
Gain Error
Figure 6. Equivalent MODE Input Circuit
The first code transition should occur at an analog value 1/2
LSB above negative full scale. The last transition should occur at
an analog value 1 1/2 LSB below the positive full scale. Gain
error is the deviation of the actual difference between the first
and last code transitions and the ideal difference between the
first and last code transitions.
DRVDD
02874-A-007
D9–D0,
OR
Integral Nonlinearity (INL)
Figure 7. Equivalent Digital Output Circuit
INL refers to the deviation of each individual code from a line
drawn from “negative full scale” through “positive full scale.”
The point used as negative full scale occurs 1/2 LSB before the
first code transition. Positive full scale is defined as a level 1 1/2
LSB beyond the last code transition. The deviation is measured
from the middle of each particular code to the true straight line.
AVDD
2.6kΩ
2.6kΩ
02874-A-008
CLK
Maximum Conversion Rate
The clock rate at which parametric testing is performed.
Figure 8. Equivalent Digital Input Circuit
Minimum Conversion Rate
DEFINITIONS OF SPECIFICATIONS
Aperture Delay
Aperture delay is a measure of the sample-and-hold amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.
Aperture Jitter
Aperture jitter is the variation in aperture delay for successive
samples and can be manifested as frequency-dependent noise
on the input to the ADC.
Clock Pulse Width and Duty Cycle
Pulse width high is the minimum amount of time that the clock
pulse should be left in the Logic 1 state to achieve rated performance. Pulse width low is the minimum time the clock pulse
should be left in the low state. At a given clock rate, these specifications define an acceptable clock duty cycle.
The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Offset Error
The major carry transition should occur for an analog value 1/2
LSB below VIN+ = VIN−. Zero error is defined as the deviation
of the actual transition from that point.
Out-of-Range Recovery Time
Out-of-range recovery time is the time it takes for the ADC to
reacquire the analog input after a transient from 10% above
positive full scale to 10% above negative full scale, or from 10%
below negative full scale to 10% below positive full scale.
Output Propagation Delay
The delay between the clock logic threshold and the time when
all bits are within valid logic levels.
Differential Nonlinearity (DNL, No Missing Codes)
Power Supply Rejection
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
The specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value
Rev. B | Page 8 of 36
Data Sheet
AD9215
with the supply at its maximum limit.
Spurious-Free Dynamic Range (SFDR)
Signal-to-Noise and Distortion (SINAD) Ratio
SFDR is the difference in dB between the rms amplitude of the
input signal and the peak spurious signal.
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for SINAD is expressed in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in decibels.
Temperature Drift
The temperature drift for zero error and gain error specifies the
maximum change from the initial (25°C) value to the value at
TMIN or TMAX.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is
expressed as a percentage or in decibels.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. It may be reported in dBc
(i.e., degrades as signal levels are lowered) or in dBFS (always
related back to converter full scale).
Rev. B | Page 9 of 36
AD9215
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 3.0 V, DRVDD = 2.5 V with DCS enabled, TA = 25°C, 2 V differential input, AIN = −0.5 dBFS, VREF = 1.0 V, unless
otherwise noted.
80
0
–20
70
–40
1V p-p SFDR (dBc)
65
–100
55
6.56
13.13
19.69 26.25 32.81
FREQUENCY (MHz)
39.38
45.94
1V p-p SNR (dB)
50
52.50
5
–60
–100
55
02874-A-063
60
19.69 26.25 32.81
FREQUENCY (MHz)
AIN = –0.5dBFS
39.38
45.94
2V p-p SNR (dB)
1V p-p SNR (dB)
50
5
52.50
Figure 10. Single-Tone 32k FFT with fIN = 70.3 MHz, fSAMPLE = 105 MSPS
15
25
35
45
ENCODE (MSPS)
55
65
Figure 13. AD9215-65 SNR/SFDR vs. fSAMPLE, fIN = 10.3 MHz
0
85
AIN = –0.5dBFS
SNR = 57.7
ENOB = 9.3 BITS
SFDR = 75dB
–20
2V p-p SFDR
80
–40
75
dB
–60
–80
70
65
02874-A-065
–100
–120
85
65
–80
13.13
75
1V p-p SFDR (dBc)
70
–40
6.56
65
75
dB
AMPLITUDE (dBFS)
2V p-p SFDR (dBc)
AIN = –0.5dBFS
SNR = 57.8
ENOB = 9.4 BITS
SFDR = 75.0dB
0
35
45
55
ENCODE (MSPS)
80
0
–120
25
Figure 12. AD9215-80 SNR/SFDR vs. fSAMPLE, fIN = 10.3 MHz
Figure 9. Single-Tone 32k FFT with fIN = 10.3 MHZ, fSAMPLE = 105 MSPS
–20
15
02874-A-013
0
2V p-p SNR (dB)
0
6.56
13.13
19.69 26.25 32.81
FREQUENCY (MHz)
39.38
45.94
60
02874-A-066
–120
02874-A-062
60
02874-A-012
–60
–80
AMPLITUDE (dBFS)
AIN = –0.5dBFS
75
dB
AMPLITUDE (dBFS)
2V p-p SFDR (dBc)
AIN = –0.5dBFS
SNR = 58.0
ENOB = 9.4 BITS
SFDR = 75.5dB
2V p-p SNR
55
52.50
0
20
40
60
80
100
fSAMPLE (MSPS)
Figure 11. Single-Tone 32k FFT with fIN = 100.3 MHz, fSAMPLE = 105 MSPS
Rev. B | Page 10 of 36
Figure 14. AD9215-105 SNR/SFDR vs. fSAMPLE, fIN = 10.3 MHz
Data Sheet
AD9215
80
80
70
75
SFDR
60
70
1V p-p SFDR (dBc)
dB
dB
50
80dB REFERENCE LINE
40
65
2V p-p SNR (dB)
30
60
1V p-p SNR (dB)
–45
–40
–35 –30 –25 –20 –15
ANALOG INPUT LEVEL
–10
–5
02874-A-072
0
–50
SNR
2V p-p SFDR (dBc)
10
55
02874-A-014
20
50
0
0
Figure 15. AD9215-80 SNR/SFDR vs.
Analog Input Drive Level, fSAMPLE = 80 MSPS, fIN = 39.1 MHz
50
100
150
200
FREQUENCY (MHz)
250
300
Figure 18. AD9215-105 SNR/SFDR vs.
fIN, AIN = −0.5 dBFS, fSAMPLE = 105 MSPS
85
80
80
70
75
2 SFDR dBc
60
70
dB
dB
50
2V p-p SFDR (dBc)
65
40
–70dBFS
REFERENCE LINE
30
60
1V p-p SFDR (dBc)
2V p-p SNR (dB)
20
02874-A-067
1V p-p SNR
10
2V p-p
SNR
0
–90
–80
–70
–60
–50
–40
–30
–20
ANALOG INPUT LEVEL (–dBFS)
–10
02874-A-016
55
50
0
50
100
150
200
250
300
fIN (MHz)
0
Figure 19. AD9215-80 SNR/SFDR vs.
fIN, AIN = −0.5 dBFS, fSAMPLE = 80 MSPS
Figure 16. AD9215-105 SNR/SFDR vs.
Analog Input Drive Level, fSAMPLE = 105 MSPS, fIN = 50.3 MHz
80
80
1V p-p SFDR (dBc)
70
75
60
2V p-p SFDR (dBc)
80dB REFERENCE LINE
2V p-p SNR (dB)
70
dB
40
30
60
20
2V p-p SFDR (dBc)
2V p-p SNR (dB)
–45
–40
–35 –30 –25 –20 –15
ANALOG INPUT LEVEL
–10
–5
55
0
02874-A-017
10
0
–50
65
1V p-p SNR (dB)
02874-A-015
dB
50
50
0
Figure 17. AD9215-65 SNR/SFDR vs.
Analog Input Drive Level, fSAMPLE = 65 MSPS, fIN = 30.3 MHz
50
100
150
200
ANALOG INPUT (MHz)
Figure 20. AD9215-65 SNR/SFDR vs.
fIN, AIN = −0.5 dBFS, fSAMPLE = 65 MSPS
Rev. B | Page 11 of 36
250
300
AD9215
Data Sheet
0
80
AIN1, AIN2 = –7dBFS
SFDR = 74dBc
70
–20
60
SFDR
–40
–60
dB
dB
50
40
80dBFS REFERENCE LINE
30
–80
02874-A-060
–120
0
13.125
26.250
FREQUENCY (MHz)
39.375
10
0
–60
52.500
Figure 21. Two-Tone 32k FFT with fIN1 = 70.1 MHz,
and fIN2 = 71.1 MHz, fSAMPLE = 105 MSPS
02874-A-073
20
–100
–55
–50
–45
–40
–35 –30 –25
AIN (dBFS)
–20
–15
–10
–5
Figure 24. AD9215-80 Two-Tone SFDR vs. AIN, fIN1 = 100.3 MHz, and fIN2 =
101.3 MHz, fSAMPLE = 105 MSPS
0
80
AIN1, AIN2 = –7dBFS
SFDR = 74dBc
SFDR DCS ON
75
–20
70
–40
SFDR DCS OFF
65
SNR DCS ON
dB
dB
60
–60
55
50
–80
45
SNR DCS OFF
–120
0
13.125
26.250
FREQUENCY (MHz)
39.375
02874-A-069
40
02874-A-061
–100
35
30
20
52.500
Figure 22. Two-Tone 32k FFT with fIN1 = 100.3 MHz,
and fIN2 = 101.3 MHz, fSAMPLE = 105 MSPS
30
40
50
60
CLOCK DUTY CYCLE HIGH (%)
70
80
Figure 25. SINAD, SFDR vs.
Clock Duty Cycle, fSAMPLE = 105 MSPS, fIN = 50.3 MH
80
80
70
2V p-p SFDR (dBc)
75
60
70
SFDR
dBc
40
80dBFS REFERENCE LINE
1V p-p SFDR (dBc)
65
60
2V p-p SINAD
20
10
0
–65
–55
–45
–35
–25
AIN1, AIN2 (dBFS)
–15
55
02874-A-070
30
02874-A-068
dB
50
1V p-p SINAD
–5
50
Figure 23. AD9215-105 Two-Tone SFDR vs. AIN,
fIN1 = 70.1 MHz, and fIN2 = 71.1 MHz, fSAMPLE = 105 MSPS
–40
–20
0
20
40
TEMPERATURE (C)
60
Figure 26. SINAD, SFDR vs. Temperature,
fSAMPLE = 105 MSPS, fIN = 50 MHz
Rev. B | Page 12 of 36
80
Data Sheet
AD9215
0.6
40
30
0.2
10
INL (LSB)
GAIN ERROR (ppm/°C)
0.4
20
0
0
–10
–0.2
–20
–20
0
20
40
TEMPERATURE (°C)
60
–0.6
80
Figure 27. Gain vs. Temperature External 1 V Reference
0.4
0.3
DNL (LSB)
0.2
0.1
0
–0.1
–0.2
02874-A-064
–0.3
–0.5
0
128
256
384
512
CODE
640
768
896
0
128
256
384
512
CODE
640
768
896
1024
Figure 29. AD9215-105 Typical INL, fSAMPLE = 105 MSPS, fIN = 2.3 MHz
0.5
–0.4
02874-A-074
–40
–40
–0.4
02874-A-025
–30
1024
Figure 28. AD9215-105 Typical DNL, fSAMPLE = 105 MSPS, fIN = 2.3 MHz
Rev. B | Page 13 of 36
AD9215
Data Sheet
APPLYING THE AD9215 THEORY OF OPERATION
The analog inputs of the AD9215 are not internally dc biased.
In ac-coupled applications, the user must provide this bias externally. VCM = AVDD/2 is recommended for optimum performance, but the device functions over a wider range with reasonable performance (see Figure 31).
85
80
2V p-p SFDR
75
70
65
The output-staging block aligns the data, carries out the error
correction, and passes the data to the output buffers. The output
buffers are powered from a separate supply, allowing adjustment of the output voltage swing. During power-down, the
output buffers go into a high impedance state.
60
Analog Input and Reference Overview
40
0.25
The analog input to the AD9215 is a differential switched
capacitor SHA that has been designed for optimum performance while processing a differential input signal. The SHA
input can support a wide common-mode range and maintain
excellent performance, as shown in Figure 31. An input common-mode voltage of midsupply minimizes signal-dependent
errors and provides optimum performance.
H
T
0.5pF
T
VIN+
2V p-p SNR
55
50
02874-A-071
The input stage contains a differential SHA that can be configured as ac-coupled or dc-coupled in differential or single-ended
modes. Each stage of the pipeline, excluding the last, consists of
a low resolution flash ADC connected to a switched capacitor
DAC and interstage residue amplifier (MDAC). The residue
amplifier magnifies the difference between the reconstructed
DAC output and the flash input for the next stage in the pipeline. Redundancy is used in each one of the stages to facilitate
digital correction of flash errors.
placed across the inputs to provide dynamic charging currents.
This passive network creates a low-pass filter at the ADC’s input; therefore, the precise values are dependent upon the application. In IF undersampling applications, any shunt capacitors
should be removed. In combination with the driving source
impedance, they would limit the input bandwidth.
dB
The AD9215 architecture consists of a front-end SHA followed
by a pipelined switched capacitor ADC. Each stage provides
sufficient overlap to correct for flash errors in the preceding
stages. The quantized outputs from each stage are combined
into a final 10-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new
input sample, while the remaining stages operate on preceding
samples. Sampling occurs on the rising edge of the clock.
45
0.75
1.25
1.75
2.25
ANALOG INPUT COMMON-MODE VOLTAGE (V)
2.75
Figure 31. AD9215-105 SNR, SFDR vs. Common-Mode Voltage
For best dynamic performance, the source impedances driving
VIN+ and VIN− should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.
An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, respectively, that
define the span of the ADC core. The output common mode of
the reference buffer is set to midsupply, and the REFT and
REFB voltages and span are defined as
CPAR
REFT = 1/2 (AVDD + VREF)
T
REFB = 1/2 (AVDD − VREF)
0.5pF
CPAR
02874-A-028
VIN–
T
H
Figure 30. Switched-Capacitor SHA Input
The clock signal alternatively switches the SHA between sample
mode and hold mode (see Figure 30). When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. Also, a small shunt capacitor can be
Span = 2 × (REFT − REFB) = 2 × VREF
It can be seen from the equations above that the REFT and
REFB voltages are symmetrical about the midsupply voltage
and, by definition, the input span is twice the value of the VREF
voltage.
The internal voltage reference can be pin-strapped to fixed values of 0.5 V or 1.0 V or adjusted within the same range as discussed in the Internal Reference Connection section. Maximum
SNR performance is achieved with the AD9215 set to the largest
input span of 2 V p-p. The relative SNR degradation is 3 dB
Rev. B | Page 14 of 36
Data Sheet
AD9215
when changing from 2 V p-p mode to 1 V p-p mode.
AVDD
R
2V p-p
C
49.9Ω
AD9215
R
AVDD
C
1kΩ
VCMMIN = VREF/2
VIN–
AGND
02874-A-031
The SHA may be driven from a source that keeps the signal
peaks within the allowable range for the selected reference voltage. The minimum and maximum common-mode input levels
are defined as
VIN+
1kΩ
0.1µF
VCMMAX = (AVDD + VREF)/2
Figure 33. Differential Transformer-Coupled Configuration
The minimum common-mode input level allows the AD9215 to
accommodate ground-referenced inputs.
Although optimum performance is achieved with a differential
input, a single-ended source may be driven into VIN+ or VIN−.
In this configuration, one input accepts the signal, while the
opposite input should be set to midscale by connecting it to an
appropriate reference. For example, a 2 V p-p signal may be
applied to VIN+ while a 1 V reference is applied to VIN−. The
AD9215 then accepts a signal varying between 2 V and 0 V. In
the single-ended configuration, distortion performance may
degrade significantly as compared to the differential case. However, the effect is less noticeable at lower input frequencies.
The signal characteristics must be considered when selecting a
transformer. Most RF transformers saturate at frequencies
below a few MHz, and excessive signal power can also cause
core saturation, which leads to distortion.
Single-Ended Input Configuration
A single-ended input may provide adequate performance in
cost-sensitive applications. In this configuration, there is a degradation in SFDR and distortion performance due to the large
input common-mode swing. However, if the source impedances
on each input are kept matched, there should be little effect on
SNR performance. Figure 34 details a typical single-ended input
configuration.
Differential Input Configurations
10µF
1kΩ
2V p-p
49.9Ω
R
0.1µF 1kΩ
AVDD
C
R
1kΩ
10µF
0.1µF
C
AVDD
VIN+
AD9215
VIN–
AGND
1kΩ
02874-A-032
As previously detailed, optimum performance is achieved while
driving the AD9215 in a differential input configuration. For
baseband applications, the AD8138 differential driver provides
excellent performance and a flexible interface to the ADC. The
output common-mode voltage of the AD8138 is easily set to
AVDD/2, and the driver can be configured in a Sallen Key filter
topology to provide band limiting of the input signal.
Figure 34. Single-Ended Input Configuration
1kΩ
499Ω
0.1µF
1kΩ
523Ω
CLOCK INPUT AND CONSIDERATIONS
AVDD
R
VIN+
C
1V p-p
49.9Ω
AD8138
AD9215
R
499Ω
499Ω
C
VIN–
AGND
02874-A-030
VCM
Figure 32. Differential Input Configuration Using the AD8138
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers is not adequate to achieve the
true performance of the AD9215. This is especially true in IF
undersampling applications where frequencies in the 70 MHz to
200 MHz range are being sampled. For these applications, differential transformer coupling is the recommended input configuration. The value of the shunt capacitor is dependant on the input
frequency and source impedance and should be reduced or removed. An example of this is shown in Figure 33.
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals, and as a result may be sensitive to clock duty cycle. Commonly, a 5% tolerance is required
on the clock duty cycle to maintain dynamic performance characteristics. The AD9215 contains a clock duty cycle stabilizer
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9215. As shown in Figure 25, noise and distortion performance are nearly flat over a 50% range of duty cycle. For best
ac performance, enabling the duty cycle stabilizer is recommended for all applications.
The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately 100 clock cycles to allow
the DLL to acquire and lock to the new rate.
Rev. B | Page 15 of 36
AD9215
Data Sheet
Table 7. Reference Configuration Summary
Selected Mode
Externally Supplied Reference
Internal 0.5 V Reference
Programmed Variable
Reference
Internally Programmed 1 V
Reference
External SENSE
Connection
AVDD
VREF
External Divider
Internal Op Amp
Configuration
N/A
Voltage Follower (G = 1)
Noninverting (1 < G < 2)
Resulting VREF
(V)
N/A
0.5
0.5 × (1 + R2/R1)
Resulting Differential Span
(V p-p)
2 × External Reference
1.0
2 × VREF
AGND to 0.2 V
Internal Divider
1.0
2.0
Table 8. Digital Output Coding
VIN+ − VIN− Input Span =
1 V p-p (V)
0.500
0
−0.000978
−0.5000
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given full-scale
input frequency (fINPUT) due only to aperture jitter (tA) can be
calculated with the following equation
SNR Degradation = 20 × log10 [2 × π × fINPUT × tA]
Digital Output Offset Binary
(D9••••••D0)
11 1111 1111
10 0000 0000
01 1111 1111
00 0000 0000
Digital Output Twos
Complement (D9••••••D0)
01 1111 1111
00 0000 0000
11 1111 1111
10 0000 0000
number of output bits switching, which are determined by the
encode rate and the characteristics of the analog input signal.
Digital power consumption can be minimized by reducing the
capacitive load presented to the output drivers. The data in Figure 35 was taken with a 5 pF load on each output driver.
15
40
In the equation, the rms aperture jitter, tA, represents the rootsum square of all jitter sources, which include the clock input,
analog input signal, and ADC aperture jitter specification.
Undersampling applications are particularly sensitive to jitter.
Power Dissipation and Standby Mode
As shown in Figure 35, the power dissipated by the AD9215 is
proportional to its sample rate. The digital power dissipation
does not vary substantially between the three speed grades
because it is determined primarily by the strength of the digital
drivers and the load on each output bit. The maximum DRVDD
current can be calculated as
IDRVDD = VDRVDD × CLOAD × fCLOCK × N
where N is the number of output bits, 10 in the case of the
AD9215. This maximum current is for the condition of every
output bit switching on every clock cycle, which can only occur
for a full-scale square wave at the Nyquist frequency, fCLOCK/2. In
practice, the DRVDD current is established by the average
13
35
11
AD9215-65/80 IAVDD
IAVDD (mA)
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9215. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other
methods), it should be retimed by the original clock at the last
step.
AD9215-105 IAVDD
9
30
7
25
IDRVDD
1023
512
511
0
VIN+ − VIN− Input Span =
2 V p-p (V)
1.000
0
−0.00195
−1.00
5
3
20
IDRVDD
15
5
15
25
1
35
45
55
65
fSAMPLE (MSPS)
75
85
95
–1
105
02874-A-075
Code
Figure 35. Supply Current vs. fSAMPLE for fIN = 10.3 MHz
The analog circuitry is optimally biased so that each speed
grade provides excellent performance while affording reduced
power consumption. Each speed grade dissipates a baseline
power at low sample rates that increases linearly with the clock
frequency.
By asserting the PDWN pin high, the AD9215 is placed in
standby mode. In this state, the ADC typically dissipates 1 mW
if the CLK and analog inputs are static. During standby, the
output drivers are placed in a high impedance state. Reasserting
the PDWN pin low returns the AD9215 into its normal operational mode.
In standby mode, low power dissipation is achieved by shutting
down the reference, reference buffer, and biasing networks. The
Rev. B | Page 16 of 36
Data Sheet
AD9215
R2
VREF 0.5 1
R1
decoupling capacitors on REFT and REFB are discharged when
entering standby mode and then must be recharged when
returning to normal operation. As a result, the wake-up time is
related to the time spent in standby mode, and shorter standby
cycles result in proportionally shorter wake-up times. With the
recommended 0.1 μF and 10 μF decoupling capacitors on REFT
and REFB, it takes approximately one second to fully discharge
the reference buffer decoupling capacitors and 7 ms to restore
full operation.
VIN+
VIN–
REFT
0.1F
ADC
CORE
0.1F
Digital Outputs
0.1F
VREF
Timing
The AD9215 provides latched data outputs with a pipeline delay
of five clock cycles. Data outputs are available one propagation
delay (tOD) after the rising edge of the clock signal. Refer to Figure 2 for a detailed timing diagram.
10F
+
7k
0.1F
0.5V
SELECT
LOGIC
SENSE
7k
02874-A-034
The AD9215 output drivers can be configured to interface with
2.5 V or 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
10F
REFB
AD9215
Figure 36. Internal Reference Configuration
In all reference configurations, REFT and REFB drive the ADC
conversion core and establish its input span. The input range of
the ADC always equals twice the voltage at the reference pin for
either an internal or an external reference.
VIN+
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9215;
these transients can detract from the converter’s dynamic performance.
VIN–
REFT
0.1F
ADC
CORE
0.1F
10F
REFB
The lowest typical conversion rate of the AD9215 is 5 MSPS. At
clock rates below 5 MSPS, dynamic performance may degrade.
10F
A stable and accurate 0.5 V voltage reference is built into the
AD9215. The input range can be adjusted by varying the reference voltage applied to the AD9215, using either the internal
reference or an externally applied reference voltage. The input
span of the ADC tracks reference voltage changes linearly. Maximum SNR and DNL performance is achieved with the AD9215
set to the largest input span of 2 V p-p.
Internal Reference Connection
A comparator within the AD9215 detects the potential at the
SENSE pin and configures the reference into four possible
states, which are summarized in Table 1. If SENSE is grounded,
the reference amplifier switch is connected to the internal resistor divider (see Figure 36), setting VREF to 1 V. Connecting the
SENSE pin to the VREF pin switches the amplifier output to the
SENSE pin, configuring the internal op amp circuit as a voltage
follower and providing a 0.5 V reference output. If an external
resistor divider is connected as shown in Figure 37, the switch is
again set to the SENSE pin. This puts the reference amplifier in a
noninverting mode with the VREF output defined as
0.1F
R2
0.5V
SELECT
LOGIC
SENSE
R1
AD9215
02874-A-035
Voltage Reference
0.1F
VREF
+
Figure 37. Programmable Reference Configuration
If the internal reference of the AD9215 is used to drive multiple
converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 38 depicts how the internal reference voltage is affected by loading.
Rev. B | Page 17 of 36
AD9215
Data Sheet
Operational Mode Selection
0.05
As discussed earlier, the AD9215 can output data in either offset
binary or twos complement format. There is also a provision for
enabling or disabling the clock duty cycle stabilizer (DCS). The
MODE pin is a multilevel input that controls the data format
and DCS state. For best ac performance, enabling the duty cycle
stabilizer is recommended for all applications. The input
threshold values and corresponding mode selections are outlined in Table 9.
0
–0.10
VREF = 1.0V
–0.15
As detailed in Table 9, the data format can be selected for either
offset binary or twos complement.
02874-A-036
–0.20
–0.25
0
0.5
1.0
1.5
ILOAD (mA)
2.0
2.5
Table 9. Mode Selection
3.0
MODE Voltage
AVDD
2/3 AVDD
1/3 AVDD
AGND (Default)
Figure 38. VREF Accuracy vs. Load
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift characteristics. When multiple ADCs track one another, a single reference (internal or external) may be necessary to reduce gain
matching errors to an acceptable level. A high precision external
reference may also be selected to provide lower gain and offset
temperature drift. Figure 39 shows the typical drift characteristics of the internal reference in both 1 V and 0.5 V modes.
EVALUATION BOARD
The AD9215 evaluation board is no longer in production. The
following evaluation board documentation is provided for informational purposes only.
The AD9215 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and
configurations. The converter can be driven differentially
through an AD8351 driver, a transformer, or single-ended. Separate power pins are provided to isolate the DUT from the support circuitry. Each input configuration can be selected by
proper connection of various jumpers (refer to the schematics).
Figure 40 shows the typical bench characterization setup used
to evaluate the ac performance of the AD9215. It is critical that
signal sources with very low phase noise (
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