10-Bit, 65/80/105 MSPS
Dual A/D Converter
AD9216
FEATURES
Integrated dual 10-bit ADC
Single 3 V supply operation
SNR = 57.6 dBc (to Nyquist, AD9216-105)
SFDR = 74 dBc (to Nyquist, AD9216-105)
Low power: 150 mW/ch at 105 MSPS
Differential input with 300 MHz 3 dB bandwidth
Exceptional crosstalk immunity < -80 dB
Offset binary or twos complement data format
Clock duty cycle stabilizer
FUNCTIONAL BLOCK DIAGRAM
AVDD
VIN+_A
AGND
10
SHA
10
ADC
OUTPUT
MUX/
BUFFERS
VIN–_A
REFT_A
D9_A–D0_A
OEB_A
MUX_SELECT
REFB_A
CLOCK
DUTY CYCLE
STABILIZER
VREF
CLK_A
CLK_B
DCS
SENSE
Ultrasound equipment
IF sampling in communications receivers
3G, radio point-to-point, LMDS, MMDS
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
SHARED_REF
AGND
0.5V
PWDN_A
MODE
CONTROL
PWDN_B
DFS
REFT_B
REFB_B
10
VIN+_B
SHA
ADC
VIN–_B
OUTPUT 10
MUX/
BUFFERS
D9_B–D0_B
OEB_B
AD9216
GENERAL DESCRIPTION
The AD9216 is a dual, 3 V, 10-bit, 105 MSPS analog-to-digital
converter (ADC). It features dual high performance sampleand-hold amplifiers (SHAs) and an integrated voltage reference.
The AD9216 uses a multistage differential pipelined architecture with output error correction logic to provide 10-bit
accuracy and guarantee no missing codes over the full
operating temperature range at up to 105 MSPS data rates.
The wide bandwidth, differential SHA allows for a variety of
user selectable input ranges and offsets, including single-ended
applications. The AD9216 is suitable for various applications,
including multiplexed systems that switch full-scale voltage
levels in successive channels and for sampling inputs at
frequencies well beyond the Nyquist rate.
Dual single-ended clock inputs are used to control all internal
conversion cycles. A duty cycle stabilizer is available on the
AD9216 and can compensate for wide variations in the clock
duty cycle, allowing the converters to maintain excellent
performance. The digital output data is presented in either
straight binary or twos complement format.
DRVDD DRGND
04775-001
APPLICATIONS
Figure 1.
Fabricated on an advanced CMOS process, the AD9216 is available in a space saving, Pb-free, 64-lead LFCSP (9 mm × 9 mm) and
is specified over the industrial temperature range (−40°C to
+85°C).
PRODUCT HIGHLIGHTS
1. Pin compatible with AD9238, dual 12-bit 20 MSPS/40 MSPS/
65 MSPS ADC and AD9248, dual 14-bit 20 MSPS/40 MSPS/
65 MSPS ADC.
2. 105 MSPS capability allows for demanding, high frequency
applications.
3. Low power consumption: AD9216–105: 105 MSPS = 300 mW.
4. The patented SHA input maintains excellent performance for
input frequencies up to 200 MHz and can be configured for
single-ended or differential operation.
5. Typical channel crosstalk of < −80 dB at fIN up to 70 MHz.
6. The clock duty cycle stabilizer maintains performance over a
wide range of clock duty cycles.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
AD9216
TABLE OF CONTENTS
DC Specifications ............................................................................. 3
Output Coding............................................................................ 23
AC Specifications.............................................................................. 4
Timing ......................................................................................... 23
Logic Specifications.......................................................................... 5
Data Format ................................................................................ 23
Switching Specifications .................................................................. 6
Voltage Reference....................................................................... 24
Timing Diagram ............................................................................... 7
Dual ADC LFCSP PCB.................................................................. 26
Absolute Maximum Ratings............................................................ 8
Power Connector........................................................................ 26
Explanation of Test Levels ........................................................... 8
Analog Inputs ............................................................................. 26
ESD Caution.................................................................................. 8
Optional Operational Amplifier .............................................. 26
Pin Configuration and Function Descriptions............................. 9
Clock ............................................................................................ 26
Terminology .................................................................................... 11
Voltage Reference ....................................................................... 26
Typical Performance Characteristics ........................................... 13
Data Outputs............................................................................... 26
Equivalent Circuits ......................................................................... 19
LFCSP Evaluation Board Bill of Materials (BOM) ................ 27
Theory of Operation ...................................................................... 20
LFCSP PCB Schematics............................................................. 28
Analog Input ............................................................................... 20
LFCSP PCB Layers ..................................................................... 31
Clock Input and Considerations .............................................. 22
Thermal Considerations............................................................ 37
Power Dissipation and Standby Mode..................................... 22
Outline Dimensions ....................................................................... 38
Digital Outputs ........................................................................... 22
Ordering Guide .......................................................................... 38
REVISION HISTORY
6/05—Rev. 0 to Rev. A
Added 65 and 80 Speed Grades ........................................Universal
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Table 3............................................................................ 5
Changes to Table 4............................................................................ 6
Changes to Table 7............................................................................ 9
Added Figure 8................................................................................ 13
Added Figure 11, Figure 13, and Figure 14 ................................. 14
Changes to Figure 36...................................................................... 18
Changes to Table 12........................................................................ 27
Changes to Figure 51...................................................................... 28
Changes to Figure 52...................................................................... 29
Changes to Figure 53...................................................................... 30
Changes to Figure 54...................................................................... 31
Changes to Figure 55...................................................................... 32
Changes to Figure 56...................................................................... 33
Changes to Figure 57...................................................................... 34
Changes to Figure 58...................................................................... 35
Changes to Figure 59...................................................................... 36
Changes to Ordering Guide .......................................................... 38
10/04—Revision 0: Initial Version
Rev. A | Page 2 of 40
AD9216
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,
TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 1.
Temp
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error1
Differential Nonlinearity (DNL)2
Integral Nonlinearity (INL)2
TEMPERATURE DRIFT
Offset Error
Gain Error1
Reference Voltage
INTERNAL VOLTAGE REFERENCE
Output Voltage Error
Load Regulation @ 1.0 mA
INPUT REFERRED NOISE
Input Span = 2.0 V
ANALOG INPUT
Input Span, VREF = 1.0 V
Input Capacitance3
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltages
AVDD
DRVDD
Supply Current
IAVDD4
IDRVDD4
PSRR
POWER CONSUMPTION
PAVDD4
PDRVDD4
Standby Power5
MATCHING CHARACTERISTICS
Offset Matching Error6
Gain Matching Error (Shared Reference
Mode)
Gain Matching Error (Nonshared
Reference Mode)
Full
Test
Level
VI
AD9216BCPZ-65
Min Typ Max
10
AD9216BCPZ-80
Min Typ Max
10
AD9216BCPZ-105
Min
Typ Max
10
Unit
Bits
Full
Full
25°C
Full
25°C
Full
25°C
VI
VI
VI
IV
I
IV
I
Guaranteed
-1.9 ±0.3 +1.9
-1.6 ±0.4 +1.6
-1.0 ±0.3 +1.0
-0.9 ±0.3 +0.9
-1.4 ±0.5 +1.4
-1.0 ±0.5 +1.0
Guaranteed
-1.9 ±0.3 +1.9
-1.6 ±0.4 +1.6
-1.0 ±0.4 +1.0
-0.9 ±0.4 +0.9
-1.6 ±0.5 +1.6
-1.1 ±0.5 +1.1
Guaranteed
−2.2 ±0.3 +2.2
−1.6 ±0.4 +1.6
−1.0 ±0.5 +1.0
−1.0 ±0.5 +1.0
−2.5 ±1.0 +2.5
−1.5 ±1.0 +1.5
% FSR
% FSR
LSB
LSB
LSB
LSB
Full
Full
Full
V
V
V
±10
±75
±15
±10
±75
±15
±10
±75
±15
Full
25°C
VI
V
±2
1.0
25°C
V
0.5
0.5
0.5
LSB rms
Full
25°C
25°C
IV
V
V
2
2
7
2
2
7
2
2
7
V p-p
pF
kΩ
Full
Full
IV
IV
Full
Full
25°C
2.7
2.25
±35
3.0
2.5
3.3
3.3
VI
VI
V
72
15
±0.1
25°C
25°C
25°C
I
V
V
25°C
25°C
I
I
25°C
I
±2
1.0
3.0
2.5
3.3
3.3
80
78
18
±0.1
216
38
3.0
240
-2.6
-0.4
±0.2
±0.1
+2.6
+0.4
-1.6
±0.1
+1.6
1
2.7
2.25
±35
±2
1.0
2.7
2.25
µV/°C
ppm/°C
ppm/°C
±35
mV
mV
3.0
2.5
3.3
3.3
V
V
85
100
24
±0.1
110
mA
mA
% FSR
234
45
3.0
255
300
60
3.0
330
mW
mW
mW
-2.6
-0.4
±0.2
±0.1
+2.6
+0.4
−3.5
−0.6
±0.3
±0.1
+3.5
+0.6
% FSR
% FSR
-1.6
±0.1
+1.6
−1.6
±0.3
+1.6
% FSR
Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).
Measured with low frequency ramp at maximum clock rate.
3
Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure 37 for the equivalent analog input structure.
4
Measured with low frequency analog input at maximum clock rate with approximately 5 pF loading on each output bit.
5
Standby power is measured with the CLK_A and CLK_B pins inactive (that is, set to AVDD or AGND).
6
Both shared reference mode and nonshared reference mode.
2
Rev. A | Page 3 of 40
AD9216
AC SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,
TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 2.
Parameter
SIGNAL-TO-NOISE RATIO (SNR)
fINPUT = 2.4 MHz
fINPUT = Nyquist1
fINPUT = 69 MHz
fINPUT = 100 MHz
SIGNAL-TO-NOISE AND DISTORTION
RATIO (SINAD)
fINPUT = 2.4 MHz
fINPUT = Nyquist1
fINPUT = 69 MHz
fINPUT = 100 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fINPUT = 2.4 MHz
fINPUT = Nyquist1
fINPUT = 69 MHz
fINPUT = 100 MHz
WORST HARMONIC (SECOND OR
THIRD)
fINPUT = 2.4 MHz
fINPUT = Nyquist1
fINPUT = 69 MHz
fINPUT = 100 MHz
WORST OTHER (EXCLUDING
SECOND OR THIRD)
fINPUT = 2.4 MHz
fINPUT = Nyquist1
fINPUT = 69 MHz
fINPUT = 100 MHz
SPURIOUS-FREE DYNAMIC RANGE
(SFDR)
fINPUT = 2.4 MHz
fINPUT = Nyquist1
fINPUT = 69 MHz
fINPUT = 100 MHz
TWO-TONE SFDR (AIN = −7 dBFS)
fIN1 = 69.1 MHz, fIN2 = 70.1 MHz
fIN1 = 100.1 MHz, fIN2 = 101.1 MHz
ANALOG BANDWIDTH
CROSSTALK
1
AD9216BCPZ-65
Min
Typ
Max
AD9216BCPZ-80
Min
Typ
Max
58.6
58.4
58.4
58.0
57.5
58.5
58.1
58.5
58.0
57.5
Temp
Test
Level
25°C
Full
25°C
25°C
25°C
V
IV
I
V
V
25°C
Full
25°C
25°C
25°C
V
IV
I
V
V
25°C
Full
25°C
25°C
25°C
V
IV
I
V
V
Full
Full
25°C
25°C
25°C
IV
IV
I
V
V
−82.0
−79.5
−79.5
−79.0
−78.5
Full
Full
25°C
25°C
25°C
IV
IV
I
V
V
−82.5
−80.5
−80.5
−80.0
−79.5
Full
Full
25°C
25°C
25°C
IV
IV
I
V
V
25°C
25°C
25°C
25°C
V
V
V
V
56.6
57.2
56.4
57.0
55.9
56.4
58.5
58.3
58.3
57.5
57.0
55.4
56.2
9.4
9.4
9.4
9.3
9.3
9.1
9.2
65.1
67.8
8.9
9.0
82.0
79.5
79.5
79.0
78.5
71.0
70.0
300
−80.0
Nyquist = approximately 32 MHz, 40MHz, 50MHz for the −65, −80, and −105 grades respectively
Rev. A | Page 4 of 40
64.1
67.2
53.4
56.1
9.4
9.3
9.3
9.3
9.3
−81.5
−78.0
−78.0
−77.5
−77.0
-65.8
-68.7
54.8
56.4
58.2
58.0
58.0
57.5
57.0
−81.0
−77.0
−77.0
−76.5
−76.0
-65.1
-67.8
81.0
77.0
77.0
76.5
76.0
70.0
69.0
300
−80.0
AD9216BCPZ-105
Min Typ
Max
8.6
9.1
58.0
57.6
57.6
57.4
57.3
dB
dB
dB
dB
dB
57.8
57.4
57.4
56.8
56.7
dB
dB
dB
dB
dB
9.3
9.3
9.3
9.2
9.2
Bits
Bits
Bits
Bits
Bits
−76.0
−74.0
−74.0
−74.0
−74.0
-64.1
-67.2
−76.5
−75.0
−75.0
−75.0
−75.0
-64.5
-67.8
60.0
66.5
Unit
−60.0
−66.5
−62.0
−67.5
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
76.0
74.0
74.0
74.0
74.0
dBc
dBc
dBc
dBc
dBc
70.0
69.0
300
−80.0
dBc
dBc
MHz
dB
AD9216
LOGIC SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,
TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 3.
Parameter
LOGIC INPUTS
High Level Input
Voltage
Low Level Input
Voltage
High Level Input
Current
Low Level Input
Current
Input Capacitance
LOGIC OUTPUTS1
DRVDD = 2.5 V
High Level Output
Voltage
Low Level Output
Voltage
1
AD9216BCPZ-65
Typ
Max
Min
AD9216BCPZ-80
Typ
Max
Temp
Test
Level
Min
Full
IV
2.0
Full
IV
Full
IV
−10
+10
−10
+10
Full
IV
−10
+10
−10
+10
Full
IV
Full
IV
Full
IV
2.0
0.8
AD9216BCPZ-105
Min
Typ Max
Unit
2.0
V
0.8
2
0.8
V
−10
+10
µA
−10
+10
µA
2
2.45
2
2.45
0.05
Output voltage levels measured with 5 pF load on each output.
Rev. A | Page 5 of 40
pF
2.45
0.05
V
0.05
V
AD9216
SWITCHING SPECIFICATIONS
AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference,
TMIN to TMAX, DCS enabled, unless otherwise noted.
Table 4.
Parameter
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
CLK Period
CLK Pulse Width High
CLK Pulse Width Low
OUTPUT PARAMETERS1
Output Propagation Delay2 (tPD)
Valid Time3 (tV)
Output Rise Time (10% to 90%)
Output Fall Time (10% to 90%)
Output Enable Time4
Output Disable Time4
Pipeline Delay (Latency)
APERTURE
Aperture Delay (tA)
Aperture Uncertainty (tJ)
Wake-Up Time5
OUT-OF-RANGE RECOVERY TIME
Temp
Test Level
Full
Full
Full
Full
Full
VI
IV
VI
VI
VI
25°C
25°C
25°C
25°C
Full
Full
Full
I
I
V
V
IV
IV
IV
25°C
25°C
25°C
25°C
V
V
V
V
AD9216BCPZ-65
Min Typ Max
AD9216BCPZ-80
Min Typ Max
AD9216BCPZ-105
Min
Typ
Max
65
80
105
10
15.4
4.6
4.6
10
12.5
4.4
4.4
4.5
6.4
2.0
9.5
3.8
3.8
4.5
6.4
2.0
1.0
1.0
10
4.5
6.4
Unit
MSPS
MSPS
nS
nS
nS
nS
2.0
1.0
1.0
6
6
6
nS
nS
Cycle
Cycle
Cycle
1.5
0.5
7
1
1.5
0.5
7
1
1.5
0.5
7
1
nS
pS rms
ms
Cycle
1
1
1
1.0
1.0
1
1
1
1
CLOAD equals 5 pF maximum for all output switching parameters.
Output delay is measured from clock 50% transition to data 50% transition.
3
Valid time is approximately equal to the minimum output propagation delay.
4
Output enable time is OEB_A, OEB_B falling to respective channel outputs coming out of high impedance. Output disable time is OEB_A, OEB_B rising to respective
channel outputs going into high impedance.
5
Wake-up time is dependent on value of decoupling capacitors; typical values shown for 0.1 µF and 10 µF capacitors on REFT and REFB.
2
Rev. A | Page 6 of 40
AD9216
TIMING DIAGRAM
N+1
N
N+2
N–1
N+8
N+3
tA
ANALOG
INPUT
N+7
N+4
N+6
N+5
DATA
OUT
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
tPD
Figure 2.
Rev. A | Page 7 of 40
N
N+1
04775-002
CLK
AD9216
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
ELECTRICAL
AVDD
AGND
DRVDD
DRGND
AGND
DRGND
AVDD
DRVDD
Digital Outputs
DRGND
CLK_A, CLK_B, DCS, DFS, MUX_SELECT,
OEB_A, OEB_B, SHARED_REF,
PDWN_A, PDWN_B
VIN−_A, VIN+_A, VIN−_B, VIN+_B
AGND
REFT_A, REFB_A,VREF, REFT_B, REFB_B,
SENSE
ENVIRONMENTAL1
Operating Temperature
Junction Temperature
Lead Temperature (10 sec)
Storage Temperature
1
To
AGND
AGND
Rating
−0.3 V to
+3.9 V
−0.3 V to
+3.9 V
−0.3 V to
+0.3 V
−0.3 V to
+3.9 V
−0.3 V to
DRVDD +
0.3 V
−0.3 V to
AVDD +
0.3 V
−0.3 V to
AVDD +
0.3 V
−0.3 V to
AVDD +
0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
EXPLANATION OF TEST LEVELS
Table 6.
Test Level
I
II
III
IV
V
VI
Description
100% production tested.
100% production tested at 25°C and sample
tested at specified temperatures.
Sample tested only.
Parameter is guaranteed by design and
characterization testing.
Parameter is a typical value only.
100% production tested at 25°C; guaranteed by
design and characterization testing for industrial
temperature range; 100% production tested at
temperature extremes for military devices.
−40°C to
+85°C
150°C
300°C
−65°C to
+150°C
Typical thermal impedances (64-lead LFCSP); θJA = 26.4°C/W. These
measurements were taken on a 4-layer board (with thermal via array) in still
air, in accordance with EIA/JESD51-7.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 8 of 40
AD9216
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AVDD
CLK_A
SHARED_REF
MUX_SELECT
PDWN_A
OEB_A
DNC
D9_A (MSB)
D8_A
D7_A
D6_A
DRGND
DRVDD
D5_A
D4_A
D3_A
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN 1
INDICATOR
AD9216
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
D2_A
D1_A
D0_A (LSB)
DNC
DNC
DNC
DNC
DRVDD
DRGND
DNC
D9_B (MSB)
D8_B
D7_B
D6_B
D5_B
D4_B
04775-003
DNC =
DO NOT CONNECT
AVDD
CLK_B
DCS
DFS
PDWN_B
OEB_B
DNC
DNC
DNC
DNC
D0_B (LSB)
DRGND
DRVDD
D1_B
D2_B
D3_B
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AGND
VIN+_A
VIN–_A
AGND
AVDD
REFT_A
REFB_A
VREF
SENSE
REFB_B
REFT_B
AVDD
AGND
VIN–_B
VIN+_B
AGND
Figure 3. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
1, 4, 13, 16
2
3
5, 12, 17, 64
6
7
8
9
10
11
14
15
18
19
20
21
Mnemonic
AGND1
VIN+_A
VIN−_A
AVDD
REFT_A
REFB_A
VREF
SENSE
REFB_B
REFT_B
VIN−_B
VIN+_B
CLK_B
DCS
DFS
PDWN_B
22
OEB_B
23 to 26, 39,
42 to 45, 58
27, 30 to 38
DNC
28, 40, 53
29, 41, 52
D0_B (LSB) to
D9_B (MSB)
DRGND
DRVDD
Description
Analog Ground.
Analog Input Pin (+) for Channel A.
Analog Input Pin (−) for Channel A.
Analog Power Supply.
Differential Reference (+) for Channel A.
Differential Reference (−) for Channel A.
Voltage Reference Input/Output.
Reference Mode Selection.
Differential Reference (−) for Channel B.
Differential Reference (+) for Channel B.
Analog Input Pin (−) for Channel B.
Analog Input Pin (+) for Channel B.
Clock Input Pin for Channel B.
Duty Cycle Stabilizer (DCS) Mode Pin (Active High).
Data Output Format Select Pin. Low for offset binary; high for twos complement.
Power-Down Function Selection for Channel B.
Logic 0 enables Channel B.
Logic 1 powers down Channel B. (Outputs static, not High-Z.)
Output Enable for Channel B.
Logic 0 enables Data Bus B.
Logic 1 sets outputs to High-Z.
Do Not Connect Pins. Should be left floating.
Channel B Data Output Bits.
Digital Output Ground.
Digital Output Driver Supply. Must be decoupled to DRGND with a minimum 0.1 µF capacitor.
Recommended decoupling is 0.1 µF capacitor in parallel with 10 µF.
Rev. A | Page 9 of 40
AD9216
Pin No.
46 to 51,
54 to 57
59
Mnemonic
D0_A (LSB) to
D9_A (MSB)
OEB_A
60
PDWN_A
61
62
63
MUX_SELECT
SHARED_REF
CLK_A
1
Description
Channel A Data Output Bits.
Output Enable for Channel A.
Logic 0 enables Data Bus A.
Logic 1 sets outputs to High-Z.
Power-Down Function Selection for Channel A.
Logic 0 enables Channel A.
Logic 1 powers down Channel A. (Outputs static, not High-Z.)
Data Multiplexed Mode. (See Data Format section for how to enable.)
Shared Reference Control Bit. Low for independent reference mode; high for shared reference mode.
Clock Input Pin for Channel A.
It is recommended that all ground pins (AGND and DRGND) be tied to a common ground plane.
Rev. A | Page 10 of 40
AD9216
TERMINOLOGY
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the
encode command and the instant the analog input is sampled.
Effective Number of Bits (ENOB)
The ENOB is calculated from the measured SINAD based on
the equation (assuming full-scale input)
ENOB =
SINADMEASURED − 1.76 dB
6.02
Full-Scale Input Power
Expressed in dBm and computed using the following equation.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Clock Pulse Width/Duty Cycle
Pulse-width high is the minimum amount of time that the
clock pulse should be left in a Logic 1 state to achieve rated
performance; pulse-width low is the minimum time clock pulse
should be left in a low state. At a given clock rate, these
specifications define an acceptable clock duty cycle.
Crosstalk
Coupling onto one channel being driven by a low level (−40
dBFS) signal when the adjacent interfering channel is driven by
a full-scale signal.
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input
Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the
capacitance and differential input impedances are measured
with a network analyzer.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin
and subtracting the voltage from the other pin, which is 180°
out of phase. Peak-to-peak differential is computed by rotating
the inputs phase 180° and by taking the peak measurement
again. The difference is then computed between both peak
measurements.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
PowerFULL SCALE
⎛ V 2 FULL SCALE rms ⎞
⎜
⎟
⎜
⎟
Z INPUT
= 10 log ⎜
⎟
0.001
⎜
⎟
⎜
⎟
⎝
⎠
Gain Error
The difference between the measured and ideal full-scale input
voltage range of the ADC.
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a best straight line
determined by a least square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between a 50% crossing of the CLK rising edge and
the time when all output data bits are within valid logic levels.
Rev. A | Page 11 of 40
AD9216
Noise (for Any Range within the ADC)
This value includes both thermal and quantization noise.
− SNRdBc − SignaldBFS
⎛ FS
Vnoise = Z × 0.001 × 10 ⎜⎜ dBm
10
⎝
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value
of the worst third-order intermodulation product, in dBc.
⎞
⎟⎟
⎠
where:
Z is the input impedance.
FS is the full scale of the device for the frequency in question.
SNR is the value for the particular input level.
Signal is the signal level within the ADC reported in dB below
full scale.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious
component may or may not be an IMD product. It also may be
reported in dBc (that is, degrades as signal level is lowered) or
in dBFS (that is, always relates back to converter full scale).
Worst Other Spur
The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonic), reported in dBc.
Transient Response Time
The time it takes for the ADC to reacquire the analog input
after a transient from 10% above negative full scale to 10%
below positive full scale.
Power Supply Rejection Ratio
The specification shows the maximum change in full scale
from the value with the supply at the minimum limit to the
value with the supply at its maximum limit.
Signal-to-Noise and Distortion (SINAD)
The ratio of the rms signal amplitude (set 1 dB below full scale)
to the rms value of the sum of all other spectral components,
including harmonics, but excluding dc.
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input
after a transient from 10% above positive full scale to 10% above
negative full scale, or from 10% below negative full scale to 10%
below positive full scale.
Signal-to-Noise Ratio (without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below
full scale) to the rms value of the sum of all other spectral
components, excluding the first seven harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of
the peak spurious spectral component. The peak spurious
component may or may not be a harmonic. It also may be
reported in dBc (that is, degrades as signal level is lowered)
or dBFS (that is, always related back to converter full scale).
Rev. A | Page 12 of 40
AD9216
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 3.0 V, DRVDD = 2.5 V, T = 25°C, AIN differential drive, internal reference, DCS on, unless otherwise noted.
0
0
SNR = 57.8dB
SINAD = 57.8dB
H2 = –92.7dBc
H3 = –80.3dBc
SFDR = 78.2dBc
70MHz ON CHANNEL A ACTIVE
–20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–20
–10
–40
–60
–80
–30
–40
–50
76MHz CROSSTALK FROM
CHANNEL B
–60
–70
–80
–120
0
10
20
30
40
04775-021
04775-018
–100
–90
–100
27
50
28
29
(76)
FREQUENCY (MHz)
Figure 4. FFT: fS = 105 MSPS, AIN = 10.3 MHz at −0.5 dBFS (−105 Grade)
31
32
33
34
FREQUENCY (MHz)
35
(70)
36
Figure 7. FFT: fS = 105 MSPS, AIN =70 MHz, 76 MHz (−105 Grade)
(A Port FFT while Both A and B Ports Are Driven at −0.5 dBFS)
0
0
SNR = 56.9dB
SINAD = 56.8dB
H2 = –78.5dBc
H3 = –80dBc
SFDR = 78.3dBc
–60
–80
–100
0
10
20
30
40
76MHz
CROSSTALK
FROM
CHANNEL B
–60
–80
–100
04775-019
–120
–40
04775-048
–40
SNR = 57.6dB
SINAD = 57.4dB
H2 = –84.1dBc
H3 = –77.2dBc
SFDR = 74dBc
70MHz ON
CHANNEL A
ACTIVE
–20
AMPLITUDE (dBFS)
–20
AMPLITUDE (dBFS)
30
–120
50
0
5
10
15
20
25
30
35
40
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 8. FFT: fS = 80 MSPS, AIN =70 MHz, 76 MHz (−80 Grade)
(A Port FFT while Both A and B Ports Are Driven at −0.5 dBFS)
Figure 5. FFT: fS = 105 MSPS, AIN = 70 MHz at −0.5 dBFS (−105 Grade)
0
SNR = 56.8dB
SINAD = 56.7dB
H2 = –74dBc
H3 = –84.3dBc
SFDR = 74dBc
SNR = 57.5dB
SINAD = 57.3dB
H2 = –85.9dBc
H3 = –74.4dBc
SFDR = 72.4dBc
70MHz ON
CHANNEL A
ACTIVE
–20
–40
–60
–80
04775-020
–100
–120
0
10
20
30
40
–40
76MHz
CROSSTALK
FROM
CHANNEL B
–60
–80
–100
04775-049
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–20
0
–120
50
0
5
10
15
20
25
30
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 6. FFT: fS = 105 MSPS, AIN = 100 MHz at −0.5 dBFS (−105 Grade)
Rev. A | Page 13 of 40
Figure 9. FFT: fS = 65 MSPS, AIN =70 MHz, 76 MHz (−65 Grade)
(A Port FFT while Both A and B Ports Are Driven at −0.5 dBFS)
AD9216
100
100
H3
90
H2
H2
90
80
H3
dB
dB
80
70
SFDR
70
SFDR
SNR
SNR
60
SINAD
50
0
20
40
60
80
100
50
120
04775-051
04775-022
60
SINAD
50
0
CLOCK FREQUENCY (MHz)
100
150
200
250
300
ANALOG INPUT FREQUENCY (MHz)
Figure 13. Analog Input Frequency Sweep, AIN = −0.5 dBFS,
fS = 80 MSPS (−80 Grade)
Figure 10. SNR, SINAD, H2, H3, SFDR vs. Sample Clock Frequency
AIN = 70 MHz at −0.5 dBFS (−105 Grade)
100
100
H2
90
90
H2
H3
H3
80
dB
dB
80
70
70
SNR
SFDR
SNR
60
0
10
20
30
40
50
60
70
80
90
04775-052
04775-050
60
SINAD
50
SFDR
SINAD
50
100
0
50
100
150
200
250
300
ANALOG INPUT FREQUENCY (MHz)
CLOCK FREQUENCY (MHz)
Figure 14. Analog Input Frequency Sweep, AIN = −0.5 dBFS,
fS = 65 MSPS (−65 Grade)
Figure 11. SNR, SINAD, H2, H3, SFDR vs. Sample Clock Frequency,
AIN = 70 MHz at −0.5 dBFS (−65/80 Grade)
100
90
80
90
70
H2
SFDR dBFS
60
80
H3
dB
dB
50
40
70
SNR
20
0
50
100
150
200
250
04775-053
SNR dB
04775-023
SINAD
50
65dB REF. LINE
30
SFDR
60
SFDR dBc
10
0
–60
300
ANALOG INPUT FREQUENCY (MHz)
–50
–40
–30
–20
–10
INPUT LEVEL (dBFS)
Figure 12. Analog Input Frequency Sweep, AIN = −0.5 dBFS,
fS = 105 MSPS (−105 Grade)
Figure 15. SFDR vs. Analog Input Level,
AIN = 70 MHz, fS = 105 MSPS (−105 Grade)
Rev. A | Page 14 of 40
0
AD9216
90
90
80
80
70
70
TWO-TONE SFDR dBFS
SFDR dBFS
60
60
TWO-TONE SFDR dBc
SFDR dBc
50
dB
dB
50
70dB REF LINE
40
40
65dB REF. LINE
30
30
SNR dB
10
0
–60
–50
–40
–30
–20
–10
04775-026
20
10
04775-063
20
0
–60
0
–50
–40
–30
–20
–10
0
TWO-TONE ANALOG INPUT LEVEL (dBFS)
INPUT LEVEL (dBFS)
Figure 16. SFDR vs. Analog Input Level,
AIN = 70 MHz, fS = 80 MSPS (−80 Grade)
Figure 19. Two-Tone IMD Performance vs. Input Drive Level
(69.1 MHz and 70.1 MHz; fS = 105 MSPS (−105 Grade); F1, F2 Levels Equal)
90
90
80
SFDR dBFS
80
70
SFDR dBFS
60
60
SFDR dBc
50
50
dB
40
40
30
30
20
20
SNR dB
65dB REF. LINE
–50
–40
10
04775-054
10
0
–60
75dB REF. LINE
dB
SFDR dBc
–30
–20
–10
04775-055
70
0
–70
0
INPUT LEVEL (dBFS)
–50
–40
–30
–20
–10
0
TWO-TONE ANALOG INPUT LEVEL (dBFS)
Figure 17. SFDR vs. Analog Input Level,
AIN = 70 MHz, fS = 65 MSPS (−65 Grade )
Figure 20. Two-Tone IMD Performance vs. Input Drive Level
(69.1 MHz and 70.1 MHz; fS = 80 MSPS (−80 Grade); F1, F2 Levels Equal)
0
90
–10
80
–20
SFDR dBFS
70
–30
60
–40
SFDR dBc
dB
50
–50
75dB REF. LINE
40
–60
IMD = –69.9dBc
–70
30
20
–80
04775-025
–90
–100
0
10
20
30
40
10
0
–70
50
–60
–50
–40
–30
–20
–10
0
TWO-TONE ANALOG INPUT LEVEL (dBFS)
INPUT FREQUENCY (MHz)
Figure 18. Two-Tone IMD Performance
F1, F2 = 69.1 MHz, 70.1 MHz at −7 dBFS, 105 MSPS (−105 Grade)
04775-056
AMPLITUDE (dBFS)
–60
Figure 21. Two-Tone IMD Performance vs. Input Drive Level
(69.1 MHz and 70.1 MHz; fS = 65 MSPS (−65 Grade); F1, F2 Levels Equal)
Rev. A | Page 15 of 40
AD9216
100
80
90
75
SFDR
80
70
70
TWO-TONE SFDR dBFS
65
TWO-TONE SFDR dBc
dB
dB
60
50
60
SNR
40
55
30
50
70dB REF LINE
20
0
–60
–50
–40
–30
–20
–10
40
0.25
0
04775-030
45
04775-027
10
0.35
0.45
0.55
TWO-TONE ANALOG INPUT LEVEL (dBFS)
0.65
0.75
0.85
0.95
1.05
1.15
1.25
VREF (V)
Figure 22. Two-Tone IMD Performance vs. Input Drive Level
(100.1 MHz and 101.1 MHz; fS = 105 MSPS (−105 Grade); F1, F2 Levels Equal)
Figure 25. SNR, SFDR vs. External VREF (Full Scale = 2 × VREF)
AIN = 70.3 MHz at −0.5 dBFS, 105 MSPS (−105 Grade)
100
AVDD CURRENT (–105 GRADE)
1.0
0.8
70
0.6
GAIN ERROR (% Full Scale)
80
AVDD CURRENT (–65/80 GRADE)
60
50
40
30
DRVDD CURRENT (ALL GRADES)
20
0.4
0.2
EXTERNAL REFERENCE MODE
0
–0.2
–0.4
04775-028
–0.6
0
10
20
30
40
50
60
70
80
90
INTERNAL REFERENCE MODE
04775-031
10
–0.8
–1.0
–40
100
–20
0
SAMPLE CLOCK RATE (MSPS)
20
40
60
80
TEMPERATURE (°C)
Figure 23. IAVDD, IDRVDD vs. Sample Clock Frequency,
CLOAD = 5 pF, AIN = 70 MHz @ −0.5 dBFS
Figure 26. Typical Gain Error Variation vs. Temperature, (−105 Grade)
AIN = 70 MHz at 0.5 dBFS, 105 MSPS (Normalized to 25°C)
80
80
70
SFDR DCS ON
75
SFDR
SFDR DCS
OFF
60
70
SNR DCS ON
dB
dB
50
65
SNR DCS OFF
60
SNR
30
20
25
30
35
40
45
50
55
60
65
70
04775-032
40
04775-029
CURRENT (mA)
90
SINAD
55
–40
75
–20
0
20
40
60
80
TEMPERATURE (°C)
POSITIVE DUTY CYCLE (%)
Figure 27. SNR, SINAD, SFDR vs. Temperature, (−105 Grade)
AIN = 70 MHz at −0.5 dBFS, 105 MSPS, Internal Reference Mode
Figure 24. SNR, SFDR vs. Positive Duty Cycle DCS Enabled, Disabled;
AIN = 70 MHz at −0.5 dBFS, 105 MSPS (−105 Grade)
Rev. A | Page 16 of 40
AD9216
80
80
SFDR
75
75
SFDR
70
dB
dB
70
65
65
–20
0
20
40
60
04775-059
04775-033
SNR
SINAD
55
–40
SNR
60
60
SINAD
55
80
2.8
2.7
2.9
3.0
3.1
3.2
3.3
AVDD (V)
TEMPERATURE (°C)
Figure 31. SNR, SINAD, SFDR vs. AVDD, AIN = 70 MHz at −0.5 dBFS, 105 MSPS
(−105 Grade)
Figure 28. SNR, SINAD, SFDR vs. Temperature, (−105 Grade)
AIN = 70 MHz at −0.5 dBFS, 105 MSPS , External Reference Mode
80
80
SFDR
75
SFDR
75
70
dB
dB
70
65
65
04775-057
55
SINAD
–40
–20
0
20
40
60
SNR
60
SNR
04775-062
60
SINAD
55
80
2.7
2.8
2.9
TEMPERATURE (°C)
3.0
3.1
3.2
3.3
AVDD (V)
Figure 29. SNR, SINAD, SFDR vs. Temperature, (-80 Grade)
AIN = 70 MHz at −0.5 dBFS, 80 MSPS, Internal Reference Mode
Figure 32. SNR, SINAD, SFDR vs. AVDD, AIN = 70 MHz at −0.5 dBFS, 80 MSPS
(−80 Grade)
85
85
SFDR
80
80
75
75
dB
70
65
70
65
SNR
SNR
60
SINAD
–40
–20
0
20
40
60
SINAD
55
80
TEMPERATURE (°C)
Figure 30. SNR, SINAD, SFDR vs. Temperature, (-65 Grade)
AIN = 70 MHz at −0.5 dBFS, 65 MSPS,, Internal Reference Mode
04775-060
55
60
04775-058
dB
SFDR
2.7
2.8
2.9
3.0
3.1
3.2
3.3
AVDD (V)
Figure 33. SNR, SINAD, SFDR vs. AVDD, AIN = 70 MHz at −0.5 dBFS, 65MSPS
(−65 Grade)
Rev. A | Page 17 of 40
AD9216
2.0
5.2
1.5
5.0
1.0
4.8
TPD (ns)
LSB
0.5
0
–0.5
4.6
4.4
–1.0
04775-035
–2.0
0
200
400
600
800
4.0
–40
1000
Figure 34. Typical DNL Plot, AIN = 10.3 MHz at −0.5 dBFS, 105 MSPS
(−105 Grade)
1.5
1.0
LSB
0.5
0
–0.5
–1.0
04775-036
–1.5
–2.0
400
600
0
20
40
60
80
Figure 36. Typical Propagation Delay vs. Temperature ( All Speed Grades)
2.0
200
–20
TEMPERATURE (°C)
CODE
0
04775-061
4.2
–1.5
800
1000
CODE
Figure 35. Typical INL Plot, AIN = 10.3 MHz at −0.5 dBFS, 105 MSPS
(−105 Grade)
Rev. A | Page 18 of 40
AD9216
EQUIVALENT CIRCUITS
AVDD
AVDD
VIN+_A, VIN–_A,
VIN+_B, VIN–_B
PDWN
04775-004
04775-006
30kΩ
Figure 39. Power-Down Input
Figure 37. Equivalent Analog Input
AVDD
DRVDD
04775-005
04775-007
CLK_A, CLK_B
DCS, DFS,
MUX_SELECT,
SHARED_REF
Figure 40. Digital Outputs
Figure 38. Equivalent Clock, Digital Inputs Circuit
Rev. A | Page 19 of 40
AD9216
THEORY OF OPERATION
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC and a residual multiplier to drive the next
stage of the pipeline. The residual multiplier uses the flash
ADC output to control a switched capacitor digital-to-analog
converter (DAC) of the same resolution. The DAC output is
subtracted from the stage’s input signal and the residual is
amplified (multiplied) to drive the next pipeline stage. The
residual multiplier stage is also called a multiplying DAC
(MDAC). One bit of redundancy is used in each one of the
stages to facilitate digital correction of flash errors. The last
stage simply consists of a flash ADC.
The input stage contains a differential SHA that can be configured as ac- or dc-coupled in differential or single-ended modes.
The output-staging block aligns the data, carries out the error
correction, and passes the data to the output buffers. The output
buffers are powered from a separate supply, allowing
adjustment of the output voltage swing.
ANALOG INPUT
The analog input to the AD9216 is a differential switchedcapacitor SHA that has been designed for optimum performance while processing a differential input signal. The SHA
input accepts inputs over a wide common-mode range. An
input common-mode voltage of midsupply is recommended
to maintain optimal performance.
The SHA input is a differential switched-capacitor circuit.
In Figure 41, the clock signal alternatively switches the SHA
between sample mode and hold mode. When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. Also, a small shunt capacitor can be
placed across the inputs to provide dynamic charging currents.
This passive network creates a low-pass filter at the ADC’s
input; therefore, the precise values are dependant on the
application. In IF under-sampling applications, any shunt
capacitors should be removed. In combination with the driving source impedance, they would limit the input bandwidth.
For best dynamic performance, the source impedances driving
VIN+ and VIN− should be matched, so the common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.
H
T
T
0.5pF
VIN+
CPAR
T
0.5pF
VIN–
CPAR
T
H
04775-008
The AD9216 consists of two high performance ADCs that are
based on the AD9215 converter core. The dual ADC paths are
independent, except for a shared internal band gap reference
source, VREF. Each of the ADC paths consists of a proprietary
front end SHA followed by a pipelined, switched-capacitor ADC.
The pipelined ADC is divided into three sections, consisting of
a sample-and-hold amplifier, followed by seven 1.5-bit stages,
and a final 3-bit flash. Each stage provides sufficient overlap to
correct for flash errors in the preceding stages. The quantized
outputs from each stage are combined through the digital
correction logic block into a final 10-bit result. The pipelined
architecture permits the first stage to operate on a new input
sample, while the remaining stages operate on preceding
samples. Sampling occurs on the rising edge of the respective clock.
Figure 41. Switched-Capacitor Input
An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, respectively, that
define the span of the ADC core. The output common-mode
of the reference buffer is set to midsupply, and the REFT and
REFB voltages and span are defined as:
REFT = 1/2 (AVDD + VREF)
REFB = 1/2 (AVDD − VREF)
Span = 2 × (REFT − REFB) = 2 × VREF
It can be seen from the equations above that the REFT and
REFB voltages are symmetrical about the midsupply voltage and,
by definition, the input span is twice the value of the VREF voltage.
The SHA may be driven from a source that keeps the signal
peaks within the allowable range for the selected reference
voltage. The minimum and maximum common-mode input
levels are defined as
VCMMIN = VREF/2
VCMMAX = (AVDD + VREF)/2
The minimum common-mode input level allows the AD9216
to accommodate ground-referenced inputs. Although optimum
performance is achieved with a differential input, a single-ended
source may be driven into VIN+ or VIN−. In this configuration,
one input accepts the signal, while the opposite input should be
set to midscale by connecting it to an appropriate reference.
Rev. A | Page 20 of 40
AD9216
For example, a 2 V p-p signal may be applied to VIN+, while a
1 V reference is applied to VIN−. The AD9216 then accepts an
input signal varying between 2 V and 0 V. In the single-ended
configuration, distortion performance may degrade significantly as compared to the differential case. However, the effect
is less noticeable at lower input frequencies.
For dc-coupled applications, the AD8138, AD8139, or
AD8351 can serve as a convenient ADC driver, depending on
requirements. Figure 44 shows an example with the AD8138.
The AD9216 PCB has an optional AD8139 on board, as shown
in Figure 53. Note the AD8351 typically yields better performance for frequencies greater than 30 MHz to 40 MHz.
85
49.9Ω
499Ω
2V p-p SFDR
33Ω
499Ω
75
AD8138
1kΩ
70
20pF
33Ω
523Ω
65
dB
0.1µF
1kΩ
AVDD
VIN+
AD9216
VIN–
AGND
499Ω
04775-011
80
60
Figure 44. Driving the ADC with the AD8138
2V p-p SNR
55
50
04775-009
SENSE = GROUND
45
40
0.25
0.75
1.25
1.75
2.25
ANALOG INPUT COMMON-MODE VOLTAGE (V)
2.75
Figure 42. Input Common-Mode Voltage Sensitivity
VIN+
Differential Input Configurations
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers is not adequate to achieve the
true performance of the AD9216. This is especially true in IF
under-sampling applications where frequencies in the 70 MHz
to 200 MHz range are being sampled. For these applications,
differential transformer coupling is the recommended input
configuration, as shown in Figure 43.
50Ω
FULL
SCALE/2
10pF
49.9Ω
DIGITAL OUT = ALL ONES
Single-Ended Input Configuration
A single-ended input may provide adequate performance in
cost-sensitive applications. In this configuration, there is a
degradation in SFDR and distortion performance due to the
large input common-mode swing. However, if the source
impedances on each input are matched, there should be little
effect on SNR performance.
AVDD
AD9216
VIN_B
AGND
1kΩ
04775-010
0.1µF
DIGITAL OUT = ALL ZEROES
Figure 45. Analog Input Full Scale (Full Scale = 2 V)
50Ω
10pF
1kΩ
AVDD/2
VIN–
VIN_A
2V p-p
AVDD/2
04775-012
As previously detailed, optimum performance is achieved while
driving the AD9216 in a differential input configuration. For
baseband applications, the AD8138 differential driver provides
excellent performance and a flexible interface to the ADC. The
output common-mode voltage of the AD8138 is easily set to
AVDD/2, and the driver can be configured in a Sallen-Key filter
topology to provide band limiting of the input signal.
Figure 43. Differential Transformer Coupling
The signal characteristics must be considered when selecting a
transformer. Most RF transformers saturate at frequencies
below a few MHz, and excessive signal power can also cause
core saturation, which leads to distortion.
Rev. A | Page 21 of 40
AD9216
CLOCK INPUT AND CONSIDERATIONS
POWER DISSIPATION AND STANDBY MODE
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
The power dissipated by the AD9216 is proportional to its
sampling rates. The digital (DRVDD) power dissipation is
determined primarily by the strength of the digital drivers
and the load on each output bit. The digital drive current can
be calculated by
The AD9216 provides separate clock inputs for each channel.
The optimum performance is achieved with the clocks operated
at the same frequency and phase. Clocking the channels asynchronously may degrade performance significantly. In some
applications, it is desirable to skew the clock timing of adjacent
channels. The AD9216’s separate clock inputs allow for clock
timing skew (typically ±1 ns) between the channels without
significant performance degradation.
The AD9216 contains two clock duty cycle stabilizers, one for
each converter, that retime the nonsampling edge, providing an
internal clock with a nominal 50% duty cycle. Faster input clock
rates, where it becomes difficult to maintain 50% duty cycles,
can benefit from using DCS, as a wide range of input clock duty
cycles can be accommodated. Maintaining a 50% duty cycle
clock is particularly important in high speed applications, when
proper track-and-hold times for the converter are required to
maintain high performance. The DCS can be enabled by tying
the DCS pin high.
The duty cycle stabilizer uses a delay-locked loop to create the
nonsampling edge. As a result, any changes to the sampling
frequency require approximately 2 µs to 3 µs to allow the DLL
to acquire and settle to the new rate.
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given full-scale
input frequency (fINPUT) due only to aperture jitter (tJ) can be
calculated by
SNR degradation = 2 × log 10[1/2 × p × fINPUT × tJ]
In the equation, the rms aperture jitter, tJ, represents the rootsum square of all jitter sources, which includes the clock input,
analog input signal, and ADC aperture jitter specification. Undersampling applications are particularly sensitive to jitter.
For optimal performance, especially in cases where aperture jitter may affect the dynamic range of the AD9216, it
is important to minimize input clock jitter. The clock input
circuitry should use stable references; for example, use analog
power and ground planes to generate the valid high and low
digital levels for the AD9216 clock input. Power supplies for
clock drivers should be separated from the ADC output driver
supplies to avoid modulating the clock signal with digital noise.
Low jitter, crystal-controlled oscillators make the best clock
sources. If the clock is generated from another type of source
(by gating, dividing, or other methods), it should be retimed by
the original clock at the last step.
IDRVDD = VDRVDD × CLOAD × fCLOCK × N
where N is the number of bits changing, and CLOAD is the average
load on the digital pins that changed.
The analog circuitry is optimally biased, so each speed grade
provides excellent performance while affording reduced power
consumption. Each speed grade dissipates a baseline power at
low sample rates that increases with clock frequency.
Either channel of the AD9216 can be placed into standby mode
independently by asserting the PWDN_A or PDWN_B pins.
Time to go into or come out of standby mode is 5 cycles maximum when only one channel is being powered down. When both
channels are powered down, VREF goes to ground, resulting in a
wake-up time of ~7 ms dependent on decoupling capacitor
values.
It is recommended that the input clock(s) and analog input(s)
remain static during either independent or total standby, which
results in a typical power consumption of 3 mW for the ADC.
If the clock inputs remain active while in total standby mode,
typical power dissipation of 10 mW results.
The minimum standby power is achieved when both channels
are placed into full power-down mode (PDWN_A = PDWN_B
= HI). Under this condition, the internal references are powered
down. When either or both of the channel paths are enabled
after a power-down, the wake-up time is directly related to the
recharging of the REFT and REFB decoupling capacitors and to
the duration of the power-down.
A single channel can be powered down for moderate power
savings. The powered-down channel shuts down internal
circuits, but both the reference buffers and shared reference
remain powered on. Because the buffer and voltage reference
remain powered on, the wake-up time is reduced to several
clock cycles.
DIGITAL OUTPUTS
The AD9216 output drivers can interface directly with 3 V
logic families. Applications requiring the ADC to drive large
capacitive loads or large fanouts may require external buffers
or latches because large drive currents tend to cause current
glitches on the supplies that may affect converter performance.
The data format can be selected for either offset binary or twos
complement. This is discussed in the Data Format section.
Rev. A | Page 22 of 40
AD9216
OUTPUT CODING
DATA FORMAT
Table 8.
(VIN+) − (VIN−)
> +0.998 V
+0.998 V
+0.996 V
•
•
+0.002 V
+0.0 V
−0.002 V
•
•
−0.998 V
−1.000 V
< −1.000 V
Offset Binary
11 1111 1111
11 1111 1111
11 1111 1110
•
•
10 0000 0001
10 0000 0000
01 1111 1111
•
•
00 0000 0001
00 0000 0000
00 0000 0000
The AD9216 data output format can be configured for either
twos complement or offset binary. This is controlled by the
data format select pin (DFS). Connecting DFS to AGND
produces offset binary output data. Conversely, connecting
DFS to AVDD formats the output data as twos complement.
Twos Complement
01 1111 1111
01 1111 1111
01 1111 1110
•
•
00 0000 0001
00 0000 0000
11 1111 1111
•
•
10 0000 0001
10 0000 0000
10 0000 0000
The output data from the dual ADCs can be multiplexed onto a
single, 10-bit output bus. The multiplexing is accomplished by
toggling the MUX_SELECT bit, which directs channel data to
the same or opposite channel data port. When MUX_SELECT
is logic high, the Channel A data is directed to the Channel A
output bus, and the Channel B data is directed to the Channel B
output bus. When MUX_SELECT is logic low, the channel
data is reversed; that is, the Channel A data is directed to the
Channel B output bus, and the Channel B data is directed to
the Channel A output bus. By toggling the MUX_SELECT bit,
multiplexed data is available on either of the output data ports.
TIMING
The AD9216 provides latched data outputs with a pipeline delay
of six clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal. Refer to
Figure 2 for a detailed timing diagram.
If the ADCs are run with synchronized timing, this same clock
can be applied to the MUX_SELECT pin. Any skew between
CLK_A, CLK_B, and MUX_SELECT can degrade ac performance. It is recommended to keep the clock skew < 100 pHs.
After the MUX_SELECT rising edge, either data port has
the data for its respective channel; after the falling edge, the
alternate channel’s data is placed on the bus. Typically, the
other unused bus is disabled by setting the appropriate OEB
high to reduce power consumption and noise. Figure 46 shows
an example of multiplex mode. When multiplexing data, the
data rate is two times the sample rate. Note that both channels
must remain active in this mode and that each channel’s powerdown pin must remain low.
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9216.
These transients can detract from the converter’s dynamic
performance. The lowest conversion rate of the AD9216 is
10 MSPS. At clock rates below 10 MSPS, dynamic performance may degrade.
A–1
A1
A0
A8
A2
A7
A3
A4
B–1
B1
B0
A6
A5
B8
B2
B7
B3
B4
ANALOG INPUT
ADC A
ANALOG INPUT
ADC B
B6
B5
CLK_A = CLK_B =
MUX_SELECT
B–7
A–6
B–6
A–5
B–5
A–4
B–4
A–3
B–3
A–2
B–2
A–1
B–1
A0
B0
A1
B1
D0_A
–D11_A
Figure 46. Example of Multiplexed Data Format Using the Channel A Output and the Same Clock Tied to CLK_A, CLK_B, and MUX_SELECT
Rev. A | Page 23 of 40
04775-013
Code
1023
1023
1022
•
•
513
512
511
•
•
1
0
0
AD9216
VOLTAGE REFERENCE
A stable and accurate 0.5 V voltage reference is built into
the AD9216. The input range can be adjusted by varying the
reference voltage applied to the AD9216, using either the internal reference with different external resistor configurations or
an externally applied reference voltage. The input span of the
ADC tracks reference voltage changes linearly.
Note: The optimum performance is obtained with VREF =
1.0 V; performance degrades as VREF (and full scale) reduces
(see Figure 25). In all reference configurations, REFT and REFB
drive the ADC core and establish its input span. The input
range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference.
VIN+
Internal Reference Connection
VIN–
A comparator within the AD9216 detects the potential at the
SENSE pin and configures the reference into three possible
states, which are summarized in Table 9. If SENSE is grounded,
the reference amplifier switch is connected to the internal resistor
divider (see Figure 47), setting VREF to 1 V. If a resistor divider
is connected, as shown in Figure 48, the switch is again set to the
SENSE pin. This puts the reference amplifier in a noninverting
mode with the VREF output defined as
REFT
0.1µF
ADC
CORE
0.1µF
10µF
REFB
0.1µF
VREF
10µF
SELECT
LOGIC
0.1µF
0.5V
SENSE
AD9216
Figure 47. Internal Reference Configuration (One Channel Shown)
Table 9. Reference Configuration Summary
Selected Mode
External Reference
Programmable Reference
Internal Fixed Reference
SENSE Voltage
AVDD
0.2 V to VREF
AGND to 0.2 V
Resulting VREF (V)
N/A
0.5 × (1 + R2/R1)
1.0
Rev. A | Page 24 of 40
Resulting Differential Span (V p-p)
2 × External Reference
2 × VREF (see Figure 48)
2.0
04775-014
VREF = 0.5 × (1 + R2/R1)
AD9216
0.6
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or to improve the thermal drift
characteristics. When multiple ADCs track one another, a single
reference (internal or external) may be necessary to reduce gain
matching errors to an acceptable level. A high precision external
reference may also be selected to provide lower gain and offset
temperature drift. Figure 49 shows the typical drift
characteristics of the internal reference.
VIN+
VIN–
VREF ERROR (%)
0.4
0.3
VREF = 1.0V
0.2
0
–40
04775-016
0.1
–20
0
20
40
TEMPERATURE (°C)
60
80
Figure 49. Typical VREF Drift
0.05
0
VREF ERROR (%)
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7 kΩ load. The internal buffer still generates the positive and
negative full-scale references, REFT and REFB, for the ADC
core. The input span is always twice the value of the reference
voltage; therefore, the external reference must be limited to a
maximum of 1 V. If the internal reference of the AD9216 is
used to drive multiple converters to improve gain matching,
the loading of the reference by the other converters must be
considered. Figure 50 depicts how the internal reference
voltage is affected by loading.
0.5
–0.05
–0.10
VREF = 1.0V
–0.15
REFT
04775-017
–0.20
0.1µF
ADC
CORE
0.1µF
–0.25
10µF
0
0.5
1.0
REFB
0.1µF
1.5
ILOAD (mA)
2.0
2.5
3.0
Figure 50. VREF Accuracy vs. Load
VREF
Shared Reference Mode
10µF
10µF
R2
SELECT
LOGIC
0.5V
SENSE
04775-015
R1
AD9216
Figure 48. Programmable Reference Configuration (one channel shown)
The shared reference mode allows the user to connect
the references from the dual ADCs together externally for
superior gain and offset matching performance. If the ADCs
are to function independently, the reference decoupling can
be treated independently and can provide superior isolation
between the dual channels. To enable shared reference mode,
the SHARED_REF pin must be tied high, and the external
differential references must be externally shorted. (REFT_A
must be externally shorted to REFT_B, and REFB_A must
be shorted to REFB_B.)
Rev. A | Page 25 of 40
AD9216
DUAL ADC LFCSP PCB
The PCB requires a low jitter clock source, analog sources,
and power supplies. The PCB interfaces directly with ADI’s
standard dual-channel data capture board (HSC-ADC-EVALDC), which together with ADI’s ADC Analyzer™ software
allows for quick ADC evaluation.
POWER CONNECTOR
Power is supplied to the board via three detachable
4-lead power strips.
The single-clock input is at J5; the input clock is buffered and
drives both channel input clocks from Pin 3 at U8 through R79,
R40, and R85. Jumper E11 to E19 allows for inverting the input
clock. U8 also provides CLKA and CLKB outputs, which are
buffered by U6 and U5, which drive the DRA and DRB signals
(these are the data-ready clocks going off card). DRA and DRB
can also be inverted at their respective jumpers.
Table 11. Jumpers
Table 10. Power Connector
Terminal
VCC1 3.0 V
VDD1 2.5 V
VDL1 2.5 V
VCLK 3.0 V
+5 V
−5 V
CLOCK
Terminal
OEB A
PWDN A
MUX
SHARED REF
DRA
LATA
ENC A
OEB B
PWDN B
DFS
SHARED REF
DRB
LATB
ENC B
Comments
Analog supply for ADC
Output supply for ADC
Buffer supply
Supply for XOR Gates
Optional op amp supply
Optional op amp supply
1
VCC, VDD, and VDL are the minimum required power connections.
ANALOG INPUTS
The evaluation board accepts a 2 V p-p analog input signal
centered at ground at two SMB connectors, Input A and
Input B. These signals are terminated at their respective
primary side transformer. T1 and T2 are wideband RF
transformers that provide the single-ended-to-differential
conversion, allowing the ADC to be driven differentially,
minimizing even-order harmonics. The analog signals can
be low-pass filtered at the secondary transformer to reduce
high frequency aliasing.
Comments
Output Enable for A Side
Power-Down A
Mux Input
Shared Reference Input
Invert DRA
Invert A Latch Clock
Invert Encode A
Output Enable for B Side
Power-Down B
Data Format Select
Shared Reference Input
Invert DRB
Invert B Latch Clock
Invert Encode B
VOLTAGE REFERENCE
OPTIONAL OPERATIONAL AMPLIFIER
The PCB has been designed to accommodate an optional
AD8139 op amp that can serve as a convenient solution
for dc-coupled applications. To use the AD8139 op amp,
remove C14, R4, R5, C13, R37, and R36, and place R22, R23,
R30, and R24.
The ADC SENSE pin is brought out to E41, and the internal
reference mode is selected by placing a jumper from E41 to
ground (E27). External reference mode is selected by placing a
jumper from E41 to E25 and E30 to E2. R56 and R45 allow for
programmable reference mode selection.
DATA OUTPUTS
The ADC outputs are buffered on the PCB at U2, U4. The ADC
outputs have the recommended series resistors in line to limit
switching transient effects on ADC performance.
Rev. A | Page 26 of 40
AD9216
LFCSP EVALUATION BOARD BILL OF MATERIALS (BOM)
Table 12. Dual CSP PCB Rev. B
No.
1
2
3
Quan.
2
7
44
Device
Capacitors
Capacitors
Capacitors
Package
0201
0805
0402
Value
20 pF
10 µF
0.1 µF, (C59, C61 NP1)
Capacitors
Capacitors
Jumpers
TAJD
0201
10 µF
0.1 µF
6
3
3
1
Reference Designator
C1, C3
C2, C5, C7, C9, C10, C22, C36
C4, C6, C8, C11 to C15, C20, C21, C24 to C27, C29 to
C35, C39 to C66
C16 to C19, C37, C38,C67
C23, C28
E1 to E7, E9 to E22, E24 to E27, E29 to E31, E33 to
E38, E40 to E43, E49, E61
J1 to J6
P1, P4, P11
P1, P4, P11
P3, P8 (implemented as one 80 pin connector)
4
5
6
7
2
40
7
8
9
10
Wieland
Wieland
Samtec
11
12
13
14
15
4
6
4
4
10
R1, R2, R32, R34
R3, R7, R11, R14, R51, R61
R6, R8, R33, R42
R4, R5, R36, R37
R9, R12, R20, R35, R40, R43, R50, R53, R84, R85
Resistors
Resistors
Resistors
Resistors
Resistors
Z5.531.3425.0
25.602.5453.0
TSW-140-08L-D-RA
0402
0402
0402
0402
0402
16
17
18
6
2
34
Resistors
Resistors
Resistors
0402
0402
0402
19
4
R15, R16, R18, R26, R29, R31
R17, R25
R19, R21, R27, R28, R39, R41, R44, R46 to R49, R52,
R54, R55, R57 to R60, R62 to R73, R75, R77, R78, R81
to R83
R22 to R24, R30
Resistors
0402
20
21
22
2
7
8
R45, R56
R10, R13, R38, R74, R76, R79, R80
RZ1, RZ2, RZ3, RZ4, RZ5, RZ6, RZ9, RZ10
Resistors
Resistor
Resistor Pack
0402
0402
CTS
742C163470J
24
2
T1, T2
Transformers
T1-1WT
25
1
U1
AD9216/AD9238/AD9248
LFCSP-64
26
27
2
2
U2, U4
U3, U7
Transparent Latch/Buffer
Inverter
TSSOP-48
SC-70
28
29
3
2
U5, U6, U8
U11, U12
XOR
Amp
SO-14
SO-8/EP
30
14
P2, P5 to P7, P9, P10, P12 to P18, P21
Solder Bridge
1
SMA
Power Connector Posts
Detachable Connectors
Connector
Not Populated.
Rev. A | Page 27 of 40
36 Ω (All NP1)
50 Ω, (R11, R51 NP1)
100 Ω, (All NP1)
33 Ω
Zero Ω (R9, R12, R35,
R43, R50, R84 NP1)
499 Ω (R16, R29 NP1)
525 Ω
1 kΩ (R64, R78, R81, R82,
R83 NP1)
40 Ω (R22, R23, R24, R30
NP1)
10 kΩ (R45, R56 NP1)
22 Ω
47 Ω
Minicircuits
SN74LVCH16373ADGGR
SN74LVC1G04DCKT
(U3, U7 NP1)
SN74VCX86
AD8139
Rev. A | Page 28 of 40
1
+
+
T1
6
5
4
6
5
4
4
C19
+
CTAPB
R32
NP_36Ω
R34
NP_36Ω
EXT_VREF
E27
VD
+5V
1
C5
C45
C23
0.1µF
1
2
3
4
VD 5
VD
E6
E17
VD
R63
1kΩ
E18
E10
R62
1kΩ
E20
C8
0.1µF
VDD
AGND
VIN_A
VIN_AB
AGND1
AVDD1
E30
E2
E41
C55
10µF 0.1µF
C30
0.1µF
VREF
C2
10µF
SENSE
C11
0.1µF
AMPOUTB
R45
NP_10kΩ
R36
33Ω
C26
0.1µF
C24
0.1µF
REFT_A
REFB_A
VD
E24
R67
1kΩ
E22
E21
VD
E40
R68
1kΩ
VD
E29
R70
1kΩ
VD
E33
E26
R69
1kΩ
VDD
0.1µF
E31
TIEB
R51
NP_50Ω
J2
CLOCK B
C6
C40
R54
1kΩ
C42
0.1µF
R52
1kΩ
VCLK
33
39
38
37
36
35
34
48
47
46
45
44
43
42
41
40
R41
1kΩ
0.1µF
E4
P14
E36
C41
0.1µF
VD
R49
1kΩ
E35
VD
P13
P2 P9
8
9
10
11
12
13
14
U3
74LCX86
R9
CLKLATA
C57
0.1µF
R42
NP_100Ω
R33
NP_100Ω
ENCA
22Ω
74VCX86
7
6
5
4
3
2
1
R8
NP_100Ω
ENCB
R6
NP_100Ω
22Ω
R13
R12
DRB
R55
1kΩ
R48
1kΩ
E37 E38
E34 E16
NP_0Ω CLKLATB
NP_0Ω
VD
VD
VD
DUT CLOCK SELECTABLE
TO BE DIRECT OR
BUFFERED
R38 VCLK R50
U5
C25
0.1µF
VD
VCLK
14
E13 E12
13
VD
12
R46
Ω
1k
Ω
22
11
E14 E15
10 R10 DRA
VD
9
R47
1kΩ
8 NP_0Ω
R43
NP_0Ω
J2, J3, OPTIONAL CLOCK PATHING
U6
1A VCC
4B
1B
4A
1Y
4Y
2A
3B
2B
3A
2Y
GND 3Y
C22
10µF
1
2
3
4
5
6
7
R74
22Ω
VCLK
C58
C36 0.1µF
10µF
3Y GND
2Y
3A
2B
3B
2A
4Y
1Y
4A
1B
4B
VCC 1A
NC VCC
2
A
3
4
Y
GND
OTRB
D13B
D12B
D11B
D10B
D9B SN74LVC1G04
D8B 1
5
VDD
C4
0.1µF
P10 P12
U7
SN74LVC1G04
5
1
NC VCC
2
A
3
4
Y
GND
E3
R44
1kΩ
VD
D6A
D5A
D4A
D3A
D2A
D1A
D0A
VCLK
R39
1kΩ
TIEA
R11
NP_50Ω
J3
CLOCK A
J6
C63
0.1µF
C1
20pF
C44
E5
VD
R66
1kΩ
0.1µF 0.1µF 0.1µF 0.1µF
C39 C43
VD
4
R61
50Ω
6
REFT_A
7
REFB_A
8
VREF
VREF
SEE
9
C29
BELOW SENSE
SENSE
0.1µF
REFB_B 10
C7 C54
REFB_B
C27
REFT_B 11
REFT_B
10µF 0.1µF
0.1µF
12
VD
AVDD2
C28
13
0.1µF
AGND2
AMPOUTBB
14
VIN_BB
15
R37
VIN_B
33Ω
C3
16
AGND3
20pF
R5
33Ω
R56
NP_10kΩ
E25
E1
C66
0.1µF
+
3
–5V
AMPOUTA
10µF
C67
2
MUX
D6_A
D5_A
D4_A
D3_A
D2_A
D1_A
D0_A
DRVDD1
U1
DRGND1
OTR_B
NOTE
D13_B
14-BIT PINOUT SHOWN
FOR 14-BIT: LSB = PIN 42, PIN 23 D12_B
FOR 12-BIT: LSB = PIN 44, PIN 25
FOR 10-BIT: LSB = PIN 46, PIN 27 D11_B
D10_B
D9_B
D8_B
C62
0.1µF
R4
33Ω
+
AMPOUTAB
PADS TO SHORT
REFERENCES TOGETHER
REFTA
P15
REFTB
P16
REFBA
P18
REFBB
P17
CTAPA
R2
NP_36Ω
R1
NP_36Ω
VREF AND SENSE CIRCUIT
C13
R7
50Ω 0.1µF
3
CTAPB 2
R60
1kΩ
VD
VD
R58
1kΩ
2
3
+
VCLK
3
VDD VDL EXT_VREF VCLK
2
10µF 10µF 10µF 10µF 10µF
T2
10µF
CTAPA 1
AMPINB
E43
E42
C37
VD
VDL
1
C16 C17 C18
+5V
C38
–5V
4
R65
1kΩ
ENCB
VD
04775-038
J1
AIN B
C9
10µF
R57
1kΩ
R59
1kΩ
C10
10µF
C12
0.1µF
3
VDD
R3 C14
50Ω 0.1µF
VD
VDD
VDL
VCLK
2
AMPINA
C31
0.1µF
AIN A
J4
P5
P6
P7
P21
VD
1
P1
AVDD3
CLK_B
DCS
DFS
PDWN_B
OEB_B
D0_B
D1_B
D2_B
D3_B
D4_B
DRGND
DRVDD
D5_B
D6_B
D7_B
P4
C56
0.1µF
DUT CLOCK SELECTABLE
TO BE DIRECT OR BUFFERED
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
D0B
D1B
D2B
D3B
D4B
Figure 51. PCB Schematic (1 of 3)
D5B
D6B
D7B
+
P11
65
E9
OTRA
D13A
D12A
D11A
D10A
E7
VD
EPAD
AVDD5
CLK_A
SH_REF
MUX_SEL
PWDN_A
OEB_A
OTR_A
D13_A
D12_A
D11_A
D10_A
DRGND2
DRVDD2
D9_A
D8_A
D7_A
R64
NP_1kΩ
ENCA
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
D9A
D8A
D7A
VD
AD9216
LFCSP PCB SCHEMATICS
Figure 52. PCB Schematic (2 of 3)
Rev. A | Page 29 of 40
04775-039
D5B
D4B
D3B
D2B
D1B
D0B
D6B
OTRB
D13B
D12B
D11B
D10B
D9B
D8B
D7B
D6A
D5A
D4A
D3A
D2A
D1A
D0A
OTRA
D13A
D12A
D11A
D10A
D9A
D8A
D7A
VDL
Q = OUTPUT
LE2 D = INPUT OE2
2Q8
2D8
2Q7
2D7
GND
GND
2Q6
2D6
2Q5
2D5
VCC
VCC
2Q4
2D4
2Q3
2D3
GND
GND
2Q2
2D2
2Q1
2D1
1Q8
1D8
1Q7
1D7
GND
GND
1Q6
1D6
1Q5
1D5
VCC
VCC
1Q4
1D4
1Q3
1D3
GND
GND
1Q2
1D2
1Q1
1D1
LE1
OE1
C48
C47
C46
C53
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
C52
VDL
VDL
VDL
VDL
C51
C50
0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF
C49
SN74LVCH16373A
R78
U4
NP_1kΩ
Q = OUTPUT
LE2 D = INPUT OE2
2D8
2Q8
2D7
2Q7
GND
GND
2D6
2Q6
2D5
2Q5
VCC
VCC
2D4
2Q4
2D3
2Q3
GND
GND
2D2
2Q2
2D1
2Q1
1Q8
1D8
1Q7
1D7
GND
GND
1Q6
1D6
1Q5
1D5
VCC
VCC
1Q4
1D4
1Q3
1D3
GND
GND
1Q2
1D2
1Q1
1D1
LE1
OE1
SN74LVCH16373A
R82
U2
NP_1kΩ
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
CLKLATB
25
26
27
28
29
30
VDL
31
32
33
34
35
36
37
38
39
40
41
VDL
42
43
44
45
46
47
CLKLATB
48
R81
NP_1kΩ
47Ω
RZ2
RSO16ISO
R1
1
16
2 R2
15
3 R3
14
4 R4
13
5 R5
12
6 R6
11
7 R7
10
8 R8
9
VDL
VDL
CLKLATA
CLKLATA
R83
NP_1kΩ
RZ1 47Ω
RSO16ISO
1 R1 16
2 R2 15
3 R3 14
4 R4 13
5 R5 12
6 R6 11
7 R7 10
8 R8 9
RZ4
47Ω
RSO16ISO
1 R1 16
2 R2 15
3 R3 14
4 R4 13
5 R5 12
6 R6 11
7 R7 10
8 R8 9
RZ3 47Ω
RSO16ISO
1 R1 16
2 R2 15
3 R3 14
4 R4 13
5 R5 12
6 R6 11
7 R7 10
8 R8 9
R1
R2
R3
R4
R5
R6
R7
R8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
R1
R2
R3
R4
R5
R6
R7
R8
16
15
14
13
12
11
10
9
RZ9 47Ω
RSO16ISO
1
2
3
4
5
6
7
8
RZ10 47Ω
RSO16ISO
RZ6 47Ω
RSO16ISO
1 R1 16
2 R2 15
3 R3 14
4 R4 13
5 R5 12
6 R6 11
7 R7 10
8 R8 9
RZ5 47Ω
RSO16ISO
1 R1 16
2 R2 15
3 R3 14
4 R4 13
5 R5 12
6 R6 11
7 R7 10
8 R8 9
D6Q
D5Q
D4Q
D3Q
D2Q
D1Q
D0Q
DORQ
D13Q
D12Q
D11Q
D10Q
D9Q
D8Q
D7Q
D6P
D5P
D4P
D3P
D2P
D1P
D0P
DORP
D13P
D12P
D11P
D10P
D9P
D8P
D7P
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
P3
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
P8
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
39
HEADER40
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
HEADER40
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
DRB
GND
D13Q
D12Q
D11Q
D10Q
D9Q
D8Q
D7Q
D6Q
D5Q
D4Q
D3Q
D2Q
D1Q
D0Q
DORQ
DRA
GND
D13P
D12P
D11P
D10P
D9P
D8P
D7P
D6P
D5P
D4P
D3P
D2P
D1P
D0P
DORP
AD9216
Figure 53. PCB Schematic (3 of 3)
Rev. A | Page 30 of 40
04775-040
C61
NP_0.1µF
R31
499Ω
–5V
NC
+IN
R24
NP_40Ω
9
R71
1kΩ
R72
1kΩ
–IN
AD8139
+OUT
V+
VOCM
EPAD
V–
5
–OUT
6
7
8
R29
NP_499Ω
AMPOUTB
C34
0.1µF
C64
1µF
R14
50Ω
AMPINB
J5
CLOCK A/B
VCLK
R30
NP_40Ω
C35
0.1µF
+5V
C65
0.1µF
R76
22Ω
R80
22Ω
0.1µF
9
8
14
13
12
11
10
R26
499Ω
C20
R28
1kΩ
VD
R27
1kΩ
R25
525Ω
VCLK
CLKB
CLKA
AMPOUTBB
U12
4
3
2
1
R73
1kΩ
R77
1kΩ
U8
74VCX86
1A
1B
1Y
1
2
3
4
5
6
7
C60
NP_0.1µF
C15
NP_0.1µF
SINGLE CLOCK PATH
VCC
4B
4A
2A
2B
3B
4Y
2Y
GND
3A
3Y
R15
499Ω
–5V
R79
22Ω
ENCB
9
VD
–IN
AD8139
+OUT
V+
VOCM
EPAD
–OUT
V–
NC
R23
NP_40Ω
5
6
7
8
E19
CLKA
CLKB
SCLK
MUX1
R20
0Ω
R53
0Ω
R84
NP_0Ω
R35
NP_0Ω
C32
0.1µF
+5V
R21
1kΩ
R22
NP_40Ω
AMPOUTA
U11
4
3
2
1
VD
R16
NP_499Ω
AMPINA
0.1µF
R18
499Ω
C21
R19
1kΩ
C59
0.1µF
TIEA
TIEB
MUX1
MUX
SINGLE CLOCK CIRCUIT
TO TIE CLOCKS TOGETHER
OP AMP INPUT OFF PIN ONE OF TRANSFORMER
+IN
R75
1kΩ
E11
R40
0Ω
R17
525Ω
ENCA
AMPOUTAB
C33
0.1µF
SCLK
R85
0Ω
E49
E61
AD9216
AD9216
04775–041
LFCSP PCB LAYERS
Figure 54. PCB Top-Side Silkscreen
Rev. A | Page 31 of 40
04775–042
AD9216
Figure 55. PCB Top-Side Copper Routing
Rev. A | Page 32 of 40
04775–043
AD9216
Figure 56. PCB Ground Layer
Rev. A | Page 33 of 40
04775–044
AD9216
Figure 57. PCB Split Power Plane
Rev. A | Page 34 of 40
04775–045
AD9216
Figure 58. PCB Bottom-Side Copper Routing
Rev. A | Page 35 of 40
04775–046
AD9216
Figure 59. PCB Bottom-Side Silkscreen
Rev. A | Page 36 of 40
AD9216
The AD9216 LFCSP package has an integrated heat slug that
improves the thermal and electrical properties of the package
when locally attached to a ground plane at the PCB. A thermal
(filled) via array to a ground plane beneath the part provides
a path for heat to escape the package, lowering junction
temperature. Improved electrical performance also results
from the reduction in package parasitics due to proximity
of the ground plane. Recommended array is 0.3 mm vias
on 1.2 mm pitch. θJA = 26.4°C/W with this recommended
configuration. Soldering the slug to the PCB is a requirement for this package.
Rev. A | Page 37 of 40
04775-047
THERMAL CONSIDERATIONS
Figure 60. Thermal Via Array
AD9216
OUTLINE DIMENSIONS
9.00
BSC SQ
0.60 MAX
0.60 MAX
1
PIN 1
INDICATOR
*4.85
8.75
BSC SQ
TOP
VIEW
EXPOSED PAD
4.70 SQ
4.55
(BOTTOM VIEW)
0.45
0.40
0.35
12° MAX
64
49
48
PIN 1
INDICATOR
1.00
0.85
0.80
0.30
0.25
0.18
16
17
33
32
7.50
REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
0.50 BSC
SEATING
PLANE
0.20 REF
*COMPLIANT TO JEDEC STANDARDS MO-220-VMMD
EXCEPT FOR EXPOSED PAD DIMENSION
Figure 61. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 × 9 mm Body, Very Thin Quad (CP-64-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9216BCPZ-651
AD9216BCPZRL7-651
AD9216BCPZ-801
AD9216BCPZRL7-801
AD9216BCPZ-1051
AD9216BCPZRL7-1051
AD9216-80PCB2
AD9216-105PCB
1
2
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
64-Lead Lead Frame Chip Scale Package (LFCSP-VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP-VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP-VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP-VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP-VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP-VQ)
Evaluation Board with AD9216BCPZ-80
Evaluation Board with AD9216BCPZ-105
Z = Pb-free part.
Supports AD9216-65 and AD9216-80 Evaluation.
Rev. A | Page 38 of 40
Package Option
CP-64-1
CP-64-1
CP-64-1
CP-64-1
CP-64-1
CP-64-1
AD9216
NOTES
Rev. A | Page 39 of 40
AD9216
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04775–0–6/05(A)
Rev. A | Page 40 of 40
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