AD9218-65PCB

a FEATURES Dual 10-Bit, 40 MSPS, 65 MSPS, 80 MSPS, and 105 MSPS ADC Low Power: 275 mW at 105 MSPS per Channel On-Chip Reference and Track/Holds 300 MHz Analog Bandwidth Each Channel SNR = 57 dB @ 41 MHz, Encode = 80 MSPS 1 V p-p or 2 V p-p Analog Input Range Each Channel Single 3.0 V Supply Operation (2.7 V–3.6 V) Power-Down Mode for Single Channel Operation Two’s Complement or Offset Binary Output Mode Output Data Alignment Mode Pin-Compatible with 8-Bit AD9288 –75 dBc Crosstalk between Channels APPLICATIONS Battery-Powered Instruments Hand-Held Scopemeters Low Cost Digital Oscilloscopes I and Q Communications Ultrasound Equipment 10-Bit, 40/65/80/105 MSPS 3 V Dual A/D Converter AD9218 FUNCTIONAL BLOCK DIAGRAM ENCODE A AINA T/H AINA REFINA REFOUT REFINB AINB T/H AINB ENCODE B TIMING ADC 10 REF ADC 10 TIMING AD9218 OUTPUT REGISTER D9A–D0A USER SELECT #1 USER SELECT #2 DATA FORMAT/ GAIN OUTPUT REGISTER 10 D9B–D0B 10 VD GND VDD GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD9218 is a dual 10-bit monolithic sampling analog-todigital converter with on-chip track-and-hold circuits and is optimized for low cost, low power, small size and ease of use. The product operates at a 105 MSPS conversion rate with outstanding dynamic performance over its full operating range. Each channel can be operated independently. The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power supply and an encode clock for full operation. No external reference or driver components are required for many applications. The digital outputs are TTL/CMOS-compatible and a separate output power supply pin supports interfacing with 3.3 V or 2.5 V logic. The clock input is TTL/CMOS-compatible and the 10-bit digital outputs can be operated from 3.0 V (2.5 V to 3.6 V) supplies. User-selectable options are available to offer a combination of power-down modes, digital data formats and digital data timing schemes. In power-down mode, the digital outputs are driven to a high-impedance state. Fabricated on an advanced CMOS process, the AD9218 is available in a 48-lead surface-mount plastic package (7 × 7 mm LQFP) specified over the industrial temperature range (–40°C to +85°C). Low Power—Just 275 mW power dissipation per channel at 105 MSPS. Other speed grade proportionally scaled down while maintaining high ac performance. Pin Compatibility Upgrade—Allows easy migration from 8-bit to 10-bit. Pin-compatible with the 8-bit AD9288 dual ADC. Ease of Use—On-chip reference and user controls provide flexibility in system design. High Performance—Maintain 54 dB SNR at 105 MSPS with a Nyquist input. Channel Crosstalk—Very low at –75 dBc. R EV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 AD9218–SPECIFICATIONS DC SPECIFICATIONS (V Parameter DD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.) Temp Test Level Min AD9218BST-40/-65 Typ Max Min AD9218BST-80/-105 Typ Max Unit RESOLUTION ACCURACY No Missing Codes1 Offset Error2 Gain Error2 Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error2 Reference REFERENCE Internal Reference Voltage (REFOUT) Input Resistance (REFIN A, B) ANALOG INPUTS Differential Input Voltage Range (AIN, AIN)3 Common-Mode Voltage Input Resistance Input Capacitance POWER SUPPLY VD VDD Supply Currents IVD (VD = 3.0 V)4 IVDD (VDD = 3.0 V)4 Power Dissipation DC5 IVD Power-Down Current6 Power Supply Rejection Ratio Full 25°C 25°C 25°C Full 25°C Full Full Full Full 25°C Full Full Full Full 25°C Full Full Full 25°C Full Full 25°C VI I I I VI I VI V V V I V V V VI V IV IV VI V VI VI I 1.18 9 10 GNT 2 18 3 8 ± 0.3/± 0.6 1/1.3 1/1.6 10 GNT 2 3.5 ± 0.5/± 0.8 Bits –18 –2 –1 –18 –2 –1 18 8 1.2/1.7 LSB % FS LSB LSB LSB LSB ppm/°C ppm/°C ppm/°C ± 0.8 –1/–1.6 ± 0.3/± 1 ±1 10 80 40 1.24 11 1 or 2 VD/3 10 3 3 3 108/117 7/11 325/350 20 ±1 ± 0.6/± 0.9 –1.35/–2.7 ± 0.75/± 2 ± 1/± 2.3 4 100 40 1.35/2.7 1.28 13 1.18 9 1.24 11 1 VD/3 10 3 3 3 172/183 13/17 515/550 22 ±1 1.28 13 V kΩ V V kΩ pF V V mA mA mW mA mV/V 8 14 8 14 2.7 2.7 3.6 3.6 113/122 340/365 2.7 2.7 3.6 3.6 175/188 525/565 NOTES 1 No Missing Codes across industrial temperature range guaranteed for -40 MSPS, -65 MSPS, and -80 MSPS grades. No missing codes at room temperature guaranteed for -105 grade. 2 Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1.25 V external reference) -65 Grade in 2 V p-p range, -40, -85, -105 Grades in 1 V p-p range. 3 (AIN – AIN) = ± 0.5 V in 1 V range (full scale), (AIN – AIN) = ± 1 V in 2 V range (full scale). 4 AC Power Dissipation measured with rated encode and a 10.3 MHz analog input @ 0.5 dBFS, C LOAD = 5 pF. 5 DC Power Dissipation measured with rated encode and a dc analog input (Outputs Static, IV DD = 0) 6 In power-down state IV DD = ± 10 µA typical (all grades). Specifications subject to change without notice. –2– REV. 0 AD9218 DIGITAL SPECIFICATIONS Parameter DIGITAL INPUTS Encode Input Common Mode Encode “1” Voltage Encode “0” Voltage Encode Input Resistance Logic “1” Voltage—S1, S2, DFS Logic “0” Voltage—S1, S2, DFS Logic “1” Current—S1 Logic “0” Current—S1 Logic “1” Current—S2 Logic “0” Current—S2 Logic “1” Current—DFS Logic “0” Current—DFS Input Capacitance—S1, S2, Encode Inputs Input Capacitance DFS DIGITAL OUTPUTS Logic “1” Voltage Logic “0” Voltage Output Coding Specifications subject to change without notice. (VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.) Test Temp Level Full Full Full Full Full Full Full Full Full Full Full Full 25°C 25°C Full Full V VI VI VI VI VI VI VI VI VI VI VI V V VI VI AD9218BST-40/-65 Min Typ Max VD/2 2 1.8 2 –50 –400 50 –50 30 –400 2.0 ± 10 –230 230 ± 10 100 –230 2 4.5 0.8 2.3 0.8 +50 –50 400 +50 200 –50 2 1.8 2 –50 –400 50 –50 30 –400 2.0 ± 10 –230 230 ± 10 100 –230 2 4.5 0.8 2.3 0.8 +50 –50 400 +50 200 –50 Min AD9218BST-80/-105 Typ Max VD/2 Unit V V V kΩ V V µA µA µA µA µA µA pF pF V V 2.45 0.05 Two’s Comp. or Offset Binary 2.45 0.05 Two’s Comp. or Offset Binary AC SPECIFICATIONS Parameter 1 (VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.) Temp Test Level AD9218BST-40/-65 Min Typ Max AD9218BST-80/-105 Min Typ Max Unit DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) (Without Harmonics) fIN = 10.3 MHz fIN = Nyquist2 Signal-to-Noise Ratio (SINAD) (With Harmonics) fIN = 10.3 MHz fIN = Nyquist2 Effective Number of Bits fIN = 10.3 MHz fIN = Nyquist2 Second Harmonic Distortion fIN = 10.3 MHz fIN = Nyquist2 Third Harmonic Distortion fIN = 10.3 MHz fIN = Nyquist2 Spurious Free Dynamic Range SFDR fIN = 10.3 MHz fIN = Nyquist2 Two-Tone Intermod Distortion (IMD) fIN1 = 10 MHz, fIN2 = 11 MHz at –7 dBFS fIN1 = 30 MHz, fIN2 = 31 MHz at –7 dBFS Analog Bandwidth, Full Power Crosstalk 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C I I 58/55 -/54 59/57 59/56 57/53 55/52 58/55 57/54 dB dB I I I I I I I I I I V V V V 58/54 -/53 9.4/8.8 -/8.6 –72/–66 -/–63 –68/–62 -/–60 –68/–62 -/–60 59/56 59/55 9.6/9.1 9.6/8.9 –89/–77 –89/–72 –79/–68 –78/–64 –79/–67 –78/–64 –74/–73 –73/–73 300 –75 56/52 55/51 9.1/8.4 9/8.3 –69/–60 –65/–57 –62/–57 –63/–57 –62/–57 –63/–57 58/53 57/53 9.4/8.6 9.3/8.6 –77/–68 –76/–66 –71/–63 –73/–69 –69/–62 –70/–63 dB dB Bits Bits dBc dBc dBc dBc dBc dBc dBc –77/–67 300 –75 dBc MHz dBc NOTES 1 AC specs based on an analog input voltage of –0.5 dBFS at 10.3 MHz unless otherwise noted. AC specs for -40, -80, -105 grades are tested in 1 V p-p range and driven differentially. AC specs for -65 grade are tested in 2 V p-p range and driven differentially. 2 The -65, -80, and -105 grades are tested close to Nyquist for that grade: 31 MHz, 39 MHz, and 51 MHz for the -65, -80, and -105 grades respectively. Specifications subject to change without notice. REV. 0 –3– AD9218–SPECIFICATIONS SWITCHING SPECIFICATIONS (V Parameter ENCODE INPUT PARAMETERS Maximum Encode Rate Minimum Encode Rate Encode Pulsewidth High (tEH) Encode Pulsewidth Low (tEL) Aperture Delay (tA) Aperture Uncertainty (Jitter) DIGITAL OUTPUT PARAMETERS Output Valid Time (tV)* Output Propagation Delay (tPD)* Output Rise Time (tR) Output Fall Time (tF) Out of Range Recovery Time Transient Response Time Recovery Time from Power-Down Pipeline Delay DD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted.) Test Level VI IV IV IV V V VI VI V V V V V IV AD9218BST-40/-65 Min Typ Max 40/65 20/20 7/6 7/6 2 3 3 4.5 1 1.2 5 5 10 5 7 3 4.5 1.0 1.2 5 5 10 5 6 5/3.8 5/3.8 2 3 AD9218BST-80/-105 Min Typ Max 80/105 20/20 Unit MSPS MSPS ns ns ns ps rms ns ns ns ns ns ns Cycles Cycles Temp Full Full Full Full 25°C 25°C Full Full 25°C 25°C 25°C 25°C 25°C Full NOTES *tV and t PD are measured from the 1.5 level of the ENCODE input to the 50%/50% levels of the digital outputs swing. The digital output load during test is not to exceed an ac load of 5 pF or a dc current of ± 40 µA. Rise and fall times measured from 10% to 90%. Specifications subject to change without notice. SAMPLE N+1 SAMPLE N+5 SAMPLE N+6 SAMPLE N AINA, AINB tA t EH ENCODE A&B t EL SAMPLE N+2 1/fS SAMPLE N+3 SAMPLE N+4 t PD D9A–D0A DATA N–5 DATA N–4 DATA N–3 DATA N–2 DATA N–1 DATA N tV D9B–D0B DATA N–5 DATA N–4 DATA N–3 DATA N–2 DATA N–1 DATA N Figure 1. Normal Operation, Same Clock (S1 = 1, S2 = 0) Channel Timing –4– REV. 0 AD9218 SAMPLE N AINA, AINB SAMPLE SAMPLE N+2 N+1 SAMPLE SAMPLE N+7 N+8 tA t EH ENCODE A t EL SAMPLE SAMPLE SAMPLE SAMPLE N+3 N+4 N+5 N+6 1/fS t PD ENCODE B tV D9A–D0A DATA N–10 DATA N–8 DATA N–6 DATA N–4 DATA N–2 DATA N DATA N+2 D9B–D0B DATA N–9 DATA N–7 DATA N–5 DATA N–3 DATA N–1 DATA N+1 Figure 2. Normal Operation with Two Clock Sources (S1 = 1, S2 = 0) Channel Timing SAMPLE N AINA, AINB SAMPLE SAMPLE N+2 N+1 SAMPLE SAMPLE N+7 N+8 tA t EH ENCODE A t EL SAMPLE SAMPLE SAMPLE SAMPLE N+3 N+4 N+5 N+6 1/fS t PD ENCODE B tV D9A–D0A DATA N–10 DATA N–8 DATA N–6 DATA N–4 DATA N–2 DATA N DATA N+2 D9B–D0B DATA N–11 DATA N–9 DATA N–7 DATA N–5 DATA N–3 DATA N–1 DATA N+1 Figure 3. Data Align with Two Clock Sources (S1 = 1, S2 = 1) Channel Timing REV. 0 –5– AD9218 ABSOLUTE MAXIMUM RATINGS 1 VD, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V Analog Inputs . . . . . . . . . . . . . . . . . . . . –0.5 V to VD + 0.5 V Digital Inputs . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V REFIN Inputs . . . . . . . . . . . . . . . . . . . . . –0.5 V to VD + 0.5 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature . . . . . . . . . . . . . . . . –55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C Maximum Case Temperature . . . . . . . . . . . . . . . . . . . . 150°C θJA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. 2 Measured on a four-layer board with solid ground plane. EXPLANATION OF TEST LEVELS Test Level I 100% production tested. II 100% production tested at 25°C and sample tested at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at 25° C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9218 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ORDERING GUIDE Model AD9218BST-40, -65, -80, -105 AD9218-65PCB AD9218-105PCB Temperature Range –40°C to +85°C 25°C 25°C Package Description Metric Quad Flat Pack (1.4 mm thick: LQFP) Evaluation Board (Supports -40/-65 Grade) Evaluation Board (Supports -80/-105 Grade) Package Option ST-48 Table I. User Select Modes S1 0 0 1 1 S2 0 1 0 1 User Select Options Power-Down Both Channel A and B. Power-Down Channel B Only. Normal Operation (Data Align Disabled). Data Align Enabled (data from both channels available on rising edge of Clock A. Channel B data is delayed by a 1/2 clock cycle.) –6– REV. 0 AD9218 PIN FUNCTION DESCRIPTIONS Pin No. 1, 12, 16, 27, 29, 32, 34, 45 2 3 4 Mnemonic GND AINA AINA DFS/GAIN Description Ground Analog Input for Channel A Analog Input for Channel A (Complementary) Data Format Select and Analog Input Gain Mode. (Low = offset binary output available, 1 V p-p supported; high = two’s complement output available, 1 V p-p supported; floating = offset binary output available, 2 V p-p supported; Set to VREF = two’s complement output available, 2 V p-p supported.) Reference Voltage Input for Channel A Internal Reference Voltage Reference Voltage Input for Channel B User Select #1 (Refer to Table I) User Select #2 (Refer to Table I) Analog Input for Channel B (Complementary) Analog Input for Channel B Analog Supply (3 V) Clock Input for Channel B Digital Supply (2.5 V to 3.6 V) Digital Output for Channel B (D9B = MSB) Digital Output for Channel A (D9A = MSB) Clock Input for Channel A 5 6 7 8 9 10 11 13, 30, 31, 48 14 15, 28, 33, 46 17–26 35–44 47 REFINA REFOUT REFINB S1 S2 AINB AINB VD ENCB VDD D9B–D0B D0A–D9A ENCA PIN CONFIGURATION GND D9A (MSB) ENCA D8A D7A D6A D5A D4A D3A 48 47 46 45 44 43 42 41 40 39 38 37 GND 1 AINA 2 AINA 3 DFS/GAIN 4 REFINA 5 REFOUT 6 REFINB 7 S1 8 S2 9 AINB 10 AINB 11 GND 12 D2A VDD VD PIN 1 IDENTIFIER 36 35 34 33 D1A D0A GND VDD GND VD VD GND VDD GND D0B D1B AD9218 TOP VIEW (Not to Scale) 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 GND (MSB) D9B VD VDD D8B D7B D6B D5B D4B D3B REV. 0 ENCB –7– D2B AD9218 TERMINOLOGY Analog Bandwidth Harmonic Distortion, Second The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc. Harmonic Distortion, Third The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc. Integral Nonlinearity The delay between the 50% point of the rising edge of the ENCODE command and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a “best straight line” determined by a least square curve fit. Minimum Conversion Rate The sample-to-sample variation in aperture delay. Crosstalk Coupling onto one channel being driven by a low level (–40 dBFS) signal when the adjacent interfering channel is driven by a full-scale signal. Differential Analog Input Resistance, Differential Analog Input Capacitance and Differential Analog Input Impedance The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The encode rate at which parametric testing is performed. Output Propagation Delay The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. Differential Analog Input Voltage Range The delay between a differential crossing of ENCODE and ENCODE and the time when all output data bits are within valid logic levels. Noise (for Any Range within the ADC) The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 degrees out of phase. Peak-to-peak differential is computed by rotating the inputs phase 180 degrees and again taking the peak measurement. The difference is then computed between both peak measurements. Differential Nonlinearity VNOISE = Z × 0.001 × 10  FSdBm −SNRdBc −Signal dBFS     10 Where Z is the input impedance, FS is the full scale of the device for the frequency in question, SNR is the value for the particular input level, and Signal is the signal level within the ADC reported in dB below full scale. This value includes both thermal and quantization noise. Power Supply Rejection Ratio The deviation of any code width from an ideal 1 LSB step. Effective Number of Bits The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise-and-Distortion (SINAD) The effective number of bits (ENOB) is calculated from the measured SNR based on the equation: ENOB = SNRMEASURED – 1.76 dB 6.02 The ratio of the rms signal amplitude (set 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc. Signal-to-Noise Ratio (without Harmonics) ENCODE Pulsewidth/Duty Cycle Pulsewidth high is the minimum amount of time that the ENCODE pulse should be left in Logic 1 state to achieve rated performance; pulsewidth low is the minimum time ENCODE pulse should be left in low state. See timing implications of changing tENCH in text. At a given clock rate, these specifications define an acceptable ENCODE duty cycle. Full-Scale Input Power The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal level is lowered), or dBFS (always related back to converter full scale). Two-Tone Intermodulation Distortion Rejection Expressed in dBm. Computed using the following equation: PowerFull −Scale  V 2 Full −Scale rms  Z INPUT = 10 log  0.001          The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBc. Two-Tone SFDR Gain Error Gain error is the difference between the measured and ideal full scale input voltage range of the ADC. The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal level is lowered), or in dBFS (always related back to converter full scale). –8– REV. 0 AD9218 Worst Other Spur VD The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic) reported in dBc. Transient Response Time REF 10k Transient response is defined as the time it takes for the ADC to reacquire the analog input after a transient from 10% above negative full scale to 10% below positive full scale. Out-of-Range Recovery Time Out of range recovery time is the time it takes for the ADC to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. EQUIVALENT CIRCUITS Figure 8. Reference Inputs VD S2 VD 10k 30k 40 15k 15k 30k 40 AIN AIN Figure 9. S2 Input VD Figure 4. Analog Input Stage 10k VD 2.6k S1 ENCODE 600 Figure 10. S1 Input 2.6k VD Figure 5. Encode Inputs DFS/GAIN 15k VD 15k VREF OUT Figure 11. DFS/Gain Input Figure 6. Reference Output Stage VDD 40 DX Figure 7. Digital Output Stage REV. 0 –9– AD9218 –Typical Performance Characteristics 0 –10 –20 –30 –40 dB 0 ENCODE = 105MSPS AIN = 50.1MHz AT –0.5dBFS SNR = 53.8dB SINAD = 53.4dB H2 = –69dB H3 = –65.8dB dB –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 ENCODE = 40MSPS AIN = 19.75 MHz AT –0.5dBFS SNR = 58.4dB SINAD = 58.3dB H2 = –87dB H3 = –81dB –50 –60 –70 –80 –90 –100 0 52.5 0 20 TPC 1. FFT: FS = 105 MSPS, AIN = 50.1 MHz @ –0.5 dBFS, Differential, 1 V p-p Input Range TPC 4. FFT: FS = 40 MSPS, AIN = 19.7 MHz @ –0.5 dBFS, Differential, 1 V p-p Input Range 0 –10 –20 –30 –40 dB 0 ENCODE = 80MSPS AIN = 39MHz AT –0.5dBFS SNR = 56.1dB SINAD = 55.5dB H2 = –71.8dB H3 = –66.2dB –10 –20 –30 –40 dB –50 –60 –70 –80 –90 –100 0 40 0 40 ENCODE = 105MSPS AIN = 70MHz AT –0.5dBFS SNR = 51.9dB SINAD = 51.8dB H2 = –70.5dB H3 = –76.3dB –50 –60 –70 –80 –90 –100 TPC 2. FFT: FS = 80 MSPS, AIN = 39 MHz @ –0.5 dBFS, Differential, 1 V p-p Input Range TPC 5. FFT: FS = 105 MSPS, AIN = 70 MHz @ –0.5 dBFS, Differential, 1 V p-p Input Range 0 –10 –20 –30 –40 dB –50 –60 –70 –80 –90 –100 0 32.5 ENCODE = 65MSPS AIN = 30.3MHz AT –0.5dBFS SNR = 56.1dB SINAD = 55.9dB SFDR = 72dB H2 = –83.2dB H3 = –79dB 0 –10 –20 –30 –40 ENCODE = 65MSPS AIN = 15MHz AT –0.5dBFS SNR = 56.4dB SINAD = 55.9dB H2 = –73.9dB H3 = –71.7dB dB –50 –60 –70 –80 –90 –100 0 32.5 TPC 3. FFT: FS = 65 MSPS, AIN = 30.3 MHz @ –0.5 dBFS, Differential, 2 V p-p Input Range TPC 6. FFT: FS = 65 MSPS, AIN = 15 MHz @ –0.5 dBFS; with AD8138 Driving ADC Inputs, 1 V p-p Input Range –10– REV. 0 AD9218 0 –10 –20 –30 –40 dB dB 0 ENCODE = 31MSPS AIN = 8MHz AT –0.5dBFS SNR = 59.23dB SINAD = 59.1dB H2 = –87dB H3 = –81dB –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 ENCODE = 31MSPS AIN = 8MHz AT –0.5dBFS SNR = 59dB SINAD = 58.8dB H2 = –78.7dB H3 = –72.9dB –50 –60 –70 –80 –90 –100 0 15.5 15.5 TPC 7. FFT: FS = 31 MSPS, AIN = 8 MHz @ –0.5 dBFS, Differential, 1 V p-p Input Range TPC 10. FFT: FS = 31 MSPS, AIN = 8 MHz @ –0.5 dBFS; with AD8138 Driving ADC Inputs, 1 V p-p Input Range 80 75 70 65 60 dB 0 2ND 3RD –10 –20 –30 –40 ENCODE = 105MSPS AIN1 = 30.1MHz AT –7dBFS AIN 2 = 31.1MHz AT –7dBFS SFDR = –67dBFS SFDR dB 55 50 45 40 35 30 –50 –60 –70 –80 –90 –100 0 50 100 150 AIN FREQUENCY – MHz 200 250 0 52.5 TPC 8. Harmonic Distortion (Second and Third) and SFDR vs. AIN Frequency (1 V p-p, FS = 105 MSPS) TPC 11. Two–Tone Intermodulation Distortion (30 MHz and 31 MHz; 1 V p-p, FS = 105 MSPS) 80 75 70 65 60 SFDR dB dB 0 3RD 2ND –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 ENCODE = 80MSPS AIN1 = 29.3MHz AT –7dBFS AIN 2 = 30.3MHz AT –7dBFS SFDR = –77dBFS 55 50 45 40 35 30 0 50 100 150 AIN FREQUENCY – MHz 200 250 40 TPC 9. Harmonic Distortion (Second and Third) and SFDR vs. AIN Frequency (1 V p-p, FS = 80 MSPS) TPC 12. Two–Tone Intermodulation Distortion (29.3 MHz, 30.3 MHz; 1 V p-p, FS = 80 MSPS) REV. 0 –11– AD9218 90 80 H3 1V 70 –30 0 H2 1V 1V DIFFERENTIAL DRIVE –10 –20 ENCODE = 65MSPS AIN1 = 28.1MHz AT –7dBFS AIN 2 = 29.1MHz AT –7dBFS SFDR = –72.9dBFS 60 dB SFDR 1V dB –40 –50 –60 –70 H2 2V 50 40 30 20 10 SFDR 2V H3 2V –80 2V SINGLE-ENDED DRIVE –90 –100 0 20 40 60 80 100 120 140 160 180 0 32.5 AIN FREQUENCY – MHz TPC 13. Harmonic Distortion (Second and Third) and SFDR vs. AIN Frequency (FS = 65 MSPS) TPC 16. Two-Tone Intermodulation Distortion (28 MHz, 29 MHz; 1 V p-p, FS = 65 MSPS) 90 85 2nd 80 75 dB 0 –10 –20 –30 –40 ENCODE = 40MSPS AIN1 = 10MHz AT –7dBFS AIN2 = 11MHz AT –7dBFS SFDR = 74dBc 3rd SFDR 70 65 60 55 50 10 dB –50 –60 –70 –80 –90 20 30 40 50 AIN FREQUENCY – MHz 60 70 –100 0 20 TPC 14. Harmonic Distortion (Second and Third) and SFDR vs. AIN Frequency (1 V p-p, FS = 40 MSPS) TPC 17. Two–Tone Intermodulation Distortion (10 MHz, 11 MHz; 1 V p-p, FS = 40 MSPS) 75 80 SFDR 75 SFDR 70 70 65 65 dB 60 SINAD 55 dB 60 55 SNR 50 50 45 0 20 40 60 80 ENCODE RATE – MSPS 100 120 SINAD 45 0 10 20 30 40 50 60 70 80 ENCODE RATE – MHz TPC 15. SINAD and SFDR vs. Encode Rate (fIN = 10.3 MHz, 105 MSPS Grade) AIN = –0.5 dBFS Differential, 1 V p-p Analog Input Range TPC 18. SINAD and SFDR vs. Encode Rate (AIN = 10.3 MHz, 65 MSPS Grade) AIN = –0.5 dBFS Differential, 1 V p-p Analog Input Range –12– REV. 0 AD9218 75 70 SFDR 65 65 75 SFDR 70 60 55 dB 60 dB SINAD 55 50 45 40 50 45 SINAD 40 35 30 0 1 2 3 4 5 6 ENCODE POSITIVE PULSEWIDTH – ns 7 8 0 2 4 6 8 10 12 ENCODE POSITIVE PULSEWIDTH – ns 14 TPC 19. SINAD and SFDR vs. Encode Pulsewidth High. AIN = –0.5 dBFS Single-Ended, 1 V p-p Analog Input Range 105 MSPS TPC 22. SINAD and SFDR vs. Encode Pulsewidth High. AIN = –0.5 dBFS Single Ended, 1 V p-p Analog Input Range 65 MSPS 200 50 45 4.5 180 IVD -105 160 40 35 IVDD mA 4.0 GAIN -105 30 mA 3.5 25 20 % 3.0 140 GAIN -65 120 IVD -65 -65/-105 IVDD 100 15 10 5 80 0 20 40 60 80 100 ENCODE CLOCK RATE – MSPS 120 0 140 2.0 –40 2.5 –20 0 20 40 TEMPERATURE – C 60 80 TPC 20. IVD and IVDD vs. Encode Rate (AIN = 10.3 MHz, @ –0.5 dBFS). -65/-105 MSPS Grade Cl = 5 pF TPC 23. Gain Error vs. Temperature. AIN = 10.3 MHz, -65 MSPS Grade, -105 MSPS Grade, 1 V p-p 68 1.231 1.229 1.227 1.225 1.223 1.221 1.119 66 64 SFDR -65 SFDR -105 62 dB V 60 58 56 SNR -65 SINAD -65 SNR -105 54 SINAD -105 52 –40 –40 –20 0 20 40 TEMPERATURE – C 60 80 –20 0 20 40 TEMPERATURE – C 60 80 TPC 21. VREF Output Voltage vs. Temperature (ILOAD = 300 µ A) TPC 24. SNR, SINAD, SFDR vs. Temperature. AIN = 10.3 MHz , -65 MSPS Grade, -105 MSPS Grade, 1 V p-p REV. 0 –13– AD9218 1.50 1.45 1.40 1.35 1.30 50 90 SFDR – dBFS 80 70 60 SFDR – dBc 1.25 1.20 1.15 1.10 1.05 1.00 –1.0 –0.5 0 0.5 1.0 ILOAD – mA 1.5 2.0 2.5 dB 40 30 20 10 0 –60 SNR – dBc –50 –40 –30 –20 AIN INPUT LEVEL – dBFS –10 0 70 dB REF LINE V TPC 25. VREF vs. ILOAD TPC 27. SFDR vs. AIN Input Level. 10.3 MHz AIN @ 80 MSPS 2.0 1.5 1.0 1.0 0.8 0.6 0.4 0.5 LSB LSB 0.2 0 –0.2 –0.4 0 –0.5 –1.0 –0.6 –1.5 –2.0 0 CODES 1024 –0.8 –1.0 0 CODES 1024 TPC 26. Typical INL Plot. 10.3 MHz AIN @ 80 MSPS TPC 28. Typical DNL Plot. 10.3 MHz AIN @ 80 MSPS –14– REV. 0 AD9218 THEORY OF OPERATION 500 50 ANALOG SIGNAL SOURCE 10k 0.1 F 5k 525 500 AVDD VOCM AD8138 25 500 25 15pF AIN The AD9218 ADC architecture is a bit-per-stage pipeline-type converter utilizing switch capacitor techniques. These stages determine the 7 MSBs and drive a 3-bit flash. Each stage provides sufficient overlap and error correction allowing optimization of comparator accuracy. The input buffers are differential, and both sets of inputs are internally biased. This allows the most flexible use of ac-coupled or dc-coupled and differential or single-ended input modes. The output staging block aligns the data, carries out the error correction, and feeds the data to output buffers. The set of output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. There is no discernible difference in performance between the two channels. USING THE AD9218 ENCODE Input AD9218 AIN Figure 13. Using the AD8138 to Drive the AD9218 Voltage Reference Any high-speed A/D converter is extremely sensitive to the quality of the sampling clock provided by the user. A Track/ Hold circuit is essentially a mixer. Any noise, distortion, or timing jitter on the clock will be combined with the desired signal at the A/D output. For that reason, considerable care has been taken in the design of the ENCODE input of the AD9218, and the user is advised to give commensurate thought to the clock source. The ENCODE input is fully TTL/CMOS-compatible. Digital Outputs A stable and accurate 1.25 V voltage reference is built into the AD9218 (VREF OUT). In normal operation, the internal reference is used by strapping Pin 5 (REFINA) and Pin 7 (REFINB) to Pin 6 (REFOUT). The input range for each channel can be adjusted independently by varying the reference voltage inputs applied to the AD9218. No appreciable degradation in performance occurs when the reference is adjusted ± 5%. The full-scale range of the ADC tracks reference voltage, which changes linearly. Timing The digital outputs are TTL/CMOS-compatible for lower power consumption. During power-down, the output buffers transition to a high impedance state. A data format selection option supports either two’s complement (set high) or offset binary output (set low) formats. Analog Input The AD9218 provides latched data outputs, with five pipeline delays. Data outputs are available one propagation delay (tPD) after the rising edge of the encode command (see Timing Diagram). The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9218. These transients can detract from the converter’s dynamic performance. The minimum guaranteed conversion rate of the AD9218 is 20 MSPS. At clock rates below 20 MSPS, dynamic performance will degrade. User Select Options The analog input to the AD9218 is a differential buffer. For best dynamic performance, impedance at AIN and AIN should match. Special care was taken in the design of the analog input section of the AD9218 to prevent damage and corruption of data when the input is overdriven. The nominal input range is 1.024 V p-p. Optimum performance is obtained when the part is driven differentially where common mode noise is minimized and even order harmonics are reduced. An example of driving the AD9218 differentially via a wideband RF transformer for ac-coupled applications is shown in Figure 12. Applications that require dc-coupled differential drive can be accommodated using the AD8138 differential output op amp, shown in Figure 13. AIN 50 ANALOG SIGNAL SOURCE 1:1 25 0.1 F Two pins are available for a combination of operational modes. These options allow the user to power-down both channels, excluding the reference, or just the B channel. Both modes place the output buffers in a high impedance state. Recovery from a power-down state is accomplished in 10 clock cycles following power-on. The other option allows the user to skew the B Channel output data by one-half a clock cycle. In other words, if two clocks are fed to the AD9218 and are 180 degrees out of phase, enabling the data align will allow Channel B output data to be available at the rising edge of Clock A. If the same encode clock is provided to both channels and the data align pin is enabled, output data from Channel B will be 180 degrees out of phase with respect to Channel A. If the same encode clock is provided to both channels and the data align pin is disabled, both outputs are delivered on the same rising edge of the clock. AD9218 AIN 25 Figure 12. Using a Wideband Transformer to Drive the AD9218 REV. 0 –15– AD9218 APPLICATIONS The wide analog bandwidth of the AD9218 makes it attractive for a variety of high-performance receiver and encoder applications. Figure 14 shows the dual ADC in a typical low cost I and Q demodulator implementation for cable, satellite, or wireless LAN modem receivers. The excellent dynamic performance of the ADC at higher analog input frequencies and encode rates empowers users to employ direct IF sampling techniques. IF sampling eliminates or simplifies analog mixer and filter stages to reduce total system cost and power. AD9218 BPF IF IN 90 BPF I ADC Q ADC VCO VCO wideband RF transformer T1, T2, allowing the ADC performance for differential inputs to be measured using a single-ended source. In this mode resistors R35, R33, R39, and R32 should not be in place. Each analog input is terminated on the board with 50 Ω to ground. Each input is ac-coupled on the board through a 0.1 µF capacitor to an on-chip resistor divider that provides dc bias. Single-ended performance can be measured by bypassing the transformers using connectors SMB J5 (Channel A) and J1 (Channel B). In this mode, place a 0 Ω resistor at R35 and R33 (A Channel) and place R39 and R32 (B Channel). Note that the inverting analog inputs are terminated on the board with 25 Ω (optimized for differential operation). When driving the board single-ended these resistors (R1, R3) can be changed to 50 Ω to provide balanced inputs. The operational amplifier can be used by connecting to J5 (Channel A) and J1 (Channel B). The ac-coupling capacitors on the top level should be removed from the board to use the operational amplifier. The components to use the op amp should be placed on the bottom of the board. See PCB Bill of Materials list for values. Encode Figure 14. Typical I/Q Demodulation Scheme EVALUATION BOARD The AD9218 evaluation board offers an easy way to test the AD9218. It provides a means to drive the analog inputs singleendedly or differentially. Differential drive can be tested through a wideband RF transformer or a differential output operational amplifier, the AD8138. The two encode clocks are accessible via on-board SMB connectors J2, J7. These clocks are buffered on board to provide the clocks for an on-board DAC and latches. The digital outputs and output clocks are available at two 40-pin connectors, P3 and P4. The board has several different modes of operation, and is shipped in the following configuration: • Differential Analog Input (RF Transformer Mode) • Normal Operation Timing Mode • Internal Voltage Reference Power Connector The encode clock for Channel A uses SMB connector J7. Channel B encode uses SMB connector J2. Each clock input is terminated on the board with 50 Ω to ground. The input clocks are fed directly to the ADC and to buffers U5, U6, which drive the DAC and latches. The clock inputs are TTL-compatible. Voltage Reference The AD9218 has an internal 1.25 V voltage reference. An external reference for each channel may be employed instead. The evaluation board is configured for the internal reference (use jumpers E18–E1 and E17–E19). To use external references, connect to VREFA and VREFB pins on the power connector P1 and use jumpers E20–E18 and E19–E21. Normal Operation Mode In this mode both converters are clocked by the same encode clock, latency is five clock cycles (see Timing Diagram). Signal S1 (Pin 8) is held high and signal S2 (Pin 9) is held low. This is set with the jumpers labeled S1 and S2 (near the analog input). Data Align Mode Power is supplied to the board via a detachable 12-pin power strip. +5 V – Optional Supply for Operational Amplifier –5 V – Optional Supply for Operational Amplifier VREFA – Optional External Reference Input VREFB – Optional External Reference Input VDL – Supply for Support Logic and DAC VDD – Supply for ADC Outputs VD – Supply for ADC Analog Analog Inputs In this mode channel B output is delayed an additional one-half cycle. Signals S1 (Pin 8) and signal S2 (Pin 9) are both held high. This is set with the jumpers labeled S1 and S2 (near the analog input). Data Format Select The evaluation board accepts a 1 V analog input signal centered at ground at each analog input. SMB connectors J4 and J6 are used for AIN and BIN respectively. These signals each drive a Data Format Select sets the output data format and the gain of the ADC. Setting DFS (Pin 4) low sets the output format to be offset binary and gain of 1; setting DFS high sets the output to be two’s complement and gain of 1. Removing the jumper for DFS sets the output data format to offset binary and a gain of 2; setting DFS to the middle selection sets the output data format to two’s complement and a gain of 2. –16– REV. 0 AD9218 PCB Bill of Materials # 1 2 3 6 7 Qty 29 2 7 8 3 REFDES C1, C3–C15, C20–C25, C27–C35 C2, C36 C16, C17, C18, C19, C26, C37, C38 J1, J2, J3, J4, J5, J6, J7, J8 P1, P4, P11 Device Capacitor Capacitor Capacitor Connector 4-Pin Power Connector Package 0603 0603 TAJD SMB TB4 Value 0.1 µF 15 pF 10 µF Wieland 25.531.3425.0 Z5.602.5453.0 25 Ω 50 Ω 2 kΩ 500 Ω 525 Ω 4 kΩ 0Ω 1 kΩ Minicircuits 8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 2 8 10 2 6 2 2 8 2 2 1 2 1 2 4 2 P2, P3 R1–R4, R22–R24, R30 R5–R12, R34, R37 R13, R14 R15, R17, R18, R26, R29, R31 R16, R25 R19, R27 R20, R32, R33, R35, R36, R38–R40 R21, R28 T1, T2 U1 U2, U3 U4 U5, U6 U7, U8, U9, U10 U11, U12 HEADER40 Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Transformer AD9218 74LCX821 AD9763 74LCX86 Resistor Array AD8138 0603 0603 0603 0603 0603 0603 0603 0603 ADT-1-1WT LQFP48 SO24M3 LQFP48 SO14 CTS20 SO8NB 22 Ω NOTE R22, R23, R24, R30, R32, R33, R35, R36, R38, R39, R40, C2, C36 not placed on board. Data Outputs DAC Outputs The ADC digital outputs are latched on the board by two LCX821s, the latch outputs are available at the two 40-pin connectors at Pins 23–33 on P3 (Channel A) and Pins 23–33 on P4 (Channel B). The latch output clocks (data ready) are available at Pin 4 on P3 (Channel A) and Pin 4 on P4 (Channel B). The data ready signal on Channel B can be aligned with Clock A input by connecting E43–E42 or aligned with Clock B input by connecting E42–E33. Each channel is reconstructed by an on-board dual channel DAC, an AD9763. This DAC is intended to assist in debug only. It should not be used to measure the performance of the ADC. It is a current output DAC with on-board 50 Ω termination resistors. Figure 16 is representative of the DAC output with a full-scale analog input. The scope setting was low bandwidth, 50 Ω termination. PIN 37 (CLOCK) PIN 31 (DATA) T T 1 CH1 CH1 2.00V CH2 2.00V M 10.0ns CH4 40mV 500mV M 50.0ns CH1 380mV Figure 16. DAC Output Figure 15. Data Output and Clock at 80-Pin Connector REV. 0 –17– AD9218 VREFA VREFB +5V –5V VDD VDL VD DUT CLOCK SELECTABLE TO BE DIRECT OR BUFFERED C26 10 F GND E46 C37 10 F C38 10 F C16 10 F C17 10 F C18 10 F C19 10 F ENCA ENCODE A J7 VDL E45 P12 P19 GND 74LCX86 1 2 3 P14 1A 1B 1Y 2A 2B 2Y GND U8 VCC 4B 4A 4Y 3B 3A 3Y 14 12 E3 11 10 9 8 TIEA E47 R11 GND 50 GND E35 E36 E34 P13 TIEA 13 E40 C25 0.1 F VDL E41 VDL ENCA 4 5 GND CLKDACA E39 E38 E37 P11 GND 4 32 1 P1 P4 VDL 4 3 2 1 43 2 1 CLKLATA GND 6 7 VDL GND GND GND GND VREFA VREFB GND VDD GND +5V VDL –5V VD GND DRA E9 E10 E32 E31 VD VDD VDD VDL VDD OPTIONAL INPUT PATH FOR OPAMP OR SINGLE-ENDED GND GND J5 AINA SINGLE-ENDED R36 0 AMPINA GND R34 50 R35 00 R33 00 GND R1 25 AINA GND R2 25 C10 0.1 F REFOUT C9 0.1 F GND ENCA C7 0.1 F GND 48 47 46 C8 0.1 F GND GND D9A D8A D7A D6A D5A D4A D3A 38 D3A D2A D2A 37 VD 45 44 43 42 41 40 D5A VD GND D9A D8A D7A D6A ENCA D4A VDD 39 GND 1 2 GND AINA AINAB D1A D0A GND VDD GND 36 35 34 33 32 31 30 29 28 27 26 25 D1A D0A GND GND C4 0.1 F VDD R5 50 GND J4 AINA DIFFERENTIAL GND GND J6 AINB DIFFERENTIAL R6 50 C31 GND 0.1 F 1 GND 2 C14 0.1 F C15 0.1 F C30 0.1 F GND 3 T2 AINAB VD E2 E27 GND GND 3 4 6 5 4 E25 E30 E20 E1 DFS/GAIN REFINA 5 GND VD GND C3 0.1 F GND VDD GND D0B D1B GND C1 0.1 F E23 VD E26 E29 VD T1 1 2 3 6 5 4 GND R39 0 R32 0 R3 25 R4 25 E28 GND C12 0.1 F GND E18 6 VREFA REFOUT E17 VREFB 7 REFINB E24 E21 E19 8 S1 E22 9 S2 AINBB 10 AINB AINB 11 AINB 12 GND GND AD9218 U1 VD VD GND VDD GND D0B D1B ENCB GND D9B D8B D7B D6B D5B D4B D3B 23 D3B AMPINB AINB R38 SINGLE-ENDED 0 J1 R37 50 GND GND 13 14 15 16 17 18 19 20 21 22 GND D9B D8B D7B D6B D5B D4B C11 0.1 F C5 0.1 F VD ENCB VDD GND C6 0.1 F OPTIONAL INPUT PATH FOR OPAMP OR SINGLE-ENDED GND C27 0.1 F REFINA GND DUT CLOCK SELECTABLE TO BE DIRECT OR BUFFERED C24 0.1 F REFINB E49 E48 D2B GND 24 D2B VD VDD ENCB ENCODE B J2 VDL TIEB E50 P20 P21 GND 74LCX86 1 2 3 P22 1A 1B 1Y 2A 2B 2Y GND U5 VCC 4B 4A 4Y 3B 3A 3Y 14 13 E5 C13 0.1 F VDL E44 H3 MT HOLE6 H1 MT HOLE6 H2 MT HOLE6 H4 MT HOLE6 R7 GND 50 GND E13 E16 E14 P23 TIEB ENCB 12 E4 11 10 9 8 VDL 4 5 GND CLKLATB E11 E15 E12 GND VDL DRB GND 6 7 VDL GND GND GND CLKDACB Figure 17a. PCB Schematic –18– REV. 0 GND 74LCX821 20 19 18 17 16 15 14 13 12 11 D0M GND GND 16 14 12 10 8 6 4 2 16 14 12 10 8 6 4 2 GND GND 74LCX821 20 19 18 17 16 15 14 13 12 11 D9N GND GND 12 X9 Y9 CLK 11 14 13 11 D9N X8 Y8 D8N 10 15 12 D8N X7 Y7 D7N 9 16 13 D7N X6 Y6 D6N 8 17 D0Y D0Y D0Y D0Y 14 D6N X5 Y5 D5N D0Y 7 18 15 D5N X4 Y4 D4N D0Y 6 19 U3 16 D4N X3 Y3 D3N D0Y 5 20 D4Y D5Y D6Y D7Y D8Y D9Y E42 E33 REV. 0 CT520 VALUE = 22 HEADER40 20 19 18 17 16 15 14 13 12 11 20 20 18 18 11 D0P 22 22 12 D1P 24 24 23 21 19 17 15 13 11 9 7 5 3 1 13 D2P 26 25 26 14 D3P 25 23 21 19 17 15 13 11 9 7 5 3 1 28 27 28 27 15 D4P 30 29 30 29 P3 16 D5P 32 31 32 31 D8P D7P D6P D5P D4P D3P D2P D1P D0P GND GND GND GND GND GND GND 17 D6P 34 33 D9P 34 33 18 D7P 36 35 GND 36 35 19 D8P 38 37 DRA 38 37 20 D9P 40 39 GND 40 39 D9X D8X D7X D6X D5X D4X D3X D2X D1X D0X 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 U9 20 D9M D8M D7M D6M D5M D4M D3M D2M D1M D0M 11 12 CLK 13 CLKLATA X9 Y9 14 D0X X8 Y8 D1M 10 15 D1X X7 Y7 D2M 9 16 D2X X6 Y6 D3M 8 17 D3X X5 Y5 D4M 7 18 D4X X4 Y4 D5M 6 19 D5X X3 U2 Y3 D6M 5 20 D6X X2 Y2 D7M 4 21 D7X X1 Y1 D8M 3 22 D8X X0 Y0 D9M 2 23 D9X GND VCC GND 19 18 17 16 15 14 13 12 11 1 24 C21 0.1 F VDL CT520 VALUE = 22 D0Y D1Y D2Y D3Y 2 3 4 5 6 7 8 9 10 1 1 2 3 4 5 6 7 8 9 10 U10 20 19 18 17 16 15 14 13 12 11 20 19 18 17 16 15 14 13 12 11 D0Q D1Q D2Q D3Q D4Q D5Q D6Q D7Q D8Q D9Q 40 38 36 34 32 30 28 26 24 22 20 CLKLATD E43 CT520 VALUE = 22 D9A 1 U7 D8A 2 1 D7A 3 2 D6A 4 3 D5A 5 4 D4A 6 5 D3A 7 6 D2A 8 7 D1A 9 8 D0A 10 9 10 Figure 17b. PCB Schematic –19– 20 D0N D1N D2N D3N X2 Y2 D2N 4 21 D0Y X1 Y1 D1N 3 22 D0Y X0 Y0 D0N 2 23 D0Y VCC GND 19 18 17 OE 1 24 C20 0.1 F VDL CLKLATA CT520 VALUE = 22 HEADER40 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 18 16 14 12 10 8 6 4 2 GND P2 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 GND GND D0B 1 U8 D1B 2 1 E7 E8 E6 D2B 3 2 DRA D3B 4 3 D4B 5 4 D9Q DRB D8Q D7Q D6Q D5Q D4Q D3Q D2Q D1Q D0Q GND GND GND GND GND GND GND D5B 6 5 D6B 7 6 D7B 8 7 D8B 9 8 D9B 10 9 10 AD9218 AD9218 GND GND DAC OUTPUT B J3 DAC OUTPUT A J8 C23 0.1 F R9 50 GND GND GND GND R40 00 R20 00 GND POWER-DOWN OPTION (OPTIONAL) VDL GND GND GND 43 42 GND VDL C22 0.1 F GND 48 47 46 44 R13, 2k 45 R12, 50 41 R14, 2k GND R10 50 39 38 SLEEP IB2IA2 FSADJ1 REFIO FSADJ2 REFLO ACOM IA2 MODE AVDD IB1 37 VDL 40 R8, 50 D9Y D8Y D7Y D6Y D5Y D4Y D3Y D2Y D1Y D0Y CLK2/IQRESET WRT1/IQWRT WRT2/IQSEL CLK1/IQCLK NC = NO CONNECT DB9–P2 24 DB8– P2 DCOM1 13 14 15 16 17 DVDD GND NC2 NC3 18 19 20 21 22 DCOM2 1 DB9 –P1 2 DB8–P1 3 DB7–P1 4 DB6–P1 5 DB5–P1 6 DB4–P1 7 DB3–P1 8 DB2–P1 9 DB1–P1 10 DB0–P1 11 NC 12 NC1 NC7 NC6 NC5 NC4 DB0–P2 36 35 34 33 32 31 30 29 28 27 26 25 D0X D1X D2X D3X D4X D5X D6X D7X 9763 DB1–P2 DB2–P2 DB3–P2 DB4–P2 DB5–P2 DB6–P2 DB7–P2 23 D8X CLKDACB CLKDACB CLKDACA CLKDACA GND GND GND GND D9X GND C29 0.1 F VDL R26 500 U4 GND C28 0.1 F VDL R18 500 R19 4k 5V +5V R16 525 GND 1 2 3 4 R21 1k GND C32 0.1 F GND 5V R27 4k R28 1k +5V GND C35 0.1 F GND R22 25 AINA GND R25 525 1 2 3 4 R30 25 AINBB U11 U12 –IN +OUT –IN VOCM VOCM AD8138 –OUT C2 15pF +OUT V+ V+ AD8138 –OUT C36 15pF +IN +IN NC NC V– R17 500 AMPINA GND R23 25 AIINAB AMPINB R29 500 GND V– NC = NO CONNECT NC = NO CONNECT R24 25 AINB 8 7 6 5 8 7 6 C33 0.1 F –5V R15 500 C34 0.1 F –5V R31 500 Figure 17c. PCB Schematic –20– 5 REV. 0 AD9218 Figure 18. PCB Top Side Silkscreen Figure 19. PCB Top Side Copper REV. 0 –21– AD9218 Figure 20. PCB Ground Layer Figure 21. PCB Split Power Plane –22– REV. 0 AD9218 Figure 22. PCB Bottom Side Copper Figure 23. Bottom Side Silkscreen REV. 0 –23– AD9218 Troubleshooting If the board does not seem to be working correctly, try the following: • Verify power at IC pins. • Check that all jumpers are in the correct position for the desired mode of operation. • Verify VREF is at 1.23 V. • Try running encode clock and analog inputs at low speeds (20 MSPS/1 MHz) and monitor LCX821 outputs, DAC outputs, and ADC outputs for toggling. The AD9218 Evaluation Board is provided as a design example for customers of Analog Devices, Inc. ADI makes no warranties, express, statutory, or implied, regarding merchantability or fitness for a particular purpose. OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 48-Lead LQFP (ST-48) 0.063 (1.60) MAX 0.030 (0.75) 0.018 (0.45) 0.354 (9.00) BSC SQ 48 1 37 36 TOP VIEW (PINS DOWN) 0.276 (7.00) BSC SQ 25 COPLANARITY 0.003 (0.08) 0.008 (0.2) 0.004 (0.09) 0 MIN 12 13 24 0.019 (0.5) BSC 7 0 0.011 (0.27) 0.006 (0.17) 0.057 (1.45) 0.053 (1.35) 0.006 (0.15) SEATING 0.002 (0.05) PLANE –24– REV. 0 PRINTED IN U.S.A. C02001–1.5–7/01(0)