AD9218SSTZ-105EPRL

10-Bit, 105 MSPS, 3 V, Dual ADC AD9218-EP Enhanced Product FEATURES GENERAL DESCRIPTION Dual, 10-bit, 105 MSPS ADC Low power: 275 mW at 105 MSPS per channel On-chip reference and track-and-hold 300 MHz analog bandwidth for each channel SNR = 54 dB at 51 MHz, encode = 105 MSPS 1 V p-p analog input range for each channel 3.0 V single-supply operation (2.7 V to 3.6 V) Power-down mode for single-channel operation Twos complement or offset binary output mode Output data alignment mode –75 dBc crosstalk between channels The AD9218-EP is a dual, 10-bit, monolithic sampling analogto-digital converter (ADC) with on-chip track-and-hold circuits. The product is low cost, low power, and is small and easy to use. The AD9218-EP operates at a 105 MSPS conversion rate with dynamic performance over its full operating range. Each channel can be operated independently. The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power supply and a clock for full operation. No external reference or driver components are required for many applications. The digital outputs are transistor-to-transistor logic (TTL)/ complementary metal-oxide semiconductor (CMOS) compatible, and a separate output power supply pin supports interfacing with 3.3 V or 2.5 V logic. ENHANCED PRODUCT FEATURES Supports defense and aerospace applications (AQEC standard) Extended industrial temperature range: −55°C to +105°C Controlled manufacturing baseline 1 assembly/test site 1 fabrication site Product change notification Qualification data available on request The clock input is TTL/CMOS compatible and the 10-bit digital outputs can be operated from a 3.0 V (2.5 V to 3.6 V) supply. User-selectable options offer a combination of power-down modes, digital data formats, and digital data timing schemes. In power-down mode, the digital outputs are driven to a high impedance state. The AD9218-EP is fabricated on an advanced CMOS process and is available in a 48-lead, 7 mm × 7 mm, low profile quad flat package (LQFP), and is specified over the extended industrial temperature range of −55°C to +105°C. APPLICATIONS Radar Avionics Unmanned systems Military communications Missiles and munitions Additional application and technical information can be found in the AD9218 data sheet. FUNCTIONAL BLOCK DIAGRAM ENCA AD9218-EP TIMING AINA T/H ADC AINA OUTPUT / REGISTER / 10 10 D9A TO D0A S1 REFINA REFOUT S2 REF REFINB DFS/GAIN AINB ENCB T/H ADC OUTPUT / / 10 REGISTER 10 D9B TO D0B TIMING VD GND VDD 17309-001 AINB Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9218-EP Enhanced Product TABLE OF CONTENTS Features .............................................................................................. 1 Switching Specifications ...............................................................6 Enhanced Product Features ............................................................ 1 Timing Diagrams ..........................................................................6 Applications ....................................................................................... 1 Absolute Maximum Ratings ............................................................8 General Description ......................................................................... 1 Explanation of Test Levels ............................................................8 Functional Block Diagram .............................................................. 1 Thermal Resistance .......................................................................8 Revision History ............................................................................... 2 ESD Caution...................................................................................8 Specifications..................................................................................... 3 Pin Configuration and Function Descriptions..............................9 DC Specifications ......................................................................... 3 Typical Performance Characteristics ........................................... 10 Digital Specifications ................................................................... 4 Outline Dimensions ....................................................................... 11 AC Specifications.......................................................................... 5 Ordering Guide .......................................................................... 11 REVISION HISTORY 12/2018—Revision 0: Initial Version Rev. 0 | Page 2 of 11 Enhanced Product AD9218-EP SPECIFICATIONS DC SPECIFICATIONS VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes 1 Offset Error 2 Gain Error2 Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error2 Reference REFERENCE Internal Reference Voltage (REFOUT) Input Resistance (REFINA, REFINB) ANALOG INPUTS Differential Input Voltage Range (AINx, AINx) 3 Common-Mode Voltage3 Input Resistance Input Capacitance POWER SUPPLY VD VDD Supply Currents IVD (VD = 3.0 V) 4 IVDD (VDD = 3.0 V)4 Power Dissipation DC 5 IVD Power-Down Current 6 Power Supply Rejection Ratio Temperature Test Level Min Typ 10 Max Full 25°C 25°C 25°C VI I I I Guaranteed, not tested –18 +2 +18 –2 +3.5 +8 –1 ±0.8 +1.7 LSB % FS LSB Full 25°C Full VI I VI –2.7 ±0.9 ±2 ±2.3 LSB LSB LSB Full Full Full V V V 25°C I 1.18 1.24 1.28 V Full VI 9 11 13 kΩ Full Full Full 25°C V V VI V Full Full IV IV Full 25°C Full Full 25°C VI V VI VI I +2.7 4 100 40 7 2.7 2.5 1 VD/3 10 3 Unit Bits ppm/°C ppm/°C ppm/°C 16 V V kΩ pF 3 3 3.6 3.6 V V 183 17 550 22 ±1 188 mA mA mW mA mV/V 565 No missing codes at room temperature guaranteed. Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1.25 V external reference) in 1 V p-p range. (AINx – AINx) = ±0.5 V in 1 V range (full-scale). The analog inputs self-bias to VD/3. This common-mode voltage can be overdriven externally by a low impedance source by ±300 mV (differential drive, gain = 1). 4 AC power dissipation measured with rated encode and a 10 MHz analog input at 0.5 dBFS, CLOAD = 5 pF. 5 DC power dissipation measured with rated encode and a dc analog input (outputs static, IVDD = 0). 6 In power-down state, IVDD = ±10 µA typical. 1 2 3 Rev. 0 | Page 3 of 11 AD9218-EP Enhanced Product DIGITAL SPECIFICATIONS VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted. Table 2. Parameter DIGITAL INPUTS Encode Input Common Mode Encode 1 Voltage Encode 0 Voltage Encode Input Resistance Logic 1 Voltage—S1, S2, DFS Logic 0 Voltage—S1, S2, DFS Logic 1 Current—S1 Logic 0 Current—S1 Logic 1 Current—S2 Logic 0 Current—S2 Logic 1 Current—DFS Logic 0 Current—DFS Input Capacitance—S1, S2, Encode Inputs Input Capacitance DFS DIGITAL OUTPUTS Logic 1 Voltage Logic 0 Voltage Output Coding Temperature Test Level Full Full Full Full Full Full Full Full Full Full Full Full 25°C 25°C V VI VI VI VI VI VI VI VI VI VI VI V V Full Full VI VI Rev. 0 | Page 4 of 11 Min Typ Max VD/2 2 1.75 2 2.0 –50 –400 50 –50 30 –400 ±0 –230 230 ±0 100 –230 2 4.5 0.8 2.4 0.8 50 –50 400 50 200 –50 2.45 0.05 Twos complement or offset binary Unit V V V kΩ V V µA µA µA µA µA µA pF pF V V Enhanced Product AD9218-EP AC SPECIFICATIONS VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted. Table 3. Parameter DYNAMIC PERFORMANCE 1 Signal-to-Noise Ratio (SNR) (Without Harmonics) fIN = 10 MHz fIN = Nyquist 2 Signal-to-Noise and Distortion (SINAD) (With Harmonics) fIN = 10 MHz fIN = Nyquist2 Effective Number of Bits fIN = 10 MHz fIN = Nyquist2 Second Harmonic Distortion fIN = 10 MHz fIN = Nyquist2 Third Harmonic Distortion fIN = 10 MHz fIN = Nyquist2 Spurious Free Dynamic Range (SFDR) fIN = 10 MHz fIN = Nyquist2 Two-Tone Intermodulation Distortion (IMD) fIN1 = 30 MHz, fIN2 = 31 MHz at –7 dBFS Analog Bandwidth, Full Power Crosstalk 1 2 Temperature Test Level Min Typ Max 25°C 25°C I I 53 52 55 54 dB dB 25°C 25°C I I 52 51 53 53 dB dB 25°C 25°C I I 8.4 8.3 8.6 8.6 Bits Bits 25°C 25°C I I –60 –57 –68 –66 dBc dBc 25°C 25°C I I –57 –57 –63 –69 dBc dBc 25°C 25°C I I –57 –57 –62 –63 dBc dBc 25°C 25°C 25°C V V V –67 300 –75 dBc MHz dBc AC specifications based on an analog input voltage of –0.5 dBFS at 10.0 MHz, unless otherwise noted. AC specifications are tested in 1 V p-p range and driven differentially. Tested close to Nyquist: 51 MHz. Rev. 0 | Page 5 of 11 Unit AD9218-EP Enhanced Product SWITCHING SPECIFICATIONS VDD = 3.0 V, VD = 3.0 V; external reference, unless otherwise noted. Table 4. Parameter ENCODE INPUT PARAMETERS Maximum Encode Rate Minimum Encode Rate Encode Pulse Width High (tEH) Encode Pulse Width Low (tEL) Aperture Delay (tA) Aperture Uncertainty (Jitter) DIGITAL OUTPUT PARAMETERS Output Valid Time (tV) 1 Output Propagation Delay (tPD)1 Output Rise Time (tR) Output Fall Time (tF) Out-of-Range Recovery Time Transient Response Time Recovery Time from Power-Down Pipeline Delay 1 Temperature Test Level Min Full Full Full Full 25°C 25°C VI IV IV IV V V 105 Full Full 25°C 25°C 25°C 25°C 25°C Full VI VI V V V V V IV 2.5 Typ Max Unit 2 3 MSPS MSPS ns ns ns ps rms 4.5 1.0 1.2 5 5 10 5 ns ns ns ns ns ns Cycles Cycles 20 3.8 3.8 6 tV and tPD are measured from the 1.5 level of the ENCx input to the 50%/50% levels of the digital outputs swing. The digital output load during test must not exceed an ac load of 5 pF or a dc current of ±40 µA. Rise and fall times are measured from 10% to 90%. TIMING DIAGRAMS SAMPLE N+1 SAMPLE N SAMPLE N+5 SAMPLE N+6 AINA AINB tA tEH tEL SAMPLE N+2 SAMPLE N+3 SAMPLE N+4 1/fS ENCA ENCB tV D9A TO D0A DATA N – 5 DATA N – 4 DATA N – 3 DATA N – 2 DATA N – 1 DATA N D9B TO D0B DATA N – 5 DATA N – 4 DATA N – 3 DATA N – 2 DATA N – 1 DATA N Figure 2. Normal Operation, Same Clock (S1 = 1, S2 = 0) Channel Timing Rev. 0 | Page 6 of 11 17309-002 tPD Enhanced Product AD9218-EP SAMPLE N SAMPLE N+1 SAMPLE N+2 SAMPLE N+7 SAMPLE N+8 AINA AINB tA SAMPLE SAMPLE SAMPLE SAMPLE N+3 N+4 N+5 N+6 tEL tEH 1/fS ENCA tV tPD ENCB DATA N – 10 DATA N – 8 DATA N – 9 D9B TO D0B DATA N – 6 DATA N – 7 DATA N – 4 DATA N – 5 DATA N – 2 DATA N – 3 DATA N DATA N – 1 DATA N + 2 DATA N + 1 17309-003 D9A TO D0A Figure 3. Normal Operation with Two Clock Sources (S1 = 1, S2 = 0) Channel Timing SAMPLE N SAMPLE N+1 SAMPLE N+2 SAMPLE N+7 SAMPLE N+8 AINA AINB tA tEH tEL SAMPLE SAMPLE SAMPLE SAMPLE N+3 N+4 N+5 N+6 1/fS ENCA tV tPD D9A TO D0A DATA N – 10 DATA N – 8 DATA N – 6 DATA N – 4 DATA N – 2 DATA N DATA N + 2 D9B TO D0B DATA N – 11 DATA N – 9 DATA N – 7 DATA N – 5 DATA N – 3 DATA N – 1 DATA N + 1 Figure 4. Data Align with Two Clock Sources (S1 = 1, S2 = 1) Channel Timing Rev. 0 | Page 7 of 11 17309-004 ENCB AD9218-EP Enhanced Product ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 5. Parameter VD, VDD Analog Inputs Digital Inputs REFIN Inputs Digital Output Current Operating Temperature Range Storage Temperature Range Junction Temperature Operating Case Temperature Operating Rating 4V –0.5 V to VD + 0.5 V –0.5 V to VDD + 0.5 V –0.5 V to VD + 0.5 V 20 mA –55°C to +105°C –65°C to +150°C 150°C 115°C 150°C 105°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. θJA is the natural convection, junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. θJC is the junction to case thermal resistance. Table 6. Thermal Resistance Package Type ST-481 1 III IV V VI θJC 12 Unit °C/W Thermal impedance simulated values are based on JEDEC 2S2P thermal test board. See JEDEC JESD-51. ESD CAUTION EXPLANATION OF TEST LEVELS Test Level I II θJA 73 Description 100% production tested. 100% production tested at 25°C and sample tested at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at 25°C; guaranteed by design and characterization testing for extended industrial temperature range. Rev. 0 | Page 8 of 11 Enhanced Product AD9218-EP D6A D5A D4A D3A D2A 41 40 39 38 37 GND 1 36 D1A AINA 2 35 D0A VD VD S1 8 29 GND S2 9 28 VDD AINB 10 27 GND AINB 11 26 D0B GND 12 25 D1B VDD 15 GND 16 VD 13 ENCB 14 D2B 24 30 D3B 23 31 D4B 22 GND TOP VIEW (Not to Scale) REFOUT 6 REFINB 7 D5B 21 AD9218-EP 32 D6B 20 VDD REFINA 5 D7B 19 GND 33 D8B 18 34 (MSB) D9B 17 AINA 3 DFS/GAIN 4 17309-005 D8A D9A (MSB) 44 D7A GND 45 42 VDD 46 43 VD ENCA 47 48 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 5. Pin Configuration Table 7. Pin Function Descriptions Pin Number 1, 12, 16, 27, 29, 32, 34, 45 2 Mnemonic GND Description Ground. AINA Analog Input for Channel A. 3 A INA Analog Input for Channel A (Complementary). 4 DFS/GAIN 5 6 7 8 9 10 REFINA REFOUT REFINB S1 S2 Data Format Select and Analog Input Gain Mode. Low = offset binary output available, 1 V p-p supported; high = twos complement output available, 1 V p-p supported. Reference Voltage Input for Channel A. Internal Reference Voltage. Reference Voltage Input for Channel B. User Select 1. User Select 2. Analog Input for Channel B (Complementary). 11 13, 30, 31, 48 14 15, 28, 33, 46 17 to 26 35 to 44 47 AINB VD ENCB VDD D9B to D0B D0A to D9A ENCA A INB Analog Input for Channel B. Analog Supply. Encode B. Clock input for Channel B. Digital Supply. Digital Output for Channel B (D9B = MSB). Digital Output for Channel A (D9A = MSB). Encode A. Clock input for Channel A. Rev. 0 | Page 9 of 11 AD9218-EP Enhanced Product TYPICAL PERFORMANCE CHARACTERISTICS 68 1.29 SNR SINAD SFDR 66 64 SNR, SINAD, SFDR (dB) VREF OUTPUT VOLTAGE (V) 1.27 1.25 1.23 1.21 62 60 58 56 54 1.19 1.17 –55 –35 –15 5 25 45 65 85 50 –55 105 Figure 6. VREF Output Voltage vs. Temperature (ILOAD = 300 μA) 3.5 3.0 2.5 –15 5 25 45 65 85 105 TEMPERATURE (°C) 17309-036 GAIN ERROR (%fS) 4.0 –35 –15 5 25 45 65 85 105 Figure 8. SNR, SINAD, SFDR vs. Temperature, AIN = 10 MHz, 1 V p-p 4.5 2.0 –55 –35 TEMPERATURE (°C) TEMPERATURE (°C) Figure 7. Gain Error vs. Temperature, AIN = 10 MHz, 1 V p-p Rev. 0 | Page 10 of 11 17309-037 52 Enhanced Product AD9218-EP OUTLINE DIMENSIONS 9.20 9.00 SQ 8.80 SIDE VIEW 1.60 MAX 0.75 0.60 0.45 TOP VIEW 48 37 1 1.00 REF 36 SEATING PLANE 7.20 7.00 SQ 6.80 0.20 0.15 0.09 0.15 0.10 0.05 7° 0° 0.08 MAX COPLANARITY 12 25 24 13 VIEW A 0.50 BSC VIEW A 0.27 0.22 0.17 PKG-005430 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC 01-17-2018-A 1.45 1.40 1.35 Figure 9. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD9218SSTZ-105-EP AD9218SSTZ-105EPRL 1 Temperature Range –55°C to +105°C −55°C to +105°C Package Description 48-Lead Low Profile Quad Flat Pack [LQFP] 48-Lead Low Profile Quad Flat Pack [LQFP] Z = RoHS Compliant Part. ©2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D17309-0-12/18(0) Rev. 0 | Page 11 of 11 Package Option ST-48 ST-48