Quad, 10-Bit, 40 MSPS/65 MSPS,
Serial LVDS 1.8 V ADC
AD9219
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
4 ADCs integrated into 1 package
94 mW ADC power per channel at 65 MSPS
SNR = 60 dB (to Nyquist)
ENOB = 9.7 bits
SFDR = 78 dBc (to Nyquist)
Excellent linearity
DNL = ±0.2 LSB (typical)
INL = ±0.3 LSB (typical)
Serial LVDS (ANSI-644, default)
Low power, reduced signal option (similar to IEEE 1596.3)
Data and frame clock outputs
315 MHz full-power analog bandwidth
2 V p-p input voltage range
1.8 V supply operation
Serial port control
Full-chip and individual-channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Programmable output resolution
Standby mode
APPLICATIONS
Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam-forming systems
Quadrature radio receivers
Diversity radio receivers
Tape drives
Optical networking
Test equipment
GENERAL DESCRIPTION
The AD9219 is a quad, 10-bit, 40/65 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed
for low cost, low power, small size, and ease of use. The product
operates at a conversion rate of up to 65 MSPS and is optimized for
outstanding dynamic performance and low power in applications
where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
AVDD
DRVDD
AD9219
PIPELINE
ADC
VIN + B
VIN – B
PIPELINE
ADC
VIN + C
VIN – C
PIPELINE
ADC
VIN + D
VIN – D
PIPELINE
ADC
SERIAL
LVDS
D+A
D–A
SERIAL
LVDS
D+B
D–B
SERIAL
LVDS
D+C
D–C
SERIAL
LVDS
D+D
D–D
10
10
10
VREF
SENSE
REFT
REFB
DRGND
10
VIN + A
VIN – A
+
–
REF
SELECT
FCO+
0.5V
SERIAL PORT
INTERFACE
DATA RATE
MULTIPLIER
RBIAS AGND CSB SDIO/ODM SCLK/DTP CLK+ CLK–
FCO–
DCO+
DCO–
Figure 1.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for
capturing data on the output and a frame clock output (FCO)
for signaling a new output byte are provided. Individual-channel
power-down is supported and typically consumes less than
2 mW when all channels are disabled.
The ADC contains several features designed to maximize flexibility
and minimize system cost, such as programmable clock and data
alignment and programmable digital test pattern generation. The
available digital test patterns include built-in deterministic and
pseudorandom patterns, along with custom user-defined test
patterns entered via the serial port interface (SPI).
The AD9219 is available in a RoHS compliant, 48-lead LFCSP. It is
specified over the industrial temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
Rev. G
PDWN
05726-001
FEATURES
Small Footprint. Four ADCs are contained in a small, spacesaving package.
Low power of 94 mW/channel at 65 MSPS.
Ease of Use. A data clock output (DCO) is provided that
operates at frequencies of up to 390 MHz and supports
double data rate (DDR) operation.
User Flexibility. The SPI control offers a wide range of flexible
features to meet specific system requirements.
Pin-Compatible Family. This includes the AD9287 (8-bit),
AD9228 (12-bit), and AD9259 (14-bit).
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice.
No license is granted by implication or otherwise under any patent or patent rights of Analog
Devices. Trademarks and registered trademarks are the property of their respective owners.
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Tel: 781.329.4700 ©2006–2020 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD9219
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Analog Input Considerations ................................................... 20
Applications ...................................................................................... 1
Clock Input Considerations ..................................................... 23
General Description ......................................................................... 1
Serial Port Interface (SPI) ............................................................. 31
Functional Block Diagram .............................................................. 1
Hardware Interface .................................................................... 31
Product Highlights ........................................................................... 1
Memory Map .................................................................................. 33
Revision History ............................................................................... 2
Reading the Memory Map Table ............................................. 33
Specifications .................................................................................... 4
Reserved Locations .................................................................... 33
AC Specifications ......................................................................... 5
Default Values ............................................................................ 33
Digital Specifications ................................................................... 6
Logic Levels ................................................................................. 33
Switching Specifications .............................................................. 7
Evaluation Board ............................................................................ 37
Timing Diagrams.............................................................................. 8
Power Supplies ........................................................................... 37
Absolute Maximum Ratings ......................................................... 10
Input Signals ............................................................................... 37
Thermal Impedance ................................................................... 10
Output Signals ............................................................................ 37
ESD Caution................................................................................ 10
Default Operation and Jumper Selection Settings ................ 38
Pin Configuration and Function Descriptions .......................... 11
Alternative Analog Input Drive Configuration ..................... 39
Equivalent Circuits ......................................................................... 13
Outline Dimensions ....................................................................... 53
Typical Performance Characteristics ........................................... 15
Ordering Guide .......................................................................... 53
Theory of Operation ...................................................................... 20
REVISION HISTORY
9/2020—Rev. F to Rev. G
Changed CP-48-8 to CP-48-9 ...................................... Throughout
Changes to Figure 5........................................................................ 11
Updated Outline Dimensions ....................................................... 53
Changes to Ordering Guide .......................................................... 53
9/2018—Rev. E to Rev. F
Changes to Figure 5 and Table 7 .................................................. 11
Changes to Digital Outputs and Timing Section ....................... 28
Updated Outline Dimensions ....................................................... 53
Changes to Ordering Guide .......................................................... 53
12/2011—Rev. D to Rev. E
Added Exposed Pad Notation to Figure 5 .................................. 11
Changes to Output Signals Section and Figure 71..................... 37
Change to Default Operation and Jumper Selection Settings
Section .............................................................................................. 38
Change to Figure 74 ....................................................................... 41
Changed LFCSP_WQ to LFCSP_VQ Throughout ................... 53
Added Endnote 2 in Ordering Guide .......................................... 53
5/2010—Rev. C to Rev. D
Updated Outline Dimensions ...................................................... 52
Changes to Ordering Guide .......................................................... 52
4/2010—Rev. B to Rev. C
Changes to Table 16 ....................................................................... 33
Updated Outline Dimensions ...................................................... 52
7/2007—Rev. A to Rev. B
Changes to Figure 2 and Figure 4 ...................................................7
Changes to Table 17 ....................................................................... 50
5/2007—Rev. 0 to Rev. A
Changes to Features ..........................................................................1
Changes to Logic Output (SDIO/ODM) Section .........................5
Added Endnote 3 to Table 3 ............................................................5
Changes to Pipeline Latency ............................................................6
Changes to Figure 2 to Figure 4 ......................................................7
Changes to Figure 10 ..................................................................... 12
Changes to Figure 15, Figure 23 to Figure 26 Captions............ 14
Changes to Figure 16, Figure 37, Figure 39, and Figure 40 ...... 14
Added Figure 46 and Figure 47 .................................................... 20
Rev. G | Page 2 of 53
Data Sheet
AD9219
Change to Figure 50 ........................................................................21
Changes to Figure 51 ......................................................................21
Changes to Clock Duty Cycle Considerations Section ..............22
Changes to Power Dissipation and Power-Down Mode Section ..23
Changes to Figure 58 ......................................................................23
Changes to Figure 61 to Figure 63 Captions ...............................25
Change to Table 8 ...........................................................................25
Changes to Digital Outputs and Timing Section .......................26
Changes to Table 9 Endnote ..........................................................26
Added Table 10................................................................................27
Deleted Figure 62 and Figure 63 ...................................................27
Changes to RBIAS Pin Section ......................................................28
Changes to Figure 67 ......................................................................29
Changes to Hardware Interface Section ......................................30
Added Figure 68 .............................................................................. 31
Changes to Table 15........................................................................ 31
Changes to Reading the Memory Map Table Section ............... 32
Changes to Output Signals Section .............................................. 36
Changes to Figure 71 ...................................................................... 36
Changes to Default Operation and Jumper Selection
Settings Section ............................................................................... 37
Changes to Alternative Analog Input Drive Configuration
Section .............................................................................................. 38
Changes to Figure 74 ...................................................................... 40
Changes to Table 17........................................................................ 48
Changes to Ordering Guide .......................................................... 52
4/2006—Revision 0: Initial Version
Rev. G | Page 3 of 53
AD9219
Data Sheet
SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 1.
Parameter1
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Offset Matching
Gain Error
Gain Matching
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
Reference Voltage (1 V Mode)
REFERENCE
Output Voltage Error (VREF = 1 V)
Load Regulation at 1.0 mA (VREF = 1 V)
Input Resistance
ANALOG INPUTS
Differential Input Voltage (VREF = 1 V)
Common-Mode Voltage
Differential Input Capacitance
Analog Bandwidth, Full Power
POWER SUPPLY
AVDD
DRVDD
IAVDD
IDRVDD
Total Power Dissipation (Including Output Drivers)
Power-Down Dissipation
Standby Dissipation2
CROSSTALK
CROSSTALK (Overrange Condition)3
Temperature
Min
10
Full
Full
Full
Full
Full
Full
Full
AD9219-40
Typ
Max
Guaranteed
±1
±2
±0.4
±0.3
±0.1
±0.15
Full
Full
Full
±2
±17
±21
Full
Full
Full
±2
3
6
Full
Full
Full
Full
2
AVDD/2
7
315
Full
Full
Full
Full
Full
Full
Full
Full
Full
1.7
1.7
1
1.8
1.8
130
30
295
2
72
−100
−100
Min
10
AD9219-65
Typ
Max
Guaranteed
±1
±8
±2
±8
±2
±3.5
±0.3
±0.7
±0.15
±0.4
±0.3
±0.75
±8
±8
±1.2
±0.7
±0.4
±0.4
±2
±17
±21
±30
±2
3
6
1.7
1.7
1.8
1.8
177
33
378
2
72
−100
−100
±30
Rev. G | Page 4 of 53
mV
mV
kΩ
V p-p
V
pF
MHz
1.9
1.9
190
37
408
5.8
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details of how these tests were completed.
Can be controlled via the SPI.
3
Overrange condition is specific with 6 dB of the full-scale input range.
2
mV
mV
% FS
% FS
LSB
LSB
ppm/°C
ppm/°C
ppm/°C
2
AVDD/2
7
315
1.9
1.9
142
32
313
5.8
Unit
Bits
V
V
mA
mA
mW
mW
mW
dB
dB
Data Sheet
AD9219
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 2.
Parameter1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 70 MHz
SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 70 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 70 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 70 MHz
WORST HARMONIC (Second or Third)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 70 MHz
WORST OTHER (Excluding Second or Third)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 70 MHz
TWO-TONE INTERMODULATION DISTORTION (IMD)—
AIN1 and AIN2 = −7.0 dBFS
fIN1 = 15 MHz, fIN2 = 16 MHz
fIN1 = 70 MHz, fIN2 = 71 MHz
1
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min
60.0
59.8
9.67
71
AD9219-40
Typ
Max
61.2
60.5
61.0
60.9
59.0
61.1
60.3
60.9
60.8
58.8
9.87
9.76
9.84
9.82
9.51
84
82
80
79
Full
Full
Full
Full
−84
−82
−80
−79
Full
Full
Full
Full
−90
−90
−90
−88
25°C
25°C
81.5
79.5
Min
68
−71
−77
AD9219-65
Typ
Max
60.2
60.2
60.2
60.1
dB
dB
dB
dB
60.1
60.1
60.0
59.8
dB
dB
dB
dB
9.71
9.71
9.71
9.69
Bits
Bits
Bits
Bits
78
78
77
72
dBc
dBc
dBc
dBc
−80
−80
−77
−72
dBc
dBc
dBc
dBc
−78
−78
−80
−80
−68
−70
78.1
74.5
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details of how these tests were completed.
Rev. G | Page 5 of 53
Unit
dBc
dBc
dBc
dBc
dBc
dBc
AD9219
Data Sheet
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 3.
Parameter1
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage2
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
LOGIC INPUTS (PDWN, SCLK/DTP)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (CSB)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (SDIO/ODM)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC OUTPUT (SDIO/ODM)3
Logic 1 Voltage (IOH = 800 μA)
Logic 0 Voltage (IOL = 50 μA)
DIGITAL OUTPUTS (D + x, D − x), (ANSI-644)
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
DIGITAL OUTPUTS (D + x, D − x),
(Low Power, Reduced Signal Option)
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
Temperature
Min
Full
Full
25°C
25°C
250
Full
Full
25°C
25°C
1.2
0
Full
Full
25°C
25°C
1.2
0
Full
Full
25°C
25°C
1.2
0
AD9219-40
Typ
Max
AD9219-65
Typ
Max
Min
CMOS/LVDS/LVPECL
CMOS/LVDS/LVPECL
250
1.2
20
1.5
1.2
30
0.5
3.6
0.3
1.2
DRVDD + 0.3
0.3
1.2
0
30
2
150
1.10
454
1.375
Offset binary
250
1.30
Offset binary
1
V
V
kΩ
pF
DRVDD + 0.3
0.3
V
V
kΩ
pF
1.79
0.05
0.05
454
1.375
Offset binary
Rev. G | Page 6 of 53
mV
V
LVDS
150
1.10
250
1.30
Offset binary
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details of how these tests were completed.
This is specified for LVDS and LVPECL only.
3
This is specified for 13 SDIO pins sharing the same connection.
2
V
V
LVDS
247
1.125
LVDS
Full
Full
3.6
0.3
30
2
1.79
247
1.125
V
V
kΩ
pF
70
0.5
LVDS
Full
Full
3.6
0.3
30
0.5
70
0.5
Full
Full
mV p-p
V
kΩ
pF
1.2
20
1.5
3.6
0.3
Unit
mV
V
Data Sheet
AD9219
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 4.
AD9219-40
Parameter1, 2
CLOCK3
Maximum Clock Rate
Minimum Clock Rate
Clock Pulse Width High (tEH)
Clock Pulse Width Low (tEL)
Temp
Min
Full
Full
Full
Full
40
OUTPUT PARAMETERS3
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
FCO Propagation Delay (tFCO)
DCO Propagation Delay (tCPD)4
Full
Full
Full
Full
Full
2.0
Typ
AD9219-65
Max
Min
Typ
Max
65
10
10
12.5
12.5
7.7
7.7
DCO to Data Delay (tDATA)4
Full
(tSAMPLE/20) − 300
(tSAMPLE/20) + 300
(tSAMPLE/20) − 300
2.5
300
300
2.5
tFCO +
(tSAMPLE/20)
(tSAMPLE/20)
4
Full
(tSAMPLE/20) − 300
(tSAMPLE/20)
(tSAMPLE/20) + 300
(tSAMPLE/20) − 300
(tSAMPLE/20)
(tSAMPLE/20) + 300
ps
Full
±50
±150
±50
±150
ps
25°C
25°C
Full
600
375
8
600
375
8
ns
μs
CLK
cycles
25°C
25°C
25°C
500