AD9223

Complete 12-Bit 1.5/3.0/10.0 MSPS Monolithic A/D Converters AD9221/AD9223/AD9220 FEATURES Monolithic 12-Bit A/D Converter Product Family Family Members Are: AD9221, AD9223, and AD9220 Flexible Sampling Rates: 1.5 MSPS, 3.0 MSPS, and 10.0 MSPS Low Power Dissipation: 59 mW, 100 mW, and 250 mW Single 5 V Supply Integral Nonlinearity Error: 0.5 LSB Differential Nonlinearity Error: 0.3 LSB Input Referred Noise: 0.09 LSB Complete On-Chip Sample-and-Hold Amplifier and Voltage Reference Signal-to-Noise and Distortion Ratio: 70 dB Spurious-Free Dynamic Range: 86 dB Out-of-Range Indicator Straight Binary Output Data 28-Lead SOIC and 28-Lead SSOP GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM CLK SHA VINA VINB MDAC1 GAIN = 16 A/D MDAC2 GAIN = 8 A/D MDAC3 GAIN = 4 A/D AVDD DVDD 5 4 3 A/D CAPT CAPB VREF SENSE MODE SELECT 5 3 DIGITAL CORRECTION LOGIC 12 OUTPUT BUFFERS 1V 4 3 OTR BIT 1 (MSB) BIT 12 (LSB) AD9221/AD9223/AD9220 REFCOM AVSS DVSS CML The AD9221, AD9223, and AD9220 are a generation of high performance, single supply 12-bit analog-to-digital converters. Each device exhibits true 12-bit linearity and temperature drift performance1 as well as 11.5-bit or better ac performance.2 The AD9221/AD9223/AD9220 share the same interface options, package, and pinout. Thus, the product family provides an upward or downward component selection path based on performance, sample rate and power. The devices differ with respect to their specified sampling rate, and power consumption, which is reflected in their dynamic performance over frequency. The AD9221/AD9223/AD9220 combine a low cost, high speed CMOS process and a novel architecture to achieve the resolution and speed of existing hybrid and monolithic implementations at a fraction of the power consumption and cost. Each device is a complete, monolithic ADC with an on-chip, high performance, low noise sample-and-hold amplifier and programmable voltage reference. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. The devices use a multistage differential pipelined architecture with digital output error correction logic to provide 12-bit accuracy at the specified data rates and to guarantee no missing codes over the full operating temperature range. The input of the AD9221/AD9223/AD9220 is highly flexible, allowing for easy interfacing to imaging, communications, medical, and data-acquisition systems. A truly differential input structure allows for both single-ended and differential input interfaces of varying input spans. The sample-and-hold NOTES 1 Excluding internal voltage reference. 2 Depends on the analog input configuration. amplifier (SHA) is equally suited for both multiplexed systems that switch full-scale voltage levels in successive channels as well as sampling single-channel inputs at frequencies up to and beyond the Nyquist rate. Also, the AD9221/AD9223/AD9220 is well suited for communication systems employing DirectIF down conversion since the SHA in the differential input mode can achieve excellent dynamic performance far beyond its specified Nyquist frequency.2 A single clock input is used to control all internal conversion cycles. The digital output data is presented in straight binary output format. An out-of-range (OTR) signal indicates an overflow condition that can be used with the most significant bit to determine low or high overflow. PRODUCT HIGHLIGHTS The AD9221/AD9223/AD9220 family offers a complete singlechip sampling 12-bit, analog-to-digital conversion function in pin compatible 28-lead SOIC and SSOP packages. Flexible Sampling Rates—The AD9221, AD9223, and AD9220 offer sampling rates of 1.5 MSPS, 3.0 MSPS, and 10.0 MSPS, respectively. Low Power and Single Supply—The AD9221, AD9223, and AD9220 consume only 59 mW, 100 mW, and 250 mW, respectively, on a single 5 V power supply. Excellent DC Performance Over Temperature—The AD9221/ AD9223/AD9220 provide 12-bit linearity and temperature drift performance.1 Excellent AC Performance and Low Noise—The AD9221/ AD9223/AD9220 provide better than 11.3 ENOB performance and have an input referred noise of 0.09 LSB rms.2 Flexible Analog Input Range—The versatile on-board sampleand-hold (SHA) can be configured for either single-ended or differential inputs of varying input spans. R EV. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. AD9221/AD9223/AD9220–SPECIFICATIONS DC SPECIFICATIONS Parameter RESOLUTION MAX CONVERSION RATE INPUT REFERRED NOISE (TYP) VREF = 1 V VREF = 2.5 V ACCURACY Integral Nonlinearity (INL) Differential Nonlinearity (DNL) INL1 DNL1 No Missing Codes Zero Error (@ 25°C) Gain Error (@ 25°C)2 Gain Error (@ 25°C)3 TEMPERATURE DRIFT Zero Error Gain Error2 Gain Error3 POWER SUPPLY REJECTION AVDD, DVDD (+5 V ± 0.25 V) ANALOG INPUT Input Span (with VREF = 1.0 V) Input Span (with VREF = 2.5 V) Input (VINA or VINB) Range Input Capacitance INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Output Voltage Tolerance (1 V Mode) Output Voltage (2.5 V Mode) Output Voltage Tolerance (2.5 V Mode) Load Regulation4 REFERENCE INPUT RESISTANCE POWER SUPPLIES Supply Voltages AVDD DVDD Supply Current IAVDD IDVDD POWER CONSUMPTION (AVDD = 5 V, DVDD = 5 V, fSAMPLE = Max Conversion Rate, VREF = 2.5 V, VINB = 2.5 V, TMIN to TMAX, unless otherwise noted.) AD9221 12 1.5 0.23 0.09 ± 0.4 ± 1.25 ± 0.3 ± 0.75 ± 0.6 ± 0.3 12 ± 0.3 ± 1.5 ± 0.75 ±2 ± 26 ± 0.4 ± 0.06 2 5 0 AVDD 16 1 ± 14 2.5 ± 35 2.0 5 AD9223 12 3 0.23 0.09 ± 0.5 ± 1.25 ± 0.3 ± 0.75 ± 0.6 ± 0.3 12 ± 0.3 ± 1.5 ± 0.75 ±2 ± 26 ± 0.4 ± 0.06 2 5 0 AVDD 16 1 ± 14 2.5 ± 35 2.0 5 AD9220 12 10 0.23 0.09 ± 0.5 ± 1.25 ± 0.3 ± 0.75 ± 0.7 ± 0.35 12 ± 0.3 ± 1.5 ± 0.75 ±2 ± 26 ± 0.4 ± 0.06 2 5 0 AVDD 16 1 ± 14 2.5 ± 35 2.0 5 Unit Bits min MHz min LSB rms typ LSB rms typ LSB typ LSB max LSB typ LSB max LSB typ LSB typ Bits Guaranteed % FSR max % FSR max % FSR max ppm/°C typ ppm/°C typ ppm/°C typ % FSR max V p-p min V p-p max V min V max pF typ V typ mV max V typ mV max mV max kΩ typ 5 2.7 to 5.25 14.0 11.8 0.5 0.02 59.0 70.0 5 2.7 to 5.25 26 20 0.5 0.02 100 130 5 2.7 to 5.25 58 51 4.0 5 V due to headroom issue. Optimum THD performance with VREF = 1. Noise to performance improves while THD performance degrades as VREF increases to 2.5 V. Single-supply operation (i.e., 5 V) for many op amps. Suboptimum ac performance due to input common-mode level not biased at optimum midsupply level (i.e., 2.5 V). Optimum noise performance, excellent THD performance, ability to use ± 5 V op amp. Flexible input range, optimum THD performance with VREF = 1. Noise performance improves while THD performance degrades as VREF increases to 2.5 V. Ability to use +5 V or ± 5 V op amp. Optimum full-scale THD and SFDR performance well beyond the A/D’s Nyquist frequency. Preferred mode for undersampling applications. Same as 2 V to 3 V input range with the exception that full-scale THD and SFDR performance can be traded off for better noise performance. Refer to discussion in AC Coupling and Interface Issue section and Simple AC Interface section. Optimum Noise performance. Also, the optimum THD and SFDR performance for “less than” full-scale signals (i.e., –6 dBFS). Refer to discussion in AC Coupling and Interface Issue section and Simple AC Interface section. 2 × VREF 0 to 2 × VREF VREF 13, 14 5 0 to 5 2.5 13, 14 2 × VREF 2.5 – VREF to 2.5 + VREF 2.5 24 Single-Ended AC 2 or 0 to 1 or 1 or VREF 2 × VREF 0 to 2 × VREF 5 0 to 5 2.5 2.5 15 15 16 2 × VREF 2.5 – VREF to 2.5 + VREF Differential AC (via Transformer) 2 2 to 3 3 to 2 19 2 × VREF 2.5 – VREF/2 to 2.5 + VREF/2 2.5 + VREF/2 19 to 2.5 – VREF/2 5 1.75 to 3.25 3.25 to 1.75 19 *VINA and VINB can be interchanged if signal inversion is required. R EV. E –13– AD9221/AD9223/AD9220 Table II. Reference Configuration Summary Reference Operating Mode INTERNAL INTERNAL INTERNAL EXTERNAL (Nondynamic) EXTERNAL (Dynamic) Input Span (VINA–VINB) (V p-p) 2 5 2 ≤ SPAN ≤ 5 and SPAN = 2 × VREF 2 ≤ SPAN ≤ 5 2 ≤ SPAN ≤ 5 Required VREF (V) 1 2.5 1 ≤ VREF ≤ 2.5 and VREF = (1 + R1/R2) 1 ≤ VREF ≤ 2.5 CAPT and CAPB Externally Driven Connect SENSE SENSE R1 R2 SENSE VREF SENSE VREF EXT. REF. EXT. REF. To VREF REFCOM VREF and SENSE SENSE and REFCOM AVDD EXT. REF. AVDD REFCOM CAPT CAPB DRIVING THE ANALOG INPUTS Introduction The AD9221/AD9223/AD9220 has a highly flexible input structure, allowing it to interface with single-ended or differential input interface circuitry. The applications shown in sections Driving the Analog Inputs and Reference Configurations, along with the information presented in Input and Reference Overview of this data sheet, give examples of both single-ended and differential operation. Refer to Tables I and II for a list of the different possible input and reference configurations and their associated figures in the data sheet. The optimum mode of operation, analog input range, and associated interface circuitry will be determined by the particular application’s performance requirements as well as power supply options. For example, a dc coupled single-ended input would be appropriate for most data acquisition and imaging applications. Also, many communication applications that require a dc coupled input for proper demodulation can take advantage of the excellent single-ended distortion performance of the AD9221/AD9223/ AD9220. The input span should be configured such that the system’s performance objectives and the headroom requirements of the driving op amp are simultaneously met. Alternatively, the differential mode of operation with a transformer coupled input provides the best THD and SFDR performance over a wide frequency range. This mode of operation should be considered for the most demanding spectral based applications that allow ac coupling (e.g., Direct IF to Digital Conversion). Single-ended operation requires that VINA be ac- or dc-coupled to the input signal source while VINB of the AD9221/AD9223/ AD9220 can be biased to the appropriate voltage corresponding to a midscale code transition. Note that signal inversion may be easily accomplished by transposing VINA and VINB. The rated specifications for the AD9221/AD9223/AD9220 are characterized using single-ended circuitry with input spans of 5 V and 2 V as well as VINB = 2.5 V. Differential operation requires that VINA and VINB be simultaneously driven with two equal signals that are in and out of phase versions of the input signal. Differential operation of the AD9221/AD9223/AD9220 offers the following benefits: (1) Signal swings are smaller and therefore linearity requirements placed on the input signal source may be easier to achieve, (2) Signal swings are smaller and therefore may allow the use of op amps that may otherwise have been constrained by headroom 20 30 40 AD9223 CMR – dB 50 60 AD9220 70 AD9221 80 90 0.1 1 10 FREQUENCY– MHz 100 Figure 11. AD9221/AD9223/AD9220 Input CMR vs. Input Frequency limitations, (3) Differential operation minimizes even-order harmonic products, and (4) Differential operation offers noise immunity based on the device’s common-mode rejection. Figure 11 depicts the common-mode rejection of the three devices. As is typical of most CMOS devices, exceeding the supply limits will turn on internal parasitic diodes, resulting in transient currents within the device. Figure 12 shows a simple means of clamping an ac- or dc-coupled single-ended input with the addition of two series resistors and two diodes. An optional capacitor is shown for ac-coupled applications. Note that a larger series resistor could be used to limit the fault current through D1 and D2 but should be evaluated since it can cause a degradation in overall performance. A similar clamping circuit could also be used for each input if a differential input signal is being applied. –14– R EV. E AD9221/AD9223/AD9220 VCC OPTIONAL AC COUPLING CAPACITOR RS1 30 AVDD D2 1N4148 D1 1N4148 VEE RS2 20 network can be inserted between the op amp’s output and the AD9221/AD9223/AD9220 input to provide a real pole. AD9221/ AD9223/ AD9220 Simple Op Amp Buffer Figure 12. Simple Clamping Circuit SINGLE-ENDED MODE OF OPERATION The AD9221/AD9223/AD9220 can be configured for singleended operation using dc or ac coupling. In either case, the input of the A/D must be driven from an operational amplifier that will not degrade the A/D’s performance. Because the A/D operates from a single-supply, it will be necessary to level-shift ground-based bipolar signals to comply with its input requirements. Both dc and ac coupling provide this necessary function, but each method results in different interface issues that may influence the system design and performance. DC COUPLING AND INTERFACE ISSUES In the simplest case, the input signal to the AD9221/AD9223/ AD9220 will already be biased at levels in accordance with the selected input range. It is simply necessary to provide an adequately low source impedance for the VINA and VINB analog input pins of the A/D. Figure 13 shows the recommended configuration for a single-ended drive using an op amp. In this case, the op amp is shown in a noninverting unity gain configuration driving the VINA pin. The internal reference drives the VINB pin. Note that the addition of a small series resistor of 30 Ω to 50 Ω connected to VINA and VINB will be beneficial in nearly all cases. Refer to the Analog Input Operation section for a discussion on resistor selection. Figure 13 shows the proper connection for a 0 V to 5 V input range. Alternative single-ended input ranges of 0 V to 2 × VREF can also be realized with the proper configuration of VREF (refer to the Using the Internal Reference section). +V 5V 0V U1 RS RS –V 2.5V 10 F 0.1 F SENSE Many applications require the analog input signal to be dccoupled to the AD9221/AD9223/AD9220. An operational amplifier can be configured to rescale and level shift the input signal so that it is compatible with the selected input range of the A/D. The input range to the A/D should be selected on the basis of system performance objectives as well as the analog power supply availability since this will place certain constraints on the op amp selection. Many of the new high performance op amps are specified for only ± 5 V operation and have limited input/output swing capabilities. Therefore, the selected input range of the AD9221/ AD9223/AD9220 should be sensitive to the headroom requirements of the particular op amp to prevent clipping of the signal. Also, since the output of a dual supply amplifier can swing below –0.3 V, clamping its output should be considered in some applications. In some applications, it may be advantageous to use an op amp specified for single-supply 5 V operation since it will inherently limit its output swing to within the power supply rails. An amplifier like the AD8041, AD8011, and AD817 are useful for this purpose. Rail-to-rail output amplifiers such as the AD8041 allow the AD9221/AD9223/AD9220 to be configured for larger input spans, which improves the noise performance. If the application requires the largest input span (i.e., 0 V to 5 V) of the AD9221/AD9223/AD9220, the op amp will require larger supplies to drive it. Various high speed amplifiers in the Op Amp Selection Guide of this data sheet can be selected to accommodate a wide range of supply options. Once again, clamping the output of the amplifier should be considered for these applications. Two dc-coupled op amp circuits using a noninverting and inverting topology are discussed below. Although not shown, the noninverting and inverting topologies can be easily configured as part of an antialiasing filter by using a Sallen-Key or Multiple-Feedback topology, respectively. An additional R-C VINA VINB VREF AD9221/ AD9223/ AD9220 Figure 13. Single-Ended AD9221/AD9223/AD9220 Op Amp Drive Circuit Op Amp with DC Level Shifting Figure 14 shows a dc-coupled level shifting circuit employing an op amp, A1, to sum the input signal with the desired dc offset. Configuring the op amp in the inverting mode with the given resistor values results in an ac signal gain of –1. If the signal inversion is undesirable, interchange the VINA and VINB connections to re-establish the original signal polarity. The dc voltage at VREF sets the common-mode voltage of the AD9221/AD9223/ AD9220. For example, when VREF = 2.5 V, the output level from the op amp will also be centered around 2.5 V. The use of ratio matched, thin-film resistor networks will minimize gain and offset errors. Also, an optional pull-up resistor, RP, may be used to reduce the output load on VREF to ± 1 mA. 500 1 +VCC 0.1 F +VREF –VREF RP2 0VDC 1 3 4 500 1 NC 2 7 1 A1 500 0.1 F 5 6 RS VINA AVDD 500 1 NC RS AD9221/ AD9223/ AD9220 VINB VREF NOTES 1OPTIONAL RESISTOR NETWORK-OHMTEK ORNA500D 2OPTIONAL PULL-UP RESISTOR WHEN USING INTERNAL REFERENCE Figure 14. Single-Ended Input with DC-Coupled Level Shift R EV. E –15– AD9221/AD9223/AD9220 AC COUPLING AND INTERFACE ISSUES For applications where ac coupling is appropriate, the op amp’s output can be easily level shifted to the common-mode voltage, VCM, of the AD9221/AD9223/AD9220 via a coupling capacitor. This has the advantage of allowing the op amp’s common-mode level to be symmetrically biased to its midsupply level (i.e., (VCC + VEE)/2). Op amps that operate symmetrically with respect to their power supplies typically provide the best ac performance as well as the greatest input/output span. Thus, various high speed/performance amplifiers that are restricted to +5 V/–5 V operation and/or specified for 5 V single-supply operation can be easily configured for the 5 V or 2 V input span of the AD9221/ AD9223/AD9220. The best ac distortion performance is achieved when the A/D is configured for a 2 V input span and commonmode voltage of 2.5 V. Note that differential transformer coupling, which is another form of ac coupling, should be considered for optimum ac performance. Simple AC Interface in parallel to achieve a low cutoff frequency while maintaining a low impedance over a wide frequency range. RS isolates the buffer amplifier from the A/D input. The optimum performance is achieved when VINA and VINB are driven via «Immetrical networks. The f–3 dB point can be approximated by the equation, f –3 dB = 1 / 2 × π × R / 2 × (C1 + C 2) +5V +5V VIN C1 R RS R VINA ( ) C2 –5V R +5V R C2 AD9221/ AD9223/ AD9220 RS VINB C1 Figure 15 shows a typical example of an ac-coupled, single-ended configuration. The bias voltage shifts the bipolar, ground-referenced input signal to approximately VREF. The value for C1 and C2 will depend on the size of the resistor, R. The capacitors, C1 and C2, are typically a 0.1 µF ceramic and 10 µF tantalum capacitor in parallel to achieve a low cutoff frequency while maintaining a low impedance over a wide frequency range. The combination of the capacitor and the resistor form a high-pass filter with a high-pass –3 dB frequency determined by the equation, f3 dB = 1 / 2 × π × R × (C1 + C 2) Figure 16. AC-Coupled Input-Flexible Input Span, VCM = 2 V Op Amp Selection Guide ( ) The low impedance VREF voltage source both biases the VINB input and provides the bias voltage for the VINA input. Figure 15 shows the VREF configured for 2.5 V; thus the input range C1 +5V +VREF 0V –VREF VIN C2 RS R –5V RS VINB VREF C2 C1 SENSE Op amp selection for the AD9221/AD9223/AD9220 is highly dependent on a particular application. In general, the performance requirements of any given application can be characterized by either time domain or frequency domain parameters. In either case, one should carefully select an op amp that preserves the performance of the A/D. This task becomes challenging when one considers the AD9221/AD9223/AD9220’s high performance capabilities coupled with other extraneous system level requirements such as power consumption and cost. The ability to select the optimal op amp may be further complicated by either limited power supply availability and/or limited acceptable supplies for a desired op amp. Newer, high performance op amps typically have input and output range limitations in accordance with their lower supply voltages. As a result, some op amps will be more appropriate in systems where ac-coupling is allowable. When dc-coupling is required, op amps without headroom constraints, such as rail-to-rail op amps or ones where larger supplies can be used, should be considered. The following section describes some op amps currently available from Analog Devices. The system designer is always encouraged to contact the factory or local sales office to be updated on Analog Devices’ latest amplifier product offerings. Highlights of the areas where the op amps excel and where they may limit the performance of the AD9221/AD9223/AD9220 is also included. AD817: 50 MHz Unity GBW, 70 ns Settling to 0.01%, +5 V to ± 15 V Supplies Best Applications: Sample Rates < 7 MSPS, Low Noise, 5 V p-p Input Range Limits: THD above 100 kHz Dual Version of AD817 Best Applications: Differential and/or Low Impedance Input Drivers, Low Noise Limits: THD above 100 kHz 130 MHz @ G = +2 BW, 80 ns Settling to 0.01%, +5 V to ± 15 V Supplies Best Applications: Sample Rates < 7 MSPS, Low Noise, 5 V p-p Input Range, Gains ≥ +2 Limits: THD above 100 kHz R EV. E VINA AD9220 AD9221/ AD9223/ Figure 15. AC-Coupled Input of the A/D is 0 V to 5 V. Other input ranges could be selected by changing VREF, but the A/D’s distortion performance will degrade slightly as the input common-mode voltage deviates from its optimum level of 2.5 V. Alternative AC Interface Figure 16 shows a flexible ac-coupled circuit that can be configured for different input spans. Since the common-mode voltage of VINA and VINB are biased to midsupply independent of VREF, VREF can be pin-strapped or reconfigured to achieve input spans between 2 V and 5 V p-p. The AD9221/AD9223/ AD9220’s CMRR along with the symmetrical coupling R-C networks will reject both power supply variations and noise. The resistors, R, establish the common-mode voltage. They may have a high value (e.g., 5 kΩ) to minimize power consumption and establish a low cutoff frequency. The capacitors, C1 and C2, are typically 0.1 µF ceramic and 10 µF tantalum capacitors AD826: AD818: –16– AD9221/AD9223/AD9220 AD828: Dual Version of AD818 Best Applications: Differential and/or Low Impedance Input Drivers, Low Noise, Gains ≥ +2 Limits: THD above 100 kHz Dual, 145 MHz Unity GBW, Single-Supply Current Feedback, +5 V to ± 15 V Supplies Best Applications: Differential and/or Low Impedance Input Drivers, Sample Rates < 7 MSPS Limits: THD above 1 MHz f–3 dB = 300 MHz, +5 V or ± 5 V Supplies, Current Feedback Best Applications: Single-Supply, AC-DC-Coupled, Good AC Specs, Low Noise, Low Power (5 mW) Limits: THD above 5 MHz, Usable Input/Output Range Triple, f–3 dB = 230 MHz, +5 V or ± 5 V Supplies, Current Feedback, Disable Function Best Applications: 3:1 Multiplexer, Good AC Specs Limits: THD above 5 MHz, Input Range 220 MHz Unity GBW, 16 ns Settling to 0.01%, ± 5 V Supplies Best Applications: Best AC Specs, Low Noise, AC-Coupled Limits: Usable Input/Output Range, Power Consumption 130 MHz Unity GBW, 30 ns Settling to 0.01%, ± 5 V Supplies Best Applications: Good AC Specs, Low Noise, AC-Coupled Limits: THD > 5 MHz, Usable Input Range Rail-to-Rail, 160 MHz Unity GBW, 55 ns Settling to 0.01%, 5 V Supply, 26 mW Best Applications: Low Power, Single-Supply Systems, DC-Coupled, Large Input Range Limits: Noise with 2 V Input Range Dual AD8041 Best Applications: Differential and/or Low Impedance Input Drivers Limits: Noise with 2 V Input Range THD – dB AD812: Note that although a single-ended-to-differential op amp topology would allow dc coupling of the input signal, no significant improvement in THD performance was realized when compared to the dc single-ended mode of operation up to the AD9221/ AD9223/AD9220’s Nyquist frequency (i.e., fIN < fS/2). Also, the additional op amp required in the topology tends to increase the total system noise, power consumption, and cost. Thus, a single-ended mode of operation is recommended for most applications requiring dc coupling. A dramatic improvement in THD and SFDR performance can be realized by operating the AD9221/AD9223/AD9220 in the differential mode using a transformer. Figure 17 shows a plot of THD versus Input Frequency for the differential transformer coupled circuit for each A/D while Figure 18 shows a plot of SFDR versus Input Frequency. Both figures demonstrate the enhancement in spectral performance for the differential-mode of operation. The performance enhancement between the differential and single-ended mode is most noteworthy as the input frequency approaches and goes beyond the Nyquist frequency (i.e., fIN > fS/2) corresponding to the particular A/D. The figures are also helpful in determining the appropriate A/D for Direct IF down conversion or undersampling applications. Refer to Analog Devices application notes AN-301 and AN-302 for an informative discussion on undersampling. One should select the A/D that meets or exceeds the distortion performance requirements measured over the required frequency passband. For example, the AD9220 achieves the best distortion performance over an extended frequency range as a result of its greater full-power bandwidth and thus would represent the best selection for an IF undersampling application at 21.4 MHz. Refer to the Applications section of this data sheet for more detailed information and characterization of this particular application. –50 AD8011: AD8013: AD9631: AD8047: AD8041: –60 AD8042: –70 AD9221 AD9223 –80 DIFFERENTIAL MODE OF OPERATION Since not all applications have a signal preconditioned for differential operation, there is often a need to perform a single-ended-to-differential conversion. In systems that do not need to be dc-coupled, an RF transformer with a center tap is the best method to generate differential inputs for the AD9221/ AD9223/AD9220. It provides all the benefits of operating the A/D in the differential mode without contributing additional noise or distortion. An RF transformer also has the added benefit of providing electrical isolation between the signal source and the A/D. AD9220 –90 1 10 FREQUENCY – MHz 100 Figure 17. AD9221/AD9223/AD9220 THD vs. Input Frequency (VCM = 2.5 V, 2 V p-p Input Span, AIN = –0.5 dB) R EV. E –17– AD9221/AD9223/AD9220 –55 –65 AD9221 SFDR – dB AD9223 Figure 23 of this data sheet. Figure 20 demonstrates how both spans of the AD9220 achieve the high degree of linearity and SFDR over a wide range of amplitudes required by the most demanding communication applications. Similar performance is achievable with the AD9221 and AD9223 at their corresponding Nyquist frequency. 90 SFDR – 5.0V p-p SFDR – 2.0V p-p 70 –75 –85 AD9220 80 SNR/SFDR – dB –95 1 10 FREQUENCY – MHz 100 60 50 SNR – 2.0V p-p 40 SNR – 5.0V p-p 30 20 –50 Figure 18. AD9221/AD9223/AD9220 SFDR vs. Input Frequency (VCM = 2.5 V, 2 V p-p Input Span, AIN = –0.5 dB) Figure 19 shows the schematic of the suggested transformer circuit. The circuit uses a Mini-Circuits RF transformer, model #T4-6T, which has an impedance ratio of 4 (turns ratio of 2). The schematic assumes that the signal source has a 50 Ω source impedance. The 1:4 impedance ratio requires the 200 Ω secondary termination for optimum power transfer and VSWR. The center tap of the transformer provides a convenient means of level shifting the input signal to a desired common-mode voltage. Optimum performance can be realized when the center tap is tied to CML of the AD9221/AD9223/AD9220, which is the common-mode bias level of the internal SHA. RS 33 49.9 200 0.1 F CS 15pF VINA CML –40 –30 –20 –10 INPUT AMPLITUDE – dBFS 0 Figure 20. AD9220 SFDR, SNR vs. Input Amplitude (fIN = 5 MHz, fCLK = 10 MSPS, VCM = 2.5 V, Differential) AD9221/ AD9223/ AD9220 VINB Figure 20 also reveals a noteworthy difference in the SFDR and SNR performance of the AD9220 between the 2 V p-p and 5 V p-p input span options. First, the SNR performance improves by 2 dB with a 5.0 V p-p input span due to the increase in dynamic range. Second, the SFDR performance of the AD9220 will improve for input signals below approximately –6.0 dBFS. A 3 dB to 5 dB improvement was typically realized for input signal levels between –6.0 dBFS and –36 dBFS. This improvement in SNR and SFDR for a 5.0 V p-p span may be advantageous for communication systems that have additional margin or headroom to minimize clipping of the ADC. REFERENCE CONFIGURATIONS MINI-CIRCUITS T4-1 RS 33 CS 15pF Figure 19. Transformer Coupled Input Transformers with other turns ratios may also be selected to optimize the performance of a given application. For example, a given input signal source or amplifier may realize an improvement in distortion performance at reduced output power levels and signal swings. Therefore, selecting a transformer with a higher impedance ratio (e.g., Mini-Circuits T16-6T with a 1:16 impedance ratio) effectively “steps up” the signal level, thus further reducing the driving requirements of the signal source. Referring to Figure 19, a series resistor, RS, and shunt capacitor, CS, were inserted between the AD9221/AD9223/AD9220 and the secondary of the transformer. The values of 33 Ω and 15 pF were selected to specifically optimize both the THD and SNR performance of the A/D. RS and CS help provide some isolation from transients at the A/D inputs reflected back through the primary of the transformer. The AD9221/AD9223/AD9220 can be easily configured for either a 2 V p-p input span or 5.0 V p-p input span by setting the internal reference (see Table II). Other input spans can be realized with two external gain setting resistors as shown in The figures associated with this section on internal and external reference operation do not show recommended matching series resistors for VINA and VINB for the purpose of simplicity. Please refer to the Driving the Analog Inputs, Introduction section for a discussion of this topic. Also, the figures do not show the decoupling network associated with the CAPT and CAPB pins. Please refer to the Reference Operation section for a discussion of the internal reference circuitry and the recommended decoupling network shown in Figure 10. USING THE INTERNAL REFERENCE Single-Ended Input with 0 to 2 VREF Range Figure 21 shows how to connect the AD9221/AD9223/AD9220 for a 0 V to 2 V or 0 V to 5 V input range via pin strapping the SENSE pin. An intermediate input range of 0 to 2 × VREF can be established using the resistor programmable configuration in Figure 23 and connecting VREF to VINB. In either case, both the common-mode voltage and input span are directly dependent on the value of VREF. More specifically, the common-mode voltage is equal to VREF while the input span is equal to 2 × VREF. Thus, the valid input range extends from 0 to 2 × VREF. When VINA is ≤ 0 V, the digital output will be 000 Hex; when VINA is ≥ 2 × VREF, the digital output will be FFF Hex. R EV. E –18– AD9221/AD9223/AD9220 Shorting the VREF pin directly to the SENSE pin places the internal reference amplifier in unity-gain mode and the resultant VREF output is 1 V. Therefore, the valid input range is 0 V to 2 V. However, shorting the SENSE pin directly to the REFCOM pin configures the internal reference amplifier for a gain of 2.5 and the resultant VREF output is 2.5 V. Thus, the valid input range becomes 0 V to 5 V. The VREF pin should be bypassed to the REFCOM pin with a 10 µF tantalum capacitor in parallel with a low inductance 0.1 µF ceramic capacitor. 2 VREF 0V 10 F 0.1 F VREF SHORT FOR 0V TO 2V INPUT SPAN SENSE SHORT FOR 0V TO 5V INPUT SPAN REFCOM VINA VINB Resistor Programmable Reference Figure 23 shows an example of how to generate a reference voltage other than 1 V or 2.5 V with the addition of two external resistors and a bypass capacitor. Use the equation, VREF = 1V × (1 + R1 / R2) to determine appropriate values for R1 and R2. These resistors should be in the 2 kΩ to 100 kΩ range. For the example shown, R1 equals 2.5 kΩ and R2 equals 5 kΩ. From the equation above, the resultant reference voltage on the VREF pin is 1.5 V. This sets the input span to be 3 V p-p. To assure stability, place a 0.1 µF ceramic capacitor in parallel with R1. The common-mode voltage can be set to VREF by connecting VINB to VREF to provide an input span of 0 to 2 × VREF. Alternatively, the common-mode voltage can be set to VREF by connecting VINB to a low impedance 2.5 V source. For the example shown, the valid input single range for VINA is 1 V to 4 V since VINB is set to an external, low impedance 2.5 V source. The VREF pin should be bypassed to the REFCOM pin with a 10 µF tantalum capacitor in parallel with a low inductance 0.1 µF ceramic capacitor. 4V VINA 1V 2.5V 1.5V VREF 10 F 0.1 F R1 2.5k R2 5k REFCOM C1 0.1 F SENSE VINB AD9221/ AD9223/ AD9220 Figure 21. Internal Reference—2 V p-p Input Span, VCM = 1 V, or 5 V p-p Input Span, VCM = 2.5 V Single-Ended or Differential Input, V CM = 2.5 V Figure 22 shows the single-ended configuration that gives the best dynamic performance (SINAD, SFDR). To optimize dynamic specifications, center the common-mode voltage of the analog input at approximately by 2.5 V by connecting VINB to a low impedance 2.5 V source. As described above, shorting the VREF pin directly to the SENSE pin results in a 1 V reference voltage and a 2 V p-p input span. The valid range for input signals is 1.5 V to 3.5 V. The VREF pin should be bypassed to the REFCOM pin with a 10 µF tantalum capacitor in parallel with a low inductance 0.1 µF ceramic capacitor. This reference configuration could also be used for a differential input in which VINA and VINB are driven via a transformer as shown in Figure 19. In this case, the common-mode voltage, VCM, is set at midsupply by connecting the transformer’s center tap to CML of the AD9221/AD9223/AD9220. VREF can be configured for 1 V or 2.5 V by connecting SENSE to either VREF or REFCOM respectively. Note that the valid input range for each of the differential inputs is one-half of single-ended input and thus becomes VCM – VREF/2 to VCM + VREF/2. 3.5V VINA 1.5V 2.5V 1V 10 F 0.1 F VINB VREF SENSE REFCOM AD9220 Figure 23. Resistor Programmable Reference—3 V p-p Input Span, VCM = 2.5 V USING AN EXTERNAL REFERENCE Using an external reference may enhance the dc performance of the AD9221/AD9223/AD9220 by improving drift and accuracy. Figures 24 through 26 show examples of how to use an external reference with the A/D. Table III is a list of suitable voltage references from Analog Devices. To use an external reference, the user must disable the internal reference amplifier and drive the VREF pin. Connecting the SENSE pin to AVDD disables the internal reference amplifier. Table III. Suitable Voltage References AD9221/ AD9223/ AD9220 Output Voltage Internal AD589 AD1580 REF191 Internal REF192 REF43 AD780 1.00 1.235 1.225 2.048 2.50 2.50 2.50 2.50 Drift (ppm/ C) 26 10–100 50–100 5–25 26 5–25 10–25 3–7 Initial Accuracy % (max) 1.4 1.2–2.8 0.08–0.8 0.1–0.5 1.4 0.08–0.4 0.06–0.1 0.04–0.2 Operating Current ( A) N/A 50 50 45 N/A 45 600 1000 Figure 22. Internal Reference—2 V p-p Input Span, VCM = 2.5 V R EV. E –19– AD9221/AD9223/AD9220 The AD9221/AD9223/AD9220 contains an internal reference buffer, A2 (see Figure 9), that simplifies the drive requirements of an external reference. The external reference must be able to drive a ≈5 kΩ (± 20%) load. Note that the bandwidth of the reference buffer is deliberately left small to minimize the reference noise contribution. As a result, it is not possible to change the reference voltage rapidly in this mode without the removal of the CAPT/CAPB Decoupling Network. Variable Input Span with V CM = 2.5 V conjunction with 1/2 of an OP282 to provide a very low impedance drive for VINB. The selected op amp need not be a high speed op amp and may be selected based on cost, power, and accuracy. 3.75V VINA 1.25V 820 1k 1k 2N2222 1k 7.5k 5V 10 F 0.1 F 5V 0.1 F VINB AD9221/ AD9223/ AD9220 Figure 24 shows an example of the AD9221/AD9223/AD9220 configured for an input span of 2 × VREF centered at 2.5 V. An external 2.5 V reference drives the VINB pin, thus setting the common-mode voltage at 2.5 V. The input span can be independently set by a voltage divider consisting of R1 and R2, which generates the VREF signal. A1 buffers this resistor network and drives VREF. Choose this op amp based on accuracy requirements. It is essential that a minimum of a 10 µF capacitor in parallel with a 0.1 µF low inductance ceramic capacitor decouple the reference output to ground. 2.5V+VREF 2.5V 2.5V–VREF +5V 0.1 F 2.5V REF VINA 1/2 OP282 AD1580 316 1.225V 10 F 0.1 F 5V SENSE VREF Figure 26. External Reference Using the AD1580 and Low Impedance Buffer DIGITAL INPUTS AND OUTPUTS Digital Outputs AD9221/ AD9223/ AD9220 VINB 22 F R1 A1 0.1 F R2 +5V SENSE 0.1 F VREF The AD9221/AD9223/AD9220 output data is presented in positive true straight binary for all input ranges. Table IV indicates the output data formats for various input ranges regardless of the selected input range. A twos complement output data format can be created by inverting the MSB. Table IV. Output Data Format Figure 24. External Reference—VCM = 2.5 V (2.5 V on VINB, Resistor Divider to Make VREF) Single-Ended Input with 0 to 2 VREF Range Input (V) VINA –VINB VINA –VINB VINA –VINB VINA –VINB VINA –VINB Condition (V) < – VREF = – VREF =0 = + VREF – 1 LSB ≥ + VREF Digital Output 0000 0000 0000 0000 0000 0000 1000 0000 0000 1111 1111 1111 1111 1111 1111 +FS –1 1/2 LSB OTR 1 0 0 0 1 Figure 25 shows an example of an external reference driving both VINB and VREF. In this case, both the common-mode voltage and input span are directly dependent on the value of VREF. More specifically, the common-mode voltage is equal to VREF while the input span is equal to 2 × VREF. Thus, the valid input range extends from 0 to 2 × VREF. For example, if the REF-191, a 2.048 external reference was selected, the valid input range extends from 0 to 4.096 V. In this case, 1 LSB of the AD9221/AD9223/AD9220 corresponds to 1 mV. It is essential that a minimum of a 10 µF capacitor in parallel with a 0.1 µF low inductance ceramic capacitor decouple the reference output to ground. 2 REF VINA 0V +5V 0.1 F VREF 10 F 0.1 F VREF 0.1 F +5V SENSE VINB OTR DATA OUTPUTS 1 0 0 1111 1111 1111 1111 1111 1111 1111 1111 1110 OTR –FS+1/2 LSB 0 0 1 0000 0000 0001 0000 0000 0000 0000 0000 0000 –FS –FS –1/2 LSB +FS +FS –1/2 LSB AD9221/ AD9223/ AD9220 Figure 27. Output Data Format Out Of Range (OTR) Figure 25. Input Range = 0 V to 2 × VREF Low Cost/Power Reference The external reference circuit shown in Figure 26 uses a low cost 1.225 V external reference (e.g., AD580 or AD1580) along with an op amp and transistor. The 2N2222 transistor acts in An out-of-range condition exists when the analog input voltage is beyond the input range of the converter. OTR is a digital output that is updated along with the data output corresponding to the particular sampled analog input voltage. Thus, OTR has the same pipeline delay (latency) as the digital data. It is LOW when the analog input voltage is within the analog input range. It is HIGH when the analog input voltage exceeds the input range as shown in Figure 27. OTR will remain HIGH until the analog input returns within the input range and another conversion is completed. By logical ANDing OTR with the MSB and its complement, overrange high or underrange low conditions –20– R EV. E AD9221/AD9223/AD9220 can be detected. Table V is a truth table for the over/underrange circuit in Figure 28, which uses NAND gates. Systems requiring programmable gain conditioning of the AD9221/AD9223/ AD9220 input signal can immediately detect an out-of-range condition, thus eliminating gain selection iterations. Also, OTR can be used for digital offset and gain calibration. Table V. Out-of-Range Truth Table In the equation, the rms aperture jitter, tA, represents the rootsum square of all the jitter sources, which include the clock input, analog input signal, and A/D aperture jitter specification. For example, if a 5 MHz full-scale sine wave is sampled by an A/D with a total rms jitter of 15 ps, the SNR performance of the A/D will be limited to 66.5 dB. Undersampling applications are particularly sensitive to jitter. The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9221/ AD9223/AD9220. As such, supplies for clock drivers should be separated from the A/D output driver supplies to avoid modulating the clock signal with digital noise. Low jitter crystal controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other method), it should be retimed by the original clock at the last step. Most of the power dissipated by the AD9221/AD9223/AD9220 is from the analog power supplies. However, lower clock speeds will reduce digital current slightly. Figure 29 shows the relationship between power and clock rate for each A/D. 66 64 62 60 5V p-p 58 2V p-p 56 54 52 50 48 0.5 1.0 1.5 2.0 2.5 3.0 OTR 0 0 1 1 MSB OTR MSB 0 1 0 1 Analog Input Is In Range In Range Underrange Overrange OVER = “1” UNDER = “1” MSB Figure 28. Overrange or Underrange Logic Digital Output Driver Considerations (DVDD) The AD9221, AD9223 and AD9220 output drivers can be configured to interface with 5 V or 3.3 V logic families by setting DVDD to 5 V or 3.3 V respectively. The AD9221/AD9223/ AD9220 output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause glitches on the supplies and may affect SINAD performance. Applications requiring the AD9221/ AD9223/AD9220 to drive large capacitive loads or large fanout may require additional decoupling capacitors on DVDD. In extreme cases, external buffers or latches may be required. Clock Input and Considerations POWER – mW POWER – mW The AD9221/AD9223/AD9220 internal timing uses the two edges of the clock input to generate a variety of internal timing signals. The clock input must meet or exceed the minimum specified pulsewidth high and low (tCH and tCL) specifications for the given A/D as defined in the Switching Specifications to meet the rated performance specifications. For example, the clock input to the AD9220 operating at 10 MSPS may have a duty cycle between 45% to 55% to meet this timing requirement since the minimum specified tCH and tCL is 45 ns. For clock rates below 10 MSPS, the duty cycle may deviate from this range to the extent that both tCH and tCL are satisfied. All high speed high resolution A/Ds are sensitive to the quality of the clock input. The degradation in SNR at a given full-scale input frequency (fIN) due to only aperture jitter (tA) can be calculated with the following equation: SNR = 20 log10 [1 / 2π fIN t A ] CLOCK FREQUENCY – MHz Figure 29a. AD9221 Power Consumption vs. Clock Frequency 125 120 115 110 5V p-p 105 2V p-p 100 95 90 0 1 2 3 4 5 6 CLOCK FREQUENCY – MHz Figure 29b. AD9223 Power Consumption vs. Clock Frequency R EV. E –21– AD9221/AD9223/AD9220 300 280 INPUT = 5V p-p POWER – mW 260 impedance over a wide frequency range. Note that the AVDD and AVSS pins are co-located on the AD9221/ AD9223/AD9220 to simplify the layout of the decoupling capacitors and provide the shortest possible PCB trace lengths. The AD9221/AD9223/AD9220/EB power plane layout, shown in Figure 40 depicts a typical arrangement using a multilayer PCB. INPUT = 2V p-p 26 AVDD 240 220 0.1 F 25 AVSS AD9221/ AD9223/ AD9220 200 0 2 4 6 8 10 12 14 0.1 F 15 AVDD 16 AVSS CLOCK FREQUENCY – MHz Figure 29c. AD9220 Power Consumption vs. Clock Frequency Figure 30. Analog Supply Decoupling GROUNDING AND DECOUPLING Analog and Digital Grounding Proper grounding is essential in any high speed, high resolution system. Multilayer printed circuit boards (PCBs) are recommended to provide optimal grounding and power schemes. The use of ground and power planes offers distinct advantages: 1. The minimization of the loop area encompassed by a signal and its return path. 2. The minimization of the impedance associated with ground and power paths. 3. The inherent distributed capacitor formed by the power plane, PCB insulation, and ground plane. These characteristics result in both a reduction of electromagnetic interference (EMI) and an overall improvement in performance. It is important to design a layout that prevents noise from coupling onto the input signal. Digital signals should not be run in parallel with input signal traces and should be routed away from the input circuitry. While the AD9221/AD9223/AD9220 features separate analog and digital ground pins, it should be treated as an analog component. The AVSS and DVSS pins must be joined together directly under the AD9221/AD9223/AD9220. A solid ground plane under the A/D is acceptable if the power and ground return currents are managed carefully. Alternatively, the ground plane under the A/D may contain serrations to steer currents in predictable directions where cross-coupling between analog and digital would otherwise be unavoidable. The AD9221/ AD9223/AD9220/EB ground layout, shown in Figure 39, depicts the serrated type of arrangement. The analog and digital grounds are connected by a jumper below the A/D. Analog and Digital Supply Decoupling The CML is an internal analog bias point used internally by the AD9221/AD9223/AD9220. This pin must be decoupled with at least a 0.1 µF capacitor as shown in Figure 31. The dc level of CML is approximately AVDD/2. This voltage should be buffered if it is to be used for any external biasing. AD9221/ AD9223/ AD9220 22 CML 0.1 F Figure 31. CML Decoupling The digital activity on the AD9221/AD9223/AD9220 chip falls into two general categories: correction logic and output drivers. The internal correction logic draws relatively small surges of current, mainly during the clock transitions. The output drivers draw large current impulses while the output bits are changing. The size and duration of these currents are a function of the load on the output bits: large capacitive loads are to be avoided. Note, the internal correction logic of the AD9221, AD9223, and AD9220 is referenced to AVDD while the output drivers are referenced to DVDD. The decoupling shown in Figure 32, a 0.1 µF ceramic chip capacitor, is appropriate for a reasonable capacitive load on the digital outputs (typically 20 pF on each pin). Applications involving greater digital loads should consider increasing the digital decoupling proportionally, and/or using external buffers/latches. 28 DVDD 0.1 F 27 DVSS AD9221/ AD9223/ AD9220 The AD9221/AD9223/AD9220 features separate analog and digital supply and ground pins, helping to minimize digital corruption of sensitive analog signals. In general, AVDD, the analog supply, should be decoupled to AVSS, the analog common, as close to the chip as physically possible. Figure 30 shows the recommended decoupling for the analog supplies; 0.1 µF ceramic chip capacitors should provide adequately low Figure 32. Digital Supply Decoupling A complete decoupling scheme will also include large tantalum or electrolytic capacitors on the PCB to reduce low frequency ripple to negligible levels. Refer to the AD9221/AD9223/ AD9220/EB schematic and layouts in Figures 36 to 42 for more information regarding the placement of decoupling capacitors. –22– R EV. E AD9221/AD9223/AD9220 APPLICATIONS Direct IF Down Conversion Using the AD9220 90 80 70 SFDR 60 SNR/SFDR – dB As previously noted, the AD9220’s performance in the differential mode of operation extends well beyond its baseband region and into several Nyquist zone regions. Thus, the AD9220 may be well suited as a mix down converter in both narrow and wideband applications. Various IF frequencies exist over the frequency range in which the AD9220 maintains excellent dynamic performance (e.g., refer to Figure 17 and 18). The IF signal will be aliased to the ADC’s baseband region due to the sampling process in a similar manner that a mixer will downconvert an IF signal. For signals in various Nyquist zones, the following equation may be used to determine the final frequency after aliasing. f1 NYQUIST = fSIGNAL f2 NYQUIST = fSAMPLE – fSIGNAL f3 NYQUIST = abs (fSAMPLE – fSIGNAL) f4 NYQUIST = 2 × fSAMPLE – fSIGNAL f5 NYQUIST = abs (2 × fSAMPLE – fSIGNAL) There are several potential benefits in using the ADC to alias (i.e., or mix) down a narrow-band or wideband IF signal. First and foremost is the elimination of a complete mixer stage with its associated amplifiers and filters, reducing cost and power dissipation. Second is the ability to apply various DSP techniques to perform such functions as filtering, channel selection, quadrature demodulation, data reduction, and detection. One common example is the digitization of a 21.4 MHz IF using a low jitter 10 MHz sample clock. Using the equation above for the fifth Nyquist zone, the resultant frequency after sampling is 1.4 MHz. Figure 33 shows the typical performance of the AD9220 operating under these conditions. Figure 34 demonstrates how the AD9220 is still able to maintain a high degree of linearity and SFDR over a wide amplitude. 0 1 50 SNR 40 30 20 10 0 –50 –40 –30 –20 AIN – dB –10 0 Figure 34. AD9220 Differential Input SNR/SFDR vs. Input Amplitude (AIN) @ 21.4 MHz Multichannel Data Acquisition with Autocalibration The AD9221/AD9223/AD9220 is well suited for high performance, low power data acquisition systems. Aside from its exceptional ac performance, it exhibits true 12-bit linearity and temperature drift performance (i.e., excluding internal reference). Furthermore, the A/D product family provides the system designer with an upward or downward component selection path based on power consumption and sampling rate. A typical multichannel data acquisition system is shown in Figure 35. Also shown is some additional inexpensive gain and offset autocalibration circuitry that is often required in high accuracy data acquisition systems. These additional peripheral components were selected based on their performance, power consumption, and cost. Referring to Figure 35, the AD9221/AD9223/AD9220 is configured for single-ended operation with a 2.5 V p-p input span and a 2.5 V common-mode voltage using an external, precision 2.5 voltage reference, U1. This configuration and input span allows the buffer amplifier, U4, to be single supply. Also, it simplifies the design of the low temperature drift autocalibration circuitry that uses thin-film resistors for temperature stability and ratiometric accuracy. The input of the AD9221/AD9223/AD9220 can be easily configured for a wider span but it should remain within the input/output swing capabilities of a high speed, railto-rail, single-supply amplifier, U4 (e.g., AD8041). The gain and offset calibration circuitry is based on two 8-bit, current-output DAC08s, U3 and U5. The gain calibration circuitry consisting of U3, and an op amp, U2A, is configured to provide a low drift nominal 1.25 V reference to the AD9221/ AD9223/AD9220. The resistor values that set the gain calibration range were selected to provide a nominal adjustment span of ± 128 LSBs with 1 LSB resolution with respect to the A/D. Note that the bandwidth of the reference is low and, as a result, it is not possible to change the reference voltage rapidly in this mode. –20 ENCODE = 10MSPS AIN = 21.4MHz AMPLITUDE – dB –40 –60 –80 7 8 6 9 2 5 3 4 –100 –120 1 FREQUENCY – MHz 5 Figure 33. IF Sampling a 21.4 MHz Input Using the AD9220 (VCM = 2.5 V, Input Span = 2 V p-p) R EV. E –23– AD9221/AD9223/AD9220 The offset calibration circuitry consists of a DAC, U5 and the buffer amplifier, U4. The DAC is configured for a bipolar adjustment span of ± 64 LSB with a 1/2 LSB resolution span with respect to the AD9221/AD9223/AD9220. Note that both current outputs of U5 were configured to provide a bipolar adjustment span. Also, RC is used to decouple the output of both DACs, U3 and U5, from their respective op amps. The calibration procedure consists of a two step process. First, the bipolar offset is calibrated by selecting CH2, the 2.5 V system reference, of the analog multiplexer and preloading the DAC, U5, with a midscale code of 1000 0000. If possible, several readings of the A/D should be taken and averaged to determine the required digital offset adjustment code, U5. This averaged offset code requires an extra bit of resolution since 1 LSB of U5 equates to 1/2 LSB of the AD9221/AD9223/AD9220. The required offset correction code to U5 can then be determined. Second, the system gain is calibrated by selecting CH2, a 1.25 V 0.1 F input that corresponds to –FS of the A/D. Before the value is read, U4 should be preloaded with a code of 00 (Hex). Several readings can also be taken and averaged to determine the digital gain adjustment code to U2A. In this case, 1 LSB of the A/D corresponds to 1 LSB of U4. Due to the AD9221/AD9223/AD9220’s excellent INL performance, a two-point calibration procedure (i.e., –FS to midscale) instead of an endpoint calibration procedure was chosen. Also, since the bipolar offset is insensitive to any gain adjustment (due to the differential SHA of the A/D), an iterative calibration process is not required. The temperature stability of the circuit is enhanced by selecting a dual precision op amp for U2 (e.g., OP293) and low temperature drift, thin film resistors. Note that this application circuit was not built at the release of this data sheet. Please consult Analog Devices for application assistance or comments. 1.25k 1.25V U2B 2.5k 2.5k 0.1 F 2.5k 162 2.5k 0.1 F 1.1k 2 RC 100 VREF IOUT 39 +5V SENSE U2A 1.25V 39mV CH1 CH2 CH3 CH4 CH6 CH7 CH8 0.1 F 10 F U1 REF43 2.5k VREF(+) IOUT U6 CH5 ADG608 OUT VREF(–) 2.5k U3 DAC08 AD9221/ AD9223/ AD9220 39 VINA 39 VINB BIT 1 – BIT 12 OTR U4 2.50V 2.5k VREF(+) VREF(–) 2.5k RC 100 RC 100 U5 DAC08 IOUT IOUT Figure 35. Typical Multichannel Data Acquisition System –24– R EV. E AD9221/AD9223/AD9220 +5A TPA VINA D3 1N5711 A C26 0.1 F C24 10 F 16V C25 0.1 F TPB VINB D5 1N5711 JP10 A C15 15pF A C14 0.1 F A +5A D4 1N5711 C13 15pF A NOT INSTALLED C23 0.1 F D2 1N5711 C19 0.1 F A C18 0.1 F 15 26 23 20 21 22 24 18 17 19 AGND 27 DGND 28 25 +5D 16 A C20 0.1 F +5A JP19 AD9221/ AD9223/ AD9220 BIT 1 AVDD OTR AVDD BIT 2 VINA BIT 3 CAPB BIT 4 CAPT CML U5 BIT 5 BIT 6 VINB BIT 7 VREF BIT 8 SENSE REFCOM BIT 9 BIT 10 DVSS BIT 11 DVDD BIT 12 AVSS CLK AVSS 13 14 12 11 10 9 8 7 6 5 4 3 2 1 MSB OTR BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 BIT 10 BIT 11 LSB 1 U8 2 MSB 1 19 BIT 7 9 BIT 6 8 BIT 5 7 BIT 4 6 BIT 3 5 BIT 2 4 MSB 3 2 10 74HC541N G1 Y5 G2 Y4 A7 Y3 A6 Y2 A5 U6 Y1 A4 Y0 A3 Y7 A2 Y6 A1 A0 GND +5VD 13 14 15 16 17 18 11 12 Y0A Y1A Y2A Y3A Y4A Y5A JP20 R15 TP16 22 1 J8 74HC04N R16 TP15 Y5A 22 R17 TP14 Y4A 22 R18 TP13 22 3 J8 5 J8 A TP1 C28 0.1 F A Y3A 7 J8 R19 TP12 22 9 J8 R20 TP11 22 11 J8 R21 TP10 22 13 J8 R22 22 R23 22 R24 22 R25 22 R26 22 TP9 15 J8 TP8 17 J8 TP7 19 J8 TP6 21 J8 TP5 23 J8 TP4 39 J8 TP3 33 J8 REFOUT 20 +5D2 C21 0.1 F Y2A Y1A 74HC541N 1 19 9 8 OTR 7 LSB 6 BIT 11 5 BIT 10 4 BIT 9 3 BIT 8 2 10 G1 Y7 G2 Y6 A7 Y5 A6 Y4 A5 U7 Y3 A4 Y2 A3 Y1 A2 Y0 A1 A0 GND +5VD 11 12 13 14 15 16 17 18 20 Y0A TPD JP21 REFOUT NOT INSTALLED REMOVE FOR DIFF. MODE TPC CLK JP16 4 Y7B Y2B Y3B Y4B Y5B Y6B Y7B +5D2 C22 0.1 F U8 3 5 U8 6 CLK 74HC04N JP15 TPE JP11 +5A J7 CLK IN C17 0.1 F C16 10 F 16V 74HC04N Y6B Y5B C33 0.1 F R12 10k JP12 JP13 Y4B R14 50 Y3B R13 10k JP14 R27 Y2B 22 +5REFBUF R10 820 JP18 JP17 R28 22 A U3 REF43 +5REFBUF C7 0.1 F A 9 U8 8 2 VIN 4 VOUT 6 JP9 +5REFBUF C12 0.1 F U4 F.S./GAIN ADJ R7 15k 3 7 C9 0.1 F C10 10 F 16V Q1 2N2222 A R29 316 C11 0.1 F A 2 J8 4 J8 6 J8 8 J8 10 J8 12 J8 GND A A 6 R9 50 EXTERNAL REFERENCE AND REFERENCE BUFFER 2 AD817 4 R11 1k 74HC04N 11 U8 10 U8 DECOUPLING +5D2 C27 0.1 F R8 10k A C8 10 F 16V A +SUPPLY C34 0.1 F A –SUPPLY A L1 14 J8 16 J8 +5A 18 J8 20 J8 +5REFBUF 22 J8 24 J8 25 J8 26 J8 27 J8 74HC04N 13 U8 L5 12 VINB TPF 74HC04N SPARE GATES R5 10k C3 0.1 F A J1 AIN A R1 50 A JP2 –SUPPLY R2 261 R3 261 +SUPPLY C2 0.1 F U1 3 7 6 JP6 U2 L6 C32 0.1 F A R6 10k J2 +VCC A J3 –VEE A A R4 33 J4 +5 DIG TPI JP4 A JP3 VINA J6 AGND A J5 DGND TPJ GJ1 TPH TPG 3 78L05P C29 22 F 25V A IN OUT 1 GND 2 A C30 22 F 25V A C31 22 F 25V L2 –SUPPLY JP7 L3 C5 0.1 F L4 C6 0.1 F +5D2 +5D C4 0.1 F A 28 J8 29 J8 30 J8 31 J8 32 J8 34 J8 NC 35 J8 36 J8 NC 37 J8 38 J8 40 J8 JP5 JP1 AD8047 2 4 C1 0.1 F TPK TPL POWER SUPPLY (GJ1-WIRE JUMPER CKT SIDE) A Figure 36. Evaluation Board Schematic R EV. E –25– AD9221/AD9223/AD9220 Figure 37. Evaluation Board Component Side Layout (Not to Scale) Figure 38. Evaluation Board Solder Side Layout (Not to Scale) –26– R EV. E AD9221/AD9223/AD9220 Figure 39. Evaluation Board Ground Plane Layout (Not to Scale) Figure 40. Evaluation Board Power Plane Layout R EV. E –27– AD9221/AD9223/AD9220 Figure 41. Evaluation Board Component Side Silkscreen (Not to Scale) Figure 42. Evaluation Board Component Side Silkscreen (Not to Scale) –28– R EV. E AD9221/AD9223/AD9220 OUTLINE DIMENSIONS 28-Lead Standard SmWall Outline Package [SOIC] Wide Body (R-28) Dimensions shown in millimeters and (inches) 18.10 (0.7126) 17.70 (0.6969) 28 15 7.60 (0.2992) 7.40 (0.2913) 1 14 10.65 (0.4193) 10.00 (0.3937) 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 8 0 1.27 (0.0500) 0.51 (0.0201) SEATING 0.32 (0.0126) PLANE BSC 0.33 (0.0130) 0.23 (0.0091) 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-013AE CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters 10.50 10.20 9.90 28 15 5.60 5.30 5.00 1 14 8.20 7.80 7.40 2.00 MAX 1.85 1.75 1.65 0.10 COPLANARITY 0.25 0.09 0.05 MIN 0.65 BSC 0.38 0.22 SEATING PLANE 8 4 0 0.95 0.75 0.55 COMPLIANT TO JEDEC STANDARDS MO-150AH R EV. E –29– AD9221/AD9223/AD9220 Revision History Location 2/03—Data Sheet changed from REV. D to REV. E. Page Updated graphic captions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Changes to DC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Changes to INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Changes to Digital Output Driver Considerations (DVDD) section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 –30– R EV. E – 31– –32– C00576–0–2/03(E) PRINTED IN U.S.A.