AD9224ARSZ

a FEATURES Monolithic 12-Bit, 40 MSPS A/D Converter Low Power Dissipation: 415 mW Single +5 V Supply No Missing Codes Guaranteed Differential Nonlinearity Error: ⴞ0.33 LSB Complete On-Chip Sample-and-Hold Amplifier and Voltage Reference Signal-to-Noise and Distortion Ratio: 68.3 dB Spurious-Free Dynamic Range: 81 dB Out-of-Range Indicator Straight Binary Output Data 28-Lead SSOP Package Compatible with 3 V Logic PRODUCT DESCRIPTION The AD9224 is a monolithic, single supply, 12-bit, 40 MSPS, analog-to-digital converter with an on-chip, high performance sample-and-hold amplifier and voltage reference. The AD9224 uses a multistage differential pipelined architecture with output error correction logic to provide 12-bit accuracy at 40 MSPS data rates, and guarantees no missing codes over the full operating temperature range. The AD9224 combines a low cost high speed CMOS process and a novel architecture to achieve the resolution and speed of existing bipolar implementations at a fraction of the power consumption and cost. The input of the AD9224 allows for easy interfacing to both imaging and communications systems. With a truly differential input structure, the user can select a variety of input ranges and offsets, including single-ended applications. The dynamic performance is excellent. The sample-and-hold (SHA) amplifier is well suited for both multiplexed systems that switch full-scale voltage levels in successive channels and sampling single-channel inputs at frequencies up to and well beyond the Nyquist rate. Complete 12-Bit, 40 MSPS Monolithic A/D Converter AD9224 FUNCTIONAL BLOCK DIAGRAM AVDD CLK DRVDD SHA VINA MDAC1 GAIN = 16 VINB CML A/D 5 MDAC2 GAIN = 4 5 CAPT 3 A/D 3 MDAC3 GAIN = 4 A/D 3 3 DIGITAL CORRECTION LOGIC 12 OUTPUT BUFFERS CAPB VREF SENSE MODE SELECT 1V AD9224 REFCOM AVSS A/D 4 OTR BIT 1 (MSB) BIT 12 (LSB) DRVSS A single clock input is used to control all internal conversion cycles. The digital output data is presented in straight binary output format. An out-of-range signal indicates an overflow condition which can be used with the most significant bit to determine low or high overflow. PRODUCT HIGHLIGHTS The AD9224 is fabricated on a very cost effective CMOS process. High speed precision analog circuits are now combined with high density logic circuits. The AD9224 offers a complete single-chip sampling 12-bit, 40 MSPS analog-to-digital conversion function in 28-lead SSOP package. Low Power—The AD9224 at 415 mW consumes a fraction of the power of presently available in existing monolithic solutions. On-Board Sample-and-Hold (SHA)—The versatile SHA input can be configured for either single-ended or differential inputs. Out of Range (OTR)—The OTR output bit indicates when the input signal is beyond the AD9224’s input range. The AD9224’s wideband input, combined with the power and cost savings over previously available monolithics, is suitable for applications in communications, imaging and medical ultrasound. Single Supply—The AD9224 uses a single +5 V power supply simplifying system power supply design. It also features a separate digital driver supply line to accommodate 3 V and 5 V logic families. The AD9224 has an onboard programmable reference. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. Pin Compatibility—The AD9224 is pin compatible with the AD9220, AD9221, AD9223 and AD9225 ADCs. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 AD9224–SPECIFICATIONS DC SPECIFICATIONS (AVDD = +5 V, DRVDD = +3 V, f SAMPLE = 40 MSPS, VREF = 2.0 V, VINB = 2.5 V dc, TMIN to TMAX unless otherwise noted) Parameter Min RESOLUTION 12 Bits MAX CONVERSION RATE 40 MHz INPUT REFERRED NOISE VREF = 1.0 V VREF = 2.0 V ACCURACY Integral Nonlinearity (INL) Differential Nonlinearity (DNL) No Missing Codes Guaranteed Zero Error (@ +25°C) Gain Error (@ +25°C)1 Gain Error (@ +25°C)2 Typ 0.35 0.17 12 ± 2.5 ± 1.0 ± 0.12 ± 0.3 ± 0.4 ± 0.3 ± 2.2 ± 1.6 ±2 ± 26 ± 0.4 POWER SUPPLY REJECTION AVDD (+5 V ± 0.25 V) ± 0.07 AVDD 1.0 ±5 2.0 ± 10 1.0 ± 1.0 REFERENCE INPUT RESISTANCE 5 POWER SUPPLIES Supply Voltages AVDD DRVDD Supply Current IAVDD IDRVDD ± 0.24 10 INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Output Voltage Tolerance (1 V Mode) Output Voltage (2.0 V Mode) Output Voltage Tolerance (2.0 V Mode) Output Current (Available for External Loads) Load Regulation3 4.75 2.85 POWER CONSUMPTION LSB LSB Bits % FSR % FSR % FSR ppm/°C ppm/°C ppm/°C 2 4 0 Units LSB rms LSB rms ± 1.5 ± 0.33 TEMPERATURE DRIFT Zero Error Gain Error1 Gain Error2 ANALOG INPUT Input Span (VREF = 1 V) (VREF = 2 V) Input (VINA or VINB) Range Input Capacitance Max ± 17 ± 35 ± 3.4 % FSR V p-p V p-p V pF V mV V mV mA mV kΩ 5 5.25 5.25 V (± 5% AVDD Operating) V (± 5% DRVDD Operating) 82 4.3 87 5 mA (2 V Internal VREF) mA (2 V Internal VREF) 415 425 445 450 mW (1 V Internal Ref) mW (2 V Internal Ref) NOTES 1 Includes internal voltage reference error. 2 Excludes internal voltage reference error. 3 Load regulation with 1 mA load current (in addition to that required by the AD9224). Specifications subject to change without notice. –2– REV. A AD9224 AC SPECIFICATIONS (AVDD = +5 V, DRVDD = +3 V, f SAMPLE = 40 MSPS, VREF = 2.0 V, TMIN to TMAX, Differential Input unless otherwise noted) Parameter SIGNAL-TO-NOISE AND DISTORTION RATIO (S/N+D) fINPUT = 2.5 MHz fINPUT = 10 MHz SIGNAL-TO-NOISE RATIO (SNR) fINPUT = 2.5 MHz fINPUT = 10 MHz Min Typ 65 63.5 68.3 68.0 dB dB 65.3 64.6 69.1 68.4 dB dB TOTAL HARMONIC DISTORTION (THD) fINPUT = 2.5 MHz fINPUT = 10 MHz Max –80 –78 SPURIOUS FREE DYNAMIC RANGE fINPUT = 2.5 MHz fINPUT = 10 MHz Full Power Bandwidth Small Signal Bandwidth Aperture Delay Aperture Jitter 71.1 67.9 –71 –67.4 81 79 120 120 1 4 Units dB dB dB dB MHz MHz ns ps rms Specifications subject to change without notice. DIGITAL SPECIFICATIONS (AVDD = +5 V, DRVDD = +5 V, unless otherwise noted) Parameters LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current (VIN = DRVDD) Low Level Input Current (VIN = 0 V) Input Capacitance LOGIC OUTPUTS (With DRVDD = 5 V) High Level Output Voltage (IOH = 50 µA) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOL = 1.6 mA) Low Level Output Voltage (IOL = 50 µA) Output Capacitance LOGIC OUTPUTS (With DRVDD = 3 V) High Level Output Voltage (IOH = 50 µA) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOL = 1.6 mA) Low Level Output Voltage (IOL = 50 µA) Symbol Min VIH VIL IIH IIL CIN +3.5 VOH VOH VOL VOL COUT +4.5 +2.4 VOH VOH VOL VOL +2.95 +2.80 Typ Max Units +1.0 +10 +10 5 V V µA µA pF 5 V V V V pF –10 –10 +0.4 +0.1 +0.4 +0.05 V V V V Specifications subject to change without notice. SWITCHING SPECIFICATIONS (T MIN to TMAX with AVDD = + 5 V, DRVDD = +5 V, CL = 20 pF) Parameters Symbol Min Clock Period1 CLOCK Pulsewidth High2 CLOCK Pulsewidth Low Output Delay Pipeline Delay (Latency) tC tCH tCL tOD 25 12.37 12.37 13 3 NOTES 1 The clock period may be extended to 1 ms without degradation in specified performance @ +25 °C. 2 For operation at 40 MHz, the clock must be held to 50% duty cycle. See section on clock shaping in text. Specifications subject to change without notice. REV. A Typ –3– Max Units ns ns ns ns Clock Cycles AD9224 ABSOLUTE MAXIMUM RATINGS* With Respect to Pin Name AVDD AVSS DRVDD DRVSS AVSS DRVSS AVDD DRVDD REFCOM AVSS CLK AVSS Digital Outputs DRVSS VINA, VINB AVSS VREF AVSS SENSE AVSS CAPB, CAPT AVSS Junction Temperature Storage Temperature Lead Temperature (10 sec) PIN CONFIGURATION 28-Lead SSOP Min Max Units –0.3 –0.3 –0.3 –6.5 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 +6.5 +6.5 +0.3 +6.5 +0.3 AVDD + 0.3 DRVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 +150 +150 +300 V V V V V V V V V V V °C °C °C –65 *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. S1 ANALOG INPUT S2 S4 tC tCH tCL S3 INPUT CLOCK tOD DATA OUTPUT DATA 1 Figure 1. Timing Diagram CLK 1 28 DRVDD (LSB) BIT 12 2 27 DRVSS BIT 11 3 26 AVDD BIT 10 4 25 AVSS BIT 9 5 24 VINB BIT 8 6 23 VINA BIT 7 7 AD9224 BIT 6 TOP VIEW 22 CML 8 (Not to Scale) 21 CAPT BIT 5 9 20 CAPB BIT 4 10 19 REFCOM (AVSS) BIT 3 11 18 VREF BIT 2 12 17 SENSE (MSB) BIT 1 13 16 AVSS OTR 14 15 AVDD PIN FUNCTION DESCRIPTIONS Pin Number 1 2 3–12 13 14 15, 26 16, 25 17 18 19 20 21 22 23 24 27 28 Name Description CLK BIT 12 BIT 11–2 BIT 1 OTR AVDD AVSS SENSE VREF REFCOM (AVSS) CAPB CAPT CML VINA VINB DRVSS DRVDD Clock Input Pin Least Significant Data Bit (LSB) Data Output Bit Most Significant Data Bit (MSB) Out of Range +5 V Analog Supply Analog Ground Reference Select Input Span Select (Reference I/O) Reference Common Noise Reduction Pin Noise Reduction Pin Common-Mode Level (Midsupply) Analog Input Pin (+) Analog Input Pin (–) Digital Output Driver Ground +3 V to +5 V Digital Output Driver Supply ORDERING GUIDE Model Temperature Range Package Description Package Option AD9224ARS AD9224-EB –40°C to +85°C 28-Lead Shrink Small Outline (SSOP) Evaluation Board RS-28 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9224 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. A AD9224 DEFINITIONS OF SPECIFICATION INTEGRAL NONLINEARITY (INL) APERTURE JITTER Aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the A/D. INL refers to the deviation of each individual code from a line drawn from “negative full scale” through “positive full scale.” The point used as “negative full scale” occurs 1/2 LSB before the first code transition. “Positive full scale” is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. APERTURE DELAY Aperture delay is a measure of the sample-and-hold amplifier (SHA) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion. SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD) RATIO DIFFERENTIAL NONLINEARITY (DNL, NO MISSING CODES) S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 12-bit resolution indicates that all 4096 codes, respectively, must be present over all operating ranges. EFFECTIVE NUMBER OF BITS (ENOB) For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula, ZERO ERROR The major carry transition should occur for an analog value 1/2 LSB below VINA = VINB. Zero error is defined as the deviation of the actual transition from that point. N = (SINAD – 1.76)/6.02 it is possible to get a measure of performance expressed as N, the effective number of bits. GAIN ERROR The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD. TOTAL HARMONIC DISTORTION (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels. TEMPERATURE DRIFT The temperature drift for zero error and gain error specifies the maximum change from the initial (+25°C) value to the value at TMIN or TMAX. SIGNAL-TO-NOISE RATIO (SNR) SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. POWER SUPPLY REJECTION The specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. SPURIOUS FREE DYNAMIC RANGE (SFDR) SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal. REV. A –5– AD9224 Typical Performance Characteristics (AVDD, DVDD = +5 V, F = 40 MHz [50% duty cycle] unless otherwise noted.) 1.00 2.00 0.75 1.50 0.50 1.00 0.25 0.50 INL – LSB DNL – LSB S 0.00 0.00 –0.25 –0.50 –0.50 –1.00 –0.75 –1.50 –1.00 0 511 1022 1533 2044 CODE Title 2555 3066 3577 –2.00 4095 0 511 Figure 2.␣ Typical DNL 1022 1533 2044 CODE 2555 3066 3577 4095 Figure 5. Typical INL 70 75 –0.5dB 70 65 –0.5dB –6.0dB 60 –6.0dB SINAD – dB SINAD – dB 65 60 55 –20.0dB 55 –20.0dB 50 50 45 45 40 0.5 5 10 15 20 25 30 35 40 45 50 INPUT FREQUENCY – MHz 55 60 65 40 0.5 70 10 20 30 40 50 INPUT FREQUENCY – MHz 60 70 Figure 6. SINAD vs. Input Frequency (Input Span = 2.0 V p-p, VCM = 2.5 V Differential Input) Figure 3. SINAD vs. Input Frequency (Input Span = 4.0 V p-p, VCM = 2.5 V Differential Input) –20 –40 –45 –30 –50 –40 –20.0dB –60 THD – dB THD – dB –55 –20.0dB –65 –70 –0.5dB –50 –60 –0.5dB –70 –75 –6.0dB –85 0.5 5 10 15 20 25 30 35 40 45 50 55 INPUT FREQUENCY – MHz –5.0dB –80 –80 60 65 –90 0.5 70 5 10 15 20 25 30 35 40 45 50 INPUT FREQUENCY – MHz 55 60 65 70 Figure 7.␣ THD vs. Input Frequency (Input Span = 2.0 V p-p, VCM = 2.5 V Differential Input) Figure 4.␣ THD vs. Input Frequency (Input Span = 4.0 V p-p, VCM = 2.5 V Differential Input) –6– REV. A AD9224 80 90 70 80 SFDR 70 50 THD – dB SNR/SFDR 60 40 SNR 60 30 50 20 40 10 0 –0.5 –20 –40 INPUT AMPLITUDE 30 10 –60 Figure 8. SNR/SFDR vs. AIN (Input Amplitude) (fIN = 20 MHz, Input Span = 4.0 V p-p, VCM = 2.5 V Differential Input) 20 30 40 SAMPLE RATE – MHz 50 60 Figure 11. THD vs. Sample Rate (AIN = –0.5 dB, VCM = 2.5 V Input Span = 4.0 V p-p, VCM = 2.5 V Differential Input) 90 90 80 THD 80 SNR 70 70 SNR 60 THD +SNR/–THD +SNR/–THD 60 50 40 40 30 30 20 20 10 10 0 0.5 5 10 15 20 INPUT FREQUENCY 25 0 0.5 30 Figure 9. +SNR/–THD vs. Input Frequency (Input Span = 4.0 V p-p, VCM = 2.5 V Single-Ended Input) HITS 2857 2093 N–1 N BIN 5 10 15 20 25 30 35 40 45 50 INPUT FREQUENCY 55 60 65 70 Figure 12. +SNR/–THD vs. Input Frequency (FS = 32 MHz, Input Span = 4.0 V p-p, VCM = 2.5 V Differential Input) 167819 N+1 Figure 10.␣ “Grounded-Input” Histogram (Input Span = 2 V p-p) REV. A 50 –7– AD9224 converter. Specifically, the input to the A/D core is the difference of the voltages applied at the VINA and VINB input pins. Therefore, the equation, INTRODUCTION The AD9224 is a high performance, complete single-supply 12bit ADC. The analog input range of the AD9224 is highly flexible allowing for both single-ended or differential inputs of varying amplitudes that can be ac or dc coupled. VCORE = VINA – VINB (1) defines the output of the differential input stage and provides the input to the A/D core. It utilizes a four-stage pipeline architecture with a wideband input sample-and-hold amplifier (SHA) implemented on a costeffective CMOS process. Each stage of the pipeline, excluding the last stage, consists of a low resolution flash A/D connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier amplifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each of the stages to facilitate digital correction of flash errors. The last stage simply consists of a flash A/D. The voltage, VCORE, must satisfy the condition, –VREF ≤ VCORE ≤ VREF (2) where VREF is the voltage at the VREF pin. While an infinite combination of VINA and VINB inputs exist that satisfy Equation 2, an additional limitation is placed on the inputs by the power supply voltages of the AD9224. The power supplies bound the valid operating range for VINA and VINB. The condition, The pipeline architecture allows a greater throughput rate at the expense of pipeline delay or latency. This means that while the converter is capable of capturing a new input sample every clock cycle, it actually takes three clock cycles for the conversion to be fully processed and appear at the output. This latency is not a concern in most applications. The digital output, together with the out-of-range indicator (OTR), is latched into an output buffer to drive the output pins. The output drivers of the AD9224 can be configured to interface with +5 V or +3.3 V logic families. AVSS – 0.3 V < VINA < AVDD + 0.3 V AVSS – 0.3 V < VINB < AVDD + 0.3 V (3) where AVSS is nominally 0 V and AVDD is nominally +5 V, defines this requirement. The range of valid inputs for VINA and VINB is any combination that satisfies both Equations 2 and 3. For additional information showing the relationship between VINA, VINB, VREF and the digital output of the AD9224, see Table IV. The AD9224 uses both edges of the clock in its internal timing circuitry (see Figure 1 and specification page for exact timing requirements). The A/D samples the analog input on the rising edge of the clock input. During the clock low time (between the falling edge and rising edge of the clock), the input SHA is in the sample mode; during the clock high time it is in hold. System disturbances just prior to the rising edge of the clock and/or excessive clock jitter may cause the input SHA to acquire the wrong value, and should be minimized. Refer to Table I and Table II at the end of this section for a summary of both the various analog input and reference configurations. ANALOG INPUT OPERATION Figure 14 shows the equivalent analog input of the AD9224 which consists of a differential sample-and-hold amplifier (SHA). The differential input structure of the SHA is highly flexible, allowing the devices to be easily configured for either a differential or single-ended input. The dc offset, or commonmode voltage, of the input(s) can be set to accommodate either single-supply or dual-supply systems. Note also, that the analog inputs, VINA and VINB, are interchangeable, with the exception that reversing the inputs to the VINA and VINB pins results in a polarity inversion. ANALOG INPUT AND REFERENCE OVERVIEW Figure 13 is a simplified model of the AD9224. It highlights the relationship between the analog inputs, VINA, VINB, and the reference voltage, VREF. Like the voltage applied to the top of the resistor ladder in a flash A/D converter, the value VREF defines the maximum input voltage to the A/D core. The minimum input voltage to the A/D core is automatically defined to be –VREF. CH QS2 AD9224 +VREF VINA VCORE VINB A/D CORE VINA CPIN+ CPAR QS1 12 VINB –VREF CS QS1 QH1 CS CPIN– CPAR QS2 CH Figure 13. Equivalent Functional Input Circuit Figure 14. Simplified Input Circuit The addition of a differential input structure gives the user an additional level of flexibility that is not possible with traditional flash converters. The input stage allows the user to easily configure the inputs for either single-ended operation or differential operation. The A/D’s input structure allows the dc offset of the input signal to be varied independently of the input span of the The AD9224 has a wide input range. The input peaks may be moved to AVDD or AVSS before performance is compromised. This allows for much greater flexibility when selecting singleended drive schemes. Op amps and ac coupling clamps can be set to available reference levels rather than be dictated by what the ADC “needs.” –8– REV. A AD9224 Due to the high degree of symmetry within the SHA topology, a significant improvement in distortion performance for differential input signals with frequencies up to and beyond Nyquist can be realized. This inherent symmetry provides excellent cancellation of both common-mode distortion and noise. Also, the required input signal voltage span is reduced by a half which further reduces the degree of RON modulation and its effects on distortion. VCC AD9224 RS VINA RS VINB VEE VREF 10mF 0.1mF SENSE REFCOM The optimum noise and dc linearity performance for either differential or single-ended inputs is achieved with the largest input signal voltage span (i.e., 4 V input span) and matched input impedance for VINA and VINB. Only a slight degradation in dc linearity performance exists between the 2 V and 4 V input spans. Figure 15. Series Resistor Isolates Switched-Capacitor SHA Input from Op Amp. Matching Resistors Improve SNR Performance The optimum size of this resistor is dependent on several factors, including the ADC sampling rate, the selected op amp, and the particular application. In most applications, a 30 Ω to 100 Ω resistor is sufficient. However, some applications may require a larger resistor value to reduce the noise bandwidth or possibly limit the fault current in an overvoltage condition. Other applications may require a larger resistor value as part of an antialiasing filter. In any case, since the THD performance is dependent on the series resistance and the above mentioned factors, optimizing this resistor value for a given application is encouraged. Referring to Figure 14, the differential SHA is implemented using a switched-capacitor topology. Its input impedance and its switching effects on the input drive source should be considered in order to maximize the converter’s performance. The combination of the pin capacitance, CPIN, parasitic capacitance CPAR, and the sampling capacitance, CS, is typically less than 5 pF. When the SHA goes into track mode, the input source must charge or discharge the voltage stored on CS to the new input voltage. This action of charging and discharging CS, averaged over a period of time and for a given sampling frequency, FS, makes the input impedance appear to have a benign resistive component. However, if this action is analyzed within a sampling period (i.e., T = 1/FS), the input impedance is dynamic and hence certain precautions on the input drive source should be observed. The source impedance driving VINA and VINB should be matched. Failure to provide that matching will result in the degradation of the AD9224’s SNR, THD and SFDR. For noise sensitive applications, the very high bandwidth of the AD9224 may be detrimental and the addition of a series resistor and/or shunt capacitor can help limit the wideband noise at the A/D’s input by forming a low-pass filter. Note, however, that the combination of this series resistance with the equivalent input capacitance of the AD9224 should be evaluated for those time domain applications that are sensitive to the input signal’s absolute settling time. In applications where harmonic distortion is not a primary concern, the series resistance may be selected in combination with the nominal 10 pF of input capacitance to set the filter’s 3 dB cutoff frequency. The resistive component to the input impedance can be computed by calculating the average charge drawn by CH from the input drive source. It can be shown that if CS is allowed to fully charge up to the input voltage before switches QS1 are opened, the average current into the input is the same as if there were a resistor of 1/(CS FS) ohms connected between the inputs. This means that the input impedance is inversely proportional to the converter’s sample rate. Since CS is only 5 pF, this resistive component is typically much larger than that of the drive source (i.e., 5 kΩ at FS = 40 MSPS). A better method of reducing the noise bandwidth, while possibly establishing a real pole for an antialiasing filter, is to add some additional shunt capacitance between the input (i.e., VINA and/or VINB) and analog ground. Since this additional shunt capacitance combines with the equivalent input capacitance of the AD9224, a lower series resistance can be selected to establish the filter’s cutoff frequency while not degrading the distortion performance of the device. The shunt capacitance also acts like a charge reservoir, sinking or sourcing the additional charge required by the hold capacitor, CH, further reducing current transients seen at the op amp’s output. The SHA’s input impedance over a sampling period appears as a dynamic input impedance to the input drive source. When the SHA goes into the track mode, the input source should ideally provide the charging current through RON of switch QS1 in an exponential manner. The requirement of exponential charging means that the most common input source, an op amp, must exhibit a source impedance that is both low and resistive up to and beyond the sampling frequency. The output impedance of an op amp can be modeled with a series inductor and resistor. When a capacitive load is switched onto the output of the op amp, the output will momentarily drop due to its effective output impedance. As the output recovers, ringing may occur. To remedy the situation, a series resistor can be inserted between the op amp and the SHA input as shown in Figure 15. The series resistance helps isolate the op amp from the switched-capacitor load. REV. A The effect of this increased capacitive load on the op amp driving the AD9224 should be evaluated. To optimize performance when noise is the primary consideration, increase the shunt capacitance as much as the transient response of the input signal will allow. Increasing the capacitance too much may adversely affect the op amp’s settling time, frequency response and distortion performance. –9– AD9224 REFERENCE OPERATION The AD9224 contains an onboard bandgap reference that provides a pin strappable option to generate either a 1 V or 2 V output. With the addition of two external resistors, the user can generate reference voltages other than 1 V and 2 V. Another alternative is to use an external reference for designs requiring enhanced accuracy and/or drift performance. See Table II for a summary of the pin-strapping options for the AD9224 reference configurations. Figure 16 shows a simplified model of the internal voltage reference of the AD9224. A pin strappable reference amplifier buffers a 1 V fixed reference. The output from the reference amplifier, A1, appears on the VREF pin. The voltage on the VREF pin determines the full-scale input span of the A/D. This input span equals, The actual reference voltages used by the internal circuitry of the AD9224 appear on the CAPT and CAPB pins. For proper operation when using the internal or an external reference, it is necessary to add a capacitor network to decouple these pins. Figure 17 shows the recommended decoupling network. This capacitive network performs the following three functions: (1) along with the reference amplifier, A2, it provides a low source impedance over a large frequency range to drive the A/D internal circuitry, (2) it provides the necessary compensation for A2, and (3) it bandlimits the noise contribution from the reference. The turn-on time of the reference voltage appearing between CAPT and CAPB is approximately 15 ms and should be evaluated in any power-down mode of operation. 0.1mF CAPT Full-Scale Input Span = 2 × VREF AD9224 The voltage appearing at the VREF pin as well as the state of the internal reference amplifier, A1, are determined by the voltage appearing at the SENSE pin. The logic circuitry contains two comparators which monitor the voltage at the SENSE pin. The comparator with the lowest set point (approximately 0.3 V) controls the position of the switch within the feedback path of A1. If the SENSE pin is tied to AVSS (AGND), the switch is connected to the internal resistor network thus providing a VREF of 2.0 V. If the SENSE pin is tied to the VREF pin via a short or resistor, the switch will connect to the SENSE pin. This short will provide a VREF of 1.0 V. An external resistor network will provide an alternative VREF between 1.0 V and 2.0 V. The other comparator controls internal circuitry that will disable the reference amplifier if the SENSE pin is tied AVDD. Disabling the reference amplifier allows the VREF pin to be driven by an external voltage reference. AD9224 0.1mF 10mF CAPB 0.1mF Figure 17. Recommended CAPT/CAPB Decoupling Network The A/D’s input span may be varied dynamically by changing the differential reference voltage appearing across CAPT and CAPB symmetrically around 2.5 V (i.e., midsupply). To change the reference at speeds beyond the capabilities of A2, it will be necessary to drive CAPT and CAPB with two high speed, low noise amplifiers. In this case, both internal amplifiers (i.e., A1 and A2) must be disabled by connecting SENSE to AVDD, connecting VREF to AVSS and removing the capacitive decoupling network. The external voltages applied to CAPT and CAPB must be 2.0 V + Input Span/4 and 2.0 V – Input Span/4 respectively in which the input span can be varied between 2 V and 4 V. Note that those samples within the pipeline A/D during any reference transition will be corrupted and should be discarded. TO A/D 5kV CAPT 5kV A2 5kV CAPB 5kV DISABLE A2 LOGIC VREF 1V A1 6.25kV SENSE DISABLE A1 LOGIC 6.25kV REFCOM Figure 16. Equivalent Reference Circuit –10– REV. A AD9224 Table I. Analog Input Configuration Summary Input Connection Coupling Input Span (V) ␣ ␣ ␣ ␣ ␣ ␣ Input Range (V) VINA1 VINB1 Figure # Comments Single-Ended DC 2 0 to 2 1 19, 20 Best for stepped input response applications, requires ± 5 V op amp. 2 × VREF 0 to 2 × VREF VREF 19, 20 Same as above but with improved noise performance due to increase in dynamic range. Headroom/settling time requirements of ± 5 op amp should be evaluated. 4 0 to 4 2.0 19, 20 Optimum noise performance, excellent SNR performance, often requires low distortion op amp with VCC > +5 V due to its headroom issues. 2 × VREF 2.0 – VREF ␣ ␣ ␣ ␣ to 2.0 + VREF 2.0 30 Optimum THD performance with VREF = 1. Single supply operation (i.e., +5 V) for many op amps. 2 or 2 × VREF 0 to 1 or 0 to 2 × VREF 1 or VREF 21, 22 4 0.5 to 4.5 2.5 22 Optimum noise performance, excellent THD performance, ability to use ± 5 V op amp. 2 × VREF 2.0 – VREF ␣ ␣ ␣ ␣ to 2.0 + VREF 2.0 21 Flexible input range, Optimum THD performance with VREF = 1. Ability to use either +5 V or ± 5 V op amp. 2 2 to 3 3 to 2 23, 24 Optimum full-scale THD and SFDR performance well beyond the A/Ds Nyquist frequency. Preferred mode for undersampling applications. 2 × VREF 2.0 – VREF/2 ␣ ␣ ␣ ␣ to 2.0 + VREF/2 2.0 + VREF/2 ␣ ␣ ␣ ␣ to 2.0 – VREF/2 23, 24 Same as above with the exception that full-scale THD and SFDR performance can be traded off for better noise performance. 4.0 1.5 to 3.5 3.5 to 1.5 23, 24 Optimum noise performance. Single-Ended AC Differential AC/DC (via Transformer) or Amplifier NOTE 1VINA and VINB can be interchanged if signal inversion is required. Table II. Reference Configuration Summary Reference Operating Mode Input Span (VINA–VINB) (V p-p) Required VREF (V) Connect To INTERNAL INTERNAL INTERNAL 2 4 2 ≤ SPAN ≤ 4 AND SPAN = 2 × VREF 1 2 1 ≤ VREF ≤ 2.0 AND VREF = (1 + R1/R2) SENSE SENSE R1 R2 VREF REFCOM VREF AND SENSE SENSE AND REFCOM EXTERNAL (NONDYNAMIC) 2 ≤ SPAN ≤ 4 1 ≤ VREF ≤ 2.0 SENSE VREF AVDD EXT. REF. EXTERNAL (DYNAMIC) 2 ≤ SPAN ≤ 4 CAPT and CAPB Externally Driven SENSE VREF EXT. REF. EXT. REF. AVDD AVSS CAPT CAPB REV. A –11– AD9224 DRIVING THE ANALOG INPUTS The AD9224 has a highly flexible input structure allowing it to interface with single-ended or differential input interface circuitry. The applications shown in Driving the Analog Inputs and Reference Configurations sections, along with the information presented in Input and Reference Overview of this data sheet, give examples of both single-ended and differential operation. Refer to Tables I and II for a list of the different possible input and reference configurations and their associated figures in the data sheet. The optimum mode of operation, analog input range, and associated interface circuitry will be determined by the particular applications performance requirements as well as power supply options. For example, a dc-coupled single-ended input would be appropriate for most data acquisition and imaging applications. Also, many communication applications that require a dc coupled input for proper demodulation can take advantage of the single-ended distortion performance of the AD9224. The input span should be configured so the system’s performance objectives and the headroom requirements of the driving op amp are simultaneously met. Differential modes of operation (ac or dc coupled input) provide the best THD and SFDR performance over a wide frequency range. Differential operation should be considered for the most demanding spectral based applications (e.g., direct IF-to-digital conversion). See Figures 23, 24 and section on Differential Mode of Operation. Differential input characterization was performed for this data sheet using the configuration shown in Figure 24. Single-ended operation requires that VINA be ac or dc coupled to the input signal source, while VINB of the AD9224 be biased to the appropriate voltage corresponding to a midscale code transition. Note that signal inversion may be easily accomplished by transposing VINA and VINB. Most of the single-ended specifications for the AD9224 were characterized using Figure 21 circuitry with input spans of 4 V and 2 V as well as VCM = 2.5 V. Differential operation requires that VINA and VINB be simultaneously driven with two equal signals that are in and out of phase versions of the input signal. Differential operation of the AD9224 offers the following benefits: (1) Signal swings are smaller and therefore linearity requirements placed on the input signal source may be easier to achieve, (2) Signal swings are smaller and therefore may allow the use of op amps which may otherwise have been constrained by headroom limitations, (3) Differential operation minimizes even-order harmonic products, and (4) Differential operation offers noise immunity based on the device’s common-mode rejection. As is typical of most IC devices, exceeding the supply limits will turn on internal parasitic diodes resulting in transient currents within the device. Figure 18 shows a simple means of clamping an ac or dc coupled single-ended input with the addition of two series resistors and two diodes. An optional capacitor is shown for ac coupled applications. Note that a larger series resistor could be used to limit the fault current through D1 and D2 but should be evaluated since it can cause a degradation in overall performance. A similar clamping circuit could also be used for each input if a differential input signal is being applied. The diodes might cause nonlinearity in the signal. Careful evaluation should be performed on the diodes used. VCC OPTIONAL AC COUPLING CAPACITOR AVDD RS1 30V D2 RS2 20V AD9224 D1 VEE Figure 18. Simple Clamping Circuit SINGLE-ENDED MODE OF OPERATION The AD9224 can be configured for single-ended operation using dc or ac coupling. In either case, the input of the A/D must be driven from an operational amplifier that will not degrade the A/D’s performance. Because the A/D operates from a single supply, it will be necessary to level shift ground-based bipolar signals to comply with its input requirements. Both dc and ac coupling provide this necessary function, but each method results in different interface issues which may influence the system design and performance. Single-ended operation is often limited by the availability driving op amps. Very low distortion op amps that provide great performance out to the Nyquist frequency of the converter are hard to find. Compounding the problem, for dc coupled singleended applications, is the inability of the many high performance amplifiers to maintain low distortions as their outputs approach their positive output voltage limit (i.e., 1 dB compression point). For this reason, it is recommended that applications requiring high performance dc coupling use the single-ended-todifferential circuit shown in Figure 23. DC COUPLING AND INTERFACE ISSUES Many applications require the analog input signal to be dc coupled to the AD9224. An operational amplifier can be configured to rescale and level shift the input signal so that it is compatible with the selected input range of the A/D. The input range to the A/D should be selected on the basis of system performance objectives as well as the analog power supply availability since this will place certain constraints on the op amp selection. Many of the new high performance op amps are specified for only ± 5 V operation and have limited input/output swing capabilities. The selected input range of the AD9224 should be considered with the headroom requirements of the particular op amp to prevent clipping of the signal. Also, since the output of a dual supply amplifier can swing below absolute minimum (–0.3 V), clamping its output should be considered in some applications. In some applications, it may be advantageous to use an op amp specified for single supply +5 V operation since it will inherently limit its output swing to within the power supply rails. Amplifiers like the AD8041 and AD8011 are useful for this purpose but their low bandwidths will limit the AD9224’s performance. High performance amplifiers (± 5 V) such as the AD9631, AD9632, AD8056 or AD8055 allow the AD9224 to be configured for larger input spans which will improve the ADC’s noise performance. Op amp circuits using a noninverting and inverting topologies are discussed in the next section. Although not shown, the noninverting and inverting topologies can be easily configured as part of an antialiasing filter by using a Sallen-Key or MultipleFeedback topology. An additional R-C network can be inserted between the op amp’s output and the AD9224 input to provide a filter pole. –12– REV. A AD9224 Simple Op Amp Buffer AC COUPLING AND INTERFACE ISSUES In the simplest case, the input signal to the AD9224 will already be biased at levels in accordance with the selected input range. It is simply necessary to provide an adequately low source impedance for the VINA and VINB analog pins of the A/D. Figure 19 shows the recommended configuration a single-ended drive using an op amp. In this case, the op amp is shown in a noninverting unity gain configuration driving the VINA pin. The internal reference drives the VINB pin. Note that the addition of a small series resistor of 30 Ω to 100 Ω connected to VINA and VINB will be beneficial in nearly all cases. Refer to the Analog Input Operation section for a discussion on resistor selection. Figure 19 shows the proper connection for a 0 V to 4 V input range. Alternative single ended ranges of 0 V to 2 × VREF can also be realized with the proper configuration of VREF (refer to the Using the Internal Reference section). Headroom limitations of the op amp must always be considered. For applications where ac coupling is appropriate, the op amp’s output can be easily level-shifted via a coupling capacitor. This has the advantage of allowing the op amp’s common-mode level to be symmetrically biased to its midsupply level (i.e. (VCC + VEE)/2). Op amps that operate symmetrically with respect to their power supplies typically provide the best ac performance as well as greatest input/output span. Various high speed/performance amplifiers that are restricted to +5 V/–5 V operation and/ or specified for +5 V single-supply operation can be easily configured for the 4 V or 2 V input span of the AD9224. A differential input connection should be considered for optimum ac performance. +V 4V AD9224 RS 0V U1 VINA RS VINB –V 2.0V VREF 10mF Simple AC Interface Figure 21 shows a typical example of an ac-coupled, singleended configuration. The bias voltage shifts the bipolar, groundreferenced input signal to approximately AVDD/2. The value for C1 and C2 will depend on the size of the resistor, R. The capacitors, C1 and C2, are a 0.1 µF ceramic and 10 µF tantalum capacitor in parallel to achieve a low cutoff frequency while maintaining a low impedance over a wide frequency range. The combination of the capacitor and the resistor form a high-pass filter with a high-pass –3 dB frequency determined by the equation, f–3 dB = 1/(2 × π × R × (C1 + C2)) 0.1mF SENSE The low impedance VREF voltage source both biases the VINB input and provides the bias voltage for the VINA input. Figure 21 shows the VREF configured for 2.0 V thus the input range of the A/D is 0 V to 4 V. Other input ranges could be selected by changing VREF. Figure 19. Single-Ended AD9224 Op Amp Drive Circuit Op Amp with DC Level-Shifting Figure 20 shows a dc-coupled level-shifting circuit employing an op amp, A1, to sum the input signal with the desired dc set. Configuring the op amp in the inverting mode with the given resistor values results in an ac signal gain of –1. If the signal inversion is undesirable, interchange the VINA and VINB connections to reestablish the original signal polarity. The dc voltage at VREF sets the common-mode voltage of the AD9224. For example, when VREF = 1.0 V, the input level from the op amp will also be centered around 1.0 V. The use of ratio matched, thin-film resistor networks will minimize gain and offset errors. Also, an optional pull-up resistor, RP, may be used to reduce the output load on VREF to less than 1 mA maximum. C1 10mF +2V 0V –2V 0.1mF –VREF 7 1 500V* 3 +V 0.1mF 500V* RS 6 A1 RP** VINA 5 4 AD9224 NC RS VREF VINB NC = NO CONNECT *OPTIONAL RESISTOR NETWORK-OHMTEK ORNA500D **OPTIONAL PULL-UP RESISTOR WHEN USING INTERNAL REFERENCE Figure 20. Single-Ended Input with DC-Coupled Level Shift REV. A R RS AD9224 VINA 10mF R R Figure 21. AC-Coupled Input NC 2 R RS 0.1mF 500V* VIN +V –5V 500V* 0VDC +V 4.5 2.5 0.5 C2 0.1mF +VCC +VREF AD9631 +5V –13– VINB SENSE AD9224 Alternative AC Interface Figure 22 shows a flexible ac-coupled circuit that can be configured for different input spans. Since the common-mode voltage of VINA and VINB are biased to midsupply (VCM) independent of VREF, VREF can be pin strapped or reconfigured to achieve input spans between 2 V and 4 V p-p. The AD9224’s CMRR, along with the symmetrical coupling R-C networks, will reject both power supply variations and noise. VCM establishes the common-mode voltage. VCM’s source impedance is 5 kΩ. The capacitors, C1 and C2, are typically a 0.1 µF ceramic and 10 µF tantalum capacitor in parallel to achieve a low cutoff frequency while maintaining a low impedance over a wide frequency range. RS isolates the buffer amplifier from the A/D input. The optimum performance is preserved because VINA and VINB are driven via symmetrical R-C networks. The f–3 dB point can be approximated by the equation, f –3 dB = 1 2 π × 6K +(C1+ C2) C1 10mF AD9224 RS VINA C1 10mF C2 0.1mF AD9631: f–3 dB = 250 MHz. Moderate cost. Good for single-ended drive applications when signal is anywhere between 0 V and 3 V. Limits: THD is compromised above 8 MHz. Since not all applications have a signal preconditioned for differential operation, there is often a need to perform a single-endedto-differential conversion. In systems that do not need to be dc coupled, an RF transformer with a center tap is the best method to generate differential inputs for the AD9224. It provides all the benefits of operating the A/D in the differential mode without contributing additional noise or distortion. An RF transformer also has the added benefit of providing electrical isolation between the signal source and the A/D. 1kV C3 0.1mF AD8056: Dual Version of above amp. Perfect for single-ended to differential configuration (see Figure 23). Harmonics cancel each other in differential drive, making this amplifier highly recommended for a single-ended input signal source. Handles input signals past the 20 MHz Nyquist frequency. DIFFERENTIAL MODE OF OPERATION C2 0.1mF VIN AD8055: f–3 dB = 300 MHz. Low cost. Best used for driving single-ended ac coupled configuration. Limit: THD is compromised when output is not swinging about 0 V. VCM 1kV VINB An improvement in THD and SFDR performance can be realized by operating the AD9224 in the differential mode. The performance enhancement between the differential and singleended mode is most noteworthy as the input frequency approaches and goes beyond the Nyquist frequency (i.e., fIN > FS /2). RS Figure 22. AC-Coupled Input-Flexible Input Span, VCM = 2.5 V OP AMP SELECTION GUIDE Op amp selection for the AD9224 is highly dependent on a particular application. In general, the performance requirements of any given application can be characterized by either time domain or frequency domain parameters. In either case, one should carefully select an op amp that preserves the performance of the A/D. This task becomes challenging when one considers the AD9224’s high performance capabilities coupled with other extraneous system level requirements such as power consumption and cost. The ability to select the optimal op amp may be further complicated by either limited power supply availability and/or limited acceptable supplies for a desired op amp. Newer, high performance op amps typically have input and output range limitations in accordance with their lower supply voltages. As a result, some op amps will be more appropriate in systems where accoupling is allowable. When dc-coupling is required, op amps without headroom constraints such as rail-to-rail op amps or ones where larger supplies can be used should be considered. The following section describes some op amps currently available from Analog Devices. The system designer is always encouraged to contact the factory or local sales office to be updated on Analog Devices latest amplifier product offerings. Highlights of the areas where the op amps excel and where they may limit the performance of the AD9224 is also included. The circuit shown in Figure 23 is an ideal method of applying a differential dc drive to the AD9224. We have used this configuration to drive the AD9224 from 2 V to 4 V spans at frequencies approaching Nyquist, with performance numbers matching those shown on the Specification pages of this data sheet (gathered through a transformer). The dc input is shifted to a dc point swinging symmetrically about the reference voltage. The optional resistor will provide additional current if more reference drive is required. 500V 500V 50V VREF VINA 500V 0V 500V AD9224 500V 500V +V 50V VINB 500V CML R* 500V *OPTIONAL 10mF 0.1mF Figure 23. Direct Coupled Drive Circuit with AD8056 Dual Op Amps When single-ended, dc coupling is needed. The use of the AD8056 in a differential configuration (Figure 23) is highly recommended. –14– REV. A AD9224 The noise performance of each unity gain differential driver circuit is limited by its inherent noise gain of two. For unity gain op amps ONLY, the noise gain can be reduced from two to one beyond the input signal’s passband by adding a shunt capacitor, CF, across each op amp’s feedback resistor. This will essentially establish a low-pass filter, which reduces the noise gain to one beyond the filter’s f–3 dB while simultaneously bandlimiting the input signal to f–3 dB. Note, the pole established by this filter can also be used as the real pole of an antialiasing filter. Figure 24 shows the schematic of the suggested transformer circuit. The circuit uses a Minicircuits RF transformer, model T4-1T, which has an impedance ratio of four (turns ratio of 2). The schematic assumes that the signal source has a 50 Ω source impedance. The 1:4 impedance ratio requires the 200 Ω secondary termination for optimum power transfer and VSWR. The center tap of the transformer provides a convenient means of level shifting the input signal to a desired commonmode voltage. RS 33V fIN = 10MHz 82 80 fIN = 20MHz 78 76 74 72 0.5 2 2.5 3 COMMON-MODE VOLTAGE – V 1 4.5 4 Figure 25a. THD vs. Common-Mode Voltage (AIN = 2 V Differential) 10 FUND 0 –10 –20 –30 –40 –50 –60 –70 49.9V 200V 84 THD – dB To protect the AD9224 from an undervoltage fault condition from op amps specified for ±5 V operation, two diodes to AGND can be inserted between each op amp output and the AD9224 inputs. The AD9224 will inherently be protected against any overvoltage condition if the op amps share the same positive power supply (i.e., AVDD) as the AD9224. Note, the gain accuracy and common-mode rejection of each difference amplifier in this driver circuit can be enhanced by using a matched thinfilm resistor network (i.e., Ohmtek ORNA5000F) for the op amps. The AD9224’s small signal bandwidth is 120 MHz, hence any noise falling within the baseband bandwidth of the AD9224 will degrade its overall noise performance. Transformers with other turns ratios may also be selected to optimize the performance of a given application. For example, a given input signal source or amplifier may realize an improvement in distortion performance at reduced output power levels and signal swings. For example, selecting a transformer with a higher impedance ratio (e.g., Minicircuits T16-6T with a 1:16 impedance ratio) effectively “steps up” the signal level thus further reducing the driving requirements of signal source. Referring to Figure 24, a series resistor, RS, was inserted between the AD9224 and the secondary of the transformer. The value of 33 Ω was selected to specifically optimize both the THD and SNR performance of the A/D. RS and the internal capacitance help provide a low-pass filter to block high frequency noise. The AD9224 can be easily configured for either a 2 V p-p input span or 4.0 V p-p input span by setting the internal reference (see Table II). Other input spans can be realized with two external gain setting resistors as shown in Figure 28 of this data sheet. Figure 25a demonstrates the AD9224’s high degree of linearity and THD over a wide range of common-mode voltages. THD – dB The driver circuit shown in Figure 23 is optimized for dc coupling applications requiring optimum distortion performance. This differential op amp driver circuit is configured to convert and level shift a 2 V p-p single-ended, ground referenced signal to a 4 V p-p differential signal centered at the VREF level of the ADC. The circuit is based on two op amps that are configured as matched unity gain difference amplifiers. The single-ended input signal is applied to opposing inputs of the difference amplifiers, thus providing differential drive. The common-mode offset voltage is applied to the noninverting resistor leg of each difference amplifier providing the required offset voltage. The common-mode offset can be varied over a wide span without any serious degradation in distortion performance as shown in Figure 25a, thus providing some flexibility in improving output compression distortion from some ± 5 V op amps with limited positive voltage swing. 0.1mF VINA –80 CML –90 2ND 3RD 5TH 7TH 6TH 8TH 9TH –100 AD9224 –110 VINB MINICIRCUITS T4-1T –120 0 RS 33V 17.25 26.5 35.7 45E6 54.25 63.5 72.75 COMMON-MODE VOLTAGE – V 82 Figure 25b. Frequency Domain Plot FIN = 5 MHz, FS = 40 MHz (AIN = 2 V Differential) Figure 24. Transformer Coupled Input This (Figure 24) configuration was used to gather all of the differential data on the Specifications pages. REV. A 8 –15– AD9224 REFERENCE CONFIGURATIONS Figure 26b illustrates the relation between reference voltage and THD. Note that optimal performance occurs when the reference voltage is set to 1.5 V (input span = 3 V). The figures associated with this section on internal and external reference operation do not show recommended matching series resistors for VINA and VINB for the purpose of simplicity. Please refer to the Driving the Analog Inputs section for a discussion of this topic. Also, the figures do not show the decoupling network associated with the CAPT and CAPB pins. Please refer to the Reference Operation section for a discussion of the internal reference circuitry and the recommended decoupling network shown in Figure 17. –60 –65 THD – dB –70 USING THE INTERNAL REFERENCE Single-Ended Input with 0 to 2 ⴛ VREF Range –75 Figure 26a shows how to connect the AD9224 for a 0 V to 2 V or 0 V to 4 V input range via pin strapping the SENSE pin. An intermediate input range of 0 to 2 × VREF can be established using the resistor programmable configuration in Figure 28. –80 In either case, both the midscale voltage and input span are directly dependent on the value of VREF. More specifically, the midscale voltage is equal to VREF while the input span is equal to 2 × VREF. Thus, the valid input range extends from 0 to 2 × VREF. When VINA is ≤ 0 V, the digital output will be 000 Hex; when VINA is ≥ 2 × VREF, the digital output will be FFF Hex. –90 1.0 –85 Shorting the VREF pin directly to the SENSE pin places the internal reference amplifier in unity-gain mode and the resultant VREF output is 1 V. Therefore, the valid input range is 0 V to 2 V. However, shorting the SENSE pin directly to the REFCOM pin configures the internal reference amplifier for a gain of 2.0 and the resultant VREF output is 2.0 V. Thus, the valid input range becomes 0 V to 4 V. The VREF pin should be bypassed to the REFCOM pin with a 10 µF tantalum capacitor in parallel with a low-inductance 0.1 µF ceramic capacitor. 2 3 VREF VINA 0V VINB 10mF 0.1mF VREF SHORT FOR 0V TO 2V INPUT SPAN AD9224 SENSE SHORT FOR 0V TO 4V INPUT SPAN 1.2 1.4 1.6 1.8 REFERENCE VOLTAGE – V 2.0 2.2 Figure 26b. THD vs. Reference Voltage, FS = 40 MHz, FIN = 10 MHz (Differential) Figure 27 shows the single-ended configuration that gives good dynamic performance (SINAD, SFDR). To optimize dynamic specifications, center the common-mode voltage of the analog input at approximately by 2.5 V by connecting VINB to a low impedance 2.5 V source. As described above, shorting the VREF pin directly to the SENSE pin results in a 1 V reference voltage and a 2 V p-p input span. The valid range for input signals is 1.5 V to 3.5 V. The VREF pin should be bypassed to the REFCOM pin with a 10 µF tantalum capacitor in parallel with a low-inductance 0.1 µF ceramic capacitor. This reference configuration could also be used for a differential input in which VINA and VINB are driven via a transformer as shown in Figure 24. In this case, the common-mode voltage, VCM, is set at midsupply by connecting the transformer’s center tap to CML of the AD9224. VREF can be configured for 1.0 V or 2.0 V by connecting SENSE to either VREF or REFCOM respectively. Note that the valid input range for each of the differential inputs is one half of the single-ended input and thus becomes VCM – VREF/2 to VCM + VREF/2. REFCOM 3.5V VINA VCM VINB 1.5V Figure 26a. Internal Reference—2 V p-p Input Span, VCM = 1 V, or 4 V p-p Input Span 1V 10mF 0.1mF AD9224 VREF SENSE REFCOM Figure 27. Internal Reference—2 V p-p Input Span, VCM = 2.5 V –16– REV. A AD9224 Resistor Programmable Reference Figure 28 shows an example of how to generate a reference voltage other than 1.0 V or 2.0 V with the addition of two external resistors and a bypass capacitor. Use the equation, VREF = 1 V × (1 + R1/R2), to determine appropriate values for R1 and R2. These resistors should be in the 2 kΩ to 100 kΩ range. For the example shown, R1 equals 2.5 kΩ and R2 equals 5 kΩ. From the equation above, the resultant reference voltage on the VREF pin is 1.5 V. This sets the input span to be 3 V p-p. To assure stability, place a 0.1 µF ceramic capacitor in parallel with R1. The AD9224 contains an internal reference buffer, A2 (see Figure 16), that simplifies the drive requirements of an external reference. The external reference must be able to drive about 5 kΩ (± 20%) load. Note that the bandwidth of the reference buffer is deliberately left small to minimize the reference noise contribution. As a result, it is not possible to change the reference voltage rapidly in this mode. 2.5V+VREF 2.5V 2.5V–VREF VINA AD9224 2.5V REF +5V 0.1mF VINB 22mF 0.1mF R1 4V VINA 1V A1 AD9224 2.5V VINB 1.5V 10mF 0.1mF 0.1mF R1 2.5kV VREF R2 +5V VREF C1 0.1mF SENSE Figure 29. External Reference SENSE R2 5kV Variable Input Span with V CM = 2.5 V Figure 29 shows an example of the AD9224 configured for an input span of 2 × VREF centered at 2.5 V. An external 2.5 V reference drives the VINB pin thus setting the common-mode voltage at 2.5 V. The input span can be independently set by a voltage divider consisting of R1 and R2 which generates the VREF signal. A1 buffers this resistor network and drives VREF. Choose this op amp based on accuracy requirements. It is essential that a minimum of a 10 µF capacitor in parallel with a 0.1 µF low inductance ceramic capacitor decouple the A1’s output to ground. REFCOM Figure 28. Resistor Programmable Reference—3 V p-p Input Span, VCM = 2.5 V The midscale voltage can be set to VREF by connecting VINB to VREF to provide an input span of 0 to 2 × VREF. Alternatively, the midscale voltage can be set to 2.5 V by connecting VINB to a low impedance 2.5 V source. For the example shown, the valid input single-ended range for VINA is 1 V to 4 V since VINB is set to an external, low impedance 2.5 V source. The VREF pin should be bypassed to the REFCOM pin with a 10 µF tantalum capacitor in parallel with a low inductance 0.1 µF ceramic capacitor. Single-Ended Input with 0 to 2 ⴛ VREF Range USING AN EXTERNAL REFERENCE Using an external reference may enhance the dc performance of the AD9224 by improving drift and accuracy. Figures 29 and 30 show examples of how to use an external reference with the A/D. Table III is a list of suitable voltage references from Analog Devices. To use an external reference, the user must disable the internal reference amplifier and drive the VREF pin. Connecting the SENSE pin to AVDD disables the internal reference amplifier. Figure 30 shows an example of an external reference driving both VINB and VREF. In this case, both the common-mode voltage and input span are directly dependent on the value of VREF. More specifically, the common-mode voltage is equal to VREF while the input span is equal to 2 × VREF. Thus, the valid input range extends from 0 to 2 × VREF. For example, if the REF191, a 2.048 V external reference was selected, the valid input range extends from 0 to 4.096 V. In this case, 1 LSB of the AD9224 corresponds to 1 mV. It is essential that a minimum of a 10 µF capacitor in parallel with a 0.1 µF low inductance ceramic capacitor decouple the reference output to ground. 2 3 REF VINA 0V Table III. Suitable Voltage References Internal AD589 AD1580 REF191 Internal REV. A Output Voltage Drift (ppm/ⴗC) Initial Accuracy % (max) 1.00 1.235 1.225 2.048 2.0 26 10–100 50–100 5–25 26 1.4 1.2–2.8 0.08–0.8 0.1–0.5 1.4 +5V Operating Current 1 mA 50 µA 50 µA 45 µA 1 mA VINB VREF 0.1mF 10mF 0.1mF AD9224 VREF 0.1mF +5V SENSE Figure 30. Input Range = 0 V to 2 × VREF –17– AD9224 DIGITAL INPUTS AND OUTPUTS Digital Outputs Digital Output Driver Considerations (DRVDD) The AD9224 output drivers can be configured to interface with +5 V or 3.3 V logic families by setting DRVDD to +5 V or 3.3 V respectively. The output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause glitches on the supplies and may affect SINAD performance. Applications requiring the ADC to drive large capacitive loads or large fanout may require additional decoupling capacitors on DRVDD. In extreme cases, external buffers or latches may be required. The AD9224 output data is presented in positive true straight binary for all input ranges. Table IV indicates the output data formats for various input ranges regardless of the selected input range. A twos complement output data format can be created by inverting the MSB. Table IV. Output Data Format Input (V) Condition (V) Digital Output OTR VINA–VINB VINA–VINB VINA–VINB VINA–VINB VINA–VINB < – VREF = – VREF =0 = + VREF – 1 LSB ≥ + VREF 0000 0000 0000 0000 0000 0000 1000 0000 0000 1111 1111 1111 1111 1111 1111 1 0 0 0 1 1111 1111 1111 0 1111 1111 1111 0 1111 1111 1110 The AD9224 internal timing uses the two edges of the clock input to generate a variety of internal timing signals. The clock input must meet or exceed the minimum specified pulse width high and low (tCH and tCL) specifications for the given A/D as defined in the Switching Specifications at the beginning of the data sheet to meet the rated performance specifications. For example, the clock input to the AD9224 operating at 40 MSPS may have a duty cycle between 49% to 51% to meet this timing requirement since the minimum specified tCH and tCL is 12.37 ns. For low clock rates below 40 MSPS, the duty cycle may deviate from this range to the extent that both tCH and tCL are satisfied. +FS –1 1/2 LSB OTR DATA OUTPUTS 1 Clock Input and Considerations OTR –FS+1/2 LSB 0 0 1 0000 0000 0001 0000 0000 0000 0000 0000 0000 –FS –FS –1/2 LSB High speed high resolution A/Ds are sensitive to the quality of the clock input. The degradation in SNR at a given full-scale input frequency (fIN) due only to aperture jitter (tA) can be calculated with the following equation: +FS +FS –1/2 LSB Figure 31. Output Data Format SNR = 20 log10 [1/2 π fIN tA] Out of Range (OTR) An out-of-range condition exists when the analog input voltage is beyond the input range of the converter. OTR is a digital output that is updated along with the data output corresponding to the particular sampled analog input voltage. Hence, OTR has the same pipeline delay (latency) as the digital data. It is LOW when the analog input voltage is within the analog input range. It is HIGH when the analog input voltage exceeds the input range as shown in Figure 31. OTR will remain HIGH until the analog input returns within the input range and another conversion is completed. By logical ANDing OTR with the MSB and its complement, overrange high or underrange low conditions can be detected. Table V is a truth table for the over/ underrange circuit in Figure 32 which uses NAND gates. Systems requiring programmable gain conditioning of the AD9224 input signal can immediately detect an out-of-range condition, thus eliminating gain selection iterations. Also, OTR can be used for digital offset and gain calibration. Table V. Out-of-Range Truth Table OTR MSB Analog Input Is 0 0 1 1 0 1 0 1 In Range In Range Underrange Overrange In the equation, the rms aperture jitter, tA, represents the rootsum square of all the jitter sources, which include the clock input, analog input signal, and A/D aperture jitter specification. Undersampling applications are particularly sensitive to jitter. Clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9224. Power supplies for clock drivers should be separated from the A/D output driver supplies to avoid modulating the clock signal with digital noise. Low jitter crystal controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing or other method), it should be retimed by the original clock at the last step. The clock input is referred to the analog supply. Its logic threshold is AVDD/2. If the clock is being generated by 3 V logic, it will have to be level shifted into 5 V CMOS logic levels. This can also be accomplished by ac-coupling and level-shifting the clock signal. The AD9224 has a very tight clock tolerance at 40 MHz. One way to minimize the tolerance of a 50% duty cycle clock is to divide down a clock of higher frequency, as shown in Figure 33. +5V R Q D MSB OVER = “1” 80MHz OTR MSB Q 40MHz S UNDER = “1” +5V Figure 32. Overrange or Underrange Logic Figure 33. Divide-by-Two Clock Circuit –18– REV. A AD9224 In this case an 80 MHz clock is divided by two to produce the 40 MHz clock input for the AD9224. In this configuration, the duty cycle of the 80 MHz clock is irrelevant. The input circuitry for the CLOCK pin is designed to accommodate CMOS inputs. The quality of the logic input, particularly the rising edge, is critical in realizing the best possible jitter performance of the part: the faster the rising edge, the better the jitter performance. As a result, careful selection of the logic family for the clock driver, as well as the fanout and capacitive load on the clock line, is important. Jitter-induced errors become more predominant at higher frequency, large amplitude inputs, where the input slew rate is greatest. Most of the power dissipated by the AD9224 is from the analog power supplies. However, lower clock speeds will reduce digital current. Figure 34 shows the relationship between power and clock rate. 460 440 POWER – mV 420 2V INTERNAL REFERENCE 400 380 1V INTERNAL REFERENCE The AD9224 is well suited for various IF sampling applications. The AD9224’s low distortion input SHA has a full-power bandwidth extending beyond 120 MHz, thus encompassing many popular IF frequencies. A DNL of ± 0.7 LSB (typ) combined with low thermal input referred noise allows the AD9224 in the 2 V span to provide 69 dB of SNR for a baseband input sine wave. Also, its low aperture jitter of 4 ps rms ensures minimum SNR degradation at higher IF frequencies. In fact, the AD9224 is capable of still maintaining 64.5 dB of SNR at an IF of 71 MHz with a 2 V input span. Note, although the AD9224 can yield a 1 dB to 2 dB improvement in SNR when configured for the larger 4 V span, the 2 V span achieves the optimum full- scale distortion performance at these higher input frequencies. Also, the 2 V span reduces the performance requirements of the input driver circuitry (i.e., IP3) and thus may also be more attractive from a system implementation perspective. Figure 35 shows a simplified schematic of the AD9224 configured in an IF sampling application. To reduce the complexity of the digital demodulator in many quadrature demodulation applications, the IF frequency and/or sample rate are strategically selected such that the bandlimited IF signal aliases back into the center of the ADC’s baseband region (i.e., FS/4). For example, if an IF signal centered at 45 MHz is sampled at 36 MSPS, an image of this IF signal will be aliased back to 9.0 MHz, which corresponds to one quarter of the sample rate (i.e., FS/4). This demodulation technique typically reduces the complexity of the post digital demodulator ASIC which follows the ADC. 360 SAW FILTER 340 FROM PREVIOUS STAGES MIXER 320 300 15 HIGH LINEARITY RF AMPLIFIER 20 25 30 35 40 SAMPLE RATE – MHz 45 OPTIONAL BANDPASS FILTER MINICIRCUITS T4-6T 20V VINA 200V RF2317 RF2312 50 VINB 20V CML 0.1mF Figure 34. Power Consumption vs. Clock Rate VREF Direct IF Down Conversion Using the AD9224 SENSE Sampling IF signals above an ADC’s baseband region (i.e., dc to FS/2) is becoming increasingly popular in communication applications. This process is often referred to as Direct IF Down Conversion or Undersampling. There are several potential benefits in using the ADC to alias (or mix) down a narrowband or wideband IF signal. First and foremost is the elimination of a complete mixer stage with its associated baseband amplifiers and filters, reducing cost and power dissipation. Second is the ability to apply various DSP techniques to perform such functions as filtering, channel selection, quadrature demodulation, data reduction, detection, etc. A detailed discussion on using this technique in digital receivers can be found in Analog Devices Application Notes AN-301 and AN-302. In Direct IF Down Conversion applications, one exploits the inherent sampling process of an ADC in which an IF signal lying outside the baseband region can be aliased back into the baseband region in a similar manner that a mixer will downconvert an IF signal. Similar to the mixer topology, an image rejection filter is required to limit other potential interfering signals from also aliasing back into the ADC’s baseband region. A tradeoff exists between the complexity of this image rejection filter and the ADC’s sample rate as well as dynamic range. REV. A AD9224 10mF 0.1mF REFCOM Figure 35. Example of AD9224 IF Sampling Circuit To maximize its distortion performance, the AD9224 is configured in the differential mode with a 2 V span using a transformer. The center-tap of the transformer is biased at midsupply via the CML output of the AD9224. Preceding the AD9224 and transformer is an optional bandpass filter as well as a gain stage. A low Q passive bandpass filter can be inserted to reduce outof-band distortion and noise which lies within the AD9224’s 130 MHz bandwidth. A large gain stage(s) is often required to compensate for the high insertion losses of a SAW filter used for channel selection and image rejection. The gain stage will also provide adequate isolation for the SAW filter from the charge “kick back” currents associated with the AD9224’s switched capacitor input stage. –19– AD9224 The distortion and noise performance of an ADC at the given IF frequency is of particular concern when evaluating an ADC for a narrowband IF sampling application. Both single tone and dual tone SFDR vs. amplitude are very useful in assessing an ADC’s dynamic and static nonlinearities. SNR vs. amplitude performance at the given IF is useful in assessing the ADC’s noise performance and noise contribution due to aperture jitter. In any application, one is advised to test several units of the same device under the same conditions to evaluate the given applications sensitivity to that particular device. 100 90 SNR/SFDR – dBc/dBFS 80 Figures 36–39 combine the dual tone SFDR as well as single tone SFDR and SNR performances at IF frequencies of 35 MHz, 45 MHz, 71 MHz, and 85 MHz. Note, the SFDR vs. amplitude data is referenced to dBFS while the single tone SNR data is referenced to dBc. The performance characteristics in these figures are representative of the AD9224 without any preceding gain stage. The AD9224 was operated in the differential mode (via transformer) with a 2 V span and a sample rate between 28 MSPS and 36 MSPS. The analog supply (AVDD) and the digital supply (DRVDD) were set to +5 V and +3.3 V respectively. SFDR-SINGLE TONE (dBFS) SFDR-DUAL TONE (dBFS) 70 60 SNR-SINGLE TONE (dBc) 50 40 30 20 10 0 –0.5 –5 –10 –15 AIN – dBFS –20 –25 –30 Figure 37. IF Undersampling at 45 MHz (F1 = 44.53 MHz, F2 = 45.55 MHz, fCLOCK = 36 MSPS) 100 90 100 SNR/SFDR – dBc/dBFS 80 90 SNR/SFDR – dBc/dBFS 80 SFDR-SINGLE TONE (dBFS) SFDR-DUAL TONE (dBFS) 70 60 SNR-SINGLE TONE (dBc) 50 50 30 20 10 0 –0.5 SNR-SINGLE TONE (dBc) 40 30 0 –0.5 10 –5 –10 –15 AIN – dBFS –20 –25 –30 SFDR-SINGLE TONE (dBFS) 60 40 20 SFDR-DUAL TONE (dBFS) 70 –5 –10 –15 AIN – dBFS –20 –25 –30 Figure 38. IF Undersampling at 70 MHz (F1 = 70.46 MHz, F2 = 71.36 MHz, fCLOCK = 31.5 MSPS) Figure 36. IF Undersampling at 35 MHz (F1 = 34.64 MHz, F2 = 35.43 MHz, fCLOCK = 28 MSPS) 100 90 SFDR-SINGLE TONE (dBFS) SNR/SFDR – dBc/dBFS 80 70 SFDR-DUAL TONE (dBFS) 60 50 40 SNR-SINGLE TONE (dBc) 30 20 10 0 –0.5 –5 –10 –15 AIN – dBFS –20 –25 30 Figure 39. IF Undersampling at 85 MHz (F1 = 84.46 MHz, F2 = 85.36 MHz, fCLOCK = 31 MSPS) –20– REV. A AD9224 GROUNDING AND DECOUPLING Analog and Digital Grounding Analog and Digital Driver Supply Decoupling The AD9224 features separate analog and digital supply and ground pins, helping to minimize digital corruption of sensitive analog signals. In general, AVDD, the analog supply, should be decoupled to AVSS, the analog common, as close to the chip as physically possible. Figure 41 shows the recommended decoupling for the analog supplies; 0.1 µF ceramic chip and 10 µF tantalum capacitors should provide adequately low impedance over a wide frequency range. Note that the AVDD and AVSS pins are colocated on the AD9224 to simplify the layout of the decoupling capacitors and provide the shortest possible PCB trace lengths. The AD9224/AD9225EB power plane layout, shown in Figure 48 depicts a typical arrangement using a multilayer PCB. Proper grounding is essential in any high speed, high resolution system. Multilayer printed circuit boards (PCBs) are recommended to provide optimal grounding and power schemes. The use of ground and power planes offers distinct advantages: 1. The minimization of the loop area encompassed by a signal and its return path. 2. The minimization of the impedance associated with ground and power paths. 3. The inherent distributed capacitor formed by the power plane, PCB insulation and ground plane. These characteristics result in both a reduction of electromagnetic interference (EMI) and an overall improvement in performance. AVDD It is important to design a layout that prevents noise from coupling onto the input signal. Digital signals should not be run in parallel with input signal traces and should be routed away from the input circuitry. While the AD9224 features separate analog and driver ground pins, it should be treated as an analog component. The AVSS and DRVSS pins must be joined together directly under the AD9224. A solid ground plane under the A/D is acceptable if the power and ground return currents are carefully managed. Alternatively, the ground plane under the A/D may contain serrations to steer currents in predictable directions where cross coupling between analog and digital would otherwise be unavoidable. The AD9224/AD9225EB ground layout, shown in Figure 47, depicts the serrated type of arrangement. The evaluation board is primarily built over a common ground plane. It has a “slit” to route currents near the clock driver. Figure 40 illustrates a general scheme of ground and power implementation in and around the AD9224. AVDD A A ADC IC D DIGITAL LOGIC ICs CSTRAY ANALOG CIRCUITS VIN DIGITAL CIRCUITS B A A IA CSTRAY ID AVSS A = ANALOG D = DIGITAL LOGIC SUPPLY DVDD A GND DVSS A DV 10mF AD9224 0.1mF AVSS Figure 41. Analog Supply Decoupling The CML is an internal analog bias point used internally by the AD9224. This pin must be decoupled with at least a 0.1 µF capacitor as shown in Figure 42. The dc level of CML is approximately AVDD/2. This voltage should be buffered if it is to be used for any external biasing. CML 0.1mF AD9224 Figure 42. CML Decoupling The digital activity on the AD9224 chip falls into two general categories: correction logic, and output drivers. The internal correction logic draws relatively small surges of current, mainly during the clock transitions. The output drivers draw large current impulses while the output bits are changing. The size and duration of these currents are a function of the load on the output bits: large capacitive loads are to be avoided. Note, the internal correction logic of the AD9224 is referenced to AVDD while the output drivers are referenced to DRVDD. The decoupling shown in Figure 43, a 0.1 µF ceramic chip and 10 µF tantalum capacitors are appropriate for a reasonable capacitive load on the digital outputs (typically 20 pF on each pin). Applications involving greater digital loads should consider increasing the digital decoupling proportionally, and/or using external buffers/latches. D DRVDD 10mF Figure 40. Ground and Power Consideration AD9224 0.1mF DRVSS Figure 43. Digital Supply Decoupling A complete decoupling scheme will also include large tantalum or electrolytic capacitors on the PCB to reduce low frequency ripple to negligible levels. Refer to the AD9224/AD9225EB schematic and layouts in Figures 44-50 for more information regarding the placement of decoupling capacitors. REV. A –21– AD9224 U5 REF43 TP38 2 VOUT VIN GND 4 1 1 R25 2.49kV 2 1 R27 4.99kV 2 VCCIN R29 1kV 6 U4 N2 AD187 OUT N1 –V 2 1 IN 4 2 1 C19 10mF 10V TP37 1 2 1 2 1 1 2 2 2 2 1 1 C21 + 10mF 10V 2 JP22 JP23 JP24 JP25 1 2 2 C34 0.1mF 2 1 R30 316V TP37 1 J3 C20 2 10mF 10V 1 R32 50V 2 2 C33 0.1mF 1 1 2 R21 200V 1 2 TP33 R22 200V 1 2 TP32 T1 R24 50V 5 3 1 2 C49 VEE 1 20V 1 1 P5 1 JP11 JP12 U9 11 2 10 U9 2 L5 FBEAD 2 1 2 22mF 2 20V DGND 2 U9 12 1 13 D11 DVDD 1 1 J5 1 2 U1 REF43 1 + C8 1 C16 0.1mF 2 10mF 2 10V VIN VOUT GND 3 1 J2 2 A R19 4kV 3 2 R2 5kV CCV JP17 1 B 2 C13 0.1mF 2 1 + 1 C9 TP4 1 U8 3 1 R1 50V 2 1 JP6 2 1 JP8 2 C15 0.1mF 1 8 R18 1kV JP9 1 L7404 TP10 1 TP1 1 10 L7404 2 L7404 13 12 L7404 1 U8 2 TP3 1 1 2 JP3 A1 A2 A3 A4 A5 A6 A7 A8 DVDD D4 D3 D2 D1 D0 OTR CLK 1 C10 0.1mF U8 DECOUPLING + C3 10mF 2 10V 17 16 15 14 13 12 11 2 2 2 U6 74541 Y1 18 1 19 20 VCC 10 GND G1 G2 2 3 4 5 6 7 8 9 C5 10V 10mF 1+ 2 18 A1 Y1 17 A2 Y2 U7 16 A3 74541 Y3 15 A4 Y4 14 A5 Y5 13 A6 Y6 12 A7 Y7 11 A8 Y8 1 TP9 1 1 2 3 4 5 6 7 8 VCC CLR RCO CLK QA A U2 QB B 74LS161 QC C QD D ENT ENP GND LOAD 16 15 14 13 12 11 10 DRVDD 1 JP28 1 2 L6 FBEAD 2 1 1 A B 2 1 R5 22V 1 2 1 R6 22V 1 2 1 R7 22V 1 2 1 R8 22V 2 1 1 R9 22V 1 2 1 R10 22V 1 2 1 R11 22V 1 2 1 R12 22V 1 2 1 R13 22V 1 2 1 R14 22V 1 2 1 R15 22V 1 2 1 1 3 R16 22V JP29 2 1 1 1 JP31 1 2 2 1 C55 0.1mF DUTAVDDIN 2 P6 + C58 22mF 20V 2 AGND 1 P6 2 1 TP25 1 P1 P1 2 3 P1 P1 4 5 P1 P1 6 7 P1 P1 8 9 P1 P1 10 11 P1 P1 12 13 P1 P1 14 15 P1 P1 16 17 P1 P1 18 19 P1 P1 20 21 P1 P1 22 23 P1 P1 24 25 P1 P1 26 27 P1 P1 28 29 P1 P1 30 TP24 TP23 TP22 TP21 TP20 TP19 TP26 TP18 TP17 TP16 TP15 31 P1 P1 32 33 P1 P1 34 35 P1 P1 36 37 P1 P1 38 39 P1 P1 40 TP14 TP13 TP12 TP11 2 2 1 R20 22V 10mF 10V 1 R17 22V 1 2 2 JP30 9 JP15 DUTAUDD + C23 C38 0.1mF 1 R33 1kV 2 1 L7404 2 10mF 2 10V C59 2 0.1mF 20 VCC 10 GND Y2 Y3 Y4 Y5 Y6 Y7 Y8 P3 + C1 1 C11 0.1mF 2 1 1 JP2 2 L7404 AVDD TP2 1 U8 1 2 A B 3 1 JP32 U9 3 4 U9 1 U8 11 10mF 2 10V C17 0.1mF JP14 6 1 JP7 2 1 1 CW 9 4 L7404 U8 L7404 2 2 U8 2 1 JP13 2 5 1 10mF 2 10V 1 D10 D9 D8 D7 D6 D5 + C7 U9 DECOUPLING 2 AVDD 2 3 4 5 6 7 8 9 JP27 1 2 TP40 1 C4 10V 10mF 2 +1 G1 G2 1 C37 0.1mF 1 DUTAVDD 2 1 19 2 OTR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CLK 1 2 1 C14 0.1mF 2 22mF 20V JP16 3 A B 2 C40 0.001mF TP5 C12 0.1mF 1 2 1 2 R35 50V C43 15pF 1 2 L7404 C56 0.1mF 1 TP39 L1 FBEAD 22mF 20V 2 AGND 14 13 12 11 10 9 8 7 6 5 4 3 2 1 OTR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CLK 1 1 C41 0.001mF 2 1 DRVDD 1 2 P3 + C47 C42 15pF 1 JP5 2 TP8 U9 6 JP4 1 C44 15pF 1 JP1 2 L7404 + C51 P5 1 5 2 DGND 2 TP7 1 L7404 1 2 1 8 9 2 1 C45 15pF 1 2 1 + C6 TP6 1 L7404 DRVDDIN 2 DVDDIN 1 P2 P2 JP10 1 C46 15pF 1 C54 0.1mF 2 + 22mF 2 2 TP36 1 1 1 C25 0.1mF 2 T4-6T L4 FBEAD VEEIN 1 6 3 2 P4 2 4 2 1 1 AVDD 1 1 1 2 AVDDIN1 C52 0.1mF AD9224 DUTDRVDD 2 R23 200V 1 1 2 AVDD2 AVSS2 SENSE VREF REFCOM CAPB CAPT CML U3 VINA VINB AVSS1 AVDD1 DRVSS DRVDD C24 2 0.1mF JP18 1 1 2 JP26 1 2 TP27 TP28 1 15 16 17 18 19 20 21 22 23 24 25 26 27 28 C35 0.1mF L2 FBEAD 1 1 1 1 AVDD 1 2 2 C32 0.1mF 1 2 1 C36 0.1mF 2 2 TP29 1 J1 C39 0.001mF 1 C22 + 10mF 10V 2 2 1 1 2 VCC 1 1 C57 0.1mF 2 Q1 2N2222 C27 0.1mF 1 2 C31 0.1mF 1 C53 0.1mF 2 22mF 20V AGND 2 1 3 1 VEE L3 FBEAD 1 8 +V 1 1 R4 10kV 2 7 3 1 1 2 R3 10kV 2 0.1mF 10mF 2 10V + C48 P4 1 + C2 C29 0.1mF C26 0.1mF 1 JP21 1 IN 2 1 TP31 TP30 + C28 R28 1 50V 2 1 R31 820V 1 1 2 1 R26 4.99kV 2 JP20 1 2 P4 10mF 2 10V 2 JP19 2 1 + 1 2 + C18 TP34 DUTAVDD 1 C30 0.1mF R34 2 50V 1 1 J4 VCC + 6 DVDD + C50 10mF 2 10V DVDD Figure 44. Evaluation Board Schematic –22– REV. A AD9224 Figure 45. Evaluation Board Component Side Layout (Not to Scale) Figure 48. Evaluation Board Solder Side Layout (Not to Scale) Figure 49. Evaluation Board Power Plane Layout Figure 46. Evaluation Board Ground Plane Layout (Not to Scale) Figure 47. Evaluation Board Component Side Silkscreen (Not to Scale) REV. A Figure 50. Evaluation Board Solder Side Silkscreen (Not to Scale) –23– AD9224 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead Shrink Small Outline (SSOP) (RS-28) 15 1 14 C3248a–0–1/99 28 0.212 (5.38) 0.205 (5.21) 0.07 (1.79) 0.066 (1.67) 0.078 (1.98) PIN 1 0.068 (1.73) 0.008 (0.203) 0.0256 (0.65) 0.002 (0.050) BSC 0.015 (0.38) 0.010 (0.25) 8° SEATING 0.009 (0.229) 0° PLANE 0.005 (0.127) 0.03 (0.762) 0.022 (0.558) PRINTED IN U.S.A. 0.311 (7.9) 0.301 (7.64) 0.407 (10.34) 0.397 (10.08) –24– REV. A