AD9228-65EBZ

Quad, 12-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter AD9228 FEATURES 4 ADCs integrated into 1 package 119 mW ADC power per channel at 65 MSPS SNR = 70 dB (to Nyquist) ENOB = 11.3 bits SFDR = 82 dBc (to Nyquist) Excellent linearity DNL = ±0.3 LSB (typical) INL = ±0.4 LSB (typical) Serial LVDS (ANSI-644, default) Low power, reduced signal option (similar to IEEE 1596.3) Data and frame clock outputs 315 MHz full-power analog bandwidth 2 V p-p input voltage range 1.8 V supply operation Serial port control Full-chip and individual-channel power-down modes Flexible bit orientation Built-in and custom digital test pattern generation Programmable clock and data alignment Programmable output resolution Standby mode FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DRVDD DRGND AD9228 VIN + A VIN – A VIN + B VIN – B VIN + C VIN – C VIN + D VIN – D VREF SENSE REFT REFB REF SELECT PIPELINE ADC 12 SERIAL LVDS 12 PIPELINE ADC 12 PIPELINE ADC 12 PIPELINE ADC SERIAL LVDS SERIAL LVDS D+C D–C D+D D–D SERIAL LVDS D+B D–B D+A D–A + – FCO+ 0.5V SERIAL PORT INTERFACE DATA RATE MULTIPLIER FCO– DCO+ DCO– Figure 1. APPLICATIONS Medical imaging and nondestructive ultrasound Portable ultrasound and digital beam-forming systems Quadrature radio receivers Diversity radio receivers Tape drives Optical networking Test equipment capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individualchannel power-down is supported and typically consumes less than 2 mW when all channels are disabled. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom userdefined test patterns entered via the serial port interface (SPI). The AD9228 is available in an RoHS compliant, 48-lead LFCSP. It is specified over the industrial temperature range of −40°C to +85°C. GENERAL DESCRIPTION The AD9228 is a quad, 12-bit, 40/65 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 65 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. PRODUCT HIGHLIGHTS 1. 2. 3. Small Footprint. Four ADCs are contained in a small, spacesaving package. Low power of 119 mW/channel at 65 MSPS. Ease of Use. A data clock output (DCO) is provided that operates at frequencies of up to 390 MHz and supports double data rate (DDR) operation. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements. Pin-Compatible Family. This includes the AD9287 (8-bit), AD9219 (10-bit), and AD9259 (14-bit). 4. 5. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006–2007 Analog Devices, Inc. All rights reserved. 05727-001 RBIAS AGND CSB SDIO/ODM SCLK/DTP CLK+ CLK– AD9228 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 AC Specifications.......................................................................... 4 Digital Specifications ................................................................... 5 Switching Specifications .............................................................. 6 Timing Diagrams.............................................................................. 7 Absolute Maximum Ratings............................................................ 9 Thermal Impedance ..................................................................... 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Equivalent Circuits ......................................................................... 12 Typical Performance Characteristics ........................................... 14 Theory of Operation ...................................................................... 19 Analog Input Considerations ................................................... 19 Clock Input Considerations...................................................... 22 Serial Port Interface (SPI).............................................................. 30 Hardware Interface..................................................................... 30 Memory Map .................................................................................. 32 Reading the Memory Map Table.............................................. 32 Reserved Locations .................................................................... 32 Default Values ............................................................................. 32 Logic Levels................................................................................. 32 Evaluation Board ............................................................................ 36 Power Supplies............................................................................ 36 Input Signals................................................................................ 36 Output Signals ............................................................................ 36 Default Operation and Jumper Selection Settings................. 37 Alternative Analog Input Drive Configuration...................... 38 Outline Dimensions ....................................................................... 52 Ordering Guide .......................................................................... 52 REVISION HISTORY 7/07—Rev. A to Rev. B Changes to Figure 3.......................................................................... 7 Change to Table 7 ........................................................................... 10 5/07—Rev. 0 to Rev. A Changes to Features.......................................................................... 1 Change to Effective Number of Bits (ENOB) ............................... 4 Changes to Logic Output (SDIO/ODM) Section......................... 5 Added Endnote 3 to Table 3 ............................................................ 5 Changes to Pipeline Latency ........................................................... 6 Added Endnote 2 to Table 4 ............................................................ 6 Changes to Figure 2 to Figure 4 ...................................................... 7 Changes to Figure 10...................................................................... 12 Changes to Figure 15, Figure 17 to Figure 19, Figure 37, and Figure 39 ..................................................................................... 14 Changes to Figure 23 to Figure 26 Captions ............................... 15 Change to Figure 35 Caption ........................................................ 17 Added Figure 46 and Figure 47..................................................... 20 Changes to Figure 51...................................................................... 21 Changes to Clock Duty Cycle Considerations Section.............. 22 Changes to Power Dissipation and Power-Down Mode Section ...23 Changes to Figure 61 to Figure 63 Captions ............................... 25 Changes to Table 9 Endnote.......................................................... 26 Changes to Digital Outputs and Timing Section ....................... 27 Added Table 10 ............................................................................... 27 Changes to RBIAS Pin Section ..................................................... 28 Deleted Figure 62 and Figure 63 .................................................. 27 Changes to Figure 67...................................................................... 29 Changes to Hardware Interface Section ...................................... 30 Added Figure 68 ............................................................................. 31 Changes to Table 15 ....................................................................... 31 Changes to Reading the Memory Map Table Section ............... 32 Change to Input Signals Section................................................... 36 Changes to Output Signals Section.............................................. 36 Changes to Figure 71...................................................................... 36 Changes to Default Operation and Jumper Selection Settings Section........................................... 37 Changes to Alternative Analog Input Drive Configuration Section.................................................... 38 Changes to Figure 74...................................................................... 40 Changes to Table 17 ....................................................................... 48 Changes to Ordering Guide .......................................................... 52 4/06—Revision 0: Initial Version Rev. B | Page 2 of 52 AD9228 SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 1. Parameter 1 RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error Reference Voltage (1 V Mode) REFERENCE Output Voltage Error (VREF = 1 V ) Load Regulation at 1.0 mA (VREF = 1 V ) Input Resistance ANALOG INPUTS Differential Input Voltage (VREF = 1 V ) Common-Mode Voltage Differential Input Capacitance Analog Bandwidth, Full Power POWER SUPPLY AVDD DRVDD IAVDD IDRVDD Total Power Dissipation (Including Output Drivers) Power-Down Dissipation Standby Dissipation 2 CROSSTALK CROSSTALK (Overrange Condition) 3 1 2 Temperature Min 12 AD9228-40 Typ Max Min 12 AD9228-65 Typ Max Unit Bits Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 1.7 1.7 Guaranteed ±1 ±2 ±0.4 ±0.3 ±0.25 ±0.4 ±2 ±17 ±21 ±2 3 6 2 AVDD/2 7 315 1.8 1.8 155 31 335 2 72 −100 −100 ±8 ±8 ±1.2 ±0.7 ±0.5 ±1 Guaranteed ±1 ±2 ±2 ±0.3 ±0.3 ±0.4 ±2 ±17 ±21 ±8 ±8 ±3.5 ±0.7 ±0.65 ±1 mV mV % FS % FS LSB LSB ppm/°C ppm/°C ppm/°C ±30 ±2 3 6 2 AVDD/2 7 315 ±30 mV mV kΩ V p-p V pF MHz 1.9 1.9 170 34 367 5.8 1.7 1.7 1.8 1.8 232 34 478 2 72 −100 −100 1.9 1.9 245 38 510 5.8 V V mA mA mW mW mW dB dB See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Can be controlled via the SPI. 3 Overrange condition is specific with 6 dB of the full-scale input range. Rev. B | Page 3 of 52 AD9228 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 2. Parameter 1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz WORST HARMONIC (Second or Third) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz WORST OTHER (Excluding Second or Third) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz TWO-TONE INTERMODULATION DISTORTION (IMD)— AIN1 AND AIN2 = −7.0 dBFS fIN1 = 15 MHz, fIN2 = 16 MHz fIN1 = 70 MHz, fIN2 = 71 MHz 1 Temperature Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Min AD9228-40 Typ Max 70.5 70.2 70.2 70.0 70.3 69.8 69.7 69.5 11.42 11.37 11.37 11.33 85 82 80 80 −85 −82 −80 −80 −90 −90 −90 −90 Min AD9228-65 Typ Max 70.2 70.0 70.0 69.5 70.0 70.0 69.8 69.0 11.37 11.33 11.33 11.25 85 85 84 74 −85 −85 −84 −74 −90 −90 −90 −88 Unit dB dB dB dB dB dB dB dB Bits Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc 68.5 68.5 68.0 68.0 11.1 11.1 72 73 −72 −73 −80 −79 25°C 25°C 80.8 75.0 77.8 77.0 dBc dBc See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Rev. B | Page 4 of 52 AD9228 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 3. Parameter 1 CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage 2 Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC INPUTS (PDWN, SCLK/DTP) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (CSB) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (SDIO/ODM) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC OUTPUT (SDIO/ODM) 3 Logic 1 Voltage (IOH = 800 μA) Logic 0 Voltage (IOL = 50 μA) DIGITAL OUTPUTS (D + x, D − x), (ANSI-644) Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) DIGITAL OUTPUTS (D + x, D − x), (Low Power, Reduced Signal Option) Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) 1 2 Temperature Min AD9228-40 Typ Max CMOS/LVDS/LVPECL Min AD9228-65 Typ Max CMOS/LVDS/LVPECL Unit Full Full 25°C 25°C Full Full 25°C 25°C Full Full 25°C 25°C Full Full 25°C 25°C Full Full 250 1.2 20 1.5 1.2 0 30 0.5 1.2 0 70 0.5 1.2 0 30 2 1.79 0.05 LVDS DRVDD + 0.3 0.3 3.6 0.3 3.6 0.3 250 1.2 20 1.5 1.2 30 0.5 1.2 70 0.5 1.2 0 30 2 1.79 0.05 LVDS 247 1.125 454 1.375 Offset binary DRVDD + 0.3 0.3 3.6 0.3 3.6 0.3 mV p-p V kΩ pF V V kΩ pF V V kΩ pF V V kΩ pF V V Full Full 247 1.125 454 1.375 Offset binary mV V LVDS Full Full 150 1.10 250 1.30 Offset binary 150 1.10 LVDS 250 1.30 Offset binary mV V See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. This is specified for LVDS and LVPECL only. 3 This is specified for 13 SDIO pins sharing the same connection. Rev. B | Page 5 of 52 AD9228 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 4. AD9228-40 Parameter 1 , 2 CLOCK 3 Maximum Clock Rate Minimum Clock Rate Clock Pulse Width High (tEH) Clock Pulse Width Low (tEL) OUTPUT PARAMETERS3 Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) FCO Propagation Delay (tFCO) DCO Propagation Delay (tCPD) 4 DCO to Data Delay (tDATA)4 DCO to FCO Delay (tFRAME) Data to Data Skew (tDATA-MAX − tDATA-MIN) Wake-Up Time (Standby) Wake-Up Time (Power-Down) Pipeline Latency APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter) Out-of-Range Recovery Time 4 AD9228-65 Max Min 65 10 10 7.7 7.7 3.5 2.0 2.7 300 300 2.7 tFCO + (tSAMPLE/24) (tSAMPLE/24) (tSAMPLE/24) ±50 600 375 8 3.5 Typ Max Unit MSPS MSPS ns ns ns ps ps ns ns ps ps ps ns μs CLK cycles ps ps rms CLK cycles Temp Full Full Full Full Full Full Full Full Full Full Full Full 25°C 25°C Full Min 40 Typ 12.5 12.5 2.0 2.7 300 300 2.7 tFCO + (tSAMPLE/24) (tSAMPLE/24) (tSAMPLE/24) ±50 600 375 8 2.0 3.5 2.0 3.5 (tSAMPLE/24) − 300 (tSAMPLE/24) − 300 (tSAMPLE/24) + 300 (tSAMPLE/24) + 300 ±150 (tSAMPLE/24) − 300 (tSAMPLE/24) − 300 (tSAMPLE/24) + 300 (tSAMPLE/24) + 300 ±150 25°C 25°C 25°C 500