12-Bit, 20/40/65 MSPS
3 V A/D Converter
AD9235
Data Sheet
FEATURES
APPLICATIONS
Ultrasound equipment
IF sampling in communications receivers
IS-95, CDMA-One, IMT-2000
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
FUNCTIONAL BLOCK DIAGRAM
DRVDD
AVDD
VIN+
SHA
8-STAGE
1 1/2-BIT
PIPELINE
MDAC1
VIN–
4
REFT
A/D
16
3
A/D
REFB
CORRECTION LOGIC
12
OTR
OUTPUT BUFFERS
D11
AD9235
VREF
D0
CLOCK
DUTY CYCLE
STABILIZER
SENSE
REF
SELECT
MODE
SELECT
0.5V
AGND
CLK
PDWN
MODE
DGND
02461-001
Single 3 V supply operation (2.7 V to 3.6 V)
SNR = 70 dBc to Nyquist at 65 MSPS
SFDR = 85 dBc to Nyquist at 65 MSPS
Low power: 300 mW at 65 MSPS
Differential input with 500 MHz bandwidth
On-chip reference and SHA
DNL = ±0.4 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty cycle stabilizer
Figure 1.
GENERAL DESCRIPTION
The AD9235 is a family of monolithic, single 3 V supply, 12-bit,
20/40/65 MSPS analog-to-digital converters (ADCs). This
family features a high performance sample-and-hold amplifier
(SHA) and voltage reference. The AD9235 uses a multistage
differential pipelined architecture with output error correction
logic to provide 12-bit accuracy at 20/40/65 MSPS data rates
and guarantee no missing codes over the full operating
temperature range.
The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and offsets including single-ended
applications. It is suitable for multiplexed systems that switch
full-scale voltage levels in successive channels and for sampling
single-channel inputs at frequencies well beyond the Nyquist rate.
Combined with power and cost savings over previously available
ADCs, the AD9235 is suitable for applications in communications, imaging, and medical ultrasound.
A single-ended clock input is used to control all internal
conversion cycles. A duty cycle stabilizer (DCS) compensates
for wide variations in the clock duty cycle while maintaining
excellent overall ADC performance. The digital output data is
presented in straight binary or twos complement formats. An
out-of-range (OTR) signal indicates an overflow condition that
can be used with the most significant bit to determine low or
high overflow.
Fabricated on an advanced CMOS process, the AD9235 is available in a 28-lead TSSOP and a 32-lead LFCSP and is specified
over the industrial temperature range (–40°C to +85°C).
PRODUCT HIGHLIGHTS
1. The AD9235 operates from a single 3 V power supply and
features a separate digital output driver supply to accommodate 2.5 V and 3.3 V logic families.
2. Operating at 65 MSPS, the AD9235 consumes a low 300 mW.
3. The patented SHA input maintains excellent performance for
input frequencies up to 100 MHz and can be configured for
single-ended or differential operation.
4. The AD9235 pinout is similar to the AD9214-65, a 10-bit,
65 MSPS ADC. This allows a simplified upgrade path from
10 bits to 12 bits for 65 MSPS systems.
5. The clock DCS maintains overall ADC performance over a
wide range of clock pulse widths.
6. The OTR output bit indicates when the signal is beyond the
selected input range.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.
AD9235
Data Sheet
TABLE OF CONTENTS
Specifications..................................................................................... 3
Applying the AD9235 .................................................................... 15
DC Specifications ......................................................................... 3
Theory of Operation .................................................................. 15
Digital Specifications ................................................................... 4
Analog Input ............................................................................... 15
Switching Specifications .............................................................. 4
Clock Input Considerations ...................................................... 16
AC Specifications.......................................................................... 5
Power Dissipation and Standby Mode .................................... 17
Absolute Maximum Ratings ............................................................ 7
Digital Outputs ........................................................................... 18
Explanation of Test Levels ........................................................... 7
Voltage Reference ....................................................................... 18
ESD Caution .................................................................................. 7
Operational Mode Selection ..................................................... 19
Pin Configurations and Function Descriptions ........................... 8
TSSOP Evaluation Board .......................................................... 19
Definitions of Specifications ........................................................... 9
LFCSP Evaluation Board ........................................................... 20
Equivalent Circuits ......................................................................... 10
Outline Dimensions ....................................................................... 36
Typical Performance Characteristics ........................................... 11
Ordering Guide .......................................................................... 37
REVISION HISTORY
10/12—Rev. C to Rev. D
Changes to Figure 4 and Table 6 ................................................................8
Updated Outline Dimensions (Changed CP-32-2 to CP-32-7) ..... 36
Changes to Ordering Guide .......................................................... 37
10/04—Data Sheet changed from Rev. B to Rev. C
Changes to Format ............................................................. Universal
Changes to Specifications .................................................................3
Changes to the Ordering Guide.................................................... 37
5/03—Data Sheet changed from Rev. A to Rev. B
Added CP-32 Package (LFCSP) ........................................ Universal
Changes to Several Pin Names.......................................... Universal
Changes to Features...........................................................................1
Changes to Product Description .....................................................1
Changes to Product Highlights........................................................1
Changes to Specifications .................................................................2
Replaced Figure 1 ..............................................................................3
Changes to Absolute Maximum Ratings ........................................5
Changes to Ordering Guide .............................................................5
Changes to Pin Function Descriptions ...........................................6
New Definitions of Specifications Section .....................................7
Changes to TPCs 1 to 12 .................................................................. 9
Changes to Theory of Operation Section.....................................13
Changes to Analog Input Section..................................................13
Changes to Single-ended Input Configuration Section .............14
Replaced Figure 8 ............................................................................14
Changes to Clock Input Considerations Section ........................14
Changes to Table I ...........................................................................15
Changes to Power Dissipation and Standby Mode Section .......15
Changes to Digital Outputs Section..............................................15
Changes to Timing Section ............................................................15
Changes to Figure 13.......................................................................16
Changes to Figures 16 to 26 ...........................................................17
Added LFCSP Evaluation Board Section .....................................17
Inserted Figures 27 to 35 ................................................................25
Added Table III ................................................................................30
Updated Outline Dimensions ........................................................31
8/02—Data Sheet changed from Rev. 0 to Rev. A
Updated RU-28 Package ................................................................ 24
Rev. D | Page 2 of 40
Data Sheet
AD9235
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference, TMIN to TMAX,
unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes Guaranteed
Offset Error
Gain Error 1
Differential Nonlinearity (DNL) 2
Integral Nonlinearity (INL)2
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
Output Voltage Error (0.5 V Mode)
Load Regulation @ 0.5 mA
INPUT REFERRED NOISE
VREF = 0.5 V
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 0.5 V
Input Span, VREF = 1.0 V
Input Capacitance 3
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltages
AVDD
DRVDD
Supply Current
IAVDD2
IDRVDD2
PSRR
POWER CONSUMPTION
DC Input 4
Sine Wave Input2
Standby Power 5
Temp
Full
Test
Level
VI
AD9235BRU/BCP-20
Min Typ
Max
12
AD9235BRU/BCP-40
Min Typ
Max
12
AD9235BRU/BCP-65
Min Typ
Max
12
Full
Full
Full
Full
25°C
Full
25°C
VI
VI
VI
IV
I
IV
I
12
12
12
Full
Full
V
V
±2
±12
Full
Full
Full
Full
VI
V
V
V
±5
0.8
±2.5
0.1
25°C
25°C
V
V
0.54
0.27
0.54
0.27
0.54
0.27
LSB rms
LSB rms
Full
Full
Full
Full
IV
IV
V
V
1
2
7
7
1
2
7
7
1
2
7
7
V p-p
V p-p
pF
kΩ
Full
Full
IV
IV
Full
Full
Full
V
V
V
30
2
±0.01
Full
Full
Full
V
VI
V
90
95
1.0
±0.30
±0.30
±0.35
±0.35
±0.45
±0.40
2.7
2.25
3.0
3.0
±1.20
±2.40
±0.65
±0.50
±0.50
±0.35
±0.35
±0.50
±0.40
±0.80
±1.20
±2.50
±0.75
±0.50
±0.50
±0.40
±0.35
±0.70
±0.45
±0.90
±2
±12
±35
3.6
3.6
±5
0.8
±2.5
0.1
2.7
2.25
3.0
3.0
165
180
1.0
±1.30
±3
±12
±35
3.6
3.6
55
5
±0.01
110
±1.20
±2.60
±0.80
±5
0.8
±2.5
0.1
2.7
2.25
3.0
3.0
300
320
1.0
Bits
% FSR
% FSR
LSB
LSB
LSB
LSB
ppm/°C
ppm/°C
±35
3.6
3.6
100
7
±0.01
205
Unit
Bits
mV
mV
mV
mV
V
V
mA
mA
% FSR
350
mW
mW
mW
Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).
Measured at maximum clock rate, fIN = 2.4 MHz, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 5 for the equivalent analog input structure.
4
Measured with dc input at maximum clock rate.
5
Standby power is measured with a dc input, the CLK pin inactive (i.e., set to AVDD or AGND).
1
2
Rev. D | Page 3 of 40
AD9235
Data Sheet
DIGITAL SPECIFICATIONS
Table 2.
Parameter
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
LOGIC OUTPUTS 1
DRVDD = 3.3 V
High-Level Output Voltage
(IOH = 50 µA)
High-Level Output Voltage
(IOH = 0.5 mA)
Low-Level Output Voltage
(IOL = 1.6 mA)
Low-Level Output Voltage
(IOL = 50 µA)
DRVDD = 2.5 V
High-Level Output Voltage
(IOH = 50 µA)
High-Level Output Voltage
(IOH = 0.5 mA)
Low-Level Output Voltage
(IOL = 1.6 mA)
Low-Level Output Voltage
(IOL = 50 µA)
1
Temp
Test
Level
AD9235BRU/BCP-20
Min
Typ
Max
AD9235BRU/BCP-40
Min
Typ
Max
AD9235BRU/BCP-65
Min
Typ
Max
Full
Full
Full
Full
Full
IV
IV
IV
IV
V
2.0
2.0
2.0
Full
IV
3.29
3.29
3.29
V
Full
IV
3.25
3.25
3.25
V
Full
IV
0.2
0.2
0.2
V
Full
IV
0.05
0.05
0.05
V
Full
IV
2.49
2.49
2.49
V
Full
IV
2.45
2.45
2.45
V
Full
IV
0.2
0.2
0.2
V
Full
IV
0.05
0.05
0.05
V
0.8
+10
+10
–10
–10
0.8
+10
+10
–10
–10
2
0.8
+10
+10
–10
–10
2
2
Unit
V
V
µA
µA
pF
Output voltage levels measured with 5 pF load on each output.
SWITCHING SPECIFICATIONS
Table 3.
Parameter
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Minimum Conversion Rate
CLK Period
CLK Pulse-Width High 1
CLK Pulse-Width Low1
DATA OUTPUT PARAMETERS
Output Delay 2 (tPD)
Pipeline Delay (Latency)
Aperture Delay (tA)
Aperture Uncertainty Jitter (tJ)
Wake-Up Time 3
OUT-OF-RANGE RECOVERY TIME
1
2
3
Temp
Test
Level
AD9235BRU/BCP-20
Min
Typ
Max
AD9235BRU/BCP-40
Min
Typ
Max
AD9235BRU/BCP-65
Min
Typ
Max
Full
Full
Full
Full
Full
VI
V
V
V
V
20
40
65
Full
Full
Full
Full
Full
Full
V
V
V
V
V
V
1
50.0
15.0
15.0
1
25.0
8.8
8.8
3.5
7
1.0
0.5
3.0
1
1
15.4
6.2
6.2
3.5
7
1.0
0.5
3.0
1
For the AD9235-65 model only, with duty cycle stabilizer enabled. DCS function not applicable for -20 and -40 models.
Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output.
Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB.
Rev. D | Page 4 of 40
3.5
7
1.0
0.5
3.0
2
Unit
MSPS
MSPS
ns
ns
ns
ns
Cycles
ns
ps rms
ms
Cycles
Data Sheet
AD9235
N+1
N
N+2
N–1
tA
ANALOG
INPUT
N+8
N+3
N+7
N+4
N+5
N+6
DATA
OUT
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
tPD = 6.0ns MAX
2.0ns MIN
N
02461-002
CLK
Figure 2. Timing Diagram
AC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, AIN = –0.5 dBFS, 1.0 V internal reference, TMIN to TMAX,
unless otherwise noted.
Table 4.
Parameter
SIGNAL-TO-NOISE RATIO
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
fINPUT = 100 MHz
SIGNAL-TO-NOISE RATIO
AND DISTORTION
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
fINPUT = 100 MHz
TOTAL HARMONIC DISTORTION
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
fINPUT = 100 MHz
WORST HARMONIC
(SECOND OR THIRD)
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
AD9235BRU/BCP-20
Min Typ
Max
Temp
Test Level
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
V
IV
I
IV
I
IV
I
V
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
V
IV
I
IV
I
IV
I
V
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
V
IV
I
IV
I
IV
I
V
–88.0
–86.0
–87.4
Full
Full
Full
IV
IV
IV
–90.0
70.0
AD9235BRU/BCP-40
Min Typ
Max
70.8
70.4
70.6
AD9235BRU/BCP-65
Min Typ
Max
70.6
69.9
70.5
69.9
68.7
68.5
69.7
70.1
68.3
70.6
70.3
70.5
70.5
70.4
69.7
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
70.2
70.3
68.3
68.6
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
70.3
70.4
68.7
68.3
69.5
69.9
67.8
–89.0
–87.5
–79.0
–85.5
–86.0
–84.0
–79.0
–81.8
–82.0
–78.0
–82.5
–74.0
–80.0
–90.0
–80.0
–83.5
Rev. D | Page 5 of 40
Unit
–74.0
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
AD9235
Parameter
SPURIOUS-FREE DYNAMIC RANGE
fINPUT = 2.4 MHz
fINPUT = 9.7 MHz
fINPUT = 19.6 MHz
fINPUT = 32.5 MHz
fINPUT = 100 MHz
Data Sheet
Temp
Test Level
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
V
IV
I
IV
I
IV
I
V
AD9235BRU/BCP-20
Min Typ
Max
80.0
AD9235BRU/BCP-40
Min Typ
Max
92.0
88.5
91.0
AD9235BRU/BCP-65
Min Typ
Max
92.0
80.0
92.0
89.0
90.0
74.0
84.0
Rev. D | Page 6 of 40
85.0
83.0
85.0
80.5
Unit
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Data Sheet
AD9235
ABSOLUTE MAXIMUM RATINGS
Table 5.
With
Pin Name
Respect to
ELECTRICAL
AVDD
AGND
DRVDD
DGND
AGND
DGND
AVDD
DRVDD
Digital
DGND
Outputs
CLK, MODE
AGND
VIN+, VIN–
AGND
VREF
AGND
SENSE
AGND
REFB, REFT
AGND
PDWN
AGND
ENVIRONMENTAL 1
Operating Temperature
Junction Temperature
Lead Temperature (10 sec)
Storage Temperature
1
Min
Max
Unit
–0.3
–0.3
–0.3
–3.9
–0.3
+3.9
+3.9
+0.3
+3.9
DRVDD + 0.3
V
V
V
V
V
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
V
V
V
V
V
V
–40
+85
150
300
+150
°C
°C
°C
°C
–65
Absolute maximum ratings are limiting values to be applied
individually and beyond which the serviceability of the circuit
may be impaired. Functional operability is not necessarily
implied. Exposure to absolute maximum rating conditions for
an extended period of time may affect device reliability.
EXPLANATION OF TEST LEVELS
Test
Levels
I
II
III
IV
V
VI
Description
100% production tested.
100% production tested at 25°C and sample tested at
specified temperatures.
Sample tested only.
Parameter is guaranteed by design and characterization testing.
Parameter is a typical value only.
100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices.
Typical thermal impedances (28-lead TSSOP), θJA = 67.7°C/W; (32-lead
LFCSP), θJA = 32.5°C/W, θJC = 32.71°C/W. These measurements were taken on
a 4-layer board in still air, in accordance with EIA/JESD51-1.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation
or loss of functionality.
Rev. D | Page 7 of 40
AD9235
Data Sheet
OTR 1
28 D11 (MSB)
MODE 2
27 D10
26 D9
DNC
CLK
DNC
PDWN
DNC
DNC
D0 (LSB)
D1
25 D8
TOP VIEW
(Not to Scale)
23 DGND
7
22 D7
AGND 8
21 D6
VIN+ 9
20 D5
VIN– 10
19 D4
AGND 11
18
AVDD 12
17 D2
D3
CLK 13
16
D1
PDWN 14
15
D0 (LSB)
1
2
3
4
5
6
7
8
AD9235
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
VREF
SENSE
MODE
OTR
D11 (MSB)
D10
D9
D8
9
10
11
12
13
14
15
16
REFT 6
24 DRVDD
D2
D3
D4
D5
D6
D7
DGND
DRVDD
AD9235
02461-003
VREF 4
REFB 5
NOTES
1. DNC = DO NOT CONNECT.
2. IT IS RECOMMENDED THAT THE EXPOSED PADDLE
BE SOLDERED TO THE GROUND PLANE.
Figure 3. 28-Lead TSSOP Pin Configuration
02461-004
SENSE 3
AVDD
32 AVDD
31 AGND
30 VIN–
29 VIN+
28 AGND
27 AVDD
26 REFT
25 REFB
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 4. 32-Lead LFCSP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
28-Lead TSSOP
1
2
3
4
5
6
7, 12
8, 11
9
10
13
14
15 to 22, 25 to 28
23
24
Pin No.
32-Lead LFCSP
21
22
23
24
25
26
27, 32
28, 31
29
30
2
4
7 to 14, 17 to 20
15
16
Mnemonic
OTR
MODE
SENSE
VREF
REFB
REFT
AVDD
AGND
VIN+
VIN–
CLK
PDWN
D0 (LSB) to D11 (MSB)
DGND
DRVDD
1, 3, 5, 6
EP
DNC
EPAD
Description
Out-of-Range Indicator.
Data Format and Clock Duty Cycle Stabilizer (DCS) Mode Selection.
Reference Mode Selection.
Voltage Reference Input/Output.
Differential Reference (−).
Differential Reference (+).
Analog Power Supply.
Analog Ground.
Analog Input Pin (+).
Analog Input Pin (−).
Clock Input Pin.
Power-Down Function Selection (Active High).
Data Output Bits.
Digital Output Ground.
Digital Output Driver Supply. Must be decoupled to DGND with a minimum.
0.1 µF capacitor. Recommended decoupling is 0.1 µF in parallel with 10 µF.
Do Not Connect.
Exposed Pad. It is recommended that the exposed paddle be soldered to the
ground plane. There is an increased reliability of the solder joints and maximum thermal capability of the package is achieved with exposed paddle
soldered to the customer board.
Rev. D | Page 8 of 40
Data Sheet
AD9235
DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth (Full Power Bandwidth)
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay (tA)
The delay between the 50% point of the rising edge of the clock
and the instant at which the analog input is sampled.
Aperture Jitter (tJ)
The sample-to-sample variation in aperture delay.
Integral Nonlinearity (INL)
The deviation of each individual code from a line drawn from
negative full scale through positive full scale. The point used as
negative full scale occurs ½ LSB before the first code transition.
Positive full scale is defined as a level 1 ½ LSBs beyond the last
code transition. The deviation is measured from the middle of
each particular code to the true straight line.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 12-bit resolution indicates that all 4096
codes must be present over all operating ranges.
Offset Error
The major carry transition should occur for an analog value
½ LSB below VIN+ = VIN–. Offset error is defined as the
deviation of the actual transition from that point.
Gain Error
The first code transition should occur at an analog value ½ LSB
above negative full scale. The last transition should occur at an
analog value 1 ½ LSB below the positive full scale. Gain error is
the deviation of the actual difference between first and last code
transitions and the ideal difference between first and last code
transitions.
Temperature Drift
The temperature drift for offset error and gain error specifies
the maximum change from the initial (25°C) value to the value
at TMIN or TMAX.
Power Supply Rejection Ratio
The change in full scale from the value with the supply
at the minimum limit to the value with the supply at its
maximum limit.
Total Harmonic Distortion (THD) 1
The ratio of the rms sum of the first six harmonic components
to the rms value of the measured input signal.
1
Signal-to-Noise and Distortion (SINAD)1
The ratio of the rms signal amplitude (set 0.5 dB below full
scale) to the rms value of the sum of all other spectral components below the Nyquist frequency, including harmonics but
excluding dc.
Effective Number of Bits (ENOB)
The ENOB for a device for sine wave inputs at a given input
frequency can be calculated directly from its measured SINAD
using the following formula
N = (SINAD − 1.76)/6.02
Signal-to-Noise Ratio (SNR)1
The ratio of the rms signal amplitude (set at 0.5 dB below full
scale) to the rms value of the sum of all other spectral components below the Nyquist frequency, excluding the first six
harmonics and dc.
Spurious-Free Dynamic Range (SFDR)1
The difference in dB between the rms amplitude of the input
signal and the peak spurious signal.
Two-Tone SFDR1
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
Clock Pulse Width and Duty Cycle
Pulse-width high is the minimum amount of time that the
clock pulse should be left in the Logic 1 state to achieve rated
performance. Pulse-width low is the minimum time the clock
pulse should be left in the low state. At a given clock rate, these
specifications define an acceptable clock duty cycle.
Minimum Conversion Rate
The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the
guaranteed limit.
Maximum Conversion Rate
The clock rate at which parametric testing is performed.
Output Propagation Delay (tPD)
The delay between the clock logic threshold and the time when
all bits are within valid logic levels.
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input
after a transition from 10% above positive full scale to 10%
above negative full scale, or from 10% below negative full scale
to 10% below positive full scale.
AC specifications may be reported in dBc (degrades as signal levels are
lowered) or in dBFS (always related back to converter full scale).
Rev. D | Page 9 of 40
AD9235
Data Sheet
EQUIVALENT CIRCUITS
AVDD
DRVDD
VIN+, VIN–
02461-007
02461-005
D11–D0,
OTR
Figure 5. Equivalent Analog Input Circuit
Figure 7. Equivalent Digital Output Circuit
AVDD
AVDD
CLK,
PDWN
02461-008
20kΩ
02461-006
MODE
Figure 6. Equivalent MODE Input Circuit
Figure 8. Equivalent Digital Input Circuit
Rev. D | Page 10 of 40
Data Sheet
AD9235
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 3.0 V, DRVDD = 2.5 V, fSAMPLE = 65 MSPS with DCS disabled, TA = 25°C, 2 V differential input, AIN = −0.5 dBFS, VREF = 1.0 V,
unless otherwise noted.
0
100
SNR = 70.3dBc
SINAD = 70.2dBc
ENOB = 11.4 BITS
THD = –86.3dBc
SFDR = 89.9dBc
SFDR (2V DIFF)
95
90
85
–40
SNR/SFDR (dBc)
–60
–80
80
SNR (2V SE)
75
70
65
SNR (2V DIFF)
60
–100
55
0
6.5
13.0
19.5
FREQUENCY (MHz)
26.0
32.5
SFDR (2V SE)
50
40
02461-009
–120
Figure 9. Single Tone 8K FFT with fIN = 10 MHz
50
55
SAMPLE RATE (MSPS)
60
65
Figure 12. AD9235-65: Single Tone SNR/SFDR vs.
fCLK with fIN = Nyquist (32.5 MHz)
100
0
SNR = 69.4dBc
SINAD = 69.1dBc
ENOB = 11.2 BITS
THD = –81.0dBc
SFDR = 83.8dBc
–20
95
90
85
–40
SNR/SFDR (dBc)
MAGNITUDE (dBFS)
45
02461-012
MAGNITUDE (dBFS)
–20
–60
–80
SFDR (2V DIFF)
80
SNR (2V SE)
75
SNR (2V DIFF)
70
65
SFDR (2V SE)
60
–100
78.0
84.5
FREQUENCY (MHz)
91.0
50
20
02461-010
71.5
Figure 10. Single Tone 8K FFT with fIN = 70 MHz
30
SAMPLE RATE (MSPS)
35
40
Figure 13. AD9235-40: Single Tone SNR/SFDR vs. fCLK with fIN = Nyquist (20 MHz)
100
0
SNR = 68.5dBc
SINAD = 66.5dBc
ENOB = 10.8 BITS
THD = –71.0dBc
SFDR = 71.2dBc
–20
SFDR (2V DIFF)
95
90
85
SNR/SFDR (dBc)
–40
–60
–80
SFDR (2V SE)
80
75
SNR (2V SE)
70
65
SNR (2V DIFF)
60
–100
–120
97.5
104.0
110.5
117.0
FREQUENCY (MHz)
123.5
Figure 11. Single Tone 8K FFT with fIN = 100 MHz
130.0
50
0
5
10
SAMPLE RATE (MSPS)
15
20
02461-014
55
02461-011
MAGNITUDE (dBFS)
25
02461-013
55
–120
65.0
Figure 14. AD9235-20: Single Tone SNR/SFDR vs. fCLK with fIN = Nyquist (10 MHz)
Rev. D | Page 11 of 40
AD9235
100
Data Sheet
SFDR
SINGLE-ENDED (dBFS)
95
SFDR
DIFFERENTIAL (dBFS)
90
SFDR
DIFFERENTIAL (dBc)
SFDR
SNR
DIFFERENTIAL (dBFS)
80
85
SNR/SFDR (dBc)
SNR/SFDR (dBFS and dBc)
90
70
SNR
SINGLE-ENDED (dBFS)
60
SFDR
SINGLE-ENDED (dBc)
SNR
SINGLE-ENDED (dBc)
50
80
75
SNR
70
–25
–10
–15
AIN (dBFS)
–20
–5
0
65
02461-015
40
–30
0
90
125
70
SNR
SINGLE-ENDED
(dBFS)
SFDR
SINGLE-ENDED (dBc)
SNR
DIFFERENTIAL (dBc)
SFDR
85
SNR/SFDR (dBc)
SNR/SFDR (dBFS and dBc)
SFDR
SINGLE-ENDED
(dBFS)
SFDR
DIFFERENTIAL
SNR
DIFFERENTIAL (dBc)
(dBFS)
60
100
95
SFDR
DIFFERENTIAL (dBFS)
90
80
50
75
INPUT FREQUENCY (MHz)
Figure 18. AD9235-65: SNR/SFDR vs. fIN
Figure 15. AD9235-65: Single Tone SNR/SFDR vs.
AIN with fIN = Nyquist (32.5 MHz)
100
25
02461-018
SNR
DIFFERENTIAL (dBc)
80
75
SNR
70
50
SNR
SINGLE-ENDED (dBc)
–15
AIN (dBFS)
–10
–5
0
65
0
25
50
75
INPUT FREQUENCY (MHz)
100
125
02461-019
–20
125
02461-020
–25
02461-016
40
–30
Figure 19. AD9235-40: SNR/SFDR vs. fIN
Figure 16. AD9235-40: Single Tone SNR/SFDR vs. AIN with fIN = Nyquist (20 MHz)
95
100
SFDR DIFFERENTIAL (dBFS)
SFDR
SINGLE-ENDED (dBFS)
80
SNR
DIFFERENTIAL (dBFS)
SFDR
DIFFERENTIAL (dBc)
90
SFDR
SFDR
SINGLE-ENDED(dBc)
85
SNR/SFDR (dBc)
SNR/SFDR (dBFS and dBc)
90
70
SNR
SINGLE-ENDED (dBFS)
60
SNR
DIFFERENTIAL(dBc)
75
SNR
70
50
SNR
SINGLE-ENDED (dBc)
–25
–20
–15
AIN (dBFS)
–10
–5
0
02461-017
40
–30
80
Figure 17. AD9235-20: Single Tone SNR/SFDR vs. AIN with fIN = Nyquist (10 MHz)
Rev. D | Page 12 of 40
65
0
25
50
75
INPUT FREQUENCY (MHz)
100
Figure 20. AD9235-20: SNR/SFDR vs. fIN
Data Sheet
AD9235
0
95
SNR = 64.6dBFS
SFDR = 81.6dBFS
2V SFDR
90
–20
1V SFDR
SNR/SFDR (dBFS)
MAGNITUDE (dBFS)
85
–40
–60
–80
80
75
2V SNR
70
1V SNR
–100
45.5
52.0
FREQUENCY (MHz)
58.5
65.0
60
–24
Figure 21. Dual Tone 8K FFT with fIN1 = 45 MHz and fIN2 = 46 MHz
–21
–18
–15
AIN (dBFS)
–12
–9
–6
02461-024
39.0
02461-021
–120
32.5
65
Figure 24. Dual Tone SNR/SFDR vs. AIN with fIN1 = 45 MHz and fIN2 = 46 MHz
95
0
SNR = 64.3dBFS
SFDR = 81.1dBFS
2V SFDR
90
–20
1V SFDR
–40
SNR/SFDR (dBFS)
MAGNITUDE (dBFS)
85
–60
–80
80
75
2V SNR
70
1V SNR
–100
78.0
84.5
FREQUENCY (MHz)
91.0
97.5
60
–24
Figure 22. Dual Tone 8K FFT with fIN1 = 69 MHz and fIN2 = 70 MHz
–21
–18
–15
AIN (dBFS)
–12
–9
–6
02461-025
71.5
02461-022
–120
65.0
65
Figure 25. Dual Tone SNR/SFDR vs. AIN with fIN1 = 69 MHz and fIN2 = 70 MHz
0
95
SNR = 62.5dBFS
SFDR = 75.6dBFS
90
–20
2V SFDR
1V SFDR
SNR/SFDR (dBFS)
–40
–60
–80
80
75
2V SNR
70
1V SNR
–100
136.5
143.0
149.5
FREQUENCY (MHz)
156.0
162.0
60
–24
Figure 23. Dual Tone 8K FFT with fIN1 = 144 MHz and fIN2 = 145 MHz
–21
–18
–15
AIN (dBFS)
–12
–9
–6
02461-026
–120
130.0
65
02461-023
MAGNITUDE (dBFS)
85
Figure 26. Dual Tone SNR/SFDR vs. AIN with fIN1 = 144 MHz and fIN2 = 145 MHz
Rev. D | Page 13 of 40
AD9235
Data Sheet
75
20
12.2
15
AD9235-65: 11.7
2V SINAD
AD9235-40:
1V SINAD
10.7
66
GAIN DRAFT (ppm/°C)
11.2
AD9235-20:
1V SINAD
10
ENOB (Bits)
69
SINAD (dBc)
AD9235-40:
2V SINAD
AD9235-20:
2V SINAD
72
AD9235-65:
1V SINAD
5
0
–5
–10
10.2
63
0
40
20
30
SAMPLE RATE (MSPS)
10
50
02461-027
9.7
60
60
–20
–40
Figure 27. SINAD vs. fCLK with fIN = Nyquist
–20
0
20
40
TEMPERATURE (°C)
60
80
02461-030
–15
Figure 30. A/D Gain vs. Temperature Using an External Reference
90
1.0
SFDR: DCS ON
0.8
80
0.6
SINAD: DCS ON
70
0.4
0.2
INL (LSB)
SINAD/SFDR (dBc)
SFDR: DCS OFF
SINAD: DCS OFF
60
50
0
–0.2
–0.4
–0.6
40
–0.8
50
55
DUTY CYCLE (%)
65
60
–1.0
0
500
1000
Figure 28. SINAD/SFDR vs. Clock Duty Cycle
2000 2500
CODE
3000
3500
4000
3500
4000
Figure 31. Typical INL
1.0
90
85
1500
02461-031
45
02461-032
40
02461-028
30
35
SFDR 2V DIFF
0.8
0.6
0.4
SFDR 1V DIFF
70
DNL (LSB)
75
SINAD 2V DIFF
65
60
0.2
0
–0.2
–0.4
SINAD 1V DIFF
–0.6
55
50
–40 –30 –20 –10
–0.8
0
10 20 30 40 50
SAMPLE RATE (MSPS)
60
70
80
02461-029
SINAD/SFDR (dBc)
80
Figure 29. SINAD/SFDR vs. Temperature with fIN = 32.5 MHz
–1.0
0
500
1000
1500 2000 2500
CODE
Figure 32. Typical DNL
Rev. D | Page 14 of 40
3000
Data Sheet
AD9235
APPLYING THE AD9235
ANALOG INPUT
The analog input to the AD9235 is a differential switched
capacitor SHA that has been designed for optimum performance while processing a differential input signal. The SHA
input can support a wide common-mode range and maintain
excellent performance, as shown in Figure 34. An input
common-mode voltage of midsupply minimizes signaldependent errors and provides optimum performance.
Referring to Figure 33, the clock signal alternatively switches
the SHA between sample mode and hold mode. When the SHA
is switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. Also, a small shunt capacitor can be
placed across the inputs to provide dynamic charging currents.
This passive network creates a low-pass filter at the ADC’s
input; therefore, the precise values are dependent upon the
application. In IF undersampling applications, any shunt
capacitors should be removed. In combination with the driving
source impedance, they would limit the input bandwidth.
T
T
5pF
VIN+
CPAR
T
5pF
VIN–
CPAR
T
H
Figure 33. Switched-Capacitor SHA Input
An internal differential reference buffer creates positive and
negative reference voltages, REFT and REFB, respectively, that
define the span of the ADC core. The output common mode of
the reference buffer is set to midsupply, and the REFT and
REFB voltages and span are defined as:
REFT = ½(AVDD + VREF)
REFB = ½(AVDD − VREF)
Span = 2 × (REFT − REFB) = 2 × VREF
It can be seen from the equations above that the REFT and
REFB voltages are symmetrical about the midsupply voltage
and, by definition, the input span is twice the value of the
VREF voltage.
90
–90
THD 2.5MHz 2V DIFF
85
–85
80
–80
THD 35MHz 2V DIFF
75
Rev. D | Page 15 of 40
–75
SNR 2.5MHz 2V DIFF
70
–70
SNR 35MHz 2V DIFF
65
–65
60
–60
55
–55
50
0
0.5
1.0
1.5
2.0
COMMON-MODE LEVEL (V)
2.5
–50
3.0
Figure 34. AD9235-65: SNR, THD vs. Common-Mode Level
THD (dBc)
The input stage contains a differential SHA that can be ac- or
dc-coupled in differential or single-ended modes. The outputstaging block aligns the data, carries out the error correction,
and passes the data to the output buffers. The output buffers are
powered from a separate supply, allowing adjustment of the
output voltage swing. During power-down, the output buffers
go into a high impedance state.
H
02461-034
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
For best dynamic performance, the source impedances driving
VIN+ and VIN– should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC.
02461-033
The AD9235 architecture consists of a front end SHA followed
by a pipelined switched capacitor ADC. The pipelined ADC is
divided into three sections, consisting of a 4-bit first stage
followed by eight 1.5-bit stages and a final 3-bit flash. Each stage
provides sufficient overlap to correct for flash errors in the
preceding stages. The quantized outputs from each stage are
combined into a final 12-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate
on a new input sample while the remaining stages operate on
preceding samples. Sampling occurs on the rising edge
of the clock.
SNR (dBc)
THEORY OF OPERATION
AD9235
Data Sheet
differential transformer coupling is the recommended input
configuration, as shown in Figure 36.
22Ω
15pF
2Vp-p
The SHA may be driven from a source that keeps the signal
peaks within the allowable range for the selected reference voltage. The minimum and maximum common-mode input levels
are defined as:
1kΩ
15pF
0.1µF
Although optimum performance is achieved with a differential
input, a single-ended source may be driven into VIN+ or VIN–.
In this configuration, one input accepts the signal, while the
opposite input should be set to midscale by connecting it to an
appropriate reference. For example, a 2 V p-p signal may be
applied to VIN+ while a 1 V reference is applied to VIN–. The
AD9235 then accepts an input signal varying between 2 V and
0 V. In the single-ended configuration, distortion performance
may degrade significantly as compared to the differential case.
However, the effect is less noticeable at lower input frequencies and
in the lower speed grade models (AD9235-40 and AD9235-20).
1kΩ
The signal characteristics must be considered when selecting a
transformer. Most RF transformers saturate at frequencies
below a few MHz, and excessive signal power can also cause
core saturation, which leads to distortion.
Single-Ended Input Configuration
A single-ended input may provide adequate performance in
cost-sensitive applications. In this configuration, there is degradation in SFDR and in distortion performance due to the large
input common-mode swing. However, if the source
impedances on each input are matched, there should be little
effect on SNR performance. Figure 37 details a typical singleended input configuration.
0.33µF
2Vp-p
As previously detailed, optimum performance is achieved while
driving the AD9235 in a differential input configuration. For
baseband applications, the AD8138 differential driver provides
excellent performance and a flexible interface to the ADC. The
output common-mode voltage of the AD8138 is easily set to
AVDD/2, and the driver can be configured in a Sallen-Key filter
topology to provide band limiting of the input signal.
49.9Ω
499Ω
22Ω
AVDD
VIN+
499Ω
15pF
AD8138
AD9235
523Ω
499Ω
15pF
VIN–
AGND
02461-035
22Ω
Figure 35. Differential Input Configuration Using the AD8138
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers is not adequate to achieve the
true performance of the AD9235. This is especially true in IF
undersampling applications where frequencies in the 70 MHz to
100 MHz range are being sampled. For these applications,
1kΩ
22Ω
AVDD
VIN+
Differential Input Configurations
1kΩ
VIN–
AGND
49.9Ω
10µF
0.1µF
1kΩ
15pF
1kΩ
22Ω
1kΩ
15pF
AD9235
VIN–
AGND
02461-037
The minimum common-mode input level allows the AD9235 to
accommodate ground-referenced inputs.
0.1µF
AD9235
Figure 36. Differential Transformer-Coupled Configuration
VCMMAX = (AVDD + VREF)/2
1kΩ
49.9Ω
22Ω
VCMMIN = VREF/2
1Vp-p
AVDD
VIN+
02461-036
The internal voltage reference can be pin-strapped to fixed
values of 0.5 V or 1.0 V, or adjusted within the same range as
discussed in the Internal Reference Connection section. Maximum SNR performance is achieved with the AD9235 set to the
largest input span of 2 V p-p. The relative SNR degradation is
3 dB when changing from 2 V p-p mode to 1 V p-p mode.
Figure 37. Single-Ended Input Configuration
CLOCK INPUT CONSIDERATIONS
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals, and as a result, may be sensitive to clock duty cycle. Commonly a 5% tolerance is required
on the clock duty cycle to maintain dynamic performance characteristics. The AD9235 contains a clock duty cycle stabilizer
(DCS) that retimes the nonsampling edge, providing an internal
clock signal with a nominal 50% duty cycle. This allows a wide
range of clock input duty cycles without affecting the performance of the AD9235. As shown in Figure 30, noise and distortion performance are nearly flat over a 30% range of duty cycle.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately 100 clock cycles to
allow the DLL to acquire and lock to the new rate.
Rev. D | Page 16 of 40
Data Sheet
AD9235
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given full-scale
input frequency (fINPUT) due only to aperture jitter (tJ) can be
calculated by
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9235. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other
methods), it should be retimed by the original clock at the last
step.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 38, the power dissipated by the AD9235 is
proportional to its sample rate. The digital power dissipation
does not vary substantially between the three speed grades
because it is determined primarily by the strength of the digital
drivers and the load on each output bit. The maximum DRVDD
current can be calculated as
IDRVDD = VDRVDD × CLOAD × fCLK × N
where N is the number of output bits, 12 in the case of the
AD9235. This maximum current occurs when every output bit
switches on every clock cycle, i.e., a full-scale square wave at the
Nyquist frequency, fCLK/2. In practice, the DRVDD current is
established by the average number of output bits switching,
which is determined by the encode rate and the characteristics
of the analog input signal.
AD9235-65
275
250
225
200
175
AD9235-40
150
125
100
75
AD9235-20
50
0
10
20
30
40
SAMPLE RATE (MSPS)
50
60
02461-038
In the equation, the rms aperture jitter, tJ, represents the rootsum square of all jitter sources, which include the clock input,
analog input signal, and ADC aperture jitter specification.
Undersampling applications are particularly sensitive to jitter.
300
TOTAL POWER (mW)
SNR Degradation = −20 × log10[2π × fINPUT × tJ]
325
Figure 38. Total Power vs. Sample Rate with fIN = 10 MHz
For the AD9235-20 speed grade, the digital power consumption
can represent as much as 10% of the total dissipation. Digital
power consumption can be minimized by reducing the capacitive load presented to the output drivers. The data in Figure 38
was taken with a 5 pF load on each output driver.
The analog circuitry is optimally biased so that each speed
grade provides excellent performance while affording reduced
power consumption. Each speed grade dissipates a baseline
power at low sample rates that increases linearly with the clock
frequency.
By asserting the PDWN pin high, the AD9235 is placed in
standby mode. In this state, the ADC typically dissipates 1 mW
if the CLK and analog inputs are static. During standby, the
output drivers are placed in a high impedance state. Reasserting
the PDWN pin low returns the AD9235 into its normal
operational mode.
Low power dissipation in standby mode is achieved by shutting
down the reference, reference buffer, and biasing networks. The
decoupling capacitors on REFT and REFB are discharged when
entering standby mode and then must be recharged when
returning to normal operation. As a result, the wake-up time is
related to the time spent in standby mode, and shorter standby
cycles result in proportionally shorter wake-up times. With the
recommended 0.1 µF and 10 µF decoupling capacitors on REFT
and REFB, it takes approximately 1 sec to fully discharge the
reference buffer decoupling capacitors and 3 ms to restore full
operation.
Rev. D | Page 17 of 40
AD9235
Data Sheet
Table 7. Reference Configuration Summary
SENSE Voltage
AVDD
VREF
0.2 V to VREF
AGND to 0.2 V
Internal Switch Position
N/A
SENSE
SENSE
Internal Divider
DIGITAL OUTPUTS
The AD9235 output drivers can be configured to interface with
2.5 V or 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fan-outs may require external buffers or latches.
Resulting VREF (V)
N/A
0.5
0.5 × (1 + R2/R1)
1.0
SENSE pin. This puts the reference amplifier in a noninverting
mode with the VREF output defined as
VREF = 0.5 × (1 + R2/R1)
VIN+
VIN–
0.1µF
0.1µF
VREF
The AD9235 provides latched data outputs with a pipeline delay
of seven clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. Refer to
Figure 2 for a detailed timing diagram.
The lowest typical conversion rate of the AD9235 is 1 MSPS. At
clock rates below 1 MSPS, dynamic performance may degrade.
VOLTAGE REFERENCE
+
10µF
0.1µF
REFB
10µF
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9235;
these transients can detract from the converter’s dynamic
performance.
REFT
ADC
CORE
As detailed in Table 8, the data format can be selected for either
offset binary or twos complement.
Timing
Resulting Differential Span (V p-p)
2 × External Reference
1.0
2 × VREF (See Figure 40)
2.0
+
0.1µF
0.5V
SELECT
LOGIC
SENSE
02461-039
Selected Mode
External Reference
Internal Fixed Reference
Programmable Reference
Internal Fixed Reference
AD9235
Figure 39. Internal Reference Configuration
In all reference configurations, REFT and REFB drive the A/D
conversion core and establish its input span. The input range of
the ADC always equals twice the voltage at the reference pin for
either an internal or an external reference.
A stable and accurate 0.5 V voltage reference is built into the
AD9235. The input range can be adjusted by varying the reference voltage applied to the AD9235, using either the internal
reference or an externally applied reference voltage. The input
span of the ADC tracks reference voltage changes linearly.
VIN+
VIN–
REFT
0.1µF
ADC
CORE
0.1µF
+
10µF
REFB
0.1µF
VREF
10µF
Internal Reference Connection
+
0.1µF
R2
A comparator within the AD9235 detects the potential at the
SENSE pin and configures the reference into one of four possible states, which are summarized in Table 7. If SENSE is
grounded, the reference amplifier switch is connected to the
internal resistor divider (see Figure 39), setting VREF to 1 V.
Connecting the SENSE pin to VREF switches the reference
amplifier output to the SENSE pin, completing the loop and
providing a 0.5 V reference output. If a resistor divider is
connected as shown in Figure 40, the switch is again set to the
Rev. D | Page 18 of 40
0.5V
SELECT
LOGIC
SENSE
R1
AD9235
Figure 40. Programmable Reference Configuration
02461-040
If the ADC is being driven differentially through a transformer,
the reference voltage can be used to bias the center tap
(common-mode voltage).
Data Sheet
AD9235
External Reference Operation
OPERATIONAL MODE SELECTION
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or to improve thermal drift
characteristics. When multiple ADCs track one another, a single
reference (internal or external) may be necessary to reduce gain
matching errors to an acceptable level. A high precision external
reference may also be selected to provide lower gain and offset
temperature drift. Figure 41 shows the typical drift characteristics of the internal reference in both 1 V and 0.5 V modes.
As discussed earlier, the AD9235 can output data in either offset
binary or twos complement format. There is also a provision for
enabling or disabling the clock DCS. The MODE pin is a multilevel input that controls the data format and DCS state. The
input threshold values and corresponding mode selections are
outlined in Table 8.
1.2
1.0
VREF ERROR (%)
VREF = 1.0V
0.8
MODE Voltage
AVDD
2/3 AVDD
1/3 AVDD
AGND (Default)
Data Format
Twos Complement
Twos Complement
Offset Binary
Offset Binary
Duty Cycle Stabilizer
Disabled
Enabled
Enabled
Disabled
The MODE pin is internally pulled down to AGND by a 20 kΩ
resistor.
VREF = 0.5V
0.6
TSSOP EVALUATION BOARD
0.4
0
–40 –30 –20 –10
0
10 20 30 40 50
TEMPERATURE (°C)
60
70
02461-041
0.2
80
Figure 41. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7 kΩ load. The internal buffer still generates the positive and
negative full-scale references, REFT and REFB, for the ADC
core. The input span is always twice the value of the reference
voltage; therefore, the external reference must be limited to a
maximum of 1 V.
If the internal reference of the AD9235 is used to drive multiple
converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 42
depicts how the internal reference voltage is affected by loading.
0.05
0
–0.05
0.5V ERROR (%)
–0.10
1V ERROR (%)
–0.20
–0.25
0.5
1.0
1.5
LOAD (mA)
The AUXCLK input should be selected in applications requiring
the lowest jitter and SNR performance, i.e., IF undersampling
characterization. It allows the user to apply a clock input signal
that is 4× the target sample rate of the AD9235. A low-jitter,
differential divide-by-4 counter, the MC100LVEL33D, provides
a 1× clock output that is subsequently returned back to the CLK
input via JP9. For example, a 260 MHz signal (sinusoid) is
divided down to a 65 MHz signal for clocking the ADC. Note
that R1 must be removed with the AUXCLK interface. Lower
jitter is often achieved with this interface since many RF signal
generators display improved phase noise at higher output
frequencies and the slew rate of the sinusoidal output signal is
4× that of a 1× signal of equal amplitude.
Complete schematics and layout plots follow and demonstrate
the proper routing and grounding techniques that should be
applied at the system level.
–0.15
0
The AD9235 evaluation board provides the support circuitry
required to operate the ADC in its various modes and configurations. The converter can be driven differentially, through an
AD8138 driver or a transformer, or single-ended. Separate power pins are provided to isolate the DUT from the support circuitry. Each input configuration can be selected by proper connection of various jumpers (refer to the schematics). Figure 43
shows the typical bench characterization setup used to evaluate
the ac performance of the AD9235. It is critical that signal
sources with very low phase noise (
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