APPLICATIONS
Medical ultrasound
High speed imaging
Quadrature radio receivers
Diversity radio receivers
Test equipment
GENERAL DESCRIPTION
The AD9253-EP is a quad, 14-bit, 125 MSPS analog-to-digital
converter (ADC) with an on-chip, sample-and-hold circuit
designed for low cost, low power, small size, and ease of use.
The product operates at a conversion rate of up to 125 MSPS
and is optimized for outstanding dynamic performance and
low power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are required
for many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for
capturing data on the output and a frame clock output (FCO)
for signaling a new output byte are provided. Individual channel
power-down is supported and typically consumes less than 2 mW
when all channels are disabled. The ADC contains several features
FUNCTIONAL BLOCK DIAGRAM
AVDD
PDWN
DRVDD
14
VIN+A
VIN–A
14
VIN+B
DIGITAL
SERIALIZER
PIPELINE
ADC
VIN–B
RBIAS
VREF
SERIAL
LVDS
D0+A
D0–A
D1+A
D1–A
SERIAL
LVDS
D0+B
D0–B
SERIAL
LVDS
SERIAL
LVDS
D1+B
D1–B
FCO+
FCO–
D0+C
D0–C
D1+C
D1–C
SERIAL
LVDS
D0+D
D0–D
SERIAL
LVDS
D1+D
D1–D
DCO+
DCO–
SERIAL
LVDS
DIGITAL
SERIALIZER
PIPELINE
ADC
SENSE
1V
REF
SELECT
AD9253-EP
SERIAL
LVDS
AGND
14
VIN+C
VIN–C
PIPELINE
ADC
VIN+D
VIN–D
PIPELINE
ADC
DIGITAL
SERIALIZER
14
DIGITAL
SERIALIZER
CLK–
CLK+
CLOCK
MANAGEMENT
SYNC
SERIAL PORT
INTERFACE
SCLK/DTP
VCM
CSB
1.8 V supply operation
Military temperature range (−55°C to +125°C)
Controlled manufacturing baseline
Qualification data available on request
Low power: 110 mW per channel at 125 MSPS
SNR = 74 dB (to Nyquist)
SFDR = 90 dBc (to Nyquist)
DNL = ±0.8 LSB (typical); INL = ±2.0 LSB (typical)
Serial LVDS (ANSI-644, default) and low power, reduced signal
option (similar to IEEE 1596.3)
650 MHz full power analog bandwidth
2 V p-p input voltage range
Serial port control
Full chip and individual channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Multichip sync and clock divider
Programmable output clock and data alignment
Programmable output resolution
Standby mode
10065-001
FEATURES
SDIO/OLM
Preliminary Technical Data
Quad, 14-Bit, 125 MSPS Serial LVDS 1.8 V
Analog-to-Digital Converter
AD9253-EP
Figure 1.
designed to maximize flexibility and minimize system cost, such as
programmable output clock and data alignment and digital test
pattern generation. The available digital test patterns include
built-in deterministic and pseudorandom patterns, along with
custom user-defined test patterns entered via the serial port
interface (SPI).
The AD9253-EP is available in a RoHS-compliant, 48-lead LFCSP
and is specified over an extended temperature range of −55°C to
+125°C. This product is protected by a U.S. patent. Additional
application and technical information can be found in the AD9253
data sheet.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
Small Footprint. Four ADCs are contained in a small, spacesaving package.
Low power of 110 mW/channel at 125 MSPS with scalable
power options.
Ease of Use. A DCO operates at frequencies of up to 500 MHz
and supports double data rate (DDR) operation.
User Flexibility. The SPI control offers a wide range of
flexible features to meet specific system requirements.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.
AD9253-EP
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Digital Specifications ....................................................................5
Applications ....................................................................................... 1
Switching Specifications ...............................................................6
General Description ......................................................................... 1
Absolute Maximum Ratings ............................................................7
Functional Block Diagram .............................................................. 1
Thermal Resistance .......................................................................7
Product Highlights ........................................................................... 1
ESD Caution...................................................................................7
Revision History ............................................................................... 2
Pin Configuration and Function Descriptions..............................8
Specifications..................................................................................... 3
Outline Dimensions ....................................................................... 10
DC Specifications ......................................................................... 3
Ordering Guide .......................................................................... 10
AC Specifications.......................................................................... 4
REVISION HISTORY
10/12—PrA: Initial Version
Rev. PrA | Page 2 of 12
Preliminary Technical Data
AD9253-EP
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 1.
Parameter1
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Offset Matching
Gain Error
Gain Matching
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
INTERNAL VOLTAGE REFERENCE
Output Voltage (1 V Mode)
Load Regulation at 1.0 mA (VREF = 1 V)
Input Resistance
INPUT-REFERRED NOISE
VREF = 1.0 V
ANALOG INPUTS
Differential Input Voltage (VREF = 1 V)
Common-Mode Voltage
Differential Input Resistance
Differential Input Capacitance
POWER SUPPLY
AVDD
DRVDD
IAVDD2
IDRVDD (ANSI-644 Mode)2
IDRVDD (Reduced Range Mode)2
TOTAL POWER CONSUMPTION
DC Input
Sine Wave Input (Four Channels Including Output Drivers ANSI-644 Mode)
Sine Wave Input (Four Channels Including Output Drivers Reduced Range Mode)
Power-Down Mode
Standby Mode3
1
Temp
Min
14
Full
Full
Full
Full
Full
Full
25°C
Guaranteed
−0.3
+0.1
+0.2
+0.6
−3
+2
1.1
1.6
−0.8
+1.9
±0.8
Full
25°C
−4.5
Max
−0.8
−0.6
−12
Full
Full
Full
Full
Typ
0.98
+4.5
Rev. PrA | Page 3 of 12
% FSR
% FSR
% FSR
% FSR
LSB
LSB
±2.0
LSB
LSB
±2
ppm/°C
1.0
2
7.5
1.02
V
mV
kΩ
25°C
0.94
LSB rms
Full
Full
2
0.9
5.2
3.5
V p-p
V
kΩ
pF
Full
Full
Full
Full
Full
25°C
Full
Full
25°C
Full
Full
1.7
1.7
1.8
1.8
183
61
53
403
440
425
2
235
1.9
1.9
205
63
480
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
Measured with a low input frequency, full-scale sine wave on all four channels.
3
It can be controlled via the SPI.
2
Unit
Bits
V
V
mA
mA
mA
mW
mW
mW
mW
mW
AD9253-EP
Preliminary Technical Data
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 2.
Parameter1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
WORST HARMONIC (SECOND OR THIRD)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
WORST OTHER HARMONIC (EXCLUDING SECOND OR THIRD)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 200 MHz
TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND AIN2 = −7.0 dBFS
fIN1 = 70.5 MHz, fIN2 = 72.5 MHz
CROSSTALK2
CROSSTALK (OVERRANGE CONDITION)3
POWER SUPPLY REJECTION RATIO (PSRR)4
AVDD
DRVDD
ANALOG INPUT BANDWIDTH, FULL POWER
1
Temp
Min
Typ
72
75.3
75.2
74.1
72.2
70.7
dBFS
dBFS
dBFS
dBFS
dBFS
71.7
75.2
75.1
74.0
71.9
70.4
dBFS
dBFS
dBFS
dBFS
dBFS
25°C
25°C
Full
25°C
25°C
12.2
12.2
12.0
11.7
11.4
Bits
Bits
Bits
Bits
Bits
25°C
25°C
Full
25°C
25°C
98
92
90
85
83
dBc
dBc
dBc
dBc
dBc
25°C
25°C
Full
25°C
25°C
−98
−92
−90
−85
−83
−76
dBc
dBc
dBc
dBc
dBc
25°C
25°C
Full
25°C
25°C
−101
−100
−95
−96
−92
−83
dBFS
dBFS
dBFS
dBFS
dBFS
25°C
Full
25°C
86
−95
−89
dBc
dB
dB
25°C
25°C
25°C
48
75
650
dB
dB
MHz
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
76
Max
Unit
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
Crosstalk is measured at 70 MHz with an −1.0 dBFS analog input on one channel and no input on the adjacent channel.
3
The overrange condition is specified with 3 dB of the full-scale input range.
4
PSRR is measured by injecting a sinusoidal signal at 10 MHz to the power supply pin and measuring the output spur on the FFT. PSRR is calculated as the ratio of the
amplitudes of the spur voltage over the pin voltage, expressed in decibels.
2
Rev. PrA | Page 4 of 12
Preliminary Technical Data
AD9253-EP
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 3.
Parameter1
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage2
Input Voltage Range
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
LOGIC INPUTS (PDWN, SYNC, SCLK)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (CSB)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (SDIO/OLM)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC OUTPUT (SDIO/OLM)3
Logic 1 Voltage (IOH = 800 μA)
Logic 0 Voltage (IOL = 50 μA)
DIGITAL OUTPUTS (D0±x, D1±x), ANSI-644
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
DIGITAL OUTPUTS (D0±x, D1±x), LOW POWER, REDUCED SIGNAL OPTION
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
1
Temp
Min
Full
Full
Full
25°C
25°C
CMOS/LVDS/LVPECL
0.2
3.6
AGND − 0.2
AVDD + 0.2
0.9
15
4
Full
Full
25°C
25°C
1.2
0
Full
Full
25°C
25°C
1.2
0
Full
Full
25°C
25°C
1.2
0
Typ
Max
V
V
kΩ
pF
AVDD + 0.2
0.8
V
V
kΩ
pF
AVDD + 0.2
0.8
V
V
kΩ
pF
26
2
26
5
1.79
0.05
Rev. PrA | Page 5 of 12
V
V
Full
Full
290
1.15
LVDS
345
400
1.25
1.35
Twos complement
mV
V
Full
Full
160
1.15
LVDS
200
230
1.25
1.35
Twos complement
mV
V
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
This is specified for LVDS and LVPECL only.
3
This is specified for 13 SDIO/OLM pins sharing the same connection.
2
V p-p
V
V
kΩ
pF
AVDD + 0.2
0.8
30
2
Full
Full
Unit
AD9253-EP
Preliminary Technical Data
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.
Table 4.
Parameter1, 2
CLOCK3
Input Clock Rate
Conversion Rate
Clock Pulse Width High (tEH)
Clock Pulse Width Low (tEL)
OUTPUT PARAMETERS3
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
FCO Propagation Delay (tFCO)
DCO Propagation Delay (tCPD)4
DCO-to-Data Delay (tDATA)4
DCO-to-FCO Delay (tFRAME)4
Lane Delay (tLD)
Data to Data Skew (tDATA-MAX − tDATA-MIN)
Wake-Up Time (Standby)
Wake-Up Time (Power-Down)5
Pipeline Latency
APERTURE
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Out-of-Range Recovery Time
Temp
Min
Full
Full
Full
Full
10
10
Max
Unit
1000
125
4.00
4.00
MHz
MSPS
ns
ns
Full
25°C
25°C
Full
2.3
300
300
2.3
tFCO + (tSAMPLE/16)
(tSAMPLE/16)
(tSAMPLE/16)
90
±50
250
375
16
ns
ps
ps
ns
ns
ps
ps
ps
ps
ns
μs
Clock cycles
25°C
25°C
25°C
1
135
1
Full
Full
Full
Full
Full
Full
Full
1.5
(tSAMPLE/16) − 300
(tSAMPLE/16) − 300
1
Typ
3.1
(tSAMPLE/16) + 300
(tSAMPLE/16) + 300
±200
ns
fs rms
Clock cycles
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
Measured on standard FR-4 material.
3
Can be adjusted via the SPI. The conversion rate is the clock rate after the divider.
4
tSAMPLE/16 is based on the number of bits in two LVDS data lanes. tSAMPLE = 1/fS.
5
Wake-up time is defined as the time required to return to normal operation from power-down mode.
2
Rev. PrA | Page 6 of 12
Preliminary Technical Data
AD9253-EP
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 5.
Parameter
Electrical
AVDD to AGND
DRVDD to AGND
Digital Outputs (D0±x, D1±x, DCO+,
DCO−, FCO+, FCO−) to AGND
CLK+, CLK− to AGND
VIN+x, VIN−x to AGND
SCLK/DTP, SDIO/OLM, CSB to AGND
SYNC, PDWN to AGND
RBIAS to AGND
VREF, SENSE to AGND
Environmental
Operating Temperature Range (Ambient)
Maximum Junction Temperature
Lead Temperature (Soldering, 10 sec)
Storage Temperature Range (Ambient)
Rating
Table 6.
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
Package
Type
48-Lead
LFCSP
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
Air Flow
Velocity
(m/sec)
0.0
1.0
2.5
1
θJC
θJA1
20.3
17.6
16.5
ΨJT
0.10
0.16
0.20
ΨJB
5.9
N/A2
N/A2
θJC
TOP
BOTTOM
6.1
N/A2
N/A2
1.0
N/A2
N/A2
Unit
°C/W
°C/W
°C/W
θJA for a 4-layer printed circuit board (PCB) with solid ground plane (simulated).
Exposed pad soldered to PCB.
2
N/A = not applicable.
ESD CAUTION
−55°C to +125°C
150°C
300°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. PrA | Page 7 of 12
AD9253-EP
Preliminary Technical Data
48
47
46
45
44
43
42
41
40
39
38
37
VIN+C
VIN–C
AVDD
AVDD
SYNC
VCM
VREF
SENSE
RBIAS
AVDD
VIN–B
VIN+B
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD9253-EP
TOP VIEW
(Not to Scale)
36
35
34
33
32
31
30
29
28
27
26
25
VIN+A
VIN–A
AVDD
PDWN
CSB
SDIO/OLM
SCLK/DTP
DRVDD
D0+A
D0–A
D1+A
D1–A
NOTES
1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE
PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART.
THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR
PROPER OPERATION.
10065-007
D1–C
D1+C
D0–C
D0+C
DCO–
DCO+
FCO–
FCO+
D1–B
D1+B
D0–B
D0+B
13
14
15
16
17
18
19
20
21
22
23
24
VIN+D 1
VIN–D 2
AVDD 3
AVDD 4
CLK– 5
CLK+ 6
AVDD 7
DRVDD 8
D1–D 9
D1+D 10
D0–D 11
D0+D 12
Figure 2. Pin Configuration, Top View
Table 7. Pin Function Descriptions
Pin No.
0
1
2
3, 4, 7, 34, 39, 45, 46
5, 6
8, 29
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Mnemonic
AGND,
Exposed Pad
VIN+D
VIN−D
AVDD
CLK−, CLK+
DRVDD
D1−D
D1+D
D0−D
D0+D
D1−C
D1+C
D0−C
D0+C
DCO−
DCO+
FCO−
FCO+
D1−B
D1+B
D0−B
D0+B
D1−A
D1+A
D0−A
D0+A
Description
Analog Ground, Exposed Pad. The exposed thermal pad on the bottom of the package provides the
analog ground for the part. This exposed pad must be connected to ground for proper operation.
ADC D Analog Input True.
ADC D Analog Input Complement.
1.8 V Analog Supply Pins.
Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs.
Digital Output Driver Supply.
Channel D Digital Output 1 Complement.
Channel D Digital Output 1 True.
Channel D Digital Output 0 Complement.
Channel D Digital Output 0 True.
Channel C Digital Output 1 Complement.
Channel C Digital Output 1 True.
Channel C Digital Output 0 Complement.
Channel C Digital Output 0 True.
Data Clock Output Complement.
Data Clock Output True.
Frame Clock Output Complement.
Frame Clock Output True.
Channel B Digital Output 1 Complement.
Channel B Digital Output 1 True.
Channel B Digital Output 0 Complement.
Channel B Digital Output 0 True.
Channel A Digital Output 1 Complement.
Channel A Digital Output 1 True.
Channel A Digital Output 0 Complement.
Channel A Digital Output 0 True.
Rev. PrA | Page 8 of 12
Preliminary Technical Data
Pin No.
30
31
32
33
Mnemonic
SCLK/DTP
SDIO/OLM
CSB
PDWN
35
36
37
38
40
41
42
43
44
47
48
VIN−A
VIN+A
VIN+B
VIN−B
RBIAS
SENSE
VREF
VCM
SYNC
VIN−C
VIN+C
AD9253-EP
Description
SPI Clock Input/Digital Test Pattern.
SPI Data Input and Output Bidirectional SPI Data/Output Lane Mode.
SPI Chip Select Bar. Active low enable; 30 kΩ internal pull-up.
Digital Input, 30 kΩ Internal Pull-Down.
PDWN high = power-down device.
PDWN low = run device, normal operation.
ADC A Analog Input Complement.
ADC A Analog Input True.
ADC B Analog Input True.
ADC B Analog Input Complement.
Sets Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground.
Reference Mode Selection.
Voltage Reference Input and Output.
Analog Input Common-Mode Voltage.
Digital Input. SYNC input to clock divider.
ADC C Analog Input Complement.
ADC C Analog Input True.
Rev. PrA | Page 9 of 12
AD9253-EP
Preliminary Technical Data
OUTLINE DIMENSIONS
0.30
0.23
0.18
PIN 1
INDICATOR
37
36
48
1
0.50
BSC
TOP VIEW
0.80
0.75
0.70
0.45
0.40
0.35
EXPOSED
PAD
24
SEATING
PLANE
5.65
5.60 SQ
5.55
13
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
PIN 1
INDICATOR
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WKKD.
02-14-2011-B
7.10
7.00 SQ
6.90
Figure 3. 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
7 mm × 7 mm Body, Very Very Thin Quad
(CP-48-13)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD9253-TCPZ-125EP
AD9253-TCPZR7-125EP
1
Temperature Range
−55°C to +125°C
−55°C to +125°C
Package Description
48-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
48-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Z = RoHS Compliant Part.
Rev. PrA | Page 10 of 12
Package Option
CP-48-13
CP-48-13
Preliminary Technical Data
AD9253-EP
NOTES
Rev. PrA | Page 11 of 12
AD9253-EP
Preliminary Technical Data
NOTES
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11074-0-11/12(0)
Rev. PrA | Page 12 of 12
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