Quad, 14-Bit, 50 MSPS
Serial LVDS 1.8 V ADC
AD9259
Data Sheet
4 ADCs integrated into 1 package
98 mW ADC power per channel at 50 MSPS
SNR = 73 dB (to Nyquist)
ENOB = 12 bits
SFDR = 84 dBc (to Nyquist)
Excellent linearity
DNL = ±0.5 LSB (typical)
INL = ±1.5 LSB (typical)
Serial LVDS (ANSI-644, default)
Low power, reduced signal option (similar to IEEE 1596.3)
Data and frame clock outputs
315 MHz full-power analog bandwidth
2 V p-p input voltage range
1.8 V supply operation
Serial port control
Full-chip and individual-channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Programmable output resolution
Standby mode
APPLICATIONS
Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam-forming systems
Quadrature radio receivers
Diversity radio receivers
Tape drives
Optical networking
Test equipment
GENERAL DESCRIPTION
The AD9259 is a quad, 14-bit, 50 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed
for low cost, low power, small size, and ease of use. The product
operates at a conversion rate of up to 50 MSPS and is optimized for
outstanding dynamic performance and low power in applications
where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
FUNCTIONAL BLOCK DIAGRAM
AVDD
PDWN
DRVDD
AD9259
14
VIN + A
VIN – A
T/H
PIPELINE
ADC
VIN + B
VIN – B
T/H
PIPELINE
ADC
VIN + C
VIN – C
T/H
PIPELINE
ADC
VIN + D
VIN – D
T/H
PIPELINE
ADC
SERIAL
LVDS
D+A
D–A
SERIAL
LVDS
D+B
D–B
SERIAL
LVDS
D+C
D–C
SERIAL
LVDS
D+D
D–D
14
14
14
VREF
SENSE
REFT
REFB
DRGND
+
–
REF
SELECT
FCO+
0.5V
SERIAL PORT
INTERFACE
DATA RATE
MULTIPLIER
RBIAS AGND CSB SDIO/ODM SCLK/DTP CLK+ CLK–
FCO–
DCO+
DCO–
05965-001
FEATURES
Figure 1.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock output (DCO) for
capturing data on the output and a frame clock output (FCO)
for signaling a new output byte are provided. Individual-channel
power-down is supported and typically consumes less than 2 mW
when all channels are disabled.
The ADC contains several features designed to maximize flexibility
and minimize system cost, such as programmable clock and data
alignment and programmable digital test pattern generation. The
available digital test patterns include built-in deterministic and
pseudorandom patterns, along with custom user-defined test
patterns entered via the serial port interface (SPI).
The AD9259 is available in a RoHS-compliant, 48-lead LFCSP. It is
specified over the industrial temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
Small Footprint. Four ADCs are contained in a small, spacesaving package.
Low power of 98 mW/channel at 50 MSPS.
Ease of Use. A data clock output (DCO) operates at
frequencies of up to 350 MHz and supports double data
rate (DDR) operation.
User Flexibility. The SPI control offers a wide range of flexible
features to meet specific system requirements.
Pin-Compatible Family. This includes the AD9287 (8-bit),
AD9219 (10-bit), and AD9228 (12-bit).
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice.
No license is granted by implication or otherwise under any patent or patent rights of Analog
Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2020 Analog Devices, Inc. All rights reserved.
AD9259
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Analog Input Considerations ................................................... 19
Applications ...................................................................................... 1
Clock Input Considerations ..................................................... 21
General Description ......................................................................... 1
Serial Port Interface (SPI) ............................................................. 29
Functional Block Diagram .............................................................. 1
Hardware Interface .................................................................... 29
Product Highlights ........................................................................... 1
Memory Map .................................................................................. 31
Revision History ............................................................................... 3
Reading the Memory Map Table ............................................. 31
Specifications .................................................................................... 4
Reserved Locations .................................................................... 31
AC Specifications ......................................................................... 5
Default Values ............................................................................ 31
Digital Specifications ................................................................... 6
Logic Levels ................................................................................. 31
Switching Specifications .............................................................. 7
Evaluation Board ............................................................................ 35
Timing Diagrams ......................................................................... 8
Power Supplies ........................................................................... 35
Absolute Maximum Ratings ......................................................... 10
Input Signals ............................................................................... 35
Thermal Impedance ................................................................... 10
Output Signals ............................................................................ 35
ESD Caution................................................................................ 10
Default Operation and Jumper Selection Settings ................ 36
Pin Configuration and Function Descriptions .......................... 11
Alternative Analog Input Drive Configuration ..................... 37
Equivalent Circuits ......................................................................... 13
Outline Dimensions ....................................................................... 51
Typical Performance Characteristics ........................................... 15
Ordering Guide .......................................................................... 51
Theory of Operation ...................................................................... 19
Rev. F | Page 2 of 52
Data Sheet
AD9259
REVISION HISTORY
11/2020—Rev. E to Rev. F
Changed CP-48-8 to CP-48-9 ..................................... Throughout
Changes to Figure 5 ........................................................................11
Updated Outline Dimensions .......................................................51
Changes to Ordering Guide...........................................................51
12/2011—Rev. D to Rev. E
Changes to Output Signals Section and Figure 60 .....................35
Change to Default Operation and Jumper Selection Settings
Section...............................................................................................36
Change to Figure 63 ........................................................................39
Added Endnote 2 in Ordering Guide ...........................................51
4/2010—Rev. C to Rev. D
Changes to Table 16 ........................................................................33
Updated Outline Dimensions .......................................................51
Changes to Ordering Guide...........................................................51
11/2009—Rev. B to Rev. C
Added EPAD Note to Figure 5......................................................11
Changes to Input Signals Section and Figure 60 ........................35
Updated Outline Dimensions .......................................................51
Changes to Ordering Guide...........................................................51
7/2007—Rev. A to Rev. B
Change to General Description....................................................... 1
Changes to Figure 2 and Figure 4 ................................................... 7
Changes to the Hardware Interface Section ................................29
Changes to Table 17 ........................................................................48
5/2007—Rev. 0 to Rev. A
Changes to Effective Number of Bits (ENOB) .................................... 4
Changes to Logic Output (SDIO/ODM) .............................................. 5
Added Endnote 3 to Table 3 .................................................................... 5
Change to Pipeline Latency ..................................................................... 6
Changes to Figure 2 to Figure 4 .............................................................. 7
Changes to Figure 10............................................................................... 12
Changes to Figure 15 to Figure 17, Figure 22, and Figure 31 ......... 14
Changes to Figure 21 and Figure 22 Captions ................................... 15
Changes to Figure 41............................................................................... 19
Changes to Clock Duty Cycle Considerations Section .................... 20
Changes to Power Dissipation and Power-Down Mode Section .. 21
Changes to Figure 50 to Figure 52 Captions ...................................... 23
Change to Table 8 .................................................................................... 23
Changes to Table 9 Endnote.................................................................. 24
Changes to Digital Outputs and Timing Section .............................. 25
Added Table 10 ........................................................................................ 25
Changes to RBIAS Pin Section.............................................................. 26
Deleted Figure 53 and Figure 54 ........................................................... 26
Changes to Figure 56............................................................................... 27
Changes to Hardware Interface Section.............................................. 28
Added Figure 57....................................................................................... 29
Changes to Table 15 ................................................................................ 29
Changes to Reading the Memory Map Table Section...................... 30
Change to Output Signals Section ........................................................ 34
Changes to Figure 60............................................................................... 34
Changes to Default Operation and
Jumper Selection Settings Section ................................................... 35
Changes to Alternative Analog Input Drive
Configuration Section........................................................................ 36
Changes to Figure 63............................................................................... 38
Changes to Table 17 ................................................................................ 46
Changes to Ordering Guide .................................................................. 50
6/2006—Revision 0: Initial Version
Rev. F | Page 3 of 52
AD9259
Data Sheet
SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 1.
Parameter1
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Offset Matching
Gain Error
Gain Matching
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
Reference Voltage (1 V Mode)
REFERENCE
Output Voltage Error (VREF = 1 V)
Load Regulation at 1.0 mA (VREF = 1 V)
Input Resistance
ANALOG INPUTS
Differential Input Voltage (VREF = 1 V)
Common-Mode Voltage
Differential Input Capacitance
Analog Bandwidth, Full Power
POWER SUPPLY
AVDD
DRVDD
IAVDD
IDRVDD
Total Power Dissipation (Including Output Drivers)
Power-Down Dissipation
Standby Dissipation2
CROSSTALK
CROSSTALK (Overrange Condition)3
Temperature
Typ
Max
Unit
Bits
Full
Full
Full
Full
Full
Full
Full
Guaranteed
±1
±2
±0.5
±0.3
±0.5
±1.5
±8
±8
±2
±0.7
±1.0
±3.5
mV
mV
% FS
% FS
LSB
LSB
Full
Full
Full
±2
±17
±21
Full
Full
Full
±5
3
6
Full
Full
Full
Full
2
AVDD/2
7
315
Full
Full
Full
Full
Full
Full
Full
Full
Full
1
Min
14
1.7
1.7
1.8
1.8
185
32.5
392
2
72
−100
−100
ppm/°C
ppm/°C
ppm/°C
±30
mV
mV
kΩ
V p-p
V
pF
MHz
1.9
1.9
192.5
34.7
409
4
V
V
mA
mA
mW
mW
mW
dB
dB
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, at www.analog.com for definitions and for details on how these tests were
completed.
2
Can be controlled via the SPI.
3
Overrange condition is specific with 6 dB of the full-scale input range.
Rev. F | Page 4 of 52
Data Sheet
AD9259
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 2.
Parameter1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 70 MHz
SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 70 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 70 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 70 MHz
WORST HARMONIC (Second or Third)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 70 MHz
WORST OTHER (Excluding Second or Third)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 70 MHz
TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1
AND AIN2 = −7.0 dBFS
fIN1 = 15 MHz, fIN2 = 16 MHz
fIN1 = 70 MHz, fIN2 = 71 MHz
1
Temperature
Min
Typ
Max
Unit
Full
Full
Full
71.0
73.5
73.0
72.8
dB
dB
dB
Full
Full
Full
70.2
72.7
72.2
72.0
dB
dB
dB
Full
Full
Full
11.5
11.92
11.85
11.8
Bits
Bits
Bits
Full
Full
Full
73
84
84
78
dBc
dBc
dBc
Full
Full
Full
−88
−84
−78
−73
dBc
dBc
dBc
Full
Full
Full
−90
−90
−88
−80
dBc
dBc
dBc
25°C
25°C
80.0
80.0
dBc
dBc
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, at www.analog.com for definitions and for details on how these tests were
completed.
Rev. F | Page 5 of 52
AD9259
Data Sheet
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 3.
Parameter1
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage2
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
LOGIC INPUTS (PDWN, SCLK/DTP)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (CSB)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (SDIO/ODM)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC OUTPUT (SDIO/ODM)3
Logic 1 Voltage (IOH = 800 μA)
Logic 0 Voltage (IOL = 50 μA)
DIGITAL OUTPUTS (D + x, D − x), (ANSI-644)
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
DIGITAL OUTPUTS (D + x, D − x),
(Low Power, Reduced Signal Option)
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
Temperature
Min
Full
Full
25°C
25°C
250
Full
Full
25°C
25°C
1.2
Full
Full
25°C
25°C
1.2
Full
Full
25°C
25°C
1.2
0
Typ
Max
Unit
CMOS/LVDS/LVPECL
mV p-p
V
kΩ
pF
1.2
20
1.5
3.6
0.3
V
V
kΩ
pF
3.6
0.3
V
V
kΩ
pF
DRVDD + 0.3
0.3
V
V
kΩ
pF
30
0.5
70
0.5
30
2
Full
Full
1.79
0.05
V
V
454
1.375
mV
V
250
1.30
mV
V
LVDS
Full
Full
247
1.125
Offset binary
LVDS
Full
Full
150
1.10
Offset binary
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, at www.analog.com for definitions and for details on how these tests were
completed.
2
This is specified for LVDS and LVPECL only.
3
This is specified for 13 SDIO pins sharing the same connection.
Rev. F | Page 6 of 52
Data Sheet
AD9259
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 4.
Parameter1, 2
CLOCK3
Maximum Clock Rate
Minimum Clock Rate
Clock Pulse Width High (tEH)
Clock Pulse Width Low (tEL)
OUTPUT PARAMETERS3
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
FCO Propagation Delay (tFCO)
DCO Propagation Delay (tCPD)4
DCO to Data Delay (tDATA)4
DCO to FCO Delay (tFRAME)4
Data to Data Skew
(tDATA-MAX − tDATA-MIN)
Wake-Up Time (Standby)
Wake-Up Time (Power-Down)
Pipeline Latency
APERTURE
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
Out-of-Range Recovery Time
Temp
Min
Full
Full
Full
Full
50
Full
Full
Full
Full
Full
2.0
Full
Full
Full
Typ
Max
10
10
10
2.0
(tSAMPLE/28) − 300
(tSAMPLE/28) − 300
2.7
300
300
2.7
tFCO +
(tSAMPLE/28)
(tSAMPLE/28)
(tSAMPLE/28)
±50
3.5
3.5
(tSAMPLE/28) + 300
(tSAMPLE/28) + 300
±150
Unit
MSPS
MSPS
ns
ns
ns
ps
ps
ns
ns
ps
ps
ps
25°C
25°C
Full
600
375
8
ns
μs
CLK
cycles
25°C
25°C
25°C
500
