16-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,
1.8 V Analog-to-Digital Converter
AD9266
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
1.8 V analog supply operation
1.8 V to 3.3 V output supply
SNR
77.6 dBFS at 9.7 MHz input
71.1 dBFS at 200 MHz input
SFDR
93 dBc at 9.7 MHz input
80 dBc at 200 MHz input
Low power
56 mW at 20 MSPS
113 mW at 80 MSPS
Differential input with 700 MHz bandwidth
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = −0.6/+1.1 LSB
Interleaved data output for reduced pin-count interface
Serial port control options
Offset binary, Gray code, or twos complement data format
Optional clock duty cycle stabilizer
Integer 1-to-8 input clock divider
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock output (DCO) with programmable clock and
data alignment
AVDD
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
Smart antenna systems
Battery-powered instruments
Handheld scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
PET/SPECT imaging
Rev. B
SDIO SCLK CSB
AGND
RBIAS
SPI
AD9266
PROGRAMMING DATA
VIN+
ADC
CORE
VIN–
CMOS
OUTPUT BUFFER
VCM
DRVDD
OR
D15_D14
8
VREF
D1_D0
DCO
SENSE
REF
SELECT
DUTY CYCLE
STABILIZER
MODE
CONTROLS
PDWN DFS MODE
CLK+ CLK–
08678-001
DIVIDE
1 TO 8
Figure 1.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
The AD9266 operates from a single 1.8 V analog power
supply and features a separate digital output driver supply
to accommodate 1.8 V to 3.3 V logic families.
The sample-and-hold circuit maintains excellent
performance for input frequencies up to 200 MHz and is
designed for low cost, low power, and ease of use.
A standard serial port interface supports various product
features and functions, such as data output formatting,
internal clock divider, power-down, DCO and data output
(D15_D14 to D1_D0) timing and offset adjustments, and
voltage reference modes.
The AD9266 is packaged in a 32-lead RoHS-compliant
LFCSP that is pin compatible with the AD9609 10-bit
ADC, the AD9629 12-bit ADC, and the AD9649 14-bit
ADC, enabling a simple migration path between 10-bit and
16-bit converters sampling from 20 MSPS to 80 MSPS.
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Technical Support
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AD9266
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Voltage Reference ....................................................................... 19
Applications ....................................................................................... 1
Clock Input Considerations ...................................................... 20
Functional Block Diagram .............................................................. 1
Power Dissipation and Standby Mode .................................... 22
Product Highlights ........................................................................... 1
Digital Outputs ........................................................................... 22
Revision History ............................................................................... 2
Timing ......................................................................................... 23
General Description ......................................................................... 3
Output Test ...................................................................................... 24
Specifications..................................................................................... 4
Output Test Modes ..................................................................... 24
DC Specifications ......................................................................... 4
Serial Port Interface (SPI) .............................................................. 25
AC Specifications.......................................................................... 5
Configuration Using the SPI ..................................................... 25
Digital Specifications ................................................................... 6
Hardware Interface..................................................................... 26
Switching Specifications .............................................................. 7
Configuration Without the SPI ................................................ 26
Timing Specifications .................................................................. 8
SPI Accessible Features .............................................................. 26
Absolute Maximum Ratings............................................................ 9
Memory Map .................................................................................. 27
Thermal Characteristics .............................................................. 9
Reading the Memory Map Register Table............................... 27
ESD Caution .................................................................................. 9
Open Locations .......................................................................... 27
Pin Configuration and Function Descriptions ........................... 10
Default Values ............................................................................. 27
Typical Performance Characteristics ........................................... 11
Memory Map Register Table ..................................................... 28
AD9266-80 .................................................................................. 11
Memory Map Register Descriptions ........................................ 30
AD9266-65 .................................................................................. 13
Applications Information .............................................................. 31
AD9266-40 .................................................................................. 14
Design Guidelines ...................................................................... 31
AD9266-20 .................................................................................. 15
Outline Dimensions ....................................................................... 32
Equivalent Circuits ......................................................................... 16
Ordering Guide .......................................................................... 32
Theory of Operation ...................................................................... 17
Analog Input Considerations.................................................... 17
REVISION HISTORY
3/16—Rev. A to Rev. B
Change to Product Highlights Section .......................................... 1
Changes to Pipeline Delay (Latency) Parameter, Table 4 ............ 7
Changes to Figure 3 and Table 8 ................................................... 10
Changes to Clock Input Options Section .................................... 20
Changes to Data Clock Output Section ....................................... 23
6/12—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................ 4
Changes to Table 4 ............................................................................ 7
Changed Built-In Self-Test (BIST) and Output Test Section to
Output Test Section ........................................................................ 24
Changes to Output Test Section; Deleted Built-In Self-Test
(BIST) Section ................................................................................. 24
Changes to Table 16 ........................................................................ 28
4/10—Revision 0: Initial Version
Rev. B | Page 2 of 32
Data Sheet
AD9266
GENERAL DESCRIPTION
The AD9266 is a monolithic, single-channel 1.8 V supply,
16-bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS analog-to-digital
converter (ADC). It features a high performance sample-andhold circuit and on-chip voltage reference.
A differential clock input with a selectable internal 1-to-8 divide
ratio controls all internal conversion cycles. An optional duty cycle
stabilizer (DCS) compensates for wide variations in the clock duty
cycle while maintaining excellent overall ADC performance.
The product uses multistage differential pipeline architecture
with output error correction logic to provide 16-bit accuracy at
80 MSPS data rates and to guarantee no missing codes over the
full operating temperature range.
The interleaved digital output data is presented in offset binary,
gray code, or twos complement format. A DCO is provided to
ensure proper latch timing with receiving logic. Both 1.8 V and
3.3 V CMOS levels are supported.
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom
user-defined test patterns entered via the serial port interface (SPI).
The AD9266 is available in a 32-lead RoHS-compliant LFCSP
and is specified over the industrial temperature range (−40°C
to +85°C).
Rev. B | Page 3 of 32
AD9266
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error 1
Differential Nonlinearity
(DNL) 2
Integral Nonlinearity
(INL)2
TEMPERATURE DRIFT
Offset Error
INTERNAL VOLTAGE
REFERENCE
Output Voltage (1 V Mode)
Load Regulation Error
at 1.0 mA
INPUT-REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 1.0 V
Input Capacitance 3
Input Common-Mode
Voltage
Input Common-Mode
Range
REFERENCE INPUT
RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD2
IDRVDD2 (1.8 V)
IDRVDD2 (3.3 V)
POWER CONSUMPTION
DC Input
Sine Wave Input2
(DRVDD = 1.8 V)
Sine Wave Input2
(DRVDD = 3.3 V)
Standby Power 4
Power-Down Power
Temp
Full
AD9266-20/AD9266-40
Min
Typ
Max
16
Min
16
AD9266-65
Typ
Max
Min
16
AD9266-80
Typ
Max
Unit
Bits
Full
Full
Full
Full
Guaranteed
+0.05
±0.30
−2.5/−2.0
−0.9/+1.2
Guaranteed
+0.05
±0.30
−1.0
−0.9/+1.7
Guaranteed
+0.05
±0.30
+1.0
−0.9/+1.7
25°C
Full
−0.5/+0.6
−0.5/+1.0
−0.6/+1.1
25°C
±1.8
±2.4
±3.5
LSB
Full
±2
±2
±2
ppm/°C
Full
Full
±5.5
0.983
0.995
2
±6.5
1.007
0.983
0.995
2
1.007
±6.2
0.983
0.995
2
1.007
% FSR
% FSR
LSB
LSB
LSB
V
mV
25°C
2.8
2.8
2.8
LSB rms
Full
Full
Full
2
6.5
0.9
2
6.5
0.9
2
6.5
0.9
V p-p
pF
V
Full
0.5
Full
Full
Full
1.3
0.5
7.5
1.7
1.7
1.3
0.5
7.5
1.7
1.7
1.3
7.5
1.9
3.6
54.5
57.6
1.9
3.6
Full
31.4/40.7
33.2/42.5
Full
1.7/3.3
5.2
6.3
mA
Full
3.0/5.9
9.3
11.6
mA
Full
Full
57/73
60/79
Full
66/93
129
151
mW
Full
Full
40
0.5
44
0.5
44
0.5
mW
mW
98
107
113
1.7
1.7
kΩ
1.8
63/82
1.8
V
1.8
1.9
3.6
V
V
62.5
65.7
mA
113
124
Measured with 1.0 V external reference.
Measured with a 10 MHz input frequency at rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between the differential inputs.
4
Standby power is measured with a dc input and the CLK active.
1
2
Rev. B | Page 4 of 32
130
mW
mW
Data Sheet
AD9266
AC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
Table 2.
Parameter 1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 200 MHz
SIGNAL-TO-NOISE-AND-DISTORTION (SINAD)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 200 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 200 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 200 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 200 MHz
WORST OTHER (HARMONIC OR SPUR)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 200 MHz
TWO-TONE SFDR
fIN = 30.5 MHz (−7 dBFS), 32.5 MHz (−7 dBFS)
ANALOG INPUT BANDWIDTH
1
Temp
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
Full
25°C
Full
25°C
AD9266-20/AD9266-40
Min
Typ
Max
Min
AD9266-65
Typ
Max
78.2
77.6
AD9266-80
Min Typ Max
77.9
77.5
76.7
77.6
77.3
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
76.6
75.8/76.4
76.6
76.6
75.5
72.1
78.0
77.5
77.7
77.3
76.2
77.4
77.1
69.4
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
76.2
75.7/76.3
76.5
Unit
76.6
75.5
25°C
25°C
25°C
25°C
12.7
12.6
12.3/12.4
12.6
12.5
12.4
12.6
12.5
12.4
11.2
Bits
Bits
Bits
Bits
25°C
25°C
Full
25°C
Full
25°C
−97
−96/−93
−96
−94
−95
−93
dBc
dBc
dBc
dBc
dBc
dBc
25°C
25°C
Full
25°C
Full
25°C
95
93
−80
−80
−97/−95
−98
−95
−80
−80
95
92
80
94
92
dBc
dBc
dBc
dBc
dBc
dBc
80
93
95
93
80
80
25°C
25°C
Full
25°C
Full
25°C
−102
−102
25°C
25°C
90
700
−101
−101
−89
−101
−99
−98
−86
dBc
dBc
dBc
dBc
dBc
dBc
90
700
dBc
MHz
−89
−100
−98
−89
90
700
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Rev. B | Page 5 of 32
AD9266
Data Sheet
DIGITAL SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (SCLK/DFS, MODE, SDIO/PDWN) 1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (CSB) 2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
DIGITAL OUTPUTS
DRVDD = 3.3 V
High Level Output Voltage, IOH = 50 µA
High Level Output Voltage, IOH = 0.5 mA
Low Level Output Voltage, IOL = 1.6 mA
Low Level Output Voltage, IOL = 50 µA
DRVDD = 1.8 V
High Level Output Voltage, IOH = 50 µA
High Level Output Voltage, IOH = 0.5 mA
Low Level Output Voltage, IOL = 1.6 mA
Low Level Output Voltage, IOL = 50 µA
1
2
Temp
Full
Full
Full
Full
Full
Full
Full
Min
AD9266-20/AD9266-40/AD9266-65/AD9266-80
Typ
Max
CMOS/LVDS/LVPECL
0.9
0.2
GND − 0.3
−10
−10
8
Full
Full
Full
Full
Full
Full
1.2
0
−50
−10
Full
Full
Full
Full
Full
Full
1.2
0
−10
40
Full
Full
Full
Full
3.29
3.25
Full
Full
Full
Full
1.79
1.75
10
4
3.6
AVDD + 0.2
+10
+10
12
V
V
µA
µA
kΩ
pF
DRVDD + 0.3
0.8
+10
135
V
V
µA
µA
kΩ
pF
26
2
Rev. B | Page 6 of 32
V
V p-p
V
µA
µA
kΩ
pF
DRVDD + 0.3
0.8
−75
+10
30
2
Internal 30 kΩ pull-down.
Internal 30 kΩ pull-up.
Unit
0.2
0.05
V
V
V
V
0.2
0.05
V
V
V
V
Data Sheet
AD9266
SWITCHING SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate1
CLK Period—Divide-by-1 Mode (tCLK)
CLK Pulse Width High (tCH)
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
DATA OUTPUT PARAMETERS
Data Propagation Delay (tPD)
DCO Propagation Delay (tDCO)
DCO to Data Skew (tSKEW)
Pipeline Delay (Latency)
Wake-Up Time2
Standby
OUT-OF-RANGE RECOVERY TIME
2
AD9266-20/AD9266-40
Min
Typ
Max
Full
Full
Full
3
50/25
80/320
20/40
AD9266-65
Typ
Max
1.84
1.86
−0.53
3
3
0.1
8
350
600/400
2
520
65
3
15.38
25.0/12.5
1.0
0.1
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min
Min
AD9266-80
Typ
Max
3
12.5
7.69
1.0
0.1
3.90
4.04
0.72
1.84
1.86
−0.53
3
3
0.1
8
350
300
2
625
80
MHz
MSPS
ns
ns
ns
ps rms
3.90
4.04
0.72
ns
ns
ns
Cycles
μs
ns
Cycles
6.25
1.0
0.1
3.90
4.04
0.72
1.84
1.86
−0.53
3
3
0.1
8
350
260
2
Unit
Conversion rate is the clock rate after the CLK divider.
Wake-up time is dependent on the value of the decoupling capacitors.
tA
N–1
N
N+6
N+1
N+7
N+5
VIN
N+8
N+2
tCLK
N+3
CLK+
CLK–
tDCO
DCO
tSKEW
tSKEW
D1_D0
D1N–9
D0N–9
D1N–8
D0 N–8
D1N–7
D0N–7
D1N–6
D0 N–6
D15 N–9 D14 N–9 D15N–8 D14 N–8
D15N–7
D14 N–7 D15N–6 D14 N–6
D1 N–5
D0N–5
D1N–4
D0N–4
tPD
D15_D14
D15 N–5 D14 N–5
Figure 2. CMOS Output Data Timing
Rev. B | Page 7 of 32
D15 N–4 D14 N–4
08678-002
1
Temp
AD9266
Data Sheet
TIMING SPECIFICATIONS
Table 5.
Parameter
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
tDIS_SDIO
Test Conditions/Comments
Min
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an output
relative to the SCLK falling edge
Time required for the SDIO pin to switch from an output to an input
relative to the SCLK rising edge
2
2
40
2
2
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
10
ns
Rev. B | Page 8 of 32
Typ
Max
Unit
Data Sheet
AD9266
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Table 6.
Parameter
AVDD to AGND
DRVDD to AGND
VIN+, VIN− to AGND
CLK+, CLK− to AGND
VREF to AGND
SENSE to AGND
VCM to AGND
RBIAS to AGND
CSB to AGND
SCLK/DFS to AGND
SDIO/PDWN to AGND
MODE/OR to AGND
D1_D0 Through D15_D14 to AGND
DCO to AGND
Operating Temperature Range (Ambient)
Maximum Junction Temperature Under Bias
Storage Temperature Range (Ambient)
Rating
−0.3 V to +2.0 V
−0.3 V to +3.9 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−40°C to +85°C
150°C
−65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
The exposed paddle is the only ground connection for the chip.
The exposed paddle must be soldered to the AGND plane of the
user’s circuit board. Soldering the exposed paddle to the user’s
board also increases the reliability of the solder joints and
maximizes the thermal capability of the package.
Table 7. Thermal Resistance
Package Type
32-Lead LFCSP,
5 mm × 5 mm
Airflow
Velocity
(m/sec)
0
θJA1, 2
37.1
1.0
2.5
32.4
29.1
θJC1, 3
3.1
θJB1, 4
20.7
ΨJT1, 2
0.3
Unit
°C/W
0.5
0.8
°C/W
°C/W
Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board.
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3
Per MIL-Std 883, Method 1012.1.
4
Per JEDEC JESD51-8 (still air).
1
2
Typical θJA is specified for a 4-layer PCB with a solid ground
plane. As shown in Table 7, airflow improves heat dissipation,
which reduces θJA. In addition, metal in direct contact with the
package leads from metal traces, through holes, ground, and
power planes reduces the θJA.
ESD CAUTION
Rev. B | Page 9 of 32
AD9266
Data Sheet
32
31
30
29
28
27
26
25
AVDD
VIN+
VIN–
AVDD
RBIAS
VCM
SENSE
VREF
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
AD9266
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
AVDD
MODE/OR
DCO
(MSB) D15_D14
D13_D12
D11_D10
D9_D8
D7_D6
NOTES
1. DNC = DO NOT CONNECT.
2. THE EXPOSED PADDLE IS THE ONLY GROUND CONNECTION ON THE DEVICE. IT MUST
BE SOLDERED TO THE ANALOG GROUND OF THE PCB TO ENSURE PROPER FUNCTIONALITY,
HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH.
08678-003
DNC
DNC
DNC
DNC
DRVDD
D1_D0 (LSB)
D3_D2
D5_D4
9
10
11
12
13
14
15
16
CLK+
CLK–
AVDD
CSB
SCLK/DFS
SDIO/PDWN
DNC
DNC
Figure 3. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
0
Mnemonic
EPAD
1, 2
3, 24, 29, 32
4
5
CLK+, CLK−
AVDD
CSB
SCLK/DFS
6
SDIO/PDWN
7 to 12
14 to 21
13
22
23
DNC
D1_D0 (LSB) to
(MSB) D15_D14
DRVDD
DCO
MODE/OR
25
26
27
28
30, 31
VREF
SENSE
VCM
RBIAS
VIN−, VIN+
Description
Exposed Paddle. The exposed paddle is the only ground connection on the device. It must be
soldered to the analog ground of the PCB to ensure proper functionality, heat dissipation, noise, and
mechanical strength.
Differential Encode Clock for PECL, LVDS, or 1.8 V CMOS Inputs.
1.8 V Supply Pin for ADC Core Domain.
SPI Chip Select. Active low enable, 30 kΩ internal pull-up.
SPI Clock Input in SPI Mode (SCLK). 30 kΩ internal pull-down.
Data Format Select in Non-SPI Mode (DFS). Static control of data output format. 30 kΩ internal pull-down.
DFS high = twos complement output; DFS low = offset binary output.
SPI Data Input/Output (SDIO). Bidirectional SPI data I/O with 30 kΩ internal pull-down.
Non-SPI Mode Power-Down (PDWN). Static control of chip power-down with 30 kΩ internal pulldown. See Table 14 for details.
Do Not Connect.
ADC Digital Outputs.
1.8 V to 3.3 V Supply Pin for Output Driver Domain.
Data Clock Digital Output.
Chip Mode Select Input (MODE)/Out-of-Range Digital Output in SPI Mode (OR).
Default = out-of-range (OR) digital output (SPI Register 0x2A, Bit 0 = 1).
Option = chip mode select input (SPI Register 0x2A, Bit 0 = 0).
Chip power-down (SPI Register 0x08, Bits[7:5] = 100b).
Chip standby (SPI Register 0x08, Bits[7:5] = 101b).
Normal operation, output disabled (SPI Register 0x08, Bits[7:5] = 110b).
Normal operation, output enabled (SPI Register 0x08, Bits[7:5] = 111b).
Out-of-range (OR) digital output only in non-SPI mode.
1.0 V Voltage Reference Input/Output. See Table 10.
Reference Mode Selection. See Table 10.
Analog Output Voltage at Mid AVDD Supply. Sets common mode of the analog inputs.
Set Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground.
ADC Analog Inputs.
Rev. B | Page 10 of 32
Data Sheet
AD9266
TYPICAL PERFORMANCE CHARACTERISTICS
AD9266-80
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
0
0
80MSPS
9.7MHz @ –1dBFS
SNR = 76.8dB (77.8dBFS)
SFDR = 94.3dBc
–40
–60
–80
–100
–120
–60
–80
–100
10
15
20
25
30
35
40
FREQUENCY (MHz)
–140
0
5
10
15
20
25
30
35
40
FREQUENCY (MHz)
Figure 4. AD9266-80 Single-Tone FFT with fIN = 9.7 MHz
08678-034
5
08678-033
0
Figure 7. AD9266-80 Single-Tone FFT with fIN = 30.6 MHz
0
0
80MSPS
69MHz @ –1dBFS
SNR = 75.1dB (76.1dBFS)
SFDR = 89.5dBc
–20
80MSPS
210MHz @ –1dBFS
SNR = 70dB (71dBFS)
SFDR = 79.7dBc
–20
–40
AMPLITUDE (dBFS)
–60
–80
–100
–120
–40
–60
–80
–100
0
5
10
15
20
25
30
35
FREQUENCY (MHz)
40
–140
08678-035
–140
0
15
20
25
30
35
40
Figure 8. AD9266-80 Single-Tone FFT with fIN = 210 MHz
0
10
80MSPS
28.3MHz @ –7dBFS
30.6MHz @ –7dBFS
SFDR = 89.5dBc (96.5dBFS)
–10
SFDR (dBc)
SFDR/IMD3 (dBc/dBFS)
–30
10
FREQUENCY (MHz)
Figure 5. AD9266-80 Single-Tone FFT with fIN = 69 MHz
–15
5
08678-036
–120
–45
–60
–75
2F1 + F2
2F2 + F1
–90
F2 – F1
–105
F1 + F2
2F2 – F1
2F1 – F2
–30
IMD3 (dBc)
–50
–70
SFDR (dBFS)
–90
–110
–120
IMD3 (dBFS)
4
8
12
16
20
24
28
FREQUENCY (MHz)
32
36
–130
–95
08678-053
–135
Figure 6. AD9266-80 Two-Tone FFT with fIN1 = 28.3 MHz and fIN2 = 30.6 MHz
–85
–75
–65
–55
–45
–35
INPUT AMPLITUDE (dBFS)
–25
–15
08678-054
AMPLITUDE (dBFS)
–40
–120
–140
AMPLITUDE (dBFS)
80MSPS
30.6MHz @ –1dBFS
SNR = 76.5dB (77.5dBFS)
SFDR = 85.7dBc
–20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–20
Figure 9. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 28.3 MHz
and fIN2 = 30.6 MHz
Rev. B | Page 11 of 32
AD9266
Data Sheet
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
100
1.5
SFDR (dBc)
90
1.0
70
SNR (dBFS)
DNL ERROR (LSB)
SNR/SFDR (dBFS/dBc)
80
60
50
40
30
20
0.5
0
–0.5
–1.0
0
50
100
150
INPUT FREQUENCY (MHz)
200
–1.5
08678-057
0
0
Figure 10. AD9266-80 SNR/SFDR vs. Input Frequency (AIN) with 2 V p-p Full Scale
32,768
OUTPUT CODE
49,152
65,536
Figure 13. DNL Error with fIN = 9.7 MHz
100
6
90
SFDR (dBc)
4
80
70
SNR (dBFS)
INL ERROR (LSB)
SNR/SFDR (dBFS/dBc)
16,384
08678-038
10
60
50
40
30
20
2
0
–2
–4
20
30
40
50
60
SAMPLE RATE (MSPS)
70
80
–6
08678-055
0
10
0
Figure 11. AD9266-80 SNR/SFDR vs. Sample Rate with AIN = 9.7 MHz
16,384
32,768
OUTPUT CODE
49,152
65,536
08678-037
10
Figure 14. INL with fIN = 9.7 MHz
120
4.0M
SFDRFS
2.8 LSB RMS
3.5M
100
NUMBER OF HITS
SNR/SFDR (dBFS/dBc)
3.0M
80
SNRFS
SFDR
60
SNR
40
2.5M
2.0M
1.5M
1.0M
20
500k
–10
0
0
OUTPUT CODE
Figure 12. AD9266-80 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz
Rev. B | Page 12 of 32
Figure 15. Grounded Input Histogram
08678-048
–40
–30
–20
INPUT AMPLITUDE (dBFS)
N – 12
N – 11
N – 10
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
N + 10
–50
08678-061
0
–65 –60
Data Sheet
AD9266
AD9266-65
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
120
0
65MSPS
9.7MHz @ –1dBFS
SNR = 76.9dB (77.9dBFS)
SFDR = 95.9dBc
SFDRFS
100
–40
SNR/SFDR (dBFS/dBc)
–60
–80
–100
SNRFS
SFDR
60
SNR
40
20
–120
0
5
10
15
20
25
30
FREQUENCY (MHz)
0
–65 –60
08678-030
–140
–50
–40
–30
–20
INPUT AMPLITUDE (dBFS)
–10
0
Figure 19. AD9266-65 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz
Figure 16. AD9266-65 Single-Tone FFT with fIN = 9.7 MHz
100
0
65MSPS
69MHz @ –1dBFS
SNR = 75.5dB (76.5dBFS)
SFDR = 87.4dBc
–20
SFDR (dBc)
90
80
SNR/SFDR (dBFS/dBc)
–40
AMPLITUDE (dBFS)
80
08678-060
AMPLITUDE (dBFS)
–20
–60
–80
–100
70
SNR (dBFS)
60
50
40
30
20
–120
5
10
15
20
25
30
FREQUENCY (MHz)
0
65MSPS
30.6MHz @ –1dBFS
SNR = 76.6dB (77.6dBFS)
SFDR = 89.9dBc
–60
–80
–100
–120
0
5
10
15
20
25
30
FREQUENCY (MHz)
08678-031
AMPLITUDE (dBFS)
–40
–140
0
50
100
150
INPUT FREQUENCY (MHz)
200
Figure 20. AD9266-65 SNR/SFDR vs. Input Frequency (AIN) with
2 V p-p Full Scale
Figure 17. AD9266-65 Single-Tone FFT with fIN = 69 MHz
–20
0
Figure 18. AD9266-65 Single-Tone FFT with fIN = 30.6 MHz
Rev. B | Page 13 of 32
08678-056
0
08678-032
10
–140
AD9266
Data Sheet
AD9266-40
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
120
0
40MSPS
9.7MHz @ –1dBFS
SNR = 76.9dB (77.9dBFS)
SFDR = 95.1dBc
SFDRFS
100
–40
SNR/SFDR (dBFS/dBc)
–60
–80
–100
SNRFS
SFDR
60
SNR
40
20
–120
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (MHz)
0
–65 –60
08678-028
–140
0
40MSPS
30.6MHz @ –1dBFS
SNR = 76.6dB (77.6dBFS)
SFDR = 88.8dBc
–20
–40
–60
–80
–100
–140
2
4
6
8
10
12
14
16
18
FREQUENCY (MHz)
20
08678-029
–120
0
–50
–40
–30
–20
INPUT AMPLITUDE (dBFS)
–10
0
Figure 23. AD9266-40 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz
Figure 21. AD9266-40 Single-Tone FFT with fIN = 9.7 MHz
AMPLITUDE (dBFS)
80
08678-059
AMPLITUDE (dBFS)
–20
Figure 22. AD9266-40 Single-Tone FFT with fIN = 30.6 MHz
Rev. B | Page 14 of 32
Data Sheet
AD9266
AD9266-20
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
0
120
20MSPS
9.7MHz @ –1dBFS
SNR = 76.9dB (77.9dBFS)
SFDR = 95.6dBc
SFDRFS
100
–40
SNR/SFDR (dBFS/dBc)
–60
–80
–100
60
SFDR (dBc)
40
SNR (dBc)
20
–120
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (MHz)
0
–90
08678-024
–140
Figure 24. AD9266-20 Single-Tone FFT with fIN = 9.7 MHz
20MSPS
30.6MHz @ –1dBFS
SNR = 76.7dB (77.7dBFS)
SFDR = 90.7dBc
–20
–40
–60
–80
–100
–140
1
2
3
4
5
6
7
8
9
FREQUENCY (MHz)
10
08678-026
–120
0
–80
–70
–60
–50
–40
–30
–20
INPUT AMPLITUDE (dBFS)
–10
0
Figure 26. AD9266-20 SNR/SFDR vs. Input Amplitude (AIN) with fIN = 9.7 MHz
0
AMPLITUDE (dBFS)
SNRFS
80
08678-058
AMPLITUDE (dBFS)
–20
Figure 25. AD9266-20 Single-Tone FFT with fIN = 30.6 MHz
Rev. B | Page 15 of 32
AD9266
Data Sheet
EQUIVALENT CIRCUITS
DRVDD
AVDD
VIN±
08678-042
08678-039
D1_D0 TO D15_D14,
OR
Figure 27. Equivalent Analog Input Circuit
Figure 31. Equivalent D1_D0 to D15_D14 and OR Digital Output Circuit
DRVDD
AVDD
SCLK/DFS,
MODE,
SDIO/PDWN
VREF
30kΩ
08678-047
7.5kΩ
350Ω
08678-043
375Ω
Figure 32. Equivalent SCLK/DFS, MODE, and SDIO/PDWN Input Circuit
Figure 28. Equivalent VREF Circuit
AVDD
DRVDD
AVDD
375Ω
CSB
30kΩ
350Ω
08678-045
08678-046
SENSE
Figure 29. Equivalent SENSE Circuit
Figure 33. Equivalent CSB Input Circuit
AVDD
5Ω
CLK+
AVDD
15kΩ
0.9V
AVDD
RBIAS
AND VCM
375Ω
08678-044
08678-040
CLK–
15kΩ
5Ω
Figure 30. Equivalent Clock Input Circuit
Figure 34. Equivalent RBIAS and VCM Circuit
Rev. B | Page 16 of 32
Data Sheet
AD9266
THEORY OF OPERATION
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor DAC
and an interstage residue amplifier (for example, a multiplying
digital-to-analog converter (MDAC)). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
high IF frequencies. Either a shunt capacitor or two single-ended
capacitors can be placed on the inputs to provide a matching
passive network. This ultimately creates a low-pass filter at the
input to limit unwanted broadband noise. See the AN-742
Application Note, the AN-827 Application Note, and the Analog
Dialogue article “Transformer-Coupled Front-End for Wideband
A/D Converters” (Volume 39, April 2005) for more information. In
general, the precise values depend on the application.
Input Common Mode
The analog inputs of the AD9266 are not internally dc-biased.
Therefore, in ac-coupled applications, the user must provide
a dc bias externally. Setting the device so that VCM = AVDD/2
is recommended for optimum performance, but the device can
function over a wider range with reasonable performance, as
shown in Figure 36.
100
The output staging block aligns the data, corrects errors, and
passes the data to the CMOS output buffers. The output buffers
are powered from a separate (DRVDD) supply, allowing adjustment of the output voltage swing. During power-down, the
output buffers go into a high impedance state.
95
SFDR (dBc)
SNR/SFDR (dBFS/dBc)
90
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9266 is a differential switchedcapacitor circuit designed for processing differential input
signals. This circuit can support a wide common-mode range
while maintaining excellent performance. By using an input
common-mode voltage of midsupply, users can minimize
signal-dependent errors and achieve optimum performance.
85
80
SNR (dBFS)
75
70
65
60
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
INPUT COMMON-MODE VOLTAGE (V)
Figure 36. SNR/SFDR vs. Input Common-Mode Voltage,
fIN = 32.5 MHz, fS = 80 MSPS
H
An on-board, common-mode voltage reference is included in
the design and is available from the VCM pin. The VCM pin
must be decoupled to ground by a 0.1 μF capacitor, as described
in the Applications Information section.
H
CSAMPLE
S
S
S
S
CSAMPLE
Differential Input Configurations
H
H
Optimum performance is achieved while driving the AD9266 in a
differential input configuration. For baseband applications, the
AD8138, ADA4937-2, and ADA4938-2 differential drivers provide
excellent performance and a flexible interface to the ADC.
08678-006
CPAR
Figure 35. Switched-Capacitor Input Circuit
The clock signal alternately switches the input circuit between
sample-and-hold mode (see Figure 35). When the input circuit
is switched to sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current injected from the output
stage of the driving source. In addition, low Q inductors or ferrite
beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and, therefore, achieve
the maximum bandwidth of the ADC. Such use of low Q inductors
or ferrite beads is required when driving the converter front end at
The output common-mode voltage of the ADA4938-2 is easily
set with the VCM pin of the AD9266 (see Figure 37), and the
driver can be configured in a Sallen-Key filter topology to
provide band limiting of the input signal.
200Ω
VIN
76.8Ω
33Ω
ADA4938-2
0.1µF
VIN–
90Ω
120Ω
10pF
33Ω
AVDD
ADC
VIN+
VCM
200Ω
Figure 37. Differential Input Configuration Using the ADA4938-2
Rev. B | Page 17 of 32
08678-007
CPAR
VIN+
VIN–
08678-049
The AD9266 architecture consists of a multistage, pipelined ADC.
Each stage provides sufficient overlap to correct for flash errors in
the preceding stage. The quantized outputs from each stage are
combined into a final 16-bit result in the digital correction logic.
The pipelined architecture permits the first stage to operate with
a new input sample, whereas the remaining stages operate with
preceding samples. Sampling occurs on the rising edge of the clock.
AD9266
Data Sheet
In any configuration, the value of Shunt Capacitor C is dependent
on the input frequency and source impedance and may need to
be reduced or removed. Table 9 displays the suggested values to set
the RC network. However, these values are dependent on the
input signal and should be used only as a starting guide.
For baseband applications less than approximately 10 MHz
where SNR is a key parameter, differential transformer coupling is
the recommended input configuration. An example is shown in
Figure 38. To bias the analog input, the VCM voltage can be
connected to the center tap of the secondary winding of the
transformer.
R
VCM
08678-008
VIN–
0.1µF
C Differential (pF)
22
Open
Single-Ended Input Configuration
Figure 38. Differential Transformer-Coupled Configuration
A single-ended input can provide adequate performance in
cost-sensitive applications. In this configuration, SFDR and
distortion performance degrade due to the large input commonmode swing. If the source impedances on each input are matched,
there should be little effect on SNR performance. Figure 39
shows a typical single-ended input configuration.
The signal characteristics must be considered when selecting
a transformer. Most RF transformers saturate at frequencies
below a few megahertz (MHz). Excessive signal power can also
cause core saturation, which leads to distortion.
At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD9266. For applications greater
than approximately 10 MHz where SNR is a key parameter,
differential double balun coupling is the recommended input
configuration (see Figure 40).
10µF
AVDD
1kΩ
1V p-p
49.9Ω
0.1µF
R
0.1µF
ADC
C
1kΩ
10µF
VIN+
1kΩ
AVDD
An alternative to using a transformer-coupled input at frequencies
in the second Nyquist zone is to use the AD8352 differential driver.
An example is shown in Figure 41. See the AD8352 data sheet
for more information.
R
VIN–
1kΩ
Figure 39. Single-Ended Input Configuration
0.1µF
0.1µF
R Series
(Ω Each)
33
125
Frequency Range (MHz)
0 to 70
70 to 200
ADC
C
R
VIN+
2V p-p
25Ω
PA
S
S
P
0.1µF
25Ω
ADC
C
0.1µF
R
VCM
VIN–
Figure 40. Differential Double Balun Input Configuration
VCC
ANALOG INPUT
0Ω
16
1
8, 13
11
0.1µF
2
CD
RD
RG
3
ANALOG INPUT
0.1µF 0Ω
R
VIN+
200Ω
10
ADC
C
AD8352
4
5
0.1µF
0.1µF
200Ω
R
14
0.1µF
0.1µF
Figure 41. Differential Input Configuration Using the AD8352
Rev. B | Page 18 of 32
VIN–
VCM
08678-011
0.1µF
08678-009
49.9Ω
08678-010
2V p-p
Table 9. Example RC Network
VIN+
R
Data Sheet
AD9266
0
Internal Reference Connection
A comparator within the AD9266 detects the potential at the
SENSE pin and configures the reference into two possible modes,
which are summarized in Table 10. If SENSE is grounded, the
reference amplifier switch is connected to the internal resistor
divider (see Figure 42), setting VREF to 1.0 V.
–0.5
–1.0
INTERNAL VREF = 0.995V
–1.5
–2.0
–2.5
–3.0
0
0.6
0.8
1.0
1.2
1.4
1.6
2.0
1.8
Figure 43. VREF Accuracy vs. Load Current
External Reference Operation
VIN–
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift characteristics. Figure 44 shows the typical drift characteristics of the
internal reference in 1.0 V mode.
ADC
CORE
VREF
4
SELECT
LOGIC
3
2
SENSE
08678-012
ADC
VREF ERROR (mV)
0.5V
Figure 42. Internal Reference Configuration
If the internal reference of the AD9266 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 43 shows
how the internal reference voltage is affected by loading.
VREF ERROR (mV)
1
0
–1
–2
–3
–4
–5
–6
–40
–20
0
20
40
TEMPERATURE (°C)
60
80
08678-052
0.1µF
0.4
LOAD CURRENT (mA)
VIN+
1.0µF
0.2
08678-014
A stable and accurate 1.0 V voltage reference is built into the
AD9266. The VREF can be configured using either the internal
1.0 V reference or an externally applied 1.0 V reference voltage.
The various reference modes are summarized in the sections that
follow. The Reference Decoupling section describes the best
practices for PCB layout of VREF.
REFERENCE VOLTAGE ERROR (%)
VOLTAGE REFERENCE
Figure 44. Typical VREF Drift
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
7.5 kΩ load (see Figure 28). The internal buffer generates the positive and negative full-scale references for the ADC core. Therefore,
the external reference must be limited to a maximum of 1.0 V.
Table 10. Reference Configuration Summary
Selected Mode
Fixed Internal Reference
Fixed External Reference
SENSE Voltage (V)
AGND to 0.2
AVDD
Resulting VREF (V)
1.0 internal
1.0 applied to external VREF pin
Rev. B | Page 19 of 32
Resulting Differential Span (V p-p)
2.0
2.0
AD9266
Data Sheet
CLOCK INPUT CONSIDERATIONS
For optimum performance, clock the AD9266 sample clock inputs,
CLK+ and CLK−, with a differential signal. The signal is typically
ac-coupled into the CLK+ and CLK− pins via a transformer or
capacitors. These pins are biased internally (see Figure 45) and
require no external bias.
AVDD
CLK–
2pF
08678-016
2pF
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9266 while
preserving the fast rise and fall times of the signal that are
critical to a low jitter performance.
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 48. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515/AD9516-0/AD9516-1/AD9516-2/
AD9516-3/AD9516-4/AD9516-5/AD9517-0/AD9517-1/
AD9517-2/AD9517-3/AD9517-4 clock drivers offer excellent
jitter performance.
0.9V
CLK+
The back-to-back Schottky diodes across the transformer/
balun secondary limit clock excursions into the AD9266 to
approximately 0.8 V p-p differential.
Figure 45. Equivalent Clock Input Circuit
0.1µF
The AD9266 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter is
of great concern, as described in the Jitter Considerations section.
Figure 46 and Figure 47 show two preferred methods for clocking the AD9266 (at clock rates up to 625 MHz when using the
internal clock divider). A low jitter clock source is converted from
a single-ended signal to a differential signal using either an RF
transformer or an RF balun.
Mini-Circuits®
ADT1-1WT, 1:1 Z
XFMR
0.1µF
CLOCK
INPUT
100Ω
ADC
0.1µF
CLK–
50kΩ
50kΩ
240Ω
240Ω
Figure 48. Differential PECL Sample Clock (Up to 625 MHz)
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 49. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516-0/
AD9516-1/AD9516-2/AD9516-3/AD9516-4/AD9516-5/
AD9517-0/AD9517-1/AD9517-2/AD9517-3/AD9517-4 clock
drivers offer excellent jitter performance.
0.1µF
CLK+
100Ω
50Ω
CLK+
AD951x
PECL DRIVER
ADC
0.1µF
0.1µF
08678-017
SCHOTTKY
DIODES:
HSMS2822
0.1µF
0.1µF
CLOCK
INPUT
CLK–
Figure 46. Transformer-Coupled Differential Clock (Up to 200 MHz)
CLK+
0.1µF
CLOCK
INPUT
AD951x
LVDS DRIVER
100Ω
ADC
0.1µF
CLK–
50kΩ
08678-020
0.1µF
CLOCK
INPUT
0.1µF
CLOCK
INPUT
08678-019
Clock Input Options
50kΩ
Figure 49. Differential LVDS Sample Clock (Up to 625 MHz)
CLK+
50Ω
ADC
0.1µF
1nF
CLK–
SCHOTTKY
DIODES:
HSMS2822
08678-018
CLOCK
INPUT
0.1µF
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate, and
bypass the CLK− pin to ground with a 0.1 μF capacitor (see
Figure 50).
Figure 47. Balun-Coupled Differential Clock (Up to 625 MHz)
VCC
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 625 MHz, and the RF transformer is recommended for clock frequencies from 10 MHz to 200 MHz.
0.1µF
CLOCK
INPUT
50Ω1
1kΩ
AD951x
CMOS DRIVER
OPTIONAL
0.1µF
100Ω
1kΩ
CLK+
ADC
CLK–
0.1µF
150Ω RESISTOR IS OPTIONAL.
Figure 50. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
Rev. B | Page 20 of 32
08678-021
1nF
Data Sheet
AD9266
Input Clock Divider
Jitter Considerations
The AD9266 contains an input clock divider with the ability
to divide the input clock by integer values between 1 and 8.
Optimum performance can be obtained by enabling the internal
duty cycle stabilizer (DCS) when using divide ratios other than
1, 2, or 4.
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR from the low frequency
SNR (SNRLF) at a given input frequency (fINPUT) due to jitter
(tJRMS) can be calculated by
Clock Duty Cycle
SNRHF = −10 log[(2π × fINPUT × tJRMS)2 + 10 ( − SNRLF /10) ]
In the previous equation, the rms aperture jitter represents the
clock input jitter specification. IF undersampling applications
are particularly sensitive to jitter, as illustrated in Figure 52.
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
80
75
The AD9266 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows the user to
provide a wide range of clock input duty cycles without affecting
the performance of the AD9266. Noise and distortion performance are nearly flat for a wide range of duty cycles with the DCS on,
as shown in Figure 51.
0.05ps
70
0.5ps
60
55
80
1.0ps
1.5ps
50
DCS OFF
DCS ON
79
3.0ps
45
1
78
SNR (dBFS)
100
FREQUENCY (MHz)
77
1k
Figure 52. SNR vs. Input Frequency and Jitter
76
75
74
73
72
35
40
45
50
55
POSITIVE DUTY CYCLE (%)
60
65
70
08678-064
71
70
30
10
2.0ps
2.5ps
08678-022
SNR (dBFS)
0.2ps
65
Figure 51. SNR vs. DCS On/Off
Jitter in the rising edge of the input is still of concern and is not
easily reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates less than
20 MHz nominally. The loop has a time constant associated
with it that must be considered in applications in which the
clock rate can change dynamically. A wait time of 1.5 µs to 5 µs
is required after a dynamic clock frequency increase or decrease
before the DCS loop is relocked to the input signal.
Treat the clock input as an analog signal when aperture jitter may
affect the dynamic range of the AD9266. To avoid modulating the
clock signal with digital noise, keep power supplies for clock
drivers separate from the ADC output driver supplies. Low jitter,
crystal-controlled oscillators make the best clock sources. If the
clock is generated from another type of source (by gating, dividing,
or another method), it should be retimed by the original clock at
the last step.
For more information, see the AN-501 Application Note and
the AN-756 Application Note.
Rev. B | Page 21 of 32
AD9266
Data Sheet
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 53, the analog core power dissipated by the
AD9266 is proportional to its sample rate. The digital power
dissipation of the CMOS outputs are determined primarily by
the strength of the digital drivers and the load on each output bit.
The maximum DRVDD current (IDRVDD) can be calculated as
IDRVDD = VDRVDD × CLOAD × fCLK × N
where N is the number of output bits (nine, in the case of the
AD9266).
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the Nyquist
frequency of fCLK/2. In practice, the DRVDD current is established by the average number of output bits switching, which
is determined by the sample rate and the characteristics of the
analog input signal.
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in Figure 53 was
taken using the same operating conditions as those used for the
Typical Performance Characteristics, with a 5 pF load on each
output driver.
AD9266-80
85
65
AD9266-20
45
20
30
40
50
The AD9266 output drivers can be configured to interface with
1.8 V to 3.3 V CMOS logic families. Output data can also be
multiplexed onto a single output bus to reduce the total number
of traces required.
The CMOS output drivers are sized to provide sufficient output
current to drive a wide variety of logic families. However, large
drive currents tend to cause current glitches on the supplies and
may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
Table 11. SCLK/DFS and SDIO/PDWN Mode Selection
(External Pin Mode)
AD9266-40
10
DIGITAL OUTPUTS
As detailed in the AN-877 Application Note, Interfacing to High
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI control.
AD9266-65
95
60
70
CLOCK RATE (MSPS)
80
08678-067
ANALOG CORE POWER (mW)
105
55
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map section
for more details.
The output data format can be selected to be either offset binary
or twos complement by setting the SCLK/DFS pin when operating
in the external pin mode (see Table 11).
115
75
down mode and then must be recharged when returning to normal
operation. As a result, wake-up time is related to the time spent
in power-down mode, and shorter power-down cycles result in
proportionally shorter wake-up times.
Voltage at Pin
AGND
SCLK/DFS
Offset binary (default)
DRVDD
Twos complement
SDIO/PDWN
Normal operation
(default)
Outputs disabled
Digital Output Enable Function (OEB)
Figure 53. Analog Core Power vs. Clock Rate
In SPI mode, the AD9266 can be placed in power-down mode
directly via the SPI port, or by using the programmable external
MODE pin. In non-SPI mode, power-down is achieved by asserting the PDWN pin high. In this state, the ADC typically dissipates
500 µW. During power-down, the output drivers are placed in
a high impedance state. Asserting PDWN low (or the MODE pin
in SPI mode) returns the AD9266 to its normal operating mode.
Note that PDWN is referenced to the digital output driver
supply (DRVDD) and should not exceed that supply voltage.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering power-
When using the SPI interface, the data outputs and DCO can be
independently three-stated by using the programmable external
MODE pin. The MODE pin (OEB) function is enabled via Bits[6:5]
of Register 0x08.
If the MODE pin is configured to operate in traditional OEB
mode and the MODE pin is low, the output data drivers and
DCOs are enabled. If the MODE pin is high, the output data
drivers and DCOs are placed in a high impedance state. This
OEB function is not intended for rapid access to the data bus.
Note that the MODE pin is referenced to the digital output
driver supply (DRVDD) and should not exceed that supply
voltage.
Rev. B | Page 22 of 32
Data Sheet
AD9266
TIMING
The AD9266 provides latched data with a pipeline delay of
eight clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal.
Minimize the length of the output data lines and loads placed
on them to reduce transients within the AD9266. These
transients can degrade converter dynamic performance.
The lowest typical conversion rate of the AD9266 is 3 MSPS. At
clock rates below 3 MSPS, dynamic performance may degrade.
Data Clock Output (DCO)
The AD9266 provides a DCO signal that is intended for
capturing the data in an external register. The CMOS data outputs
are valid on the rising and falling edge of DCO. See Figure 2 for
a graphical timing description.
Table 12. Output Data Format
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
Condition (V)
< −VREF − 0.5 LSB
= −VREF
=0
= +VREF − 1.0 LSB
> +VREF − 0.5 LSB
Offset Binary Output Mode
0000 0000 0000 0000
0000 0000 0000 0000
1000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1111
Rev. B | Page 23 of 32
Twos Complement Mode
1000 0000 0000 0000
1000 0000 0000 0000
0000 0000 0000 0000
0111 1111 1111 1111
0111 1111 1111 1111
OR
1
0
0
0
1
AD9266
Data Sheet
OUTPUT TEST
The AD9266 includes various output test options to place
predictable values on the outputs of the AD9266.
OUTPUT TEST MODES
The output test options are described in Table 16 at Address 0x0D.
When an output test mode is enabled, the analog section of the
ADC is disconnected from the digital back end blocks and the
test pattern is run through the output formatting block. Some of
the test patterns are subject to output formatting, and some are
not. The PN generators from the PN sequence tests can be reset
by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be
performed with or without an analog signal (if present, the analog
signal is ignored), but they do require an encode clock. For more
information, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
Rev. B | Page 24 of 32
Data Sheet
AD9266
SERIAL PORT INTERFACE (SPI)
The AD9266 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through
a structured register space provided inside the ADC. The SPI gives
the user added flexibility and customization, depending on the
application. Addresses are accessed via the serial port and can
be written to or read from via the port. Memory is organized
into bytes that can be further divided into fields, which are
documented in the Memory Map section. For more detailed
operational information, see the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
The falling edge of CSB, in conjunction with the rising edge of
SCLK, determines the start of the framing. An example of the
serial timing and its definitions can be found in Figure 54 and
Table 5.
CONFIGURATION USING THE SPI
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and its length is determined
by the W0 and W1 bits, as shown in Figure 54.
Other modes involving the CSB pin are available. CSB can be
held low indefinitely, which permanently enables the device;
this is called streaming. CSB can stall high between bytes to
allow for additional external timing. When CSB is tied high,
SPI functions are placed in high impedance mode. This mode
turns on any SPI pin secondary functions.
Three pins define the SPI of this ADC: SCLK, SDIO, and CSB
(see Table 13). The SCLK (a serial clock) is used to synchronize
the read and write data presented from and to the ADC. SDIO
(serial data input/output) is a dual-purpose pin that allows data to
be sent and read from the internal ADC memory map registers.
The CSB (chip select bar) is an active-low control that enables
or disables the read and write cycles.
All data is composed of 8-bit words. The first bit of the first byte in
a multibyte serial data transfer frame indicates whether a read
command or a write command is issued. This allows the serial
data input/output (SDIO) pin to change direction from an input
to an output at the appropriate point in the serial frame.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. If the instruction is a readback
operation, performing a readback causes the serial data input/
output (SDIO) pin to change direction from an input to an output
at the appropriate point in the serial frame.
Table 13. Serial Port Interface Pins
Pin
SCLK
SDIO
CSB
Function
Serial clock. The serial shift clock input, which is used to
synchronize serial interface reads and writes.
Serial data input/output. A dual-purpose pin that
typically serves as an input or an output, depending on
the instruction being sent and the relative position in the
timing frame.
Chip select bar. An active-low control that gates the read
and write cycles.
tHIGH
tDS
tS
tDH
Data can be sent in MSB-first mode or in LSB-first mode. MSB
first is the default on power-up and can be changed via the SPI
port configuration register. For more information about this
and other features, see the AN-877 Application Note, Interfacing
to High Speed ADCs via SPI.
tCLK
tH
tLOW
CSB
SDIO DON’T CARE
DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
Figure 54. Serial Port Interface Timing Diagram
Rev. B | Page 25 of 32
D4
D3
D2
D1
D0
DON’T CARE
08678-023
SCLK DON’T CARE
AD9266
Data Sheet
HARDWARE INTERFACE
The pins described in Table 13 constitute the physical interface
between the programming device of the user and the serial port
of the AD9266. The SCLK pin and the CSB pin function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used for
other devices, it may be necessary to provide buffers between
this bus and the AD9266 to prevent these signals from transitioning at the converter inputs during critical sampling periods.
SDIO/PDWN and SCLK/DFS serve a dual function when the
SPI interface is not being used. When the pins are strapped to
DRVDD or ground during device power-on, they are associated
with a specific function. The Digital Outputs section describes
the strappable functions supported on the AD9266.
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SDIO/PDWN pin and the SCLK/DFS pin serve as standalone
CMOS-compatible control pins. When the device is powered up, it
is assumed that the user intends to use the pins as static control
lines for the power-down and output data format feature control. In
this mode, connect the CSB chip select to DRVDD, which
disables the serial port interface.
Table 14. Mode Selection
Pin
SDIO/PDWN
SCLK/DFS
External
Voltage
DRVDD
AGND (default)
DRVDD
AGND (default)
Configuration
Chip power-down mode
Normal operation (default)
Twos complement enabled
Offset binary enabled
SPI ACCESSIBLE FEATURES
Table 15 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in the AN-877 Application Note, Interfacing to High Speed ADCs
via SPI. The AD9266 part-specific features are described in
detail in Table 16.
Table 15. Features Accessible Using the SPI
Feature
Modes
Clock
Offset
Test I/O
Output Mode
Output Phase
Output Delay
Rev. B | Page 26 of 32
Description
Allows the user to set either power-down mode
or standby mode
Allows the user to access the DCS via the SPI
Allows the user to digitally adjust the converter
offset
Allows the user to set test modes to have known
data on output bits
Allows the user to set up outputs
Allows the user to set the output clock polarity
Allows the user to vary the DCO delay
Data Sheet
AD9266
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
DEFAULT VALUES
Each row in the memory map register table (see Table 16)
contains eight bit locations. The memory map is roughly
divided into four sections: the chip configuration registers
(Address 0x00 to Address 0x02); the device index and transfer
register (Address 0xFF); the program registers, including setup,
control, and test (Address 0x08 to Address 0x2A); and the
AD9266-specific customer SPI control register (Address 0x101).
After the AD9266 is reset, critical registers are loaded with
default values. The default values for the registers are given in
the memory map register table (see Table 16).
Table 16 documents the default hexadecimal value for each
hexadecimal address shown. The column with the heading
Bit 7 (MSB) is the start of the default hexadecimal value given.
For example, Address 0x2A, the OR/MODE select register,
has a hexadecimal default value of 0x01. This means that in
Address 0x2A, Bits[7:1] = 0, and Bit 0 = 1. This setting is the
default OR/MODE setting. The default value results in the
programmable external MODE/OR pin (Pin 23) functioning
as an out-of-range digital output. For more information on this
function and others, see the AN-877 Application Note, Interfacing
to High Speed ADCs via SPI. This application note details the
functions controlled by Register 0x00 to Register 0xFF. The
remaining register, Register 0x101, is documented in the
Memory Map Register Descriptions section that follows
Table 16.
Logic Levels
An explanation of logic level terminology follows:
“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
Transfer Register Map
Address 0x08 to Address 0x18 are shadowed. Writes to these
addresses do not affect part operation until a transfer command
is issued by writing 0x01 to Address 0xFF, setting the transfer bit.
This allows these registers to be updated internally and simultaneously when the transfer bit is set. The internal update takes
place when the transfer bit is set, and then the bit autoclears.
OPEN LOCATIONS
All address and bit locations that are not included in the SPI map
are not currently supported for this device. Unused bits of a valid
address location should be written with 0s. Writing to these locations is required only when part of an address location is open
(for example, Address 0x2A). If the entire address location is
open, it is omitted from the SPI map (for example, Address 0x13)
and should not be written.
Rev. B | Page 27 of 32
AD9266
Data Sheet
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 16 are not currently supported for this device.
Table 16.
Addr
Bit 7
(Hex) Register Name
(MSB)
Chip Configuration Registers
0x00
0
SPI port
configuration
0x01
Chip ID
0x02
Chip grade
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
LSB
first
Soft
reset
1
1
Soft
reset
LSB first
0
8-bit chip ID, Bits[7:0]
AD9266 = 0x78
Open
Speed grade ID, Bits[6:4] (identify
device variants of chip ID)
20 MSPS = 000
40 MSPS = 001
65 MSPS = 010
80 MSPS = 011
Device Index and Transfer Register
0xFF
Transfer
Program Registers
0x08
Modes
0x09
Clock
0x0B
Clock divide
0x0D
Test mode
0x10
Offset adjust
0x14
Output mode
External
Pin 23 mode
input enable
Read
only
Transfer
Open
External Pin 23
function when high
00 = full powerdown
01 = standby
10 = normal mode:
output disabled
11 = normal mode:
output enabled
Open
Open
00 = chip run
01 = full power-down
10 = standby
11 = chip wide digital
reset
Duty cycle
stabilize
Clock divider, Bits[2:0]
Clock divide ratio:
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
User test mode
Output test mode, Bits[3:0] (local)
Reset PN
Reset PN
long gen
short gen
00 = single
0000 = off (default)
0001 = midscale short
01 = alternate
0010 = positive FS
10 = single once
0011 = negative FS
11 = alternate once
0100 = alternating checkerboard
0101 = PN 23 sequence
0110 = PN 9 sequence
0111 = 1/0 word toggle
1000 = user input
1001 = 1/0 bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency
8-bit device offset adjustment, Bits[7:0] (local)
Offset adjust in LSBs from +127 to −128 (twos complement format)
Open
Open
00 = 3.3 V CMOS
Output
Output
00 = offset binary
disable
invert
01 = twos complement
10 = 1.8 V CMOS
10 = gray code
11 = offset binary
Rev. B | Page 28 of 32
0x18
Read
only
Open
Open
Default
Value
(Hex)
Comments
The nibbles are
mirrored so that
LSB- or MSB-first
mode registers
correctly, regardless
of shift mode.
Unique chip ID
used to differentiate
devices; read only.
Unique speed
grade ID used
to differentiate
devices; read only.
0x00
Synchronously
transfers data from
the master shift
register to the slave.
0x00
Determines various
generic modes of
chip operation.
0x01
Enable internal
duty cycle stabilizer
(DCS).
The divide ratio is
the value plus 1.
0x00
0x00
When set, the test
data is placed on
the output pins in
place of normal data.
0x00
Device offset trim.
0x00
Configures the
outputs and the
format of the data.
Data Sheet
AD9266
Addr
(Hex)
0x15
Register Name
Output adjust
0x16
Output phase
DCO output
polarity
0 = normal
1 = inverted
0x17
Output delay
Enable DCO
delay
Open
Enable
data
delay
0x19
USER_PATT1_LSB
B7
B6
B5
B4
0x1A
USER_PATT1_MSB
B15
B14
B13
0x1B
USER_PATT2_LSB
B7
B6
0x1C
USER_PATT2_MSB
B15
B14
0x2A
OR/MODE select
Bit 7
(MSB)
Bit 6
3.3 V DCO
drive strength
00 = 1 stripe (default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
AD9266-Specific Customer SPI Control Register
USR2
0x10
1
Bit 5
Bit 4
1.8 V DCO
drive strength
00 = 1 stripe
01 = 2 stripes
10 = 3 stripes (default)
11 = 4 stripes
Open
Bit 3
Bit 2
3.3 V data
drive strength
00 = 1 stripe (default)
01 = 2 stripes
10 = 3 stripes
11 = 4 stripes
Bit 0
Bit 1
(LSB)
1.8 V data drive strength
00 = 1 stripe
01 = 2 stripes
10 = 3 stripes (default)
11 = 4 stripes
Default
Value
(Hex)
0x22
B3
Input clock phase adjust, Bits[2:0]
(Value is number of input clock
cycles of phase delay)
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
DCO/data delay[2:0] (typical values)
000 = 0.56 ns
001 = 1.12 ns
010 = 1.68 ns
011 = 2.24 ns
100 = 2.80 ns
101 = 3.36 ns
110 = 3.92 ns
111 = 4.48 ns
B2
B1
B0
B12
B11
B10
B9
B8
0x00
B5
B4
B3
B2
B1
B0
0x00
B13
B12
B11
B10
B9
B8
0x00
0 = MODE
1 = OR
(default)
0x01
Disable
SDIO pulldown
0x08
Open
Open
Open
Enable
GCLK
detect
Rev. B | Page 29 of 32
Run
GCLK
Open
Comments
Determines CMOS
output drive
strength properties.
0x00
On devices that use
global clock divide,
determines which
phase of the divider
output is used to
supply the output
clock; internal
latching is
unaffected.
0x00
Sets the fine
output delay of the
output clock but
does not change
internal timing.
(Typical values)
0x00
User-defined
pattern, 1 LSB.
User-defined
pattern, 1 MSB.
User-defined
pattern, 2 LSB.
User-defined
pattern, 2 MSB.
Selects I/O
functionality in
conjunction with
Address 0x08 for
MODE (input) or
OR (output) on
External Pin 23.
Enables internal
oscillator for clock
rates of
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