AD9277

Octal LNA/VGA/AAF/14-Bit ADC and CW I/Q Demodulator AD9277 FEATURES 8 channels of LNA, VGA, AAF, ADC, and I/Q demodulator Low noise preamplifier (LNA) Input-referred noise: 0.75 nV/√Hz typical at 5 MHz (gain = 21.3 dB) SPI-programmable gain: 15.6 dB/17.9 dB/21.3 dB Single-ended input: VIN maximum = 733 mV p-p/ 550 mV p-p/367 mV p-p Dual-mode active input impedance matching Bandwidth (BW) > 100 MHz Full-scale (FS) output: 4.4 V p-p differential Variable gain amplifier (VGA) Attenuator range: −42 dB to 0 dB Postamp gain: 21 dB/24 dB/27 dB/30 dB Linear-in-dB gain control Antialiasing filter (AAF) Programmable second-order LPF from 8 MHz to 18 MHz Programmable HPF Analog-to-digital converter (ADC) 14 bits at 10 MSPS to 50 MSPS SNR: 73 dB SFDR: 75 dB Serial LVDS (ANSI-644, IEEE 1596.3 reduced range link) Data and frame clock outputs CW mode I/Q demodulator Individual programmable phase rotation Output dynamic range per channel >160 dBFS/√Hz Low power: 207 mW per channel at 14 bits/50 MSPS (TGC), 94 mW per channel for CW Doppler Flexible power-down modes Overload recovery in 48dB Figure 55. Gain Requirements of TGC Operation for a 14-Bit, 50 MSPS ADC Rev. 0 | Page 29 of 48 AD9277 Table 10. Sensitivity and Dynamic Range Trade-Offs 1, 2, 3 LNA Gain (V/V) 6 (dB) 15.6 Full-Scale Input (V p-p) 0.733 Input Noise (nV/√Hz) 0.98 Postamp Gain (dB) 21 24 27 30 21 24 27 30 21 24 27 30 VGA Channel Typical Output Dynamic Range (dB) GAIN+ = 0 V 68.9 67.4 65.3 62.8 68.9 67.4 65.3 62.8 68.9 67.4 65.3 62.8 4 8 17.9 0.550 0.86 12 21.3 0.367 0.75 GAIN+ = 1.6 V 65.8 63.4 60.8 57.9 65.1 62.7 60.0 57.1 63.7 61.1 58.3 55.4 5 Input-Referred Noise 6 @ GAIN+ = 1.6 V (nV/√Hz) 1.312 1.241 1.204 1.185 1.090 1.040 1.014 1.000 0.876 0.848 0.833 0.826 1 2 LNA: output full scale = 4.4 V p-p differential. Filter: loss ≈ 1 dB, NBW = 16.67 MHz, GAIN− = 0.8 V. 3 ADC: 50 MSPS, 73 dB SNR, 2 V p-p full-scale input. 4 Output dynamic range at minimum VGA gain (VGA dominated). 5 Output dynamic range at maximum VGA gain (LNA dominated). 6 Channel noise at maximum VGA gain. Table 10 demonstrates the sensitivity and dynamic range trade-offs that can be achieved relative to various LNA and VGA gain settings. For example, when the VGA is set for the minimum gain voltage, the TGC path is dominated by VGA noise and achieves the maximum output SNR. However, as the postamp gain options are increased, the input-referred noise is reduced and the SNR is degraded. If the VGA is set for the maximum gain voltage, the TGC path is dominated by LNA noise and achieves the lowest inputreferred noise, but with degraded output SNR. The higher the TGC (LNA + VGA) gain, the lower the output SNR. As the postamp gain is increased, the input-referred noise is reduced. At low gains, the VGA should limit the system noise performance (SNR); at high gains, the noise is defined by the source and the LNA. The maximum voltage swing is bound by the full-scale peak-to-peak ADC input voltage (2 V p-p). Both the LNA and VGA have full-scale limitations within each section of the TGC path. These limitations are dependent on the gain setting of each function block and on the voltage applied to the GAIN+ and GAIN− pins. The LNA has three limitations, or full-scale settings, that can be applied through the SPI. Similarly, the VGA has four postamp gain settings that can be applied through the SPI. The voltage applied to the GAIN± pins determines which amplifier (the LNA or VGA) saturates first. The maximum signal input level that can be applied as a function of voltage on the GAIN± pins for the selectable gain options of the SPI is shown in Figure 56 to Figure 58. 0.9 0.8 INPUT FULL-SCALE (V p-p) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 PGA GAIN = 27dB PGA GAIN = 30dB 0 0.2 0.4 0.6 0.8 1.0 GAIN+ (V) 1.2 1.4 1.6 08181-050 PGA GAIN = 21dB PGA GAIN = 24dB 0 Figure 56. LNA with 15.6 dB Gain Setting/VGA Full-Scale Limitations Rev. 0 | Page 30 of 48 AD9277 0.6 0.5 INPUT FULL-SCALE (V p-p) PGA GAIN = 21dB 0.4 PGA GAIN = 24dB 0.3 0.2 0.1 PGA GAIN = 27dB PGA GAIN = 30dB 0 0.2 0.4 0.6 0.8 1.0 GAIN+ (V) 1.2 1.4 1.6 08181-051 0 The input of the VGA is a 14-stage differential resistor ladder with 3.5 dB per tap. The resulting total gain range is 42 dB, which allows for range loss at the endpoints. The effective input resistance per side is 180 Ω nominally for a total differential resistance of 360 Ω. The ladder is driven by a fully differential input signal from the LNA. LNA outputs are dc-coupled to avoid external decoupling capacitors. The common-mode voltage of the attenuator and the VGA is controlled by an amplifier that uses the same midsupply voltage derived in the LNA, permitting dc coupling of the LNA to the VGA without introducing large offsets due to commonmode differences. However, any offset from the LNA becomes amplified as the gain increases, producing an exponentially increasing VGA output offset. The input stages of the X-AMP are distributed along the ladder, and a biasing interpolator, controlled by the gain interface, determines the input tap point. With overlapping bias currents, signals from successive taps merge to provide a smooth attenuation range from −42 dB to 0 dB. This circuit technique results in linear-in-dB gain law conformance and low distortion levels—only deviating ±0.5 dB or less from the ideal. The gain slope is monotonic with respect to the control voltage and is stable with variations in process, temperature, and supply. The X-AMP inputs are part of a programmable gain feedback amplifier that completes the VGA. Its bandwidth is approximately 100 MHz. The input stage is designed to reduce feedthrough to the output and to ensure excellent frequency response uniformity across the gain setting. Figure 57. LNA with 17.9 dB Gain Setting/VGA Full-Scale Limitations 0.40 0.35 PGA GAIN = 21dB INPUT FULL SCALE (V p-p) 0.30 PGA GAIN = 24dB 0.25 0.20 0.15 PGA GAIN = 27dB 0.10 PGA GAIN = 30dB 0.05 08181-052 0 0 0.2 0.4 0.6 0.8 GAIN+ (V) 1.0 1.2 1.4 1.6 Gain Control The gain control interface, GAIN±, is a differential input. VGAIN varies the gain of all VGAs through the interpolator by selecting the appropriate input stages connected to the input attenuator. For GAIN− at 0.8 V, the nominal GAIN+ range for 28.5 dB/V is 0 V to 1.6 V, with the best gain linearity from about 0.16 V to 1.44 V, where the error is typically less than ±0.5 dB. For GAIN+ voltages greater than 1.44 V and less than 0.16 V, the error increases. The value of GAIN+ can exceed the supply voltage by 1 V without gain foldover. Gain control response time is less than 750 ns to settle within 10% of the final value for a change from minimum to maximum gain. The GAIN+ and GAIN− pins can be interfaced in one of two ways. Using a single-ended method, a Kelvin type of connection to ground can be used, as shown in Figure 60. For driving multiple devices, it is preferable to use a differential method, as shown in Figure 61. In either method, the GAIN+ and GAIN− pins should be dc-coupled and driven to accommodate a 1.6 V full-scale input. 08181-053 Figure 58. LNA with 21.3 dB Gain Setting/VGA Full-Scale Limitations Variable Gain Amplifier (VGA) The differential X-AMP VGA provides precise input attenuation and interpolation. It has a low input-referred noise of 3.8 nV/√Hz and excellent gain linearity. A simplified block diagram is shown in Figure 59. GAIN± GAIN INTERPOLATOR + gm POSTAMP VIP 3.5dB VIN – POSTAMP GAIN+ 100Ω 0.01µF 50Ω 0V TO 1.6V DC 08181-054 Figure 59. Simplified VGA Schematic GAIN– 0.01µF KELVIN CONNECTION Figure 60. Single-Ended GAIN+, GAIN− Pin Configuration Rev. 0 | Page 31 of 48 AD9277 AVDD2 499Ω GAIN+ 100Ω 0.01µF GAIN– 100Ω 0.01µF ±0.4V DC AT 0.8V CM 499Ω 0.8V CM 523Ω 10kΩ 08181-055 31.3kΩ ±0.8V DC 50Ω AD8138 ±0.4V DC AT 0.8V CM 499Ω The antialiasing filter is a combination of a single-pole highpass filter and a second-order low-pass filter. The high-pass filter can be configured at a ratio of the low-pass filter cutoff. This is selectable through the SPI. The filter uses on-chip tuning to trim the capacitors and, in turn, to set the desired cutoff frequency and reduce variations. The default −3 dB low-pass filter cutoff is 1/3 or 1/4.5 the ADC sample clock rate. The cutoff can be scaled to 0.7, 0.8, 0.9, 1, 1.1, 1.2, or 1.3 times this frequency through the SPI. The cutoff tolerance is maintained from 8 MHz to 18 MHz. 4kΩ C 30C Figure 61. Differential GAIN+, GAIN− Pin Configuration VGA Noise In a typical application, a VGA compresses a wide dynamic range input signal to within the input span of an ADC. The input-referred noise of the LNA limits the minimum resolvable input signal, whereas the output-referred noise, which depends primarily on the VGA, limits the maximum instantaneous dynamic range that can be processed at any one particular gain control voltage. This latter limit is set in accordance with the total noise floor of the ADC. Output-referred noise as a function of GAIN+ is shown in Figure 11, Figure 12, and Figure 14 for the short-circuit input conditions. The input noise voltage is simply equal to the output noise divided by the measured gain at each point in the control range. The output-referred noise is a flat 60 nV/√Hz (postamp gain = 24 dB) over most of the gain range because it is dominated by the fixed output-referred noise of the VGA. At the high end of the gain control range, the noise of the LNA and of the source prevails. The input-referred noise reaches its minimum value near the maximum gain control voltage, where the inputreferred contribution of the VGA is miniscule. At lower gains, the input-referred noise and, therefore, the noise figure, increase as the gain decreases. The instantaneous dynamic range of the system is not lost, however, because the input capacity increases as the input-referred noise increases. The contribution of the ADC noise floor has the same dependence. The important relationship is the magnitude of the VGA output noise floor relative to that of the ADC. Gain control noise is a concern in very low noise applications. Thermal noise in the gain control interface can modulate the channel gain. The resultant noise is proportional to the output signal level and is usually evident only when a large signal is present. The gain interface includes an on-chip noise filter, which significantly reduces this effect at frequencies above 5 MHz. Care should be taken to minimize noise impinging at the GAIN± inputs. An external RC filter can be used to remove VGAIN source noise. The filter bandwidth should be sufficient to accommodate the desired control bandwidth. 4kΩ 10kΩ/n 4kΩ 2kΩ 4C 2kΩ C 08181-056 30C C = 0.8pF TO 5.1pF n = 0 TO 7 4kΩ Figure 62. Simplified Antialiasing Filter Schematic Tuning is normally off to avoid changing the capacitor settings during critical times. The tuning circuit is enabled and disabled through the SPI. Initializing the tuning of the filter must be performed after initial power-up and after reprogramming the filter cutoff scaling or ADC sample rate. Occasional retuning during an idle time is recommended to compensate for temperature drift. A total of eight SPI-programmable settings allows the user to vary the high-pass filter cutoff frequency as a function of the low-pass cutoff frequency. Two examples are shown in Table 11: one is for an 8 MHz low-pass cutoff frequency, and the other is for an 18 MHz low-pass cutoff frequency. In both cases, as the ratio decreases, the amount of rejection on the low-end frequencies increases. Therefore, making the entire AAF frequency pass band narrow can reduce low frequency noise or maximize dynamic range for harmonic processing. Table 11. SPI-Selectable High-Pass Filter Cutoff Options High-Pass Cutoff Frequency Low-Pass Cutoff Low-Pass Cutoff = 8 MHz = 18 MHz 387 kHz 872 kHz 698 kHz 1.571 MHz 1.010 MHz 2.273 MHz 1.323 MHz 2.978 MHz 1.638 MHz 3.685 MHz 1.953 MHz 4.394 MHz 2.270 MHz 5.107 MHz 2.587 MHz 5.822 MHz Antialiasing Filter (AAF) The filter that the signal reaches prior to the ADC is used to reject dc signals and to band limit the signal for antialiasing. Figure 62 shows the architecture of the filter. SPI Setting 0 1 2 3 4 5 6 7 1 Ratio1 20.65 11.45 7.92 6.04 4.88 4.10 3.52 3.09 Ratio = low-pass filter cutoff frequency/high-pass filter cutoff frequency. Rev. 0 | Page 32 of 48 AD9277 ADC The AD9277 uses a pipelined ADC architecture. The quantized output from each stage is combined into a 14-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on preceding samples. Sampling occurs on the rising edge of the clock. The output staging block aligns the data, corrects errors, and passes the data to the output buffers. The data is then serialized and aligned to the frame and output clocks. 3.3V 50Ω * VFAC3 OUT AD951x FAMILY 0.1µF CLK LVDS DRIVER CLK 100Ω 0.1µF CLK– 08181-059 0.1µF CLK+ ADC 0.1µF *50Ω RESISTOR IS OPTIONAL. Figure 65. Differential LVDS Sample Clock CLOCK INPUT CONSIDERATIONS For optimum performance, the AD9277 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally and require no additional bias. Figure 63 shows the preferred method for clocking the AD9277. A low jitter clock source, such as the Valpey Fisher oscillator VFAC3-BHL−50 MHz, is converted from single-ended to differential using an RF transformer. The back-to-back Schottky diodes across the secondary transformer limit clock excursions into the AD9277 to approximately 0.8 V p-p differential. This helps to prevent the large voltage swings of the clock from feeding through to other portions of the AD9277, and it preserves the fast rise and fall times of the signal, which are critical to low jitter performance. 3.3V MINI-CIRCUITS ADT1-1WT, 1:1Z 0.1µF XFMR 0.1µF 0.1µF SCHOTTKY DIODES: HSM2812 In some applications, it is acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, CLK+ should be driven directly from a CMOS gate, and the CLK− pin should be bypassed to ground with a 0.1 μF capacitor in parallel with a 39 kΩ resistor (see Figure 66). Although the CLK+ input circuit supply is AVDD1 (1.8 V), this input is designed to withstand input voltages of up to 3.3 V, making the selection of the drive logic voltage very flexible. 3.3V VFAC3 OUT 0.1µF CLK AD951x FAMILY OPTIONAL 0.1µF 100Ω 50Ω * CMOS DRIVER CLK CLK+ ADC CLK– 08181-060 0.1µF 0.1µF *50Ω RESISTOR IS OPTIONAL. 39kΩ Figure 66. Single-Ended 1.8 V CMOS Sample Clock 3.3V VFAC3 OUT 0.1µF CLK AD951x FAMILY OPTIONAL 0.1µF 100Ω 0.1µF OUT VFAC3 CLK+ 50Ω 100Ω 50Ω * ADC CLK– 08181-057 CMOS DRIVER CLK CLK+ ADC 0.1µF CLK– 08181-061 0.1µF Figure 63. Transformer-Coupled Differential Clock If a low jitter clock is available, another option is to ac-couple a differential PECL signal to the sample clock input pins, as shown in Figure 64. The AD951x family of clock drivers offers excellent jitter performance. 3.3V 50Ω* VFAC3 OUT *50Ω RESISTOR IS OPTIONAL. Figure 67. Single-Ended 3.3 V CMOS Sample Clock Clock Duty Cycle Considerations Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to the clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9277 contains a duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9277. When the DCS is on, noise and distortion performance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, keep in mind that the dynamic range performance can be affected when operated in this mode. See Table 18 for more details on using this feature. AD951x FAMILY 0.1µF CLK PECL DRIVER CLK 240Ω 240Ω 08181-058 0.1µF CLK+ 100Ω 0.1µF CLK– ADC 0.1µF *50Ω RESISTOR IS OPTIONAL. Figure 64. Differential PECL Sample Clock Rev. 0 | Page 33 of 48 AD9277 The duty cycle stabilizer uses a delay-locked loop (DLL) to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately eight clock cycles to allow the DLL to acquire and lock to the new rate. 300 250 IAVDD1 Clock Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated as follows: SNR Degradation = 20 × log10(1/2 × π × fA × tJ) In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter. IF undersampling applications are particularly sensitive to jitter (see Figure 68). The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9277. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources, such as the Valpey Fisher VFAC3 series. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock during the last step. Refer to the AN-501 Application Note and the AN-756 Application Note for more in-depth information about how jitter performance relates to ADCs (visit www.analog.com). 130 120 110 100 16 BITS 14 BITS 12 BITS 10 BITS 8 BITS 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps 10 100 ANALOG INPUT FREQUENCY (MHz) 1000 08181-062 CURRENT (mA) 200 150 100 IDRVDD 50 0 10 20 30 40 50 SAMPLING FREQUENCY (MSPS) Figure 69. Supply Current vs. fSAMPLE for fIN = 5 MHz 220 215 210 POWER/CHANNEL (mW) 205 200 195 190 185 180 175 0 10 20 30 40 50 08181-064 170 RMS CLOCK JITTER REQUIREMENT SAMPLING FREQUENCY (MSPS) Figure 70. Power per Channel vs. fSAMPLE for fIN = 5 MHz SNR (dB) 90 80 70 60 50 40 30 1 The AD9277 features scalable LNA bias currents (see Table 18, Register 0x12). The default LNA bias current settings are high. Figure 71 shows the typical reduction of AVDD2 current with each bias setting. It is also recommended that the LNA offset be adjusted using Register 0x10 (see Table 18) when the LNA bias setting is low. HIGH LNA BIAS SETTING Figure 68. Ideal SNR vs. Input Frequency and Jitter MID-HIGH Power Dissipation and Power-Down Mode As shown in Figure 69 and Figure 70, the power dissipated by the AD9277 is proportional to its sample rate. The digital power dissipation does not vary significantly because it is determined primarily by the DRVDD supply and the bias current of the LVDS output drivers. MID-LOW LOW 08181-065 0 50 100 150 200 250 300 TOTAL AVDD2 CURRENT (mA) 350 400 Figure 71. AVDD2 Current at Different LNA Bias Settings, fSAMPLE = 50 MSPS Rev. 0 | Page 34 of 48 08181-063 0 AD9277 By asserting the PDWN pin high, the AD9277 is placed into power-down mode. In this state, the device typically dissipates 5 mW. During power-down, the LVDS output drivers are placed into a high impedance state. The AD9277 returns to normal operating mode when the PDWN pin is pulled low. This pin is both 1.8 V and 3.3 V tolerant. By asserting the STBY pin high, the AD9277 is placed into a standby mode. In this state, the device typically dissipates 200 mW. During standby, the entire part is powered down except for the internal references. The LVDS output drivers are placed into a high impedance state. This mode is well suited for applications that require power savings because it allows the device to be powered down when not in use and then quickly powered up. The time to power the device back up is also greatly reduced. The AD9277 returns to normal operating mode when the STBY pin is pulled low. This pin is both 1.8 V and 3.3 V tolerant. In power-down mode, low power dissipation is achieved by shutting down the reference, reference buffer, PLL, and biasing networks. The decoupling capacitors on VREF are discharged when entering power-down mode and must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in the power-down mode: shorter cycles result in proportionally shorter wake-up times. To restore the device to full operation, approximately 0.5 ms is required when using the recommended 1 μF and 0.1 μF decoupling capacitors on the VREF pin and the 0.01 μF decoupling capacitors on the GAIN± pins. Most of this time is dependent on the gain decoupling: higher value decoupling capacitors on the GAIN± pins result in longer wake-up times. A number of other power-down options are available when using the SPI port interface. The user can individually power down each channel or put the entire device into standby mode. This allows the user to keep the internal PLL powered up when fast wake-up times are required. The wake-up time is slightly dependent on gain. To achieve a 1 μs wake-up time when the device is in standby mode, 0.8 V must be applied to the GAIN± pins. See Table 18 for more details on using these features. The AD9277 LVDS outputs facilitate interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments. Single point-to-point network topologies are recommended with a 100 Ω termination resistor placed as close to the receiver as possible. No far-end receiver termination and poor differential trace routing may result in timing errors. It is recommended that the trace length be no longer than 24 inches and that the differential output traces be kept close together and at equal lengths. An example of the FCO, DCO, and data stream with proper trace length and position is shown in Figure 72. CH1 500mV/DIV = DCO CH2 500mV/DIV = DATA CH3 500mV/DIV = FCO 5.0ns/DIV Figure 72. LVDS Output Timing Example in ANSI-644 Mode (Default) An example of the LVDS output using the ANSI-644 standard (default) data eye and a time interval error (TIE) jitter histogram with trace lengths less than 24 inches on regular FR-4 material is shown in Figure 73. Figure 74 shows an example of the trace lengths exceeding 24 inches on regular FR-4 material. Notice that the TIE jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position; therefore, the user must determine whether the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches. Additional SPI options allow the user to further increase the internal termination (and therefore increase the current) of all eight outputs in order to drive longer trace lengths (see Figure 75). Even though this produces sharper rise and fall times on the data edges, is less prone to bit errors, and improves frequency distribution (see Figure 75), the power dissipation of the DRVDD supply increases when this option is used. In cases that require increased driver strength to the DCO± and FCO± outputs because of load mismatch, the user can double the drive strength by setting Bit 0 in Register 0x15. Note that this feature cannot be used with Bits[5:4] in Register 0x15 because these bits take precedence over this feature. See Table 18 for more details. DIGITAL OUTPUTS AND TIMING The AD9277 differential outputs conform to the ANSI-644 LVDS standard on default power-up. This can be changed to a low power, reduced signal option similar to the IEEE 1596.3 standard via the SPI, using Register 0x14, Bit 6. This LVDS standard can further reduce the overall power dissipation of the device by approximately 36 mW. The LVDS driver current is derived on chip and sets the output current at each output equal to a nominal 3.5 mA. A 100 Ω differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver. Rev. 0 | Page 35 of 48 08181-066 AD9277 600 400 EYE: ALL BITS ULS: 2398/2398 EYE DIAGRAM VOLTAGE (V) 400 300 200 100 0 –100 –200 –300 –400 EYE: ALL BITS ULS: 2399/2399 EYE DIAGRAM VOLTAGE (V) 200 100 0 –100 –200 –400 –600 –1.5ns –1.0ns –0.5ns 0ns 0.5ns 1.0ns 1.5ns –1.5ns –1.0ns –0.5ns 0ns 0.5ns 1.0ns 1.5ns 25 25 TIE JITTER HISTOGRAM (Hits) 15 TIE JITTER HISTOGRAM (Hits) 20 20 15 10 10 5 5 08181-067 0 –200ps –100ps 0ps 100ps 200ps 0 –200ps –100ps 0ps 100ps 200ps Figure 73. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths of Less Than 24 Inches on Standard FR-4 Figure 74. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths of Greater Than 24 Inches on Standard FR-4 Rev. 0 | Page 36 of 48 08181-068 AD9277 600 EYE: ALL BITS 400 EYE DIAGRAM VOLTAGE (V) ULS: 2396/2396 200 0 –200 Two output clocks are provided to assist in capturing data from the AD9277. DCO± is used to clock the output data and is equal to six times the sampling clock rate. Data is clocked out of the AD9277 and must be captured on the rising and falling edges of DCO±, which supports double data rate (DDR) capturing. The frame clock output (FCO±) is used to signal the start of a new output byte and is equal to the sampling clock rate. See the timing diagram shown in Figure 2 for more information. When using the serial port interface (SPI), the DCO± phase can be adjusted in 60° increments relative to the data edge. This enables the user to refine system timing margins if required. The default DCO± timing, as shown in Figure 2, is 180° relative to the output data edge. An 8-, 10-, or 12-bit serial stream can also be initiated from the SPI. This allows the user to implement different serial streams and to test the device’s compatibility with lower and higher resolution systems. When changing the resolution to an 8-, 10-, or 12-bit serial stream, the data stream is shortened. When using the SPI, all of the data outputs can also be inverted from their nominal state by setting Bit 2 in the output mode register (Address 0x14). This is not to be confused with inverting the serial stream to an LSB first mode. In default mode, as shown in Figure 2, the MSB is represented first in the data output serial stream. However, this order can be inverted so that the LSB is represented first in the data output serial stream (see Figure 3). There are 14 digital output test pattern options available that can be initiated through the SPI. This feature is useful when validating receiver capture and timing. Refer to Table 13 for the output bit sequencing options available. Some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. Note that some patterns may not adhere to the data format select option. In addition, custom user-defined test patterns can be assigned in the user pattern registers (Address 0x19 through Address 0x1C). All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths in order to verify data capture to the receiver. The PN sequence short pattern produces a pseudorandom bit sequence that repeats itself every 29 − 1 bits, or 511 bits. A description of the PN sequence short and how it is generated can be found in Section 5.1 of the ITU-T O.150 (05/96) standard. The only difference is that the starting value is a specific value instead of all 1s (see Table 14 for the initial values). –400 –600 –1.5ns –1.0ns –0.5ns 0ns 0.5ns 1.0ns 1.5ns 25 TIE JITTER HISTOGRAM (Hits) 20 15 10 5 0 –200ps –100ps 0ps 100ps 200ps Figure 75. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω Termination On and Trace Lengths of Greater Than 24 Inches on Standard FR-4 The format of the output data is offset binary by default. Table 12 provides an example of the output coding format. To change the output data format to twos complement, see the Memory Map section. Table 12. Digital Output Coding Code 16383 8192 8191 0 (VIN+) − (VIN−), Input Span = 2 V p-p (V) +1.00 0.00 −0.000488 −1.00 Digital Output Offset Binary (D13 to D0) 11 1111 1111 1111 10 0000 0000 0000 01 1111 1111 1111 00 0000 0000 0000 Data from each ADC is serialized and provided on a separate channel. The data rate for each serial stream is equal to 14 bits times the sample clock rate, with a maximum of 700 Mbps (14 bits × 50 MSPS = 700 Mbps). The lowest typical conversion rate is 10 MSPS, but the PLL can be set up for encode rates as low as 5 MSPS via the SPI if lower sample rates are required for a specific application. See Table 18 for details on enabling this feature. Rev. 0 | Page 37 of 48 08181-069 AD9277 Table 13. Flexible Output Test Modes Output Test Mode Bit Sequence 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Pattern Name Off (default) Midscale short +Full-scale short −Full-scale short Checkerboard PN sequence long PN sequence short One-/zero-word toggle User input 1-/0-bit toggle 1× sync One bit high Mixed bit frequency Digital Output Word 1 N/A 10 0000 0000 0000 11 1111 1111 1111 00 0000 0000 0000 10 1010 1010 1010 N/A N/A 11 1111 1111 1111 Register 0x19 and Register 0x1A 10 1010 1010 1010 00 0000 0011 1111 10 0000 0000 0000 10 1010 0011 0011 Digital Output Word 2 N/A Same Same Same 01 0101 0101 0101 N/A N/A 00 0000 0000 0000 Register 0x1B and Register 0x1C N/A N/A N/A N/A Subject to Data Format Select N/A Yes Yes Yes No Yes Yes No No No No No No The PN sequence long pattern produces a pseudorandom bit sequence that repeats itself every 223 − 1 bits, or 8,388,607 bits. A description of the PN sequence long and how it is generated can be found in Section 5.6 of the ITU-T O.150 (05/96) standard. The only differences are that the starting value is a specific value instead of all 1s and that the AD9277 inverts the bit stream with relation to the ITU-T standard (see Table 14 for the initial values). Table 14. PN Sequence Sequence PN Sequence Short PN Sequence Long Initial Value 0x0DF 0x29B80A First Three Output Samples (MSB First) 0x37E4, 0x3533, 0x0063 0x191F, 0x35C2, 0x2359 RBIAS Pin To set the internal core bias current of the ADC, place a resistor nominally equal to 10.0 kΩ to ground at the RBIAS pin. Using a resistor other than the recommended 10.0 kΩ resistor for RBIAS degrades the performance of the device. Therefore, it is imperative that at least a 1% tolerance on this resistor be used to achieve consistent performance. Voltage Reference A stable and accurate 0.5 V voltage reference is built into the AD9277. This is gained up internally by a factor of 2, setting VREF to 1.0 V, which results in a full-scale differential input span of 2.0 V p-p for the ADC. VREF is set internally by default, but the VREF pin can be driven externally with a 1.0 V reference to achieve more accuracy. However, the AD9277 does not support ADC full-scale ranges below 2.0 V p-p. When applying the decoupling capacitors to the VREF pin, use ceramic, low ESR capacitors. These capacitors should be close to the reference pin and on the same layer of the PCB as the AD9277. The VREF pin should have both a 0.1 μF capacitor and a 1 μF capacitor connected in parallel to the analog ground. These capacitor values are recommended for the ADC to properly settle and acquire the next valid sample. The reference settings can be selected using the SPI. The settings allow two options: using the internal reference or using an external reference. The internal reference option is the default setting and has a resulting differential span of 2 V p-p. Table 15. SPI-Selectable Reference Settings SPI-Selected Mode External Reference Internal Reference (Default) Resulting VREF (V) N/A 1.0 Resulting Differential Span (V p-p) 2 × external reference 2.0 See the Memory Map section for information on how to change these additional digital output timing features through the SPI. SDIO Pin This pin is required to operate the SPI. It has an internal 30 kΩ pull-down resistor that pulls this pin low and is only 1.8 V tolerant. If applications require that this pin be driven from a 3.3 V logic level, insert a 1 kΩ resistor in series with this pin to limit the current. SCLK Pin This pin is required to operate the SPI port interface. It has an internal 30 kΩ pull-down resistor that pulls this pin low and is both 1.8 V and 3.3 V tolerant. CSB Pin This pin is required to operate the SPI port interface. It has an internal 70 kΩ pull-up resistor that pulls this pin high and is both 1.8 V and 3.3 V tolerant. Rev. 0 | Page 38 of 48 AD9277 SERIAL PORT INTERFACE (SPI) The AD9277 serial port interface allows the user to configure the signal chain for specific functions or operations through a structured register space provided inside the chip. The SPI offers the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields, as documented in the Memory Map section. Detailed operational information can be found in the Analog Devices, Inc., AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Three pins define the serial port interface, or SPI: SCLK, SDIO, and CSB (see Table 16). The SCLK (serial clock) pin is used to synchronize the read and write data presented to the device. The SDIO (serial data input/output) pin is a dual-purpose pin that allows data to be sent to and read from the internal memory map registers of the device. The CSB (chip select bar) pin is an active low control that enables or disables the read and write cycles. Table 16. Serial Port Pins Pin SCLK SDIO Function Serial clock. Serial shift clock input. SCLK is used to synchronize serial interface reads and writes. Serial data input/output. Dual-purpose pin that typically serves as an input or an output, depending on the instruction sent and the relative position in the timing frame. Chip select bar (active low). This control gates the read and write cycles. CSB The falling edge of CSB in conjunction with the rising edge of SCLK determines the start of the framing sequence. During an instruction phase, a 16-bit instruction is transmitted, followed by one or more data bytes, which is determined by Bit Field W0 and Bit Field W1. An example of the serial timing and its definitions can be found in Figure 76 and Table 17. tDS tS CSB tHIGH tDH tLOW tCLK tH SCLK DON’T CARE DON’T CARE SDIO DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE Figure 76. Serial Timing Details Table 17. Serial Timing Definitions Parameter tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO tDIS_SDIO Timing (ns min) 5 2 40 5 2 16 16 10 10 Description Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the clock Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 76) Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 76) Rev. 0 | Page 39 of 48 08181-072 AD9277 During normal operation, CSB is used to signal to the device that SPI commands are to be received and processed. When CSB is brought low, the device processes SCLK and SDIO to execute instructions. Normally, CSB remains low until the communication cycle is complete. However, if connected to a slow device, CSB can be brought high between bytes, allowing older microcontrollers enough time to transfer data into shift registers. CSB can be stalled when transferring one, two, or three bytes of data. When W0 and W1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until CSB is taken high to end the communication cycle. This allows complete memory transfers without the need for additional instructions. Regardless of the mode, if CSB is taken high in the middle of a byte transfer, the SPI state machine is reset and the device waits for a new instruction. In addition to the operation modes, the SPI port can be configured to operate in different manners. For applications that do not require a control port, the CSB line can be tied and held high. This places the remainder of the SPI pins in their secondary mode (see the AN-877 Application Note). CSB can also be tied low to enable 2-wire mode. When CSB is tied low, SCLK and SDIO are the only pins required for communication. Although the device is synchronized during power-up, caution must be exercised when using 2-wire mode to ensure that the serial port remains synchronized with the CSB line. When operating in 2-wire mode, it is recommended that a 1-, 2-, or 3-byte transfer be used exclusively. Without an active CSB line, streaming mode can be entered but not exited. In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used to both program the chip and to read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the serial data input/output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. Data can be sent in MSB first mode or LSB first mode. MSB first mode is the default at power-up and can be changed by adjusting the configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. HARDWARE INTERFACE The pins described in Table 16 constitute the physical interface between the user’s programming device and the serial port of the AD9277. The SCLK and CSB pins function as inputs when using the SPI. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. If multiple SDIO pins share a common connection, ensure that proper VOH levels are met. Figure 77 shows the number of SDIO pins that can be connected together and the resulting VOH level, assuming the same load for each AD9277. 1.800 1.795 1.790 1.785 1.780 1.775 1.770 1.765 1.760 1.755 1.750 1.745 1.740 1.735 1.730 1.725 1.720 1.715 VOH (V) 0 10 20 30 40 50 60 70 80 90 100 NUMBER OF SDIO PINS CONNECTED TOGETHER Figure 77. SDIO Pin Loading This interface is flexible enough to be controlled by either serial PROMs or PIC microcontrollers, providing the user with an alternative method, other than a full SPI controller, for programming the device (see the AN-812 Application Note). Rev. 0 | Page 40 of 48 08181-071 AD9277 MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map register table has eight bit locations. The memory map is roughly divided into three sections: the chip configuration register map (Address 0x00 to Address 0x02), the device index and transfer register map (Address 0x04 to Address 0xFF), and the program register map (Address 0x08 to Address 0x2D). The leftmost column of the memory map indicates the register address, and the default value is shown in the second rightmost column. The Bit 7 (MSB) column is the start of the default hexadecimal value given. For example, Address 0x09, the clock register, has a default value of 0x01, meaning that Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. This setting is the default for the duty cycle stabilizer in the on condition. By writing a 0 to Bit 0 of this address, followed by 0x01 in Register 0xFF (the transfer bit), the duty cycle stabilizer is turned off. It is important to follow each writing sequence with a transfer bit to update the SPI registers. All registers except Register 0x00, Register 0x02, Register 0x04, Register 0x05, and Register 0xFF are buffered with a master slave latch and require writing to the transfer bit. For more information on this and other functions, consult the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. RESERVED LOCATIONS Undefined memory locations should not be written to except when writing the default values suggested in this data sheet. Addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up. DEFAULT VALUES After a reset, critical registers are automatically loaded with default values. These values are indicated in Table 18, where an X refers to an undefined feature. LOGIC LEVELS An explanation of various registers follows: “bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” Similarly, “bit is cleared” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.” Rev. 0 | Page 41 of 48 AD9277 Table 18. AD9277 Memory Map Registers Addr. Bit 7 (Hex) Register Name (MSB) Chip Configuration Registers 0x00 chip_port_config 0 Bit 6 LSB first 1 = on 0 = off (default) Bit 5 Soft reset 1 = on 0 = off (default) Bit 4 1 Bit 3 1 Bit 2 Soft reset 1 = on 0 = off (default) Bit 1 LSB first 1 = on 0 = off (default) Bit 0 (LSB) 0 Default Value 0x18 Comments Nibbles should be mirrored so that LSB or MSB first mode is set correctly regardless of shift mode. Default is unique chip ID, different for each device. Read-only register. Child ID used to differentiate ADC speed power modes. 0x01 chip_id Chip ID Bits[7:0] (AD9277 = 0x73, default) 0x02 chip_grade X X Child ID[5:4] (identify device variants of chip ID) 00 = 40 MSPS (default) 01 = 50 MSPS X X X X X X 0x00 Device Index and Transfer Registers 0x04 device_index_2 X X 0x05 device_index_1 X X 0xFF device_update X X Clock Channel DCO± 1 = on 0 = off (default) X Clock Channel FCO± 1 = on 0 = off (default) X Data Channel H 1 = on (default) 0 = off Data Channel D 1 = on (default) 0 = off X Data Channel G 1 = on (default) 0 = off Data Channel C 1 = on (default) 0 = off X Data Channel F 1 = on (default) 0 = off Data Channel B 1 = on (default) 0 = off X Data Channel E 1 = on (default) 0 = off Data Channel A 1 = on (default) 0 = off SW transfer 1 = on 0 = off (default) 0x0F Bits are set to determine which on-chip device receives the next write command. Bits are set to determine which on-chip device receives the next write command. Synchronously transfers data from the master shift register to the slave. Determines generic modes of chip operation (global). 0x0F 0x00 Program Function Registers 0x08 modes X X X 0x09 clock X X X LNA input impedance 1 = 5 kΩ 0 = 15 kΩ (default) X 0 Internal power-down mode 000 = chip run (default) 001 = full power-down 010 = standby 011 = reset 100 = CW mode (TGC PDWN) X X DCS 1 = on (default) 0 = off 0x00 X 0x01 0x0D test_io User test mode 00 = off (default) 01 = on, single alternate 10 = on, single once 11 = on, alternate once Reset PN long gen 1 = on 0 = off (default) Reset PN short gen 1 = on 0 = off (default) 0x0E GPO outputs X X X X Output test mode—see Table 13 0000 = off (default) 0001 = midscale short 0010 = +FS short 0011 = −FS short 0100 = checkerboard output 0101 = PN sequence long 0110 = PN sequence short 0111 = one-/zero-word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1× sync 1011 = one bit high 1100 = mixed bit frequency (format determined by output_mode) General-purpose digital outputs 0x00 Turns the internal duty cycle stabilizer (DCS) on and off (global). When this register is set, the test data is placed on the output pins in place of normal data. (Local, except for PN sequence.) 0x00 Values placed on GPO[0:3] pins (global). Rev. 0 | Page 42 of 48 AD9277 Addr. (Hex) 0x0F Register Name flex_channel_input Bit 7 Bit 0 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) X X X X Filter cutoff frequency control 0000 = 1.3 × 1/3 × fSAMPLE 0001 = 1.2 × 1/3 × fSAMPLE 0010 = 1.1 × 1/3 × fSAMPLE 0011 = 1.0 × 1/3 × fSAMPLE (default) 0100 = 0.9 × 1/3 × fSAMPLE 0101 = 0.8 × 1/3 × fSAMPLE 0110 = 0.7 × 1/3 × fSAMPLE 1000 = 1.3 × 1/4.5 × fSAMPLE 1001 = 1.2 × 1/4.5 × fSAMPLE 1010 = 1.1 × 1/4.5 × fSAMPLE 1011 = 1.0 × 1/4.5 × fSAMPLE 1100 = 0.9 × 1/4.5 × fSAMPLE 1101 = 0.8 × 1/4.5 × fSAMPLE 1110 = 0.7 × 1/4.5 × fSAMPLE X X 6-bit LNA offset adjustment 10 0000 for LNA bias high, mid-high, mid-low (default) 10 0001 for LNA bias low LNA gain X X X X PGA gain 00 = 15.6 dB 00 = 21 dB 01 = 17.9 dB 01 = 24 dB (default) 10 = 21.3 dB 10 = 27 dB (default) 11 = 30 dB X X X X 1 X LNA bias 00 = high (default) 01 = mid-high 10 = mid-low 11 = low Data format select X X X Output X 0 = LVDS 00 = offset binary invert ANSI-644 (default) enable (default) 01 = twos 1 = on 1 = LVDS complement 0 = off low power, (default) (IEEE 1596.3 similar) X X X DCO± X X Output driver and termination FCO± 00 = none (default) 2× drive 01 = 200 Ω strength 10 = 100 Ω 1 = on 11 = 100 Ω 0 = off (default) Default Value 0x30 Comments Antialiasing filter cutoff (global). 0x10 flex_offset 0x20 0x11 flex_gain 0x06 LNA force offset correction (local). LNA and PGA gain adjustment (global). 0x12 bias_current 0x08 LNA bias current adjustment (global). 0x14 output_mode 0x00 Configures the outputs and the format of the data (Bits[7:3] and Bits[1:0] are global; Bit 2 is local). 0x15 output_adjust 0x00 0x16 output_phase X X X X 0x18 flex_vref X 0= internal reference 1= external reference X X 0011 = output clock phase adjust (0000 through 1010) (Default: 180° relative to data edge) 0000 = 0° relative to data edge 0001 = 60° relative to data edge 0010 = 120° relative to data edge 0011 = 180° relative to data edge 0100 = 240° relative to data edge 0101 = 300° relative to data edge 0110 = 360° relative to data edge 0111 = 420° relative to data edge 1000 = 480° relative to data edge 1001 = 540° relative to data edge 1010 = 600° relative to data edge 1011 to 1111 = 660° relative to data edge X X X X 0x03 Determines LVDS or other output properties. Primarily functions to set the LVDS span and common-mode levels in place of an external resistor (Bits[7:1] are global; Bit 0 is local). On devices that utilize global clock divide, determines which phase of the divider output is used to supply the output clock. Internal latching is unaffected. 0x00 Select internal reference (recommended default) or external reference (global). Rev. 0 | Page 43 of 48 AD9277 Addr. (Hex) 0x19 Register Name user_patt1_lsb Bit 7 (MSB) B7 Bit 6 B6 Bit 5 B5 Bit 4 B4 Bit 3 B3 Bit 2 B2 Bit 1 B1 Bit 0 (LSB) B0 Default Value 0x00 Comments User-Defined Pattern 1, LSB (global). User-Defined Pattern 1, MSB (global). User-Defined Pattern 2, LSB (global). User-Defined Pattern 2, MSB (global). Serial stream control (global). 0x1A user_patt1_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 0x1B user_patt2_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 0x1C user_patt2_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 0x21 serial_control LSB first 1 = on 0 = off (default) X X X 0x22 serial_ch_stat X X X X