AD9280ARS

a Complete 8-Bit, 32 MSPS, 95 mW CMOS A/D Converter AD9280 FEATURES CMOS 8-Bit 32 MSPS Sampling A/D Converter Pin-Compatible with AD876-8 Power Dissipation: 95 mW (3 V Supply) Operation Between +2.7 V and +5.5 V Supply Differential Nonlinearity: 0.2 LSB Power-Down (Sleep) Mode Three-State Outputs Out-of-Range Indicator Built-In Clamp Function (DC Restore) Adjustable On-Chip Voltage Reference IF Undersampling to 135 MHz A single clock input is used to control all internal conversion cycles. The digital output data is presented in straight binary output format. An out-of-range signal (OTR) indicates an overflow condition which can be used with the most significant bit to determine low or high overflow. The AD9280 can operate with a supply range from +2.7 V to +5.5 V, ideally suiting it for low power operation in high speed applications. The AD9280 is specified over the industrial (–40°C to +85°C) temperature range. PRODUCT HIGHLIGHTS Low Power PRODUCT DESCRIPTION The AD9280 is a monolithic, single supply, 8-bit, 32 MSPS analog-to-digital converter with an on-chip sample-and-hold amplifier and voltage reference. The AD9280 uses a multistage differential pipeline architecture at 32 MSPS data rates and guarantees no missing codes over the full operating temperature range. The AD9280 consumes 95 mW on a 3 V supply (excluding the reference power). In sleep mode, power is reduced to below 5 mW. Very Small Package The AD9280 is available in a 28-lead SSOP package. Pin Compatible with AD876-8 The input of the AD9280 has been designed to ease the development of both imaging and communications systems. The user can select a variety of input ranges and offsets and can drive the input either single-ended or differentially. The AD9280 is pin compatible with the AD876-8, allowing older designs to migrate to lower supply voltages. 300 MHz Onboard Sample-and-Hold The versatile SHA input can be configured for either singleended or differential inputs. The sample-and-hold amplifier (SHA) is equally suited for both multiplexed systems that switch full-scale voltage levels in successive channels and sampling single-channel inputs at frequencies up to and beyond the Nyquist rate. AC-coupled input signals can be shifted to a predetermined level, with an onboard clamp circuit. The dynamic performance is excellent. Out-of-Range Indicator The OTR output bit indicates when the input signal is beyond the AD9280’s input range. Built-In Clamp Function Allows dc restoration of video signals. The AD9280 has an onboard programmable reference. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. FUNCTIONAL BLOCK DIAGRAM CLAMP CLAMP IN CLK DRVDD AVDD STBY VINA SHA SHA GAIN SHA SHA GAIN SHA GAIN MODE A/D REFTF A/D REFTS D/A A/D D/A A/D D/A A/D D/A THREESTATE CORRECTION LOGIC REFBS REFBF OUTPUT BUFFERS VREF REFSENSE GAIN 1V AD9280 OTR D7 (MSB) D0 (LSB) AVSS DRVSS REV. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2010 AD9280–SPECIFICATIONS (AVDD = +3 V, DRVDD = +3 V, FS = 32 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input Span from 0.5 V to 2.5 V, External Reference, TMIN to TMAX unless otherwise noted) Parameter Min Symbol RESOLUTION FS DC ACCURACY Differential Nonlinearity Integral Nonlinearity Offset Error Gain Error DNL INL EZS EFS ANALOG INPUT Input Voltage Range Input Capacitance Aperture Delay Aperture Uncertainty (Jitter) Input Bandwidth (–3 dB) Full Power (0 dB) DC Leakage Current INTERNAL REFERENCE Output Voltage (1 V Mode) Output Voltage Tolerance (1 V Mode) Output Voltage (2 V Mode) Load Regulation (1 V Mode) POWER SUPPLY Operating Voltage Supply Current Power Consumption Power-Down Gain Error Power Supply Rejection Max 8 CONVERSION RATE REFERENCE VOLTAGES Top Reference Voltage Bottom Reference Voltage Differential Reference Voltage Reference Input Resistance1 Typ REFTS REFBS AIN CIN tAP tAJ BW AVDD DRVDD IAVDD PD MHz ± 0.2 ± 0.3 ± 0.2 ± 1.2 ± 1.0 ± 1.5 ± 1.8 ± 3.9 LSB LSB % FSR % FSR 2 10 4.2 AVDD V AVDD – 1 V V p-p kΩ kΩ 1 4 2 REFTS V pF ns ps 300 43 MHz µA 1 ± 10 2 0.5 2.7 2.7 PSRR DYNAMIC PERFORMANCE (AIN = 0.5 dBFS) Signal-to-Noise and Distortion SINAD f = 3.58 MHz f = 16 MHz Effective Bits f = 3.58 MHz f = 16 MHz Signal-to-Noise SNR f = 3.58 MHz f = 16 MHz Total Harmonic Distortion THD f = 3.58 MHz f = 16 MHz Spurious Free Dynamic Range SFDR f = 3.58 MHz f = 16 MHz Differential Phase DP Differential Gain DG 32 REFBS VREF 46.4 47.8 Condition Bits 1 GND VREF Units 3 3 31.7 95 4 ± 25 2 5.5 5.5 36.7 110 V mV V mV V V mA mW mW 1 % FS 49 48 dB dB 7.8 7.7 Bits Bits 49 48 dB dB –62 –58 –49.5 dB dB 66 61 0.2 0.08 51.4 dB dB Degree % –2– REFTS = 2.5 V, REFBS = 0.5 V REFTS, REFBS: MODE = AVDD Between REFTF & REFBF: MODE = AVSS REFBS Min = GND: REFTS Max = AVDD Switched Input = ± FS REFSENSE = VREF REFSENSE = GND 1 mA Load Current AVDD = 3 V, MODE = AVSS AVDD = DRVDD = 3 V, MODE = AVSS STBY = AVDD, MODE and CLOCK = AVSS NTSC 40 IRE Mod Ramp REV. E AD9280 Parameter Symbol Min DIGITAL INPUTS High Input Voltage Low Input Voltage VIH VIL 2.4 DIGITAL OUTPUTS High-Z Leakage Data Valid Delay Data Enable Delay Data High-Z Delay IOZ tOD tDEN tDHZ –10 LOGIC OUTPUT (with DRVDD = 3 V) High Level Output Voltage (IOH = 50 µA) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOL = 1.6 mA) Low Level Output Voltage (IOL = 50 µA) VOH VOH VOL VOL +2.95 +2.80 LOGIC OUTPUT (with DRVDD = 5 V) High Level Output Voltage (IOH = 50 µA) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOL = 1.6 mA) Low Level Output Voltage (IOL = 50 µA) VOH VOH VOL VOL +4.5 +2.4 tCH tCL 14.7 14.7 CLOCKING Clock Pulsewidth High Clock Pulsewidth Low Pipeline Latency Typ Max Units 0.3 V V +10 25 25 13 EOC ± 60 Clamp Pulsewidth tCPW 2 µA ns ns ns +0.4 +0.05 V V V V +0.4 +0.1 V V V V Output = GND to VDD CL = 20 pF ns ns Cycles 3 CLAMP Clamp Error Voltage Condition ± 80 mV CLAMPIN = +0.5 V to +2.0 V, RIN = 10 Ω CIN = 1 µF (Period = 63.5 µs) µs NOTES 1 See Figures 1a and 1b. Specifications subject to change without notice. REFTS REFBS 10kV REFTS AD9280 REFTF 10kV 4.2kV REFBF 0.4 3 VDD AVDD REFBS MODE MODE a. b. Figure 1. Equivalent Input Load REV. E AD9280 –3– AD9280 ABSOLUTE MAXIMUM RATINGS* Parameter With Respect to AVDD AVSS DRVDD DRVSS AVSS DRVSS AVDD DRVDD MODE AVSS CLK AVSS Digital Outputs DRVSS AIN AVSS VREF AVSS REFSENSE AVSS REFTF, REFTB AVSS REFTS, REFBS AVSS Junction Temperature Storage Temperature Lead Temperature 10 sec Min Max Units –0.3 –0.3 –0.3 –6.5 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 +6.5 +6.5 +0.3 +6.5 AVDD + 0.3 AVDD + 0.3 DRVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 +150 +150 V V V V V V V V V V V V °C °C +300 °C –65 *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. AVDD DRVDD AVDD AVDD AVDD AVDD AVSS AVSS AVSS AVSS DRVSS AVSS DRVSS a. D0–D7, OTR b. Three-State, Standby, Clamp c. CLK AVDD AVDD REFBS AVDD AVDD REFBF f. CLAMPIN 22 AVDD REFTS AVSS 21 AVSS AVSS d. AIN AVSS AVSS 24 AVSS AVDD REFTF 25 e. Reference AVDD AVDD AVSS AVSS g. MODE h. REFSENSE AVDD AVSS i. VREF Figure 2. Equivalent Circuits CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9280 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. E AD9280 PIN CONFIGURATION 28-Lead Wide Body (SSOP) 28 AVDD AVSS 1 DRVDD 2 27 AIN DNC 3 26 VREF DNC 4 25 REFBS D0 5 AD9280 24 REFBF TOP VIEW 23 MODE D2 7 (Not to Scale) 22 REFTF D1 6 D3 8 21 REFTS D4 9 20 CLAMPIN D5 10 19 CLAMP D6 11 18 REFSENSE 17 STBY D7 12 OTR 13 16 THREE-STATE DRVSS 14 15 CLK 'NC = DO NOT CONNECT PIN FUNCTION DESCRIPTIONS SSOP Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 REV. E Name Description AVSS DRVDD Analog Ground Digital Driver Supply DNC DNC Do Not Connect Do Not Connect D0 D1 D2 D3 D4 D5 D6 D7 OTR DRVSS CLK THREE-STATE STBY REFSENSE CLAMP CLAMPIN REFTS REFTF MODE REFBF REFBS VREF AIN AVDD Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7, Most Significant Bit Out-of-Range Indicator Digital Ground Clock Input HI: High Impedance State. LO: Normal Operation HI: Power-Down Mode. LO: Normal Operation Reference Select HI: Enable Clamp Mode. LO: No Clamp Clamp Reference Input Top Reference Top Reference Decoupling Mode Select Bottom Reference Decoupling Bottom Reference Internal Reference Output Analog Input Analog Supply –5– AD9280 DEFINITIONS OF SPECIFICATIONS Integral Nonlinearity (INL) Offset Error The first transition should occur at a level 1 LSB above “zero.” Offset is defined as the deviation of the actual first code transition from that point. Integral nonlinearity refers to the deviation of each individual code from a line drawn from “zero” through “full scale.” The point used as “zero” occurs 1/2 LSB before the first code transition. “Full scale” is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line. Gain Error The first code transition should occur for an analog value 1 LSB above nominal negative full scale. The last transition should occur for an analog value 1 LSB below the nominal positive full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between the first and last code transitions. Differential Nonlinearity (DNL, No Missing Codes) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. It is often specified in terms of the resolution for which no missing codes (NMC) are guaranteed. Pipeline Delay (Latency) The number of clock cycles between conversion initiation and the associated output data being made available. New output data is provided every rising edge. (AVDD = +3 V, DRVDD = +3 V, FS = 32 MHz (50% Duty Cycle), MODE = AVDD, 2 V Input Typical Characterization Curves Span from 0.5 V to 2.5 V, External Reference, unless otherwise noted) 60 1.0 55 0.5 50 –0.5 AMPLITUDE SNR– dB DNL 45 0 –0.5 –6.0 AMPLITUDE 40 35 30 –20.0 AMPLITUDE 25 –1.0 0 32 64 96 128 160 CODE OFFSET 192 224 20 1.00E+05 240 Figure 3. Typical DNL 1.00E+06 1.00E+07 INPUT FREQUENCY – Hz 1.00E+08 Figure 5. SNR vs. Input Frequency 60 1.0 55 0.5 50 –0.5 AMPLITUDE SINAD – dB INL 45 0 –0.5 –6.0 AMPLITUDE 40 35 30 –20.0 AMPLITUDE 25 –1.0 0 32 64 96 128 160 CODE OFFSET 192 224 20 1.00E+05 240 1.00E+06 1.00E+07 INPUT FREQUENCY – Hz 1.00E+08 Figure 6. SINAD vs. Input Frequency Figure 4. Typical INL –6– REV. E AD9280 105 –30 –35 POWER CONSUMPTION – mW 100 –40 THD – dB –45 –20.0 AMPLITUDE –50 –55 –6.0 AMPLITUDE –60 –65 90 85 80 –0.5 AMPLITUDE –70 1.00E+05 1.00E+06 1.00E+07 INPUT FREQUENCY – Hz 75 1.00E+08 –80 1M –70 900k AIN = –0.5dBFS –60 0 10 5 15 20 25 30 CLOCK FREQUENCY – MHz 35 40 Figure 10. Power Consumption vs. Clock Frequency (MODE = AVSS) Figure 7. THD vs. Input Frequency 1M 800k 700k –50 600k HITS THD – dB 95 –40 500k 400k –30 300k –20 200k –10 100k 0 1.00E+06 1.00E+07 CLOCK FREQUENCY – Hz 0 0 1.00E+08 Figure 8. THD vs. Clock Frequency 0 N–1 N CODE N+1 Figure 11. Grounded Input Histogram 30 20 1.01 CLOCK = 32MHz 10 1.009 0 FIN = 1MHz FS = 32MHz FUND –10 –20 –30 –40 –50 1.007 –60 –70 VREF – V 1.008 –80 –90 1.006 1.005 –50 5th 4th 6th 7th 9th 8th –100 –110 –30 –10 10 30 50 TEMPERATURE – °C 70 –120 0E+0 90 4E+6 8E+6 12E+6 SINGLE-TONE FREQUENCY DOMAIN 16E+6 Figure 12. Single-Tone Frequency Domain Figure 9. Voltage Reference Error vs. Temperature REV. E 2nd3rd –7– AD9280 0 APPLYING THE AD9280 THEORY OF OPERATION SIGNAL AMPLITUDE – dB –3 The AD9280 implements a pipelined multistage architecture to achieve high sample rate with low power. The AD9280 distributes the conversion over several smaller A/D subblocks, refining the conversion with progressively higher accuracy as it passes the results from stage to stage. As a consequence of the distributed conversion, the AD9280 requires a small fraction of the 256 comparators used in a traditional flash type A/D. A sampleand-hold function within each of the stages permits the first stage to operate on a new input sample while the second, third and fourth stages operate on the three preceding samples. –6 –9 –12 –15 –18 –21 –24 1.0E+6 1.0E+7 1.0E+8 FREQUENCY – Hz 1.0E+9 OPERATIONAL MODES The AD9280 is designed to allow optimal performance in a wide variety of imaging, communications and instrumentation applications, including pin compatibility with the AD876-8 A/D. To realize this flexibility, internal switches on the AD9280 are used to reconfigure the circuit into different modes. These modes are selected by appropriate pin strapping. There are three parts of the circuit affected by this modality: the voltage reference, the reference buffer, and the analog input. The nature of the application will determine which mode is appropriate: the descriptions in the following sections, as well as Table I should assist in selecting the desired mode. Figure 13. Full Power Bandwidth 50 40 30 20 REFBS = 0.5V REFTS = 2.5V CLOCK = 32MHz IB – mA 10 0 –10 –20 –30 –40 –50 0 0.5 1.5 1.0 2.0 INPUT VOLTAGE – V 2.5 3.0 Figure 14. Input Bias Current vs. Input Voltage Table I. Mode Selection Modes Input Connect Input Span MODE Pin REFSENSE Pin TOP/BOTTOM AIN 1V AVDD AIN 2V AVDD CENTER SPAN AIN 1V AVDD/2 Short VREF and REFSENSE Together AVDD/2 AVDD/2 20 AIN 2V AVDD/2 AGND AVDD/2 AVDD/2 AIN Is Input 1 1V AVDD/2 Short VREF and REFSENSE Together AVDD/2 AVDD/2 29 AVDD/2 AGND No Connect AVDD/2 AVDD/2 No Connect Span = REFTS – REFBS (2 V max) Differential REFTS and REFBS Are Shorted Together for Input 2 2V External Ref AIN 2 V max AVDD REF REFBS Figure Short REFSENSE, REFTS and VREF Together AGND 18 AGND AGND 19 Short REFTS and VREF Together No Connect AVDD AGND AD876-8 AIN 2V Float or AVSS REFTS AVDD No Connect –8– 21, 22 Short to VREFTF Short to 23 VREFBF Short to VREFTF Short to 30 VREFBF REV. E AD9280 SUMMARY OF MODES VOLTAGE REFERENCE AIN 1 V Mode the internal reference may be set to 1 V by connecting REFSENSE and VREF together. REFTS 2 V Mode the internal reference my be set to 2 V by connecting REFSENSE to analog ground REFERENCE BUFFER Center Span Mode midscale is set by shorting REFTS and REFBS together and applying the midscale voltage to that point The MODE pin is set to AVDD/2. The analog input will swing about that midscale point. Top/Bottom Mode sets the input range between two points. The two points are between 1 V and 2 V apart. The Top/Bottom Mode is enabled by tying the MODE pin to AVDD. ANALOG INPUT Differential Mode is attained by driving the AIN pin as one differential input, shorting REFTS and REFBS together and driving them as the second differential input. The MODE pin is tied to AVDD/2. Preferred mode for optimal distortion performance. Single-Ended is attained by driving the AIN pin while the REFTS and REFBS pins are held at dc points. The MODE pin is tied to AVDD. Single-Ended/Clamped (AC Coupled) the input may be clamped to some dc level by ac coupling the input. This is done by tying the CLAMPIN to some dc point and applying a pulse to the CLAMP pin. MODE pin is tied to AVDD. SPECIAL AD876-8 Mode enables users of the AD876-8 to drop the AD9280 into their socket. This mode is attained by floating or grounding the MODE pin. INPUT AND REFERENCE OVERVIEW Figure 16, a simplified model of the AD9280, highlights the relationship between the analog input, AIN, and the reference voltages, REFTS, REFBS and VREF. Like the voltages applied to the resistor ladder in a flash A/D converter, REFTS and REFBS define the maximum and minimum input voltages to the A/D. REFBS Figure 15. AD9280 Equivalent Functional Input Circuit In single-ended operation, the input spans the range, REFBS ≤ AIN ≤ REFTS where REFBS can be connected to GND and REFTS connected to VREF. If the user requires a different reference range, REFBS and REFTS can be driven to any voltage within the power supply rails, so long as the difference between the two is between 1 V and 2 V. In differential operation, REFTS and REFBS are shorted together, and the input span is set by VREF, (REFTS – VREF/2) ≤ AIN ≤ (REFTS + VREF/2) where VREF is determined by the internal reference or brought in externally by the user. The best noise performance may be obtained by operating the AD9280 with a 2 V input range. The best distortion performance may be obtained by operating the AD9280 with a 1 V input range. REFERENCE OPERATION The AD9280 can be configured in a variety of reference topologies. The simplest configuration is to use the AD9280’s onboard bandgap reference, which provides a pin-strappable option to generate either a 1 V or 2 V output. If the user desires a reference voltage other than those two, an external resistor divider can be connected between VREF, REFSENSE and analog ground to generate a potential anywhere between 1 V and 2 V. Another alternative is to use an external reference for designs requiring enhanced accuracy and/or drift performance. A third alternative is to bring in top and bottom references, bypassing VREF altogether. Figures 16d, 16e and 16f illustrate the reference and input architecture of the AD9280. In tailoring a desired arrangement, the user can select an input configuration to match drive circuit. Then, moving to the reference modes at the bottom of the figure, select a reference circuit to accommodate the offset and amplitude of a full-scale signal. Table I outlines pin configurations to match user requirements. The input stage is normally configured for single-ended operation, but allows for differential operation by shorting REFTS and REFBS together to be used as the second input. REV. E A/D CORE AD9280 External Divider Mode the internal reference may be set to a point between 1 V and 2 V by adding external resistors. See Figure 16f. External Reference Mode enables the user to apply an external reference to REFTS, REFBS and VREF pins. This mode is attained by tying REFSENSE to VDD. SHA –9– AD9280 V* MIDSCALE +FS –FS AIN AD9280 SHA +F/S RANGE OBTAINED FROM VREF PIN OR EXTERNAL REF REFTF 0.1mF 10kV –F/S RANGE OBTAINED FROM VREF PIN OR EXTERNAL REF A2 REFBS A/D CORE 0.1mF 4.2kV TOTAL 10kV 10mF REFTF INTERNAL REF A/D CORE 4.2kV TOTAL 0.1mF AVDD/2 0.1mF 10mF 0.1mF 10kV 0.1mF 10kV MODE 10kV REFTS A2 AD9280 10kV 10kV REFBS SHA MODE (AVDD) 10kV REFTS AIN REFBF MIDSCALE OFFSET VOLTAGE IS DERIVED FROM INTERNAL OR EXTERNAL REF REFBF a. Top/Bottom Mode * MAXIMUM MAGNITUDE OF V IS DETERMINED BY INTERNAL REFERENCE b. Center Span Mode MAXIMUM MAGNITUDE OF V IS DETERMINED BY INTERNAL REFERENCE AND TURNS RATIO V AIN SHA AVDD/2 AD9280 10kV MODE AVDD/2 REFTF 0.1mF 10kV REFTS A2 REFBS 10kV INTERNAL REF A/D CORE 4.2kV TOTAL 10mF 0.1mF 0.1mF 10kV REFBF c. Differential Mode A1 1V REFSENSE AD9280 VREF (2V) VREF (1V) 0.1mF 1.0mF AVSS 10kV 10kV AD9280 d. 1 V Reference 1V A1 0.1mF A1 1V 1.0mF REFSENSE AVSS e. 2 V Reference VREF (= 1 + RA/RB) RA 0.1mF 1.0mF 1V REFSENSE RB AD9280 AD9280 AVSS INTERNAL 10K REF RESISTORS ARE SWITCHED OPEN BY THE PRESENSE OF RA AND RB. A1 VREF REFSENSE AVDD g. Internal Reference Disable (Power Reduction) f. Variable Reference (Between 1 V and 2 V) Figure 16. –10– REV. E AD9280 The actual reference voltages used by the internal circuitry of the AD9280 appear on REFTF and REFBF. For proper operation, it is necessary to add a capacitor network to decouple these pins. The REFTF and REFBF should be decoupled for all internal and external configurations as shown in Figure 17. Figure 19 shows the single-ended configuration for 2 V p-p operation. REFSENSE is connected to GND, resulting in a 2 V reference output. 2V AIN SHA 0V REFTF 10mF 10kV AD9280 0.1mF REFTS REFBF 0.1mF AD9280 AVDD REFTF 0.1mF 0.1mF 10mF 10kV A2 REFBS 0.1mF MODE A/D CORE 10kV 4.2kV TOTAL 0.1mF 10kV Figure 17. Reference Decoupling Network REFBF VREF Note: REFTF = reference top, force REFBF = reference bottom, force REFTS = reference top, sense REFBS = reference bottom, sense 1.0mF AIN SHA 0V AD9280 10kV REFTS Maximum reference drive is 1 mA. An external buffer is required for heavier loads. MODE A/D CORE 4.2kV TOTAL 0.1mF 0.1mF 1.0mF 0.1mF REF SENSE A1 AVDD/2 REFTF 0.1mF 0.1mF 10mF 10kV A2 REFBS 10kV A/D CORE 4.2kV TOTAL 0.1mF 10kV REFBF VREF 1.0mF 0.1mF REF SENSE A1 1V 1V Figure 20. Internal Reference 1 V p-p Input Span (Center Span Mode) Figure 18. Internal Reference—1 V p-p Input Span (Top/Bottom Mode) REV. E MODE 10mF REFBF VREF REFTS 0.1mF 10kV AD9280 10kV +1.5V 10kV SHA AVDD 10kV REFBS AIN 1V REFTF A2 1V Figure 20 shows the single-ended configuration that gives the good high frequency dynamic performance (SINAD, SFDR). To optimize dynamic performance, center the common-mode voltage of the analog input at approximately 1.5 V. Connect the shorted REFTS and REFBS inputs to a low impedance 1.5 V source. In this configuration, the MODE pin is driven to a voltage at midsupply (AVDD/2). 2V 1V A1 REF SENSE Figure 19. Internal Reference, 2 V p-p Input Span (Top/Bottom Mode) INTERNAL REFERENCE OPERATION Figures 18, 19 and 20 show sample connections of the AD9280 internal reference in its most common configurations. (Figures 18 and 19 illustrate top/bottom mode while Figure 20 illustrates center span mode). Figure 29 shows how to connect the AD9280 for 1 V p-p differential operation. Shorting the VREF pin directly to the REFSENSE pin places the internal reference amplifier, A1, in unity-gain mode and the resultant reference output is 1 V. In Figure 18 REFBS is grounded to give an input range from 0 V to 1 V. These modes can be chosen when the supply is either +3 V or +5 V. The VREF pin must be bypassed to AVSS (analog ground) with a 1.0 µF tantalum capacitor in parallel with a low inductance, low ESR, 0.1 µF ceramic capacitor. 0.1mF –11– AD9280 Figure 23a shows an example of the external references driving the REFTF and REFBF pins that is compatible with the AD876. REFTS is shorted to REFTF and driven by an external 4 V low impedance source. REFBS is shorted to REFBF and driven by a 2 V source. The MODE pin is connected to GND in this configuration. EXTERNAL REFERENCE OPERATION Using an external reference may provide more flexibility and improve drift and accuracy. Figures 21 through 23 show examples of how to use an external reference with the AD9280. To use an external reference, the user must disable the internal reference amplifier by connecting the REFSENSE pin to VDD. The user then has the option of driving the VREF pin, or driving the REFTS and REFBS pins. 4V The AD9280 contains an internal reference buffer (A2), that simplifies the drive requirements of an external reference. The external reference must simply be able to drive a 10 kΩ load. VIN 2V REFTS 4V REFTF 10mF Figure 21 shows an example of the user driving the top and bottom references. REFTS is connected to a low impedance 2 V source and REFBS is connected to a low impedance 1 V source. REFTS and REFBS may be driven to any voltage within the supply as long as the difference between them is between 1 V and 2 V. AD9280 0.1mF REFBF 2V 0.1mF 0.1mF REFBS VREF REFSENSE AVDD MODE 2V AIN AD9280 SHA 1V REFBS 1V REFTF A2 0.1mF REF SENSE 4.2kV TOTAL A/D CORE 10kV AVDD 0.1mF 10kV REFTS 2V Figure 23a. External Reference—2 V p-p Input Span 10kV 6 REFT 0.1mF 10kV MODE 8 5 REFBF Figure 21. External Reference Mode—1 V p-p Input Span Figure 22 shows an example of an external reference generating 2.5 V at the shorted REFTS and REFBS inputs. In this instance, a REF43 2.5 V reference drives REFTS and REFBS. A resistive divider generates a 1 V VREF signal that is buffered by A3. A3 must be able to drive a 10 kΩ, capacitive load. Choose this op amp based on noise and accuracy requirements. AD9280 3.0V 2.5V 2.0V AIN REFTS 0.1mF 1.5kV A3 0.1mF 1.0mF 0.1mF REFBS AVDD 0.1mF 0.1mF REFBF AVDD/2 +5V AVDD AVDD REFB 3 6 REFTF C2 10mF C6 0.1mF AD9280 REFBS C5 0.1mF 4 C1 0.1mF REFBF Figure 23b. Kelvin Connected Reference Using the AD9280 STANDBY OPERATION The ADC may be placed into a powered down (sleep) mode by driving the STBY (standby) pin to logic high potential and holding the clock at logic low. In this mode the typical power drain is approximately 4 mW. The ADC will “wake up” in 400 ns (typ) after the standby pulse goes low. REFTF VREF 1kV REF43 7 C4 0.1mF C3 0.1mF 2 10mF REFTS +5V 10mF 10mF 0.1mF MODE REFSENSE 0.1mF Figure 22. External Reference Mode—1 V p-p Input Span 2.5 VCM CLAMP OPERATION The AD9280ARS features an optional clamp circuit for dc restoration of video or ac coupled signals. Figure 24 shows the internal clamp circuitry and the external control signals needed for clamp operation. To enable the clamp, apply a logic high to the CLAMP pin. This will close the switch SW1. The clamp amplifier will then servo the voltage at the AIN pin to be equal to the clamp voltage applied at the CLAMPIN pin. After the desired clamp level is attained, SW1 is opened by taking CLAMP back to a logic low. Ignoring the droop caused by the input bias current, the input capacitor CIN will hold the dc voltage at AIN constant until the next clamp interval. The input resistor RIN has a minimum recommended value of 10 Ω, to maintain the closed-loop stability of the clamp amplifier. –12– REV. E AD9280 The allowable voltage range that can be applied to CLAMPIN depends on the operational limits of the internal clamp amplifier. The recommended clamp range is between 0.5 volts and 2.0 volts. back porch to truncate the SYNC below the AD9280’s minimum input voltage. With a CIN = 1 µF, and RIN = 20 Ω, the acquisition time needed to set the input dc level to one volt with 1 mV accuracy is about 140 µs, assuming a full 1 volt VC. The input capacitor should be sized to allow sufficient acquisition time of the clamp voltage at AIN within the CLAMP interval, but also be sized to minimize droop between clamping intervals. Specifically, the acquisition time when the switch is closed will equal: With a 1 µF input coupling capacitor, the droop across one horizontal can be calculated: T ACQ = RIN CIN V  ln  C   VE  where VC is the voltage change required across CIN, and VE is the error voltage. VC is calculated by taking the difference between the initial input dc level at the start of the clamp interval and the clamp voltage supplied at CLAMPIN. VE is a system dependent parameter, and equals the maximum tolerable deviation from VC. For example, if a 2-volt input level needs to be clamped to 1 volt at the AD9280’s input within 10 millivolts, then VC equals 2 – 1 or 1 volt, and VE equals 10 mV. Note that once the proper clamp level is attained at the input, only a very small voltage change will be required to correct for droop. IBIAS = 22 µA, and t = 63.5 µs, so dV = 1.397 mV, which is less than one LSB. After the input capacitor is initially charged, the clamp pulse width only needs to be wide enough to correct small voltage errors such as the droop. The fine scale settling characteristics of the clamp circuitry are shown in Table II. Depending on the required accuracy, a CLAMP pulse width of 1 µs–3 µs should work in most applications. The OFFSET values ignore the contribution of offset from the clamp amplifier; they simply compare the output code with a “final value” measured with a much longer CLAMP pulse duration. Table II. The voltage droop is calculated with the following equation: dV = () I BIAS t CIN where t = time between clamping intervals. The bias current of the AD9280 will depend on the sampling rate, FS, and the difference between the reference midpoint, (REFTS–REFBS)/2 and the input voltage. For a fixed sampling rate of 32 MHz, Figure 14 shows the input bias current for a given input. For a 1 V input range, the maximum input bias current from Figure 14 is 22 µA. For lower sampling rates the input bias current will scale proportionally. OFFSET 8 µs 4 µs 3 µs 2 µs 1 µs