AD9283

a FEATURES 8-Bit, 50, 80 and 100 MSPS ADC Low Power: 90 mW at 100 MSPS On-Chip Reference and Track/Hold 475 MHz Analog Bandwidth SNR = 46.5 dB @ 41 MHz at 100 MSPS 1 V p-p Analog Input Range Single +3.0 V Supply Operation (2.7 V–3.6 V) Power-Down Mode: 4.2 mW APPLICATIONS Battery Powered Instruments Hand-Held Scopemeters Low Cost Digital Oscilloscopes 8-Bit, 50 MSPS/80 MSPS/100 MSPS 3 V A/D Converter AD9283 FUNCTIONAL BLOCK DIAGRAM VD PWRDWN VDD AD9283 A IN A IN ENCODE TIMING REF T/H ADC OUTPUT STAGING 8 D7–D0 GND REF REF OUT IN GENERAL DESCRIPTION The AD9283 is an 8-bit monolithic sampling analog-to-digital converter with an on-chip track-and-hold circuit and is optimized for low cost, low power, small size and ease of use. The product operates at a 100 MSPS conversion rate, with outstanding dynamic performance over its full operating range. The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power supply and an encode clock for full performance operation. No external reference or driver components are required for many applications. The digital outputs are TTL/CMOS compatible and a separate output power supply pin supports interfacing with 3.3 V or 2.5 V logic. The encoder input is TTL/CMOS compatible. A power-down function may be exercised to bring total consumption to 4.2 mW. In power-down mode, the digital outputs are driven to a high impedance state. Fabricated on an advanced CMOS process, the AD9283 is available in a 20-lead surface mount plastic package (SSOP) specified over the industrial temperature range (–40°C to +85°C). R EV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 AD9283–SPECIFICATIONS (V Parameter RESOLUTION DC ACCURACY Differential Nonlinearity Integral Nonlinearity No Missing Codes Gain Error1 Gain Tempco1 ANALOG INPUT Input Voltage Range (With Respect to AIN ) Common-Mode Voltage Input Offset Voltage Reference Voltage Reference Tempco Input Resistance Input Capacitance Analog Bandwidth, Full Power SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate Encode Pulsewidth High (tEH ) Encode Pulsewidth Low (tEL ) Aperture Delay (tA) Aperture Uncertainty (Jitter) Output Valid Time (tV) 2 Output Propagation Delay (tPD)2 DIGITAL INPUTS Logic “1” Voltage Logic “0” Voltage Logic “1” Current Logic “0” Current Input Capacitance DIGITAL OUTPUTS Logic “1” Voltage Logic “0” Voltage Output Coding POWER SUPPLY Power Dissipation3, 4 Power-Down Dissipation Power Supply Rejection Ratio (PSRR) +25° C Full +25° C Full Full +25° C Full Full I VI I VI VI I VI VI Temp Test Level DD = 3.0 V, VD = 3.0 V; single-ended input; external reference, unless otherwise noted) AD9283BRS-50 Min Typ Max 8 Units Bits +1.25 +1.50 +1.25 +1.50 LSB LSB LSB LSB % FS % FS ppm/° C AD9283BRS-100 Min Typ Max 8 ± 0.5 –1.25 ± 0.75 +1.25 +1.50 +1.25 +2.25 +6 +8 AD9283BRS-80 Min Typ Max 8 ± 0.5 –1.25 ± 0.75 +1.25 +1.50 +1.25 +1.50 ± 0.5 –1.25 ± 0.75 –6 –8 Guaranteed ± 2.5 80 –6 –8 Guaranteed ± 2.5 +6 +8 80 –6 –8 Guaranteed ± 2.5 +6 +8 80 Full Full +25° C Full Full Full +25° C Full +25° C Full +25° C Full +25° C +25° C +25° C +25° C +25° C Full Full Full Full Full Full +25° C Full Full V V I VI VI VI I VI V VI V VI IV IV IV V V VI VI VI VI VI VI V VI VI –35 1.2 7 5 ± 512 ± 200 ± 10 ± 40 1.25 ± 130 10 2 475 35 1.3 13 16 –35 1.2 7 5 ± 512 ± 200 ± 10 ± 40 1.25 ± 130 10 2 475 35 1.3 13 16 –35 1.2 7 5 ± 512 ± 200 ± 10 ± 40 1.25 ± 130 10 2 475 35 1.3 13 16 mV p-p mV mV mV V ppm/° C kΩ kΩ pF µA MHz MSPS MSPS ns ns ns ps rms ns ns V V µA µA pF V V 100 4.3 4.3 0 5 3.0 4.5 1 1000 1000 80 5.0 5.0 0 5 3.0 4.5 1 1000 1000 50 8.0 8.0 0 5 3.0 4.5 1 1000 1000 2.0 2.0 7.0 2.0 0.8 ±1 ±1 2.0 7.0 2.0 0.8 ±1 ±1 7.0 2.0 0.8 ±1 ±1 2.0 2.95 0.05 Offset Binary Code 80 4.2 100 7 18 2.0 2.95 0.05 Offset Binary Code 90 4.2 120 7 18 2.95 2.0 0.05 Offset Binary Code 90 4.2 115 7 18 Full Full +25° C VI VI I mW mW mV/V – 2– REV. B AD9283 Parameter DYNAMIC PERFORMANCE Transient Response Overvoltage Recovery Time Signal-to-Noise Ratio (SNR) (Without Harmonics) fIN = 10.3 MHz fIN = 27 MHz fIN = 41 MHz fIN = 76 MHz Signal-to-Noise Ratio (SINAD) (With Harmonics) fIN = 10.3 MHz fIN = 27 MHz fIN = 41 MHz fIN = 76 MHz Effective Number of Bits fIN = 10.3 MHz fIN = 27 MHz fIN = 41 MHz fIN = 76 MHz 2nd Harmonic Distortion fIN = 10.3 MHz fIN = 27 MHz fIN = 41 MHz fIN = 76 MHz 3rd Harmonic Distortion fIN = 10.3 MHz fIN = 27 MHz fIN = 41 MHz fIN = 76 MHz Two-Tone Intermod Distortion (IMD) fIN = 10.3 MHz 5 Temp +25° C +25° C +25° C +25° C +25° C +25° C +25° C +25° C +25° C +25° C +25° C +25° C +25° C +25° C +25° C +25° C +25° C +25° C +25° C +25° C +25° C +25° C +25° C Test Level V V AD9283BRS-100 Min Typ Max 2 2 AD9283BRS-80 Min Typ Max 2 2 AD9283BRS-50 Min Typ Max 2 2 Units ns ns I I I V 46.5 46.5 43.5 46.5 46.0 44 47 47 47 44 47 47 dB dB dB dB I I I V I I I V I I I V I I I V 45 45.5 42.5 45 42.5 7.3 7.4 7.3 6.9 57 60 58 46 54.5 55 52.5 53 47 43.5 46.5 42 43.5 46.5 46 dB dB dB dB Bits Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc 7.5 7.5 7.5 7.6 7.5 55 50 60 60 55 55 60 56 55 47 70 62.5 60 55 70 60 V 52 52 52 dBc NOTES 1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.25 V external reference). 2 tV and tPD are measured from the 1.5 V level of the ENCODE input to the 50%/50% levels of the digital outputs swing. The digital output load during test is not to exceed an ac load of 10 pF or a dc current of ± 40 µA. 3 Power dissipation measured with encode at rated speed and a dc analog input. 4 Typical thermal impedance for the RS style (SSOP) 20-lead package: θJC = 46°C/W, θCA = 80 °C/W, θ JA = 126°C/W. 5 SNR/harmonics based on an analog input voltage of –0.7 dBFS referenced to a 1.024 V full-scale input range. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* VD, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4 V Analog Inputs . . . . . . . . . . . . . . . . . . . . –0.5 V to VD + 0.5 V Digital Inputs . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V VREF IN . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VD + 0.5 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature . . . . . . . . . . . . . . . . –55° C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . –65° C to +150°C Maximum Junction Temperature . . . . . . . . . . . . . . . +175°C Maximum Case Temperature . . . . . . . . . . . . . . . . . . +150°C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. ORDERING GUIDE Model Temperature Ranges Package Descriptions Package Options AD9283BRS -50, -80, -100 –40°C to +85° C 20-Lead SSOP RS-20 AD9283/PCB +25°C Evaluation Board CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9283 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. B – 3– AD9283 EXPLANATION OF TEST LEVELS Table I. Output Coding (VREF = +1.25 V) Test Level I 100% production tested. II 100% production tested at +25°C and sample tested at specified temperatures. III Sample tested only. IV Parameter is guaranteed by design and characterization testing. V Parameter is a typical value only. VI 100% production tested at +25°C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices. Step 255 • • 128 127 • • 0 AIN–AIN 0.512 • • 0.002 –0.002 • • –0.512 Digital Output 1111 1111 • • 1000 0000 0111 1111 • • 0000 0000 PIN CONFIGURATION PWRDWN 1 VREF OUT 2 VREF IN 3 GND 4 VD 5 A IN 6 20 19 18 17 D0 (LSB) D1 D2 D3 GND AD9283 16 TOP VIEW 15 V DD (Not to Scale) 14 D4 A IN 7 VD 8 GND 9 ENCODE 10 13 12 11 D5 D6 D7 (MSB) PIN FUNCTION DESCRIPTIONS Pin Number 1 2 3 4, 9, 16 5, 8 6 Name PWRDWN VREF OUT VREF IN GND VD AIN Function Power-down function select; Logic HIGH for power-down mode (digital outputs go to high impedance state). Internal Reference Output (+1.25 V typ); Bypass with 0.1 µF to Ground. Reference Input for ADC (+1.25 V typ). Ground. Analog +3 V Power Supply. Analog Input for ADC (Can be left open if operating in single-ended mode, but recommend connection to a 0.1 µF capacitor and a 25 Ω resistor in series to ground for better input matching). Analog Input for ADC Encode Clock for ADC (ADC samples on rising edge of ENCODE). Digital Outputs of ADC. Digital output power supply. Nominally +2.5 V to +3.6 V. 7 10 11–14, 17–20 15 AIN ENCODE D7–D4, D3–D0 VDD –4– REV. B AD9283 SAMPLE N AIN SAMPLE N+1 SAMPLE N+4 SAMPLE N+5 tA tEH ENCODE SAMPLE N+2 SAMPLE N+3 tEL 1/fS t PD D7–D0 DATA N–4 DATA N–3 DATA N–2 DATA N–1 DATA N tV DATA N+1 Figure 1. Timing Diagram VDD VDD 33.3k 33.3k OUT A IN 14.3k AIN 14.3k Figure 2. Equivalent Analog Input Circuit Figure 5. Equivalent Digital Output Circuit VD VD VBIAS REF IN OUT Figure 3. Equivalent Reference Input Circuit Figure 6. Equivalent Reference Output Circuit VD ENCODE Figure 4. Equivalent Encode Input Circuit REV. B –5– AD9283 0 –10 –20 –30 –40 dB dB 70 ENCODE = 100 MSPS AIN = 10.3MHz SNR = 46.5dB SINAD = 45dB 2nd = 57dBc 3rd = 54.5dBc 2ND 65 60 55 50 45 3RD ENCODE = 100 MSPS –50 –60 –70 –80 –90 40 35 30 –100 FREQUENCY 10 20 30 40 50 FREQUENCY – A IN 60 80 100 Figure 7. Spectrum: fS = 100 MSPS, fIN = 10.3 MHz Figure 10. Harmonic Distortion vs. AIN Frequency 0 –10 –20 –30 –40 dB –50 –60 –70 –80 –90 FREQUENCY ENCODE = 100 MSPS AIN = 41MHz SNR = 46.5dB SINAD = 45dB 2nd = 58dBc 3rd = 52.5dBc dB 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 FREQUENCY ENCODE = 100 MSPS AIN1 = 9MHz AIN2 = 10MHz IMD = 52dBc Figure 8. Spectrum: fS = 100 MSPS, fIN = 40 MHz Figure 11. Two-Tone Intermodulation Distortion 0 –10 –20 –30 –40 dB –50 dB 55 ENCODE = 100 MSPS AIN = 76MHz SNR = 46dB SINAD = 42.5dB 2nd = 46dBc 3rd = 53dBc ENCODE = 100 MSPS 50 SNR 45 40 –60 –70 –80 –90 FREQUENCY 30 35 SINAD 10 20 30 40 50 FREQUENCY 60 80 90 100 Figure 9. Spectrum: fS = 100 MSPS, fIN = 76 MHz Figure 12. SINAD/SNR vs. AIN Frequency –6– REV. B AD9283 49 SNR 48 SINAD 47 80 POWER – mW 120 A IN = 10.3MHz 100 AIN = 10.3MHz dB 46 60 45 40 44 20 43 10 20 30 40 50 60 ENCODE RATE 70 80 90 100 0 10 20 30 40 50 60 ENCODE RATE 70 80 90 100 Figure 13. SINAD/SNR vs. Encode Rate Figure 16. Analog Power Dissipation vs. Encode Rate 60 ENCODE = 100 MSPS A IN = 10.3MHz 50 SNR 40 SINAD dB dB 30 49 48 SNR 47 SINAD 46 20 45 10 0 7 6.5 6 5.5 5 4.5 4 ENCODE PULSEWIDTH HIGH – ns 3.5 3 44 –60 –40 –20 0 20 40 TEMPERATURE – C 60 80 100 Figure 14. SINAD/SNR vs. Encode Pulsewidth High Figure 17. SINAD/SNR vs. Temperature 0.5 0.0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 –3.5 –4.0 –4.5 –5.0 –5.5 0 100 200 300 400 BANDWIDTH – MHz 500 600 LSB dB 1.00 0.75 0.50 0.25 0.00 –0.25 –0.50 –0.75 –1.00 CODE Figure 15. ADC Frequency Response: fS = 100 MSPS Figure 18. Differential Nonlinearity REV. B –7– AD9283 2.0 1.5 1.0 0.5 LSB 0.0 –0.5 –1.0 –1.5 –2.0 Digital Outputs The digital outputs are TTL/CMOS compatible. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing to ease interfacing with 2.5 V or 3.3 V logic. The AD9283 goes into a low power state within two clock cycles following the assertion of the PWRDWN input. PWRDWN is asserted with a logic high. During power-down the outputs transition to a high impedance state. The time it takes to achieve optimal performance after disabling the powerdown mode is approximately 15 clock cycles. Care should be taken when loading the digital outputs of any high speed ADC. Large output loads create current transients on the chip that can degrade the converter’s performance. CODE Voltage Reference Figure 19. Integral Nonlinearity APPLICATIONS Theory of Operation The analog signal is applied differentially or single-endedly to the inputs of the AD9283. The signal is buffered and fed forward to an on-chip sample-and-hold circuit. The ADC core architecture is a bit-per-stage pipeline type converter utilizing switch capacitor techniques. The bit-per-stage blocks determine the 5 MSBs and drive a FLASH converter to encode the 3 LSBs. Each of the 5 MSB stages provides sufficient overlap and error correction to allow optimization of performance with respect to comparator accuracy. The output staging block aligns the data, carries out the error correction and feeds the data to the eight output buffers. The AD9283 includes an on-chip reference (nominally 1.25 V) and generates all clocking signals from one externally applied encode command. This makes the ADC easy to interface with and requires very few external components for operation. ENCODE Input A stable and accurate 1.25 V voltage reference is built into the AD9283 (VREF OUT). In normal operation, the internal reference is used by strapping Pins 2 and 3 of the AD9283 together. The input range can be adjusted by varying the reference voltage applied to the AD9283. No degradation in performance occurs when the reference is adjusted ± 5%. The full-scale range of the ADC tracks reference voltage changes linearly. Whether used or not, the internal reference (Pin 2) should be bypassed with a 0.1 µF capacitor to ground. Timing The AD9283 provides latched data outputs with four pipeline delays. Data outputs are available one propagation delay (tPD) after the rising edge of the encode command (Figure 1. Timing Diagram). The minimum guaranteed conversion rate to the ADC is 1 MSPS. The dynamic performance of the converter will degrade at encode rates below this sample rate. Evaluation Board The AD9283 evaluation board offers an easy way to test the AD9283. It only requires a 3 V supply, an analog input and encode clock to test the AD9283. The board is shipped with the 100 MSPS grade ADC. The analog input to the board accepts a 1 V p-p signal centered at ground. J1 should be used (Jump E3–E4, E18–E19) to drive the ADC through Transformer T1. J2 should be used for singleended input drive (Jump E19–E21). Both J1 and J2 are terminated to 50 Ω on the PCB. Each analog path is ac-coupled to an on-chip resistor divider which provides the required dc bias. A (TTL/CMOS Level) sample clock is applied to connector J3 which is terminated through 50 Ω on the PCB. This clock is buffered by U5 which also provides the clocks for the 574 latches, DAC, and the off-card latch clock CLKCON. (Timing can be modified at E17.) There is a reconstruction DAC (AD9760) on the PCB. The DAC is on the board to assist in debug only—the outputs should not be used to measure performance of the ADC. The ENCODE input is fully TTL/CMOS compatible with a nominal threshold of 1.5 V. Care was taken on the chip to match clock line delays and maintain sharp clock logic transitions. Any high speed A/D converter is extremely sensitive to the quality of the sampling clock provided by the user. This ADC uses an on-chip sample-and-hold circuit which is essentially a mixer. Any timing jitter on the ENCODE will be combined with the desired signal and degrade the high frequency performance of the ADC. The user is advised to give commensurate thought to the clock source. Analog Input The analog input to the ADC is fully differential and both inputs are internally biased. This allows the most flexible use of ac or dc and differential or single-ended input modes. For peak performance the inputs are biased at 0.3 × VD . See the specification table for allowable common-mode range when dc coupling the input. The inputs are also buffered to reduce the load the user needs to drive. For best dynamic performance, the impedances at AIN and AIN should be matched. The importance of this increases with sampling rate and analog input frequency. The nominal input range is 1.024 V p-p. –8– REV. B AD9283 Figure 20. Printed Circuit Board Top Side Silkscreen Figure 22. Printed Circuit Board Top Side Copper Figure 21. Printed Circuit Board Bottom Side Silkscreen Figure 23. Printed Circuit Board “Split” Power Layer REV. B –9– AD9283 Figure 24. Printed Circuit Board Ground Layer Figure 25. Printed Circuit Board Bottom Side Copper EVALUATION BOARD BILL OF MATERIALS — GS01717 # 1 2 3 4 5 QTY 15 4 24 4 1 REFDES C1, C4–C17 C18–C21 E1–E6, E8–E10, E12–E19, E21, E34–E39 J1, J2, J3, J5 P1 DEVICE Ceramic Cap Tantalum Cap W-HOLE Connector 5-Pin Connector PACKAGE 0603 BCAPTAJD VALUE 0.1 µF 10 µF SMB Wieland Connector (P/N #25.602.2553.0 Top P/N #Z5.530.0525.0 Bottom) AMP-747462-2 50 25 2K Mini-Circuits T1-1T-KK81 6 7 8 9 10 11 12 13 14 1 5 1 1 1 1 1 1 1 P2 R4, R9, R10, R21, R22 R7 R23 T1 U1 U3 U4 U5 37-Pin Connector Resistor Resistor Resistor Transformer AD9283 AD9760 74ACQ574 SN74LVC86 1206 1206 1206 SSOP-20 SOIC-28 SOIC-20 SO14 –10– REV. B REV. B VA VA E8 PWDN E10 E6 1 PWDN REFOUT REFIN 2 D0 D1 D2 D3 D4 D5 D6 D7 GND CLOCK Q7 12 11 Q6 13 Q5 14 Q4 15 Q3 16 Q2 17 Q1 18 DA1 DA2 DA3 DA4 DA5 DA6 DA7 CLKLAT Q0 17 3 4 5 6 VD 7 8 9 8 VA1 GND D7 E34 E35 11 D6 12 D5 10 9 ENC 10 13 C9 0.1 F 16 15 14 19 DA0 GND VA AIN VDD D4 AIN GND D3 D2 18 OUT_EN VCC 1 VDL 20 D1 19 U4 74ACQ574 C16 0.1 F CLKCON D0 E1 E2 2 3 C5 0.1 F 4 5 C1 0.1 F 6 7 VA C8 0.1 F C4 0.1 F 20 E5 E9 C18 10 F C19 10 F C20 10 F C21 10 F VD VDL VDAC P1 1 2 3 4 5 U1 AD9283 VA VD GND VDL VDAC J1 E3 E4 4 T1 3 VA 5 R7 25 2 C6 0.1 F Figure 26. Printed Circuit Board Schematic E36 E37 E38 E39 U3 AD9760 C13 0.1 F CLKDAC VDAC C15 0.1 F C10 0.1 F C11 0.1 F VDL CLKLAT E14 VDL E12 CLKDAC E13 14 VCC 13 4B 12 4A 11 4Y 10 3B 9 3A 8 3Y DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 C14 0.1 F VDAC R22 50 R23 2k C12 0.1 F DB1 DB0 NC1 NC2 NC3 NC4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CLK DVDD DCOM NC5 AVDD COMP2 IOUTA IOUTB ACOM COMP1 FSADJ REFIO REFLO SLEEP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 R21 50 –11– R4 50 6 1 C7 0.1 F E18 J2 E21 E19 C17 0.1 F R9 50 J3 U5 SN74LVC86 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 VDAC P2 C37DRPF J5 R10 50 1 1A 2 1B 3 1Y ENC 4 2A E15 E17 5 2B VDL CLKCON 6 E16 2Y 7 GND AD9283 AD9283 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Lead Shrink Small Outline Package (SSOP) (RS-20) C3389b–0–9/99 0.037 (0.94) 0.022 (0.559) 0.295 (7.50) 0.271 (6.90) 20 11 0.311 (7.9) 0.301 (7.64) 1 10 0.078 (1.98) PIN 1 0.068 (1.73) 0.07 (1.78) 0.066 (1.67) 0.008 (0.203) 0.002 (0.050) 0.0256 (0.65) BSC 8° SEATING 0.009 (0.229) 0° PLANE 0.005 (0.127) 0.212 (5.38) 0.205 (5.21) –12– REV. B PRINTED IN U.S.A.