14-Bit, 105/125 MSPS, IF Sampling ADC
AD9445
125 MSPS guaranteed sampling rate (AD9445BSV-125)
78.3 dBFS SNR/92 dBFS SFDR with 30 MHz input (3.2 V p-p)
74.8 dBFS SNR/95 dBFS SFDR with 30 MHz input (2.0 V p-p)
77.0 dBFS SNR/87 dBFS SFDR with 170 MHz input (3.2 V p-p)
74.6 dBFS SNR/95 dBFS SFDR with 170 MHz input (2.0 V p-p)
73.0 dBFS SNR/88 dBFS SFDR with 300 MHz input (2.0 V p-p)
102 dBFS 2-tone SFDR with 30 MHz and 31 MHz
92 dBFS 2-tone SFDR with 170 MHz and 171 MHz
60 fsec rms jitter
Excellent linearity
DNL = ±0.25 LSB typical
INL = ±0.8 LSB typical
2.0 V p-p to 4.0 V p-p differential full-scale input
Buffered analog inputs
LVDS outputs (ANSI-644 compatible) or CMOS outputs
Data format select (offset binary or twos complement)
Output clock available
3.3 V and 5 V supply operation
APPLICATIONS
Multicarrier, multimode cellular receivers
Antenna array positioning
Power amplifier linearization
Broadband wireless
Radar
Infrared imaging
Medical imaging
Communications instrumentation
FUNCTIONAL BLOCK DIAGRAM
AGND AVDD1 AVDD2
The ADC requires 3.3 V and 5.0 V power supplies and a low
voltage differential input clock for full performance operation.
No external reference or driver components are required for
many applications. Data outputs are CMOS or LVDS
compatible (ANSI-644 compatible) and include the means to
reduce the overall current needed for short trace distances.
RF ENABLE
AD9445
DFS
BUFFER
VIN+
VIN–
CLK+
CLK–
T/H
CLOCK
AND TIMING
MANAGEMENT
PIPELINE
ADC
14
CMOS
OR
LVDS
OUTPUT
STAGING
2
DCS MODE
OUTPUT MODE
OR
28
D13 TO D0
2
DCO
REF
VREF SENSE REFT REFB
Figure 1.
Optional features allow users to implement various selectable
operating conditions, including input range, data format select,
high IF sampling mode, and output data mode.
The AD9445 is available in a Pb-free, 100-lead, surface-mount,
plastic package (100-lead TQFP/EP) specified over the
industrial temperature range −40°C to +85°C.
PRODUCT HIGHLIGHTS
1.
High performance: outstanding SFDR performance for IF
sampling applications such as multicarrier, multimode 3G,
and 4G cellular base station receivers.
2.
Ease of use: on-chip reference and high input impedance
track-and-hold with adjustable analog input range and an
output clock simplifies data capture.
3.
Packaged in a Pb-free, 100-lead TQFP/EP package.
4.
Clock duty cycle stabilizer (DCS) maintains overall ADC
performance over a wide range of clock pulse widths.
5.
OR (out-of-range) outputs indicate when the signal is
beyond the selected input range.
6.
RF enable pin allows users to configure the device for
optimum SFDR when sampling frequencies above 210 MHz
(AD9445-125) or 240 MHz (AD9445-105).
GENERAL DESCRIPTION
The AD9445 is a 14-bit, monolithic, sampling analog-to-digital
converter (ADC) with an on-chip IF sampling track-and-hold
circuit. It is optimized for performance, small size, and ease of
use. The product operates at up to a 125 MSPS conversion rate
and is designed for multicarrier, multimode receivers, such as
those found in cellular infrastructure equipment.
DRGND DRVDD
05489-001
FEATURES
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
AD9445
TABLE OF CONTENTS
Features .............................................................................................. 1
Terminology .......................................................................................9
Applications....................................................................................... 1
Pin Configurations and Function Descriptions ......................... 10
General Description ......................................................................... 1
Equivalent Circuits......................................................................... 15
Functional Block Diagram .............................................................. 1
Typical Performance Characteristics ........................................... 16
Product Highlights ........................................................................... 1
Theory of Operation ...................................................................... 24
Revision History ............................................................................... 2
Analog Input and Reference Overview ................................... 24
Specifications..................................................................................... 3
Clock Input Considerations...................................................... 26
DC Specifications ......................................................................... 3
Power Considerations................................................................ 27
AC Specifications.......................................................................... 4
Digital Outputs ........................................................................... 27
Digital Specifications ................................................................... 6
Timing ......................................................................................... 27
Switching Specifications .............................................................. 6
Operational Mode Selection ..................................................... 28
Timing Diagrams.......................................................................... 7
Evaluation Board ............................................................................ 29
Absolute Maximum Ratings............................................................ 8
Outline Dimensions ....................................................................... 37
Thermal Resistance ...................................................................... 8
Ordering Guide .......................................................................... 37
ESD Caution.................................................................................. 8
REVISION HISTORY
10/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 40
AD9445
SPECIFICATIONS
DC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sampling rate, 2.0 V p-p differential input, internal
trimmed reference (1.0 V mode), AIN = −1.0 dBFS, DCS on, unless otherwise noted. RF ENABLE = AGND.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL) 1
Integral Nonlinearity (INL)1
VOLTAGE REFERENCE
Output Voltage VREF = 1.0 V
Load Regulation @ 1.0 mA
Reference Input Current (External VREF = 1.6 V)
INPUT REFERRED NOISE
ANALOG INPUT
Input Span
VREF = 1.6 V
VREF = 1.0 V
Internal Input Common-Mode Voltage
External Input Common-Mode Voltage
Input Resistance 2
Input Capacitance2
POWER SUPPLIES
Supply Voltage
AVDD1
AVDD2
DRVDD—LVDS Outputs
DRVDD—CMOS Outputs
Supply Current1
AVDD1
AVDD21, 3
IDRVDD1—LVDS Outputs
IDRVDD1—CMOS Outputs
PSRR
Offset
Gain
POWER CONSUMPTION
LVDS Outputs
CMOS Outputs (DC Input)
Temp
Full
Full
Full
25°C
Full
25°C
Full
25°C
Full
Full
Full
Full
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
AD9445BSVZ-105
Min
Typ
Max
14
AD9445BSVZ-125
Min
Typ
Max
14
Guaranteed
−7
Guaranteed
+7
−7
±3
−3
−2
−0.6
5
±0.25
0.9
1.0
±2
+3
+2
+0.65
−3
−2
−0.6
5
+1.6
−2
1.1
0.9
1.0
±2
1.0
3.2
2.0
3.5
3.2
2.0
3.5
3.9
3.3
5.0
3.3
Full
Full
Full
Full
335
169
63
14
Full
Full
1
0.2
Full
Full
2.2
2.0
+3
+2
+0.65
mV
mV
% FSR
% FSR
LSB
+2
LSB
LSB
±0.8
3.1
1
6
1
±0.25
1.0
3.1
3.14
4.75
3.0
3.0
+7
±3
±0.65
−1.6
Unit
Bits
1.1
3.9
1
6
3.46
5.25
3.6
3.6
364
196
78
3.14
4.75
3.0
3.0
3.3
5.0
3.3
384
172
63
14
2.3
2.1
V p-p
V p-p
V
V
kΩ
pF
3.46
5.25
3.6
3.6
V
V
V
V
424
199
78
mA
mA
mA
mA
1
0.2
2.4
V
mV
μA
LSB rms
mV/V
%/V
2.6
W
W
Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and
approximately 5 pF loading on each output bit for CMOS output mode.
Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input structure.
3
For RF ENABLE = AVDD1, IAVDD2 increases by ~30 mA, which increases power dissipation.
2
Rev. 0 | Page 3 of 40
AD9445
AC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sample rate, 2.0 V p-p differential input, internal
trimmed reference (1.0 V mode), AIN = −1.0 dBFS, DCS on, RF ENABLE = ground, unless otherwise noted.
Table 2.
Parameter
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 10 MHz
fIN = 30 MHz
fIN = 170 MHz
fIN = 225 MHz 1
fIN = 300 MHz 2
fIN = 400 MHz2
fIN = 450 MHz2
fIN = 10 MHz (3.2 V p-p Input)
fIN = 30 MHz (3.2 V p-p Input)
fIN = 170 MHz (3.2 V p-p Input)
fIN = 225 MHz (3.2 V p-p Input)1
fIN = 300 MHz (3.2 V p-p Input)2
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 10 MHz
fIN = 30 MHz
fIN = 170 MHz
fIN = 225 MHz1
fIN = 300 MHz2
fIN = 400 MHz2
fIN = 450 MHz2
fIN = 10 MHz (3.2 V p-p Input)
fIN = 30 MHz (3.2 V p-p Input)
fIN = 170 MHz (3.2 V p-p Input)
fIN = 225 MHz (3.2 V p-p Input)1
fIN = 300 MHz (3.2 V p-p Input)2
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10 MHz
fIN = 30 MHz
fIN = 170 MHz
fIN = 225 MHz1
fIN = 300 MHz2
fIN = 400 MHz2
fIN = 450 MHz2
Temp
25°C
25°C
Full
25°C
25°C
Full
25°C
25°C
25°C
Min
73.3
73
72.9
72.2
72.2
71.4
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
Full
25°C
25°C
25°C
AD9445BSVZ-105
Typ
Max
74.3
74.3
73.6
73
72.1
71
70.5
Min
72.9
72.5
72.3
72
71.4
71.3
77.6
77.5
76
75.3
73.7
73.2
72.8
72.3
71.4
71.3
70.2
74.2
74.2
73.3
72.5
71.7
67.2
65.2
72.8
72.3
72.4
71.9
70.7
69.3
AD9445BSVZ-125
Typ
Max
74.1
73.8
Unit
72
71
70.5
dB
dB
dB
dB
dB
dB
dB
dB
dB
77.3
77.3
76
75.4
73.5
dB
dB
dB
dB
dB
73.9
73.7
71.5
66.3
64.3
dB
dB
dB
dB
dB
dB
dB
dB
dB
73.2
72.9
73.0
72.5
25°C
25°C
25°C
25°C
25°C
77.4
77.3
75.7
75.1
72.5
76.9
76.8
75.4
75.2
71.8
dB
dB
dB
dB
dB
25°C
25°C
25°C
25°C
25°C
25°C
25°C
12.2
12.2
12.1
12.0
11.8
11.7
11.6
12.2
12.1
12.0
12.0
11.8
11.7
11.6
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Rev. 0 | Page 4 of 40
AD9445
Parameter
SPURIOUS-FREE DYNAMIC RANGE
(SFDR, Second or Third Harmonic)
fIN = 10 MHz
fIN = 30 MHz
fIN = 170 MHz
fIN = 225 MHz1
fIN = 300 MHz2
fIN = 400 MHz2
fIN = 450 MHz2
fIN = 10 MHz (3.2 V p-p Input)
fIN = 30 MHz (3.2 V p-p Input)
fIN = 170 MHz (3.2 V p-p Input)
fIN = 225 MHz (3.2 V p-p Input)1
fIN = 300 MHz (3.2 V p-p Input)2
WORST SPUR EXCLUDING SECOND OR
THIRD HARMONICS
fIN = 10 MHz
fIN = 30 MHz
fIN = 170 MHz
fIN = 225 MHz1
fIN = 300 MHz2
fIN = 400 MHz2
fIN = 450 MHz2
fIN = 10 MHz (3.2 V p-p Input)
fIN = 30 MHz (3.2 V p-p Input)
fIN = 170 MHz (3.2 V p-p Input)
fIN = 225 MHz (3.2 V p-p Input)1
fIN = 300 MHz (3.2 V p-p Input)2
TWO-TONE SFDR
fIN = 30.3 MHz @ −7 dBFS,
31.3 MHz @ −7 dBFS
fIN = 170.3 MHz @ −7 dBFS,
171.3 MHz @ −7 dBFS
ANALOG BANDWIDTH
1
2
Temp
25°C
25°C
Full
25°C
25°C
Full
25°C
25°C
25°C
Min
AD9445BSVZ-105
Typ
Max
84
83
82
76
75
76
95
92
85
82
80
83
75
75
94
87
87
75
70
25°C
25°C
25°C
25°C
25°C
92
88
86
81
77
25°C
25°C
Full
25°C
25°C
Full
25°C
25°C
25°C
−97
−99
−99
−94
−97
−93
−82
Min
−90
−90
−92
−88
−86
−90
AD9445BSVZ-125
Typ
Max
95
94
Unit
87
73
69
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
92
91
86
80
76
dBc
dBc
dBc
dBc
dBc
91
88
−97
−98
−93
−94
−92
−93
−87
−89
−88
−85
−84
−80
−82
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
25°C
25°C
25°C
25°C
25°C
−97
−97
−97
−95
−93
−95
−95
−95
−94
−91
dBc
dBc
dBc
dBc
dBc
25°C
102
102
dBFS
25°C
92
91
dBFS
Full
615
615
MHz
RF ENABLE = low (AGND ) for AD9445-105; RF ENABLE = high (AVDD1) for AD9445-125.
RF ENABLE = high (AVDD1).
Rev. 0 | Page 5 of 40
AD9445
DIGITAL SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, RLVDS_BIAS = 3.74 kΩ, unless otherwise noted.
Table 3.
Parameter
CMOS LOGIC INPUTS (DFS, DCS MODE, OUTPUT MODE)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
DIGITAL OUTPUT BITS—CMOS MODE (D0 to D13, OTR) 1
DRVDD = 3.3 V
High Level Output Voltage
Low Level Output Voltage
DIGITAL OUTPUT BITS—LVDS MODE (D0 to D13, OTR)
VOD Differential Output Voltage 2
VOS Output Offset Voltage
CLOCK INPUTS (CLK+, CLK−)
Differential Input Voltage
Common-Mode Voltage
Differential Input Resistance
Differential Input Capacitance
1
2
Temp
Full
Full
Full
Full
Full
AD9445BSVZ-105
Min
Typ
Max
AD9445BSVZ-125
Min
Typ
Max
2.0
2.0
0.8
200
+10
−10
−10
2
Full
Full
3.25
Full
Full
247
1.125
Full
Full
Full
Full
0.2
1.3
1.1
0.8
200
+10
2
3.25
0.2
1.5
1.4
2
545
1.375
247
1.125
1.6
1.7
0.2
1.3
1.1
1.5
1.4
2
Unit
V
V
μA
μA
pF
0.2
V
V
545
1.375
mV
V
1.6
1.7
V
V
kΩ
pF
Output voltage levels measured with 5 pF load on each output.
LVDS RTERM = 100 Ω.
SWITCHING SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Minimum Conversion Rate
CLK Period
CLK Pulse Width High 1 (tCLKH)
CLK Pulse Width Low1 (tCLKL)
DATA OUTPUT PARAMETERS
Output Propagation Delay—CMOS (tPD) 2 (Dx, DCO+)
Output Propagation Delay—LVDS (tPD) 3 (Dx+), (tCPD)3 (DCO+)
Pipeline Delay (Latency)
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
1
2
3
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
AD9445BSVZ-105
Min
Typ
Max
AD9445BSVZ-125
Min
Typ
Max
105
125
10
9.5
3.8
3.8
2.1
8.0
3.2
3.2
3.35
3.6
13
4.8
60
With duty cycle stabilizer (DCS) enabled.
Output propagation delay is measured from clock 50% transition to data 50% transition with 5 pF load.
LVDS RTERM = 100 Ω. Measured from the 50% point of the rising edge of CLK+ to the 50% point of the data transition.
Rev. 0 | Page 6 of 40
10
2.3
3.35
3.6
13
60
4.8
Unit
MSPS
MSPS
ns
ns
ns
ns
ns
Cycles
ns
fsec
rms
AD9445
TIMING DIAGRAMS
N–1
N
N+1
AIN
tCLKL
tCLKH
1/fS
CLK+
CLK–
tPD
N
N – 12
N – 13
DATA OUT
N+1
13 CLOCK CYCLES
05489-002
DCO+
DCO–
tCPD
Figure 2. LVDS Mode Timing Diagram
N–1
N
N+1
VIN
N+2
tCLKL
tCLKH
CLK–
CLK+
tPD
DX
13 CLOCK CYCLES
N – 13
N – 12
N–1
N
05489-003
DCO+
DCO–
Figure 3. CMOS Timing Diagram
Rev. 0 | Page 7 of 40
AD9445
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
ELECTRICAL
AVDD1
AVDD2
DRVDD
AGND
AVDD1
AVDD2
AVDD2
D0± to D13±
CLK+/CLK−
OUTPUT MODE, DCS
MODE, DFS, SFDR,
RF ENABLE
VIN+, VIN−
VREF
SENSE
REFT, REFB
ENVIRONMENTAL
Storage Temperature
Range
Operating Temperature
Range
Lead Temperature
(Soldering 10 sec)
Junction Temperature
With
Respect
To
Rating
AGND
AGND
DGND
DGND
DRVDD
DRVDD
AVDD1
DGND
AGND
AGND
−0.3 V to +4 V
−0.3 V to +6 V
−0.3 V to +4 V
−0.3 V to +0.3 V
−4 V to +4 V
−4 V to +6 V
−4 V to +6 V
–0.3 V to DRVDD + 0.3 V
–0.3 V to AVDD1 + 0.3 V
–0.3 V to AVDD1 + 0.3 V
AGND
AGND
AGND
AGND
–0.3 V to AVDD2 + 0.3 V
–0.3 V to AVDD1 + 0.3 V
–0.3 V to AVDD1 + 0.3 V
–0.3 V to AVDD1 + 0.3 V
–65°C to +125°C
–40°C to +85°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
The heat sink of the AD9445 package must be soldered to ground.
Table 6.
Package Type
100-lead TQFP/EP
θJA
19.8
θJB
8.3
θJC
2
Unit
°C/W
Typical θJA = 19.8°C/W (heat sink soldered) for multilayer
board in still air.
Typical θJB = 8.3°C/W (heat sink soldered) for multilayer board
in still air.
Typical θJC = 2°C/W (junction to exposed heat sink) represents
the thermal resistance through heat sink path.
Airflow increases heat dissipation, effectively reducing θJA. Also,
more metal directly in contact with the package leads from
metal traces through holes, ground, and power planes reduces
the θJA. It is required that the exposed heat sink be soldered to
the ground plane.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 8 of 40
AD9445
TERMINOLOGY
Analog Bandwidth (Full Power Bandwidth)
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Minimum Conversion Rate
The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Aperture Delay (tA)
The delay between the 50% point of the rising edge of the clock
and the instant at which the analog input is sampled.
Offset Error
The major carry transition should occur for an analog value of
½ LSB below VIN+ = VIN−. Offset error is defined as the
deviation of the actual transition from that point.
Aperture Uncertainty (Jitter, tJ)
The sample-to-sample variation in aperture delay.
Clock Pulse Width and Duty Cycle
Pulse width high is the minimum amount of time that the
clock pulse should be left in the Logic 1 state to achieve rated
performance. Pulse width low is the minimum time the clock
pulse should be left in the low state. At a given clock rate, these
specifications define an acceptable clock duty cycle.
Differential Nonlinearity (DNL, No Missing Codes)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 14-bit resolution indicates that all 16,384
codes must be present over all operating ranges.
(SINAD − 1.76 )
6.02
Gain Error
The first code transition should occur at an analog value of
½ LSB above negative full scale. The last transition should occur
at an analog value of 1½ LSB below the positive full scale. Gain
error is the deviation of the actual difference between first and
last code transitions and the ideal difference between first and
last code transitions.
Integral Nonlinearity (INL)
The deviation of each individual code from a line drawn from
negative full scale through positive full scale. The point used as
negative full scale occurs ½ LSB before the first code transition.
Positive full scale is defined as a level 1½ LSB beyond the last
code transition. The deviation is measured from the middle of
each particular code to the true straight line.
Maximum Conversion Rate
The clock rate at which parametric testing is performed.
Output Propagation Delay (tPD)
The delay between the clock rising edge and the time when all
bits are within valid logic levels.
Power-Supply Rejection Ratio
The change in full scale from the value with the supply at the
minimum limit to the value with the supply at the maximum
limit.
Signal-to-Noise and Distortion (SINAD)
The ratio of the rms input signal amplitude to the rms value of
the sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc.
Effective Number of Bits (ENOB)
The effective number of bits for a sine wave input at a given
input frequency can be calculated directly from its measured
SINAD using the following formula:
ENOB =
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input
after a transition from 10% above positive full scale to 10%
above negative full scale, or from 10% below negative full scale
to 10% below positive full scale.
Signal-to-Noise Ratio (SNR)
The ratio of the rms input signal amplitude to the rms value of
the sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious component
may be a harmonic. SFDR can be reported in dBc (that is, degrades
as signal level is lowered) or dBFS (always related back to converter
full scale).
Temperature Drift
The temperature drift for offset error and gain error specifies
the maximum change from the initial (25°C) value to the value
at TMIN or TMAX.
Total Harmonic Distortion (THD)
The ratio of the rms input signal amplitude to the rms value of
the sum of the first six harmonic components.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
Rev. 0 | Page 9 of 40
AD9445
DRVDD
D9–
D9+
D10–
D10+
D11–
D11+
D12–
D12+
D13–
D13+ (MSB)
DRGND
DRVDD
OR–
OR+
AGND
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AGND
AGND
RF ENABLE
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
DCS MODE 1
75
DRGND
74
D8+
3
73
D8–
DFS
4
72
D7+
LVDS_BIAS
5
71
D7–
AVDD1
6
70
D6+
SENSE
7
69
D6–
VREF
8
68
DCO+
AGND
9
67
DCO–
66
D5+
65
D5–
AVDD2 12
64
DRVDD
AVDD2 13
63
DRGND
AVDD2 14
62
D4+
AVDD2 15
61
D4–
AVDD2 16
60
D3+
AVDD2 17
59
D3–
AVDD1 18
58
D2+
AVDD1 19
57
D2–
AVDD1 20
56
D1+
AGND 21
55
D1–
VIN+ 22
54
D0+
VIN– 23
53
D0– (LSB)
AGND 24
52
DNC
AVDD2 25
51
DNC
DNC
2
OUTPUT MODE
PIN 1
AD9445
LVDS MODE
REFT 10
TOP VIEW
(Not to Scale)
REFB 11
Figure 4. 100-Lead TQFP/EP Pin Configuration in LVDS Mode
Rev. 0 | Page 10 of 40
05489-004
DNC
DNC
DRVDD
DRGND
AGND
AVDD1
AVDD1
AVDD1
AGND
CLK–
CLK+
AGND
AVDD1
AVDD2
AVDD1
AVDD2
AVDD1
AVDD1
AVDD1
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DNC = DO NOT CONNECT
AD9445
Table 7. Pin Function Descriptions—100-Lead TQFP/EP in LVDS Mode
Pin No.
1
Mnemonic
DCS MODE
2, 49 to 52
3
DNC
OUTPUT MODE
4
DFS
5
6, 18 to 20, 32 to 34, 36, 38,
43 to 45, 92 to 97
7
LVDS_BIAS
AVDD1
8
VREF
9, 21, 24, 39, 42, 46, 91, 98, 99,
Exposed Heat Sink
10
AGND
11
REFB
12 to 17, 25 to 31, 35, 37
22
23
40
41
47, 63, 75, 87
48, 64, 76, 88
53
54
55
56
57
58
59
60
61
62
65
66
67
68
69
70
71
72
73
74
77
78
79
80
81
82
AVDD2
VIN+
VIN−
CLK+
CLK−
DRGND
DRVDD
D0− (LSB)
D0+
D1−
D1+
D2−
D2+
D3−
D3+
D4−
D4+
D5−
D5+
DCO−
DCO+
D6−
D6+
D7−
D7+
D8−
D8+
D9−
D9+
D10−
D10+
D11−
D11+
SENSE
REFT
Description
Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (AGND) to
enable DCS (recommended); DCS = high (AVDD1) to disable DCS.
Do Not Connect. These pins should float.
CMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode;
OUTPUT MODE = 1 (AVDD1) for LVDS outputs.
Data Format Select Pin. CMOS control pin that determines the format of the output data.
DFS = high (AVDD1) for twos complement; DFS = low (ground) for offset binary format.
Set Pin for LVDS Output Current. Place 3.7 kΩ resistor terminated to DRGND.
3.3 V (±5%) Analog Supply.
Reference Mode Selection. Connect to AGND for internal 1 V reference; connect to
AVDD1 for external reference.
1.0 V Reference I/O. Function dependent on SENSE and external programming resistors.
Decouple to ground with 0.1 μF and 10 μF capacitors.
Analog Ground. The exposed heat sink on the bottom of the package must be
connected to AGND.
Differential Reference Output. Decoupled to ground with 0.1 μF capacitor and to REFB
(Pin 14) with 0.1 μF and 10 μF capacitors.
Differential Reference Output. Decoupled to ground with a 0.1 μF capacitor and to REFT
(Pin 13) with 0.1 μF and 10 μF capacitors.
5.0 V Analog Supply (±5%).
Analog Input—True.
Analog Input—Complement.
Clock Input—True.
Clock Input—Complement.
Digital Output Ground.
3.3 V Digital Output Supply (3.0 V to 3.6 V).
D0 Complement Output Bit (LVDS Levels).
D0 True Output Bit.
D1 Complement Output Bit.
D1 True Output Bit.
D2 Complement Output Bit.
D2 True Output Bit.
D3 Complement Output Bit.
D3 True Output Bit.
D4 Complement Output Bit.
D4 True Output Bit.
D5 Complement Output Bit.
D5 True Output Bit.
Data Clock Output—Complement.
Data Clock Output—True.
D6 Complement Output Bit.
D6 True Output Bit.
D7 Complement Output Bit.
D7 True Output Bit.
D8 Complement Output Bit.
D8 True Output Bit.
D9 Complement Output Bit.
D9 True Output Bit.
D10 Complement Output Bit.
D10 True Output Bit.
D11 Complement Output Bit.
D11 True Output Bit.
Rev. 0 | Page 11 of 40
AD9445
Pin No.
83
84
85
86
89
90
100
Mnemonic
D12−
D12+
D13−
D13+ (MSB)
OR−
OR+
RF ENABLE
Description
D12 Complement Output Bit.
D12 True Output Bit.
D13 Complement Output Bit.
D13 True Output Bit.
Out-of-Range Complement Output Bit.
Out-of-Range True Output Bit.
RF ENABLE Control Pin. CMOS-compatible control pin to optimize the configuration of
the AD9445 analog front end. Connecting RF ENABLE to AGND optimizes SFDR
performance for applications with analog input frequencies 230 MHz for the 105 MSPS speed
grade, this pin should be connected to AVDD1 for optimum SFDR performance. Power
dissipation from AVDD2 increases by 150 mW to 200 mW.
Rev. 0 | Page 12 of 40
DRVDD
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
DRGND
DRVDD
D13 (MSB)
OR
AGND
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AVDD1
AGND
AGND
RF ENABLE
AD9445
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
DCS MODE 1
75
DRGND
74
D2
3
73
D1
DFS
4
72
D0 (LSB)
LVDS_BIAS
5
71
DNC
AVDD1
6
70
DNC
SENSE
7
69
DNC
VREF
8
68
DCO+
AGND
9
67
DCO–
66
DNC
65
DNC
AVDD2 12
64
DRVDD
AVDD2 13
63
DRGND
AVDD2 14
62
DNC
AVDD2 15
61
DNC
AVDD2 16
60
DNC
AVDD2 17
59
DNC
AVDD1 18
58
DNC
AVDD1 19
57
DNC
AVDD1 20
56
DNC
AGND 21
55
DNC
VIN+ 22
54
DNC
VIN– 23
53
DNC
AGND 24
52
DNC
AVDD2 25
51
DNC
DNC
2
OUTPUT MODE
PIN 1
AD9445
CMOS MODE
REFT 10
TOP VIEW
(Not to Scale)
REFB 11
Figure 5. 100-Lead TQFP/EP Pin Configuration in CMOS Mode
Rev. 0 | Page 13 of 40
05489-005
DNC
DNC
DRVDD
DRGND
AGND
AVDD1
AVDD1
AVDD1
AGND
CLK–
CLK+
AGND
AVDD1
AVDD2
AVDD1
AVDD2
AVDD1
AVDD1
AVDD1
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
AVDD2
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DNC = DO NOT CONNECT
AD9445
Table 8. Pin Function Descriptions—100-Lead TQFP/EP in CMOS Mode
Pin No.
1
Mnemonic
DCS MODE
2, 49 to 62, 65 to 66, 69 to 71
3
DNC
OUTPUT
MODE
DFS
4
5
6, 18 to 20, 32 to 34, 36, 38,
43 to 45, 92 to 97
7
LVDS_BIAS
AVDD1
8
VREF
9, 21, 24, 39, 42, 46, 91, 98,
99, Exposed Heat Sink
10
AGND
11
REFB
12 to 17, 25 to 31, 35, 37
22
23
40
41
47, 63, 75, 87
48, 64, 76, 88
67
68
72
73
74
77
78
79
80
81
82
83
84
85
86
89
90
100
AVDD2
VIN+
VIN−
CLK+
CLK−
DRGND
DRVDD
DCO−
DCO+
D0 (LSB)
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13 (MSB)
OR
RF ENABLE
SENSE
REFT
Description
Clock Duty Cycle Stabilizer (DCS) Control Pin. CMOS compatible. DCS = low (AGND) to enable
DCS (recommended); DCS = high (AVDD1) to disable DCS.
Do Not Connect. These pins should float.
CMOS-Compatible Output Logic Mode Control Pin. OUTPUT MODE = 0 for CMOS mode;
OUTPUT MODE = 1 (AVDD1) for LVDS outputs.
Data Format Select Pin. CMOS control pin that determines the format of the output data.
DFS = high (AVDD1) for twos complement; DFS = low (ground) for offset binary format.
Set Pin for LVDS Output Current. Place 3.7 kΩ resistor terminated to DRGND.
3.3 V (±5%) Analog Supply.
Reference Mode Selection. Connect to AGND for internal 1 V reference; connect to AVDD1 for
external reference.
1.0 V Reference I/O. Function dependent on SENSE and external programming resistors.
Decouple to ground with 0.1 μF and 10 μF capacitors.
Analog Ground. The exposed heat sink on the bottom of the package must be connected to
AGND.
Differential Reference Output. Decoupled to ground with 0.1 μF capacitor and to REFB
(Pin 14) with 0.1 μF and 10 μF capacitors.
Differential Reference Output. Decoupled to ground with a 0.1 μF capacitor and to REFT
(Pin 13) with 0.1 μF and 10 μF capacitors.
5.0 V Analog Supply (±5%).
Analog Input—True.
Analog Input—Complement.
Clock Input—True.
Clock Input—Complement.
Digital Output Ground.
3.3 V Digital Output Supply (3.0 V to 3.6 V).
Data Clock Output—Complement.
Data Clock Output—True.
D0 True Output Bit (CMOS levels).
D1 True Output Bit.
D2 True Output Bit.
D3 True Output Bit.
D4 True Output Bit.
D5 True Output Bit.
D6 True Output Bit.
D7 True Output Bit.
D8 True Output Bit.
D9 True Output Bit.
D10 True Output Bit.
D11 True Output Bit.
D12 True Output Bit.
D13 True Output Bit.
Out-of-Range True Output Bit.
RF ENABLE CMOS-compatible Control Pin. Optimizes the configuration of the analog front end.
Connecting RF ENABLE to AGND optimizes SFDR performance for applications with analog input
frequencies 230 MHz
for the 105 MSPS speed grade, this pin should be connected to AVDD1 for optimum SFDR.
Power dissipation from AVDD2 increases by 150 mW to 200 mW.
Rev. 0 | Page 14 of 40
AD9445
EQUIVALENT CIRCUITS
AVDD2
VIN+
1kΩ
6pF
DRVDD
3.5V
T/H
X1
AVDD2
1kΩ
DX
6pF
05489-009
05489-006
VIN–
Figure 6. Equivalent Analog Input Circuit
Figure 9. Equivalent CMOS Digital Output Circuit
VDD
DRVDD
DRVDD
RF ENABLE, DCS
MODE, OUTPUT
MODE, DFS
K
1.2V
ILVDSOUT
05489-007
3.74kΩ
05489-010
30kΩ
LVDS_BIAS
Figure 10. Equivalent Digital Input Circuit,
DFS, DCS MODE, OUTPUT MODE
Figure 7. Equivalent LVDS_BIAS Circuit
AVDD2
DRVDD
3kΩ
3kΩ
CLK–
CLK+
V
DX–
DX+
V
V
2.5kΩ
2.5kΩ
05489-011
05489-008
V
Figure 11. Equivalent Sample Clock Input Circuit
Figure 8. Equivalent LVDS Digital Output Circuit
Rev. 0 | Page 15 of 40
AD9445
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, rated sample rate, LVDS mode, DCS enabled, TA = 25°C, 2.0 V p-p differential
input, AIN = −1.0 dBFS, internal trimmed reference (nominal VREF = 1.0 V), unless otherwise noted.
0
0
125MSPS
30.3MHz @ –1.0dBFS
SNR = 73.4dB
ENOB = 12.1BITS
SFDR = 94dBc
–10
–20
–20
–30
–40
AMPLITUDE (dBFS)
–50
–60
–70
–80
–90
–100
–40
–50
–60
–70
–80
–90
–100
–110
05489-012
–110
–120
–130
0
15.625
31.250
46.875
05489-015
AMPLITUDE (dBFS)
–30
125MSPS
225.3MHz @ –1.0dBFS
SNR = 72.9dB
ENOB = 12.1BITS
SFDR = 88dBc
–10
–120
–130
62.500
0
15.625
FREQUENCY (MHz)
Figure 12. AD9445-125 64k Point Single-Tone FFT/125 MSPS/30.3 MHz
62.500
0
125MSPS
100.3MHz @ –1.0dBFS
SNR = 0dB
ENOB = 12.1BITS
SFDR = 96dBc
–20
–30
125MSPS
300.3MHz @ –1.0dBFS
SNR = 72.0dB
ENOB = 11.8BITS
SFDR = 87dBc
–10
–20
–30
–40
AMPLITUDE (dBFS)
–50
–60
–70
–80
–90
–100
–40
–50
–60
–70
–80
–90
–100
–110
05489-013
–110
–120
–130
0
15.625
31.250
46.875
05489-016
AMPLITUDE (dBFS)
46.875
Figure 15. AD9445-125 64k Point Single-Tone FFT/125 MSPS/225.3 MHz
0
–10
–120
–130
62.500
0
15.625
FREQUENCY (MHz)
31.250
46.875
62.500
FREQUENCY (MHz)
Figure 13. AD9445-125 64k Point Single-Tone FFT/125 MSPS/100.3 MHz
Figure 16. AD9445-125 64k Point Single-Tone FFT/125 MSPS/300.3 MHz
0
0
125MSPS
170.3MHz @ –1.0dBFS
SNR = 73.2dB
ENOB = 12.0BITS
SFDR = 91dBc
–10
–20
–30
125MSPS
450.3MHz @ –1.0dBFS
SNR = 70.5dB
ENOB = 11.6BITS
SFDR = 69dBc
–10
–20
–30
–40
AMPLITUDE (dBFS)
–50
–60
–70
–80
–90
–100
–40
–50
–60
–70
–80
–90
–100
–110
05489-014
–110
–120
–130
0
15.625
31.250
46.875
05489-017
AMPLITUDE (dBFS)
31.250
FREQUENCY (MHz)
–120
–130
62.500
0
FREQUENCY (MHz)
15.625
31.250
46.875
62.500
FREQUENCY (MHz)
Figure 14. AD9445-125 64k Point Single-Tone FFT/125 MSPS/170.3 MHz
Figure 17. AD9445-125 64k Point Single-Tone FFT/125 MSPS/450.3 MHz
Rev. 0 | Page 16 of 40
AD9445
100
100
SFDR +85°C
SFDR +85°C
95
95
SFDR –40°C
SFDR +25°C
90
90
SFDR –40°C
SFDR +25°C
85
85
SNR –40°C
(dB)
(dB)
SNR +25°C
80
80
SNR –40°C
75
75
70
70
SNR +25°C
SNR +85°C
SNR +85°C
60
55
0
50
100
150
200
250
300
350
400
05489-021
65
05489-018
65
60
55
450
0
50
100
ANALOG INPUT FREQUENCY (MHz)
Figure 18. AD9445-125 SNR/SFDR vs. Analog Input Frequency,
125 MSPS, 2.0 V p-p Input Range
100
150
200
250
300
350
400
450
ANALOG INPUT FREQUENCY (MHz)
Figure 21. AD9445-125 SNR/SFDR vs. Analog Input Frequency,
125 MSPS, 3.2 V p-p Input Range
105
SFDR +25°C
SFDR +85°C
95
125M SFDR dBc
100
90
95
105M SFDR dBc
85
SFDR –40°C
90
SNR –40°C
80
(dB)
(dB)
SNR +25°C
75
85
70
80
SNR +85°C
65
125M SNR dB
60
55
10
20
30
40
50
60
70
80
90
105M SNR dB
70
100
0
20
40
ANALOG INPUT FREQUENCY (MHz)
100
120
140
Figure 22. AD9445 Single-Tone SNR/SFDR vs. Sample Rate 2.3 MHz
120
120
SFDR dBFS
SFDR dBFS
100
100
80
80
SNR dBFS
(dB)
SNR dBFS
60
40
60
40
SFDR dBc
SFDR dBc
20
20
05489-020
(dB)
80
SAMPLE RATE (MSPS)
Figure 19. AD9445-125 SNR/SFDR vs. Analog Input Frequency,
3.2 V p-p Input Range, 125 MSPS, CMOS Output Mode
SNR dB
0
–100
60
–90
–80
–70
–60
–50
–40
–30
–20
–10
05489-023
0
05489-022
05489-019
75
SNR dB
0
–100
0
ANALOG INPUT AMPLITUDE (dB)
–90
–80
–70
–60
–50
–40
–30
–20
–10
ANALOG INPUT AMPLITUDE (dB)
Figure 20. AD9445-125 SNR/SFDR vs. Analog Input Level,
125 MSPS/225.3 MHz
Figure 23. AD9445-125 SNR/SFDR vs. Analog Input Level,
125 MSPS/225.3 MHz, CMOS Output Mode
Rev. 0 | Page 17 of 40
0
AD9445
0
0
105MSPS
30.3MHz @ –1.0dBFS
SNR = 74.3dB
ENOB = 12.2BITS
SFDR = 92dBc
–10
–20
–20
–30
–40
AMPLITUDE (dBFS)
–50
–60
–70
–80
–90
–100
–40
–50
–60
–70
–80
–90
–100
–110
05489-024
–110
–120
–130
0
13.125
26.250
39.375
05489-027
AMPLITUDE (dBFS)
–30
105MSPS
225.3MHz @ –1.0dBFS
SNR = 73.0dB
ENOB = 12.0BITS
SFDR = 87dBc
–10
–120
–130
52.500
0
13.125
FREQUENCY (MHz)
Figure 24. AD9445-105 64k Point Single-Tone FFT/105 MSPS/30.3 MHz
52.500
0
105MSPS
100.3MHz @ –1.0dBFS
SNR = 73.5dB
ENOB = 11.8BITS
SFDR = 93dBc
–20
–30
105MSPS
300.3MHz @ –1.0dBFS
SNR = 72.1dB
ENOB = 11.8BITS
SFDR = 87dBc
–10
–20
–30
–40
AMPLITUDE (dBFS)
–50
–60
–70
–80
–90
–100
–40
–50
–60
–70
–80
–90
–100
–110
05489-025
–110
–120
–130
0
13.125
26.250
39.375
05489-028
AMPLITUDE (dBFS)
39.375
Figure 27. AD9445-105 64k Point Single-Tone FFT/105 MSPS/225.3 MHz
0
–10
–120
–130
52.500
0
13.125
FREQUENCY (MHz)
26.250
39.375
52.500
FREQUENCY (MHz)
Figure 25. AD9445-105 64k Point Single-Tone FFT/105 MSPS/100.3 MHz
Figure 28. AD9445-105 64k Point Single-Tone FFT/105 MSPS/300.3 MHz
0
0
105MSPS
170.3MHz @ –1.0dBFS
SNR = 73.6dB
ENOB = 12.1BITS
SFDR = 94dBc
–10
–20
–30
105MSPS
450.3MHz @ –1.0dBFS
SNR = 70.5dB
ENOB = 11.6BITS
SFDR = 70dBc
–10
–20
–30
–40
AMPLITUDE (dBFS)
–50
–60
–70
–80
–90
–100
–40
–50
–60
–70
–80
–90
–100
–110
05489-026
–110
–120
–130
0
13.125
26.250
39.375
05489-029
AMPLITUDE (dBFS)
26.250
FREQUENCY (MHz)
–120
–130
52.500
0
FREQUENCY (MHz)
13.125
26.250
39.375
52.500
FREQUENCY (MHz)
Figure 26. AD9445-105 64k Point Single-Tone FFT/105 MSPS/170.3 MHz
Figure 29. AD9445-105 64k Point Single-Tone FFT/105 MSPS/450.3 MHz
Rev. 0 | Page 18 of 40
AD9445
100
100
SFDR +25°C
SFDR –40°C
95
95
SFDR +25°C
90
90
SFDR +85°C
SFDR +85°C
SFDR –40°C
85
80
(dB)
(dB)
85
SNR –40°C
80
75
75
70
70
SNR –40°C
SNR +25°C
SNR +85°C
SNR +85°C
SNR +25°C
60
55
0
50
100
150
200
250
300
350
400
05489-033
65
05489-030
65
60
55
450
0
50
100
ANALOG INPUT FREQUENCY (MHz)
Figure 30. AD9445-105 SNR/SFDR vs. Analog Input Frequency,
105 MSPS, 2.0 V p-p
200
250
300
350
400
450
Figure 33. AD9445-105 SNR/SFDR vs. Analog Input Frequency,
105 MSPS, 3.2 V p-p
100
100
SFDR +25°C
SFDR +85°C
95
95
90
90
85
SFDR –40°C
80
SFDR dBc
85
SNR –40°C
(dB)
(dB)
150
ANALOG INPUT FREQUENCY (MHz)
80
75
SNR dB
75
70
SNR +25°C
SNR +85°C
70
65
55
0
20
40
60
80
100
120
140
160
60
2.7
180
05489-034
65
05489-031
60
2.9
Figure 31. AD9445-105 SNR/SFDR vs. Analog Input Frequency,
3.2 V p-p Input Range, 105 MSPS, CMOS Output Mode
3.5
3.7
3.9
4.1
4.3
120
SFDR dBFS
SFDR dBFS
100
100
80
80
SNR dBFS
(dB)
SNR dBFS
60
SFDR dBc
60
40
SFDR dBc
20
SNR dB
0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
05489-035
20
05489-032
(dB)
3.3
Figure 34. AD9445-105 SNR/SFDR vs. Analog Input Common Mode,
105 MSPS/10.3 MHz
120
40
3.1
ANALOG INPUT COMMON-MODE VOLTAGE
ANALOG INPUT FREQUENCY (MHz)
SNR dB
0
–100
0
ANALOG INPUT AMPLITUDE (dB)
–90
–80
–70
–60
–50
–40
–30
–20
–10
ANALOG INPUT AMPLITUDE (dB)
Figure 32. AD9445-105 SNR/SFDR vs. Analog Input Level,
105 MSPS/225.3 MHz
Figure 35. AD9445-105 SNR/SFDR vs. Analog Input Level,
105 MSPS/225.3 MHz, CMOS Output Mode
Rev. 0 | Page 19 of 40
0
AD9445
0
0
125MSPS
30.3MHz @ –7.0dBFS
31.3MHz @ –7.0dBFS
SFDR = 102dBFS
–10
–20
–20
SFDR dBc
–30
–40
SPUR AND IMD3 (dB)
–50
–60
–70
–80
–90
–100
–40
WORST IMD3 dBc
–50
–60
–70
–80
–90
–110
SFDR dBFS
05489-037
–120
–130
–140
13.625
0
27.250
40.875
–110
WORST IMD3 dBFS
–120
–100
54.500
–90
–80
FREQUENCY (MHz)
–60
–50
–40
0
0
–10
–10
–30
AMPLITUDE (dBFS)
SFDR dBc
–40
–50
WORST IMD3 dBc
–70
–80
SFDR dBFS
–90
–90
–80
–70
–40
–50
–60
–70
–80
–90
–100
–60
–50
–40
–120
05489-038
WORST IMD3 dBFS
–120
–100
0
–110
–100
–110
–10
–30
–20
–10
05489-042
–60
–20
105MSPS
30.3MHz @ –7.0dBFS
31.3MHz @ –7.0dBFS
SFDR = 102dBFS
–20
–30
–30
Figure 39. AD9445-125 Two-Tone SFDR vs. Analog Input Level
125 MSPS/170.3 MHz, 171.3 MHz
–20
SPUR AND IMD3 (dB)
–70
FUNDAMENTAL LEVEL (dB)
Figure 36. AD9445-125 64k Point Two-Tone FFT/
125 MSPS/30.3 MHz, 31.3 MHz
–130
–140
0
0
13.125
FUNDAMENTAL LEVEL (dB)
26.250
39.375
52.500
FREQUENCY (MHz)
Figure 37. AD9445-125 Two-Tone SFDR vs. Analog Input Level
125 MSPS/30.3 MHz, 31.3 MHz
Figure 40. AD9445-105 64k Point Two-Tone FFT/105 MSPS/30.3 MHz, 31.3 MHz
0
0
125MSPS
170.3MHz @ –7.0dBFS
171.3MHz @ –7.0dBFS
SFDR = 91dBFS
–10
–20
–30
–10
–20
–30
SPUR AND IMD3 (dB)
–40
–50
–60
–70
–80
–90
–100
SFDR dBc
–40
–50
WORST IMD3 dBc
–60
–70
–80
–90
–110
SFDR dBFS
–100
–120
05489-040
AMPLITUDE (dBFS)
05489-041
–100
–130
–140
0
13.625
27.250
40.875
–110
–120
–100
54.500
FREQUENCY (MHz)
05489-043
AMPLITUDE (dBFS)
–30
–10
WORST IMD3 dBFS
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
FUNDAMENTAL LEVEL (dB)
Figure 38. AD9445-125 64k Point Two-Tone FFT/
125 MSPS/170.3 MHz, 171.3 MHz
Figure 41. AD9445-105 Two-Tone SFDR vs. Analog Input Level
105 MSPS/30.3 MHz, 31.3 MHz
Rev. 0 | Page 20 of 40
AD9445
25000
30000
23754
SAMPLE SIZE = 65538
22190
26294
25000
20000
FREQUENCY
10000
9003
7968
10000
5000
05489-044
5000
1355
1127
75
62
0
N–4 N–3 N–2 N–1
N
2
3493
3350
3
0
N+1 N+2 N+3 N+4
307
227
N–4 N–3 N–2 N–1
OUTPUT CODE
N
2
N+1 N+2 N+3 N+4
OUTPUT CODE
Figure 42. AD9445-125 Grounded Input Histogram
Figure 45. AD9445-105 Grounded Input Histogram
0
0
105MSPS
170.3MHz @ –7.0dBFS
171.3MHz @ –7.0dBFS
SFDR = 92dBFS
–10
–20
–30
–0.1
–0.2
–40
GAIN ERROR (%FSR)
–50
–60
–70
–80
–90
–100
–0.3
–0.4
–0.5
–0.6
–110
–0.7
05489-045
–120
–130
–140
0
13.125
26.250
39.375
–0.8
–40
52.500
05489-048
AMPLITUDE (dBFS)
16117
15743
15000
05489-047
FREQUENCY
20000
15000
–20
0
FREQUENCY (MHz)
20
40
60
80
TEMPERATURE (°C)
Figure 43. AD9445-105 64k Point Two-Tone FFT/105 MSPS/170.3 MHz, 171.3 MHz
Figure 46. AD9445-125 Gain vs. Temperature
0.4
0
–10
0.3
–20
0.2
DNL ERROR (LSB)
SFDR dBc
–40
WORST IMD3 dBc
–60
–70
–80
–90
–100
–120
–100
WORST IMD3 dBFS
–90
–80
–70
0
–0.1
–0.2
SFDR dBFS
–110
0.1
–60
–0.3
–50
–40
–30
–20
–10
–0.4
0
0
4096
8192
12288
16384
OUTPUT CODE
FUNDAMENTAL LEVEL (dB)
Figure 44. AD9445-105 Two-Tone SFDR vs. Analog Input Level
105 MSPS/170.3 MHz, 171.3 MHz
05489-049
–50
05489-046
SPUR AND IMD3 (dB)
–30
Figure 47. AD9445-105 DNL Error vs. Output Code, 105 MSPS, 10.3 MHz
Rev. 0 | Page 21 of 40
AD9445
0.4
1.0
0.8
0.3
0.6
0.4
INL ERROR (LSB)
DNL ERROR (LSB)
0.2
0.1
0
–0.1
0.2
0
–0.2
–0.4
–0.2
05489-050
–0.4
0
4096
8192
12288
05489-053
–0.6
–0.3
–0.8
–1.0
0
16384
4096
8192
OUTPUT CODE
12288
16384
OUTPUT CODE
Figure 48. AD9445-125 DNL Error vs. Output Code, 125 MSPS, 10.3 MHz
Figure 51. AD9445-125 INL Error vs. Output Code, 125 MSPS, 10.3 MHz
400
1.014
350
1.012
300
AVDD1
ISUPPLY (mA)
VREF
1.010
1.008
250
200
AVDD2
150
1.006
100
DRVDD
1.004
–20
0
20
40
60
05489-066
05489-051
1.002
–40
50
0
20
0
80
40
60
80
120
140
160
Figure 52. AD9445-105 Power Supply Current vs. Sample Rate
10.3 MHz @ −1 dBFS
Figure 49. AD9445-125 VREF vs. Temperature
78
0.5
0.4
77
170.3MHz SNR dB
0.3
76
0.2
0.1
75
225.3MHz SNR dB
(dB)
INL ERROR (LSB)
100
SAMPLE RATE (MSPS)
TEMPERATURE (°C)
0
74
–0.1
300.3MHz SNR dB
73
–0.2
–0.3
–0.5
0
4096
8192
12288
71
1.8
16384
05489-067
05489-052
72
–0.4
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
4.2
ANALOG INPUT RANGE (V p-p)
OUTPUT CODE
Figure 50. AD9445-105 INL Error vs. Output Code, 105 MSPS, 10.3 MHz
Figure 53. AD9445-125 SNR vs. Analog Input Range, 125 MSPS/170.3 MHz,
225.3 MHz, 300.3 MHz
Rev. 0 | Page 22 of 40
AD9445
78
95
77
170.3MHz SFDR dBc
90
76
170.3MHz SFDR dBc
75
85
(dB)
(dB)
225.3MHz SFDR dBc
225.3MHz SFDR dBc
74
80
300.3MHz SFDR dBc
73
05489-068
71
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
300.3MHz SFDR dBc
70
1.8
4.2
2.0
2.2
ANALOG INPUT RANGE (V p-p)
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
4.2
ANALOG INPUT RANGE (V p-p)
Figure 54. AD9445-105 SNR vs. Analog Input Range,
105 MSPS/170.3 MHz, 225.3 MHz, 300.3 MHz
Figure 57. AD9445-105 SFDR vs. Analog Input Range,
105 MSPS/170.3 MHz, 225.3 MHz, 300.3 MHz
400
81
350
80
300
79
AVDD1
250
105M SNR dBFS
78
(dB)
ISUPPLY (mA)
05489-071
75
72
200
AVDD2
77
125M SNR dBFS
150
76
100
DRVDD
0
20
0
40
60
80
100
120
140
74
1.8
160
SAMPLE RATE (MSPS)
170.3MHz SFDR dBc
(dB)
85
80
225.3MHz SFDR dBc
05489-070
75
300.3MHz SFDR dBc
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
4.0
4.2
Figure 58. SNR vs. Analog Input Range, 2.3 MHz @ −30 dBFS
95
70
1.8
2.0
ANALOG INPUT RANGE (V p-p)
Figure 55. AD9445-125 Power Supply Current vs. Sample Rate
10.3 MHz @ −1 dBFS
90
05489-039
75
05489-069
50
3.6
3.8
4.0
4.2
ANALOG INPUT RANGE (V p-p)
Figure 56. AD9445-125 SFDR vs. Analog Input Range, 125 MSPS/170.3 MHz,
225.3 MHz, 300.3 MHz
Rev. 0 | Page 23 of 40
AD9445
THEORY OF OPERATION
The AD9445 architecture is optimized for high speed and ease
of use. The analog inputs drive an integrated, high bandwidth
track-and-hold circuit that samples the signal prior to quantization
by the 14-bit pipeline ADC core. The device includes an on-board
reference and input logic that accepts TTL, CMOS, or LVPECL
levels. The digital output logic levels are user selectable as standard
3 V CMOS or LVDS (ANSI-644 compatible) via the OUTPUT
MODE pin.
connected to AGND). Because of this trim and the maximum ac
performance provided by the 2.0 V p-p analog input range, there
is little benefit to using analog input ranges
